Mock Version: 2.16
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x7fb55bbd7820>timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=TrueprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '4ff7be2426654d8184b78cffbd02a5aa', '-D', '/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1647648000
Wrote: /builddir/build/SRPMS/pythondata-cpu-rocket-0.0.post7130-1.el9.src.rpm
Child return code was: 0
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -br --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x7fb55bbd7820>timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=TrueraiseExc=FalseprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', 'c8fb5846833f43358ecaa8eb0dd0ca1d', '-D', '/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -br --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1647648000
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.5Wpv9F
+ umask 022
+ cd /builddir/build/BUILD
+ cd /builddir/build/BUILD
+ rm -rf pythondata-cpu-rocket-0.0.post7130
+ /usr/bin/gzip -dc /builddir/build/SOURCES/pythondata-cpu-rocket-0.0.post7130.tar.gz
+ /usr/bin/tar -xof -
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ cd pythondata-cpu-rocket-0.0.post7130
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%generate_buildrequires): /bin/sh -e /var/tmp/rpm-tmp.cwFwlg
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ echo pyproject-rpm-macros
+ echo python3-devel
+ echo 'python3dist(pip) >= 19'
+ echo 'python3dist(packaging)'
+ '[' -f pyproject.toml ']'
+ '[' -f setup.py ']'
+ echo 'python3dist(setuptools) >= 40.8'
+ echo 'python3dist(wheel)'
+ rm -rfv '*.dist-info/'
+ '[' -f /usr/bin/python3 ']'
+ RPM_TOXENV=py39
+ HOSTNAME=rpmbuild
+ /usr/bin/python3 -s /usr/lib/rpm/redhat/pyproject_buildrequires.py --generate-extras --python3_pkgversion 3 -r
Handling setuptools >= 40.8 from default build backend
Requirement satisfied: setuptools >= 40.8
   (installed: setuptools 53.0.0)
Handling wheel from default build backend
Requirement not satisfied: wheel
Exiting dependency generation pass: build backend
+ RPM_EC=0
++ jobs -p
+ exit 0
Wrote: /builddir/build/SRPMS/pythondata-cpu-rocket-0.0.post7130-1.el9.buildreqs.nosrc.rpm
Child return code was: 11
Dynamic buildrequires detected
Going to install missing buildrequires. See root.log for details.
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -br --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x7fb55bbd7820>timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=TrueraiseExc=FalseprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '35b90342d6944735bc6f31d154d7b188', '-D', '/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -br --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1647648000
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.KJJAeH
+ umask 022
+ cd /builddir/build/BUILD
+ cd /builddir/build/BUILD
+ rm -rf pythondata-cpu-rocket-0.0.post7130
+ /usr/bin/gzip -dc /builddir/build/SOURCES/pythondata-cpu-rocket-0.0.post7130.tar.gz
+ /usr/bin/tar -xof -
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ cd pythondata-cpu-rocket-0.0.post7130
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%generate_buildrequires): /bin/sh -e /var/tmp/rpm-tmp.0ApGZi
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ echo pyproject-rpm-macros
+ echo python3-devel
+ echo 'python3dist(pip) >= 19'
+ echo 'python3dist(packaging)'
+ '[' -f pyproject.toml ']'
+ '[' -f setup.py ']'
+ echo 'python3dist(setuptools) >= 40.8'
+ echo 'python3dist(wheel)'
+ rm -rfv '*.dist-info/'
+ '[' -f /usr/bin/python3 ']'
+ RPM_TOXENV=py39
+ HOSTNAME=rpmbuild
+ /usr/bin/python3 -s /usr/lib/rpm/redhat/pyproject_buildrequires.py --generate-extras --python3_pkgversion 3 -r
Handling setuptools >= 40.8 from default build backend
Requirement satisfied: setuptools >= 40.8
   (installed: setuptools 53.0.0)
Handling wheel from default build backend
Requirement satisfied: wheel
   (installed: wheel 0.36.2)
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
HOOK STDOUT: running egg_info
HOOK STDOUT: writing pythondata_cpu_rocket.egg-info/PKG-INFO
HOOK STDOUT: writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt
HOOK STDOUT: writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt
HOOK STDOUT: reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: reading manifest template 'MANIFEST.in'
HOOK STDOUT: adding license file 'LICENSE'
HOOK STDOUT: writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
Handling wheel from get_requires_for_build_wheel
Requirement satisfied: wheel
   (installed: wheel 0.36.2)
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
HOOK STDOUT: running dist_info
HOOK STDOUT: writing pythondata_cpu_rocket.egg-info/PKG-INFO
HOOK STDOUT: writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt
HOOK STDOUT: writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt
HOOK STDOUT: reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: reading manifest template 'MANIFEST.in'
HOOK STDOUT: adding license file 'LICENSE'
HOOK STDOUT: writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: creating '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pythondata_cpu_rocket.dist-info'
HOOK STDOUT: adding license file "LICENSE" (matched pattern "LICEN[CS]E*")
+ RPM_EC=0
++ jobs -p
+ exit 0
Wrote: /builddir/build/SRPMS/pythondata-cpu-rocket-0.0.post7130-1.el9.buildreqs.nosrc.rpm
Child return code was: 11
Dynamic buildrequires detected
Going to install missing buildrequires. See root.log for details.
ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -ba --noprep --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'], chrootPath='/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=<mockbuild.trace_decorator.getLog object at 0x7fb55bbd7820>timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=TrueprintOutput=True)
Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']
Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', 'ae277674e057438fb46f8e6756f8007e', '-D', '/var/lib/mock/centos-stream+epel-9-x86_64-1647838915.775098/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.9m9eq__i:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;<mock-chroot>\\007"', '--setenv=PS1=<mock-chroot> \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -ba --noprep --target x86_64 --nodeps /builddir/build/SPECS/pythondata-cpu-rocket.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;<mock-chroot>\\007"', 'PS1': '<mock-chroot> \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1647648000
Executing(%generate_buildrequires): /bin/sh -e /var/tmp/rpm-tmp.d2G4qF
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ echo pyproject-rpm-macros
+ echo python3-devel
+ echo 'python3dist(pip) >= 19'
+ echo 'python3dist(packaging)'
+ '[' -f pyproject.toml ']'
+ '[' -f setup.py ']'
+ echo 'python3dist(setuptools) >= 40.8'
+ echo 'python3dist(wheel)'
+ rm -rfv pythondata_cpu_rocket.dist-info/
removed 'pythondata_cpu_rocket.dist-info/LICENSE'
removed 'pythondata_cpu_rocket.dist-info/METADATA'
removed 'pythondata_cpu_rocket.dist-info/top_level.txt'
removed directory 'pythondata_cpu_rocket.dist-info/'
+ '[' -f /usr/bin/python3 ']'
+ RPM_TOXENV=py39
+ HOSTNAME=rpmbuild
+ /usr/bin/python3 -s /usr/lib/rpm/redhat/pyproject_buildrequires.py --generate-extras --python3_pkgversion 3 -r
Handling setuptools >= 40.8 from default build backend
Requirement satisfied: setuptools >= 40.8
   (installed: setuptools 53.0.0)
Handling wheel from default build backend
Requirement satisfied: wheel
   (installed: wheel 0.36.2)
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
HOOK STDOUT: running egg_info
HOOK STDOUT: creating pythondata_cpu_rocket.egg-info
HOOK STDOUT: writing pythondata_cpu_rocket.egg-info/PKG-INFO
HOOK STDOUT: writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt
HOOK STDOUT: writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt
HOOK STDOUT: writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: reading manifest template 'MANIFEST.in'
HOOK STDOUT: adding license file 'LICENSE'
HOOK STDOUT: writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
Handling wheel from get_requires_for_build_wheel
Requirement satisfied: wheel
   (installed: wheel 0.36.2)
warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
HOOK STDOUT: running dist_info
HOOK STDOUT: writing pythondata_cpu_rocket.egg-info/PKG-INFO
HOOK STDOUT: writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt
HOOK STDOUT: writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt
HOOK STDOUT: reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: reading manifest template 'MANIFEST.in'
HOOK STDOUT: adding license file 'LICENSE'
HOOK STDOUT: writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
HOOK STDOUT: creating '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pythondata_cpu_rocket.dist-info'
HOOK STDOUT: adding license file "LICENSE" (matched pattern "LICEN[CS]E*")
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.NuEHYn
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ mkdir -p /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64-v2 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection'
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 '
+ TMPDIR=/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir
+ /usr/bin/python3 -m pip wheel --wheel-dir /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pyproject-wheeldir --no-deps --use-pep517 --no-build-isolation --disable-pip-version-check --no-clean --progress-bar off --verbose .
Processing /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130
  Preparing metadata (pyproject.toml): started
  Running command Preparing metadata (pyproject.toml)
  running dist_info
  creating /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info
  writing /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/PKG-INFO
  writing dependency_links to /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/dependency_links.txt
  writing top-level names to /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/top_level.txt
  writing manifest file '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/SOURCES.txt'
  reading manifest file '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/SOURCES.txt'
  reading manifest template 'MANIFEST.in'
  warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
  adding license file 'LICENSE'
  writing manifest file '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.egg-info/SOURCES.txt'
  creating '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-modern-metadata-hs1sb5z1/pythondata_cpu_rocket.dist-info'
  adding license file "LICENSE" (matched pattern "LICEN[CS]E*")
  Preparing metadata (pyproject.toml): finished with status 'done'
Building wheels for collected packages: pythondata-cpu-rocket
  Building wheel for pythondata-cpu-rocket (pyproject.toml): started
  Running command Building wheel for pythondata-cpu-rocket (pyproject.toml)
  running bdist_wheel
  running build
  running build_py
  creating build
  creating build/lib
  creating build/lib/pythondata_cpu_rocket
  copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket
  running egg_info
  creating pythondata_cpu_rocket.egg-info
  writing pythondata_cpu_rocket.egg-info/PKG-INFO
  writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt
  writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt
  writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
  reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
  reading manifest template 'MANIFEST.in'
  warning: no previously-included files matching '*.py[cod]' found anywhere in distribution
  adding license file 'LICENSE'
  writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt'
  creating build/lib/pythondata_cpu_rocket/verilog
  copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog
  copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog
  copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog
  copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog
  creating build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.fir -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src
  creating build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc
  installing to build/bdist.linux-x86_64/wheel
  running install
  running install_lib
  creating build/bdist.linux-x86_64
  creating build/bdist.linux-x86_64/wheel
  creating build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket
  creating build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog
  creating build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/vsrc
  creating build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog/generated-src
  copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog
  copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog
  copying build/lib/pythondata_cpu_rocket/verilog/README.md -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog
  copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket/verilog
  copying build/lib/pythondata_cpu_rocket/__init__.py -> build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket
  running install_egg_info
  Copying pythondata_cpu_rocket.egg-info to build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket-0.0.post7130-py3.9.egg-info
  running install_scripts
  adding license file "LICENSE" (matched pattern "LICEN[CS]E*")
  creating build/bdist.linux-x86_64/wheel/pythondata_cpu_rocket-0.0.post7130.dist-info/WHEEL
  creating '/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir/pip-wheel-f0k2wfit/tmp2fsqv25j/pythondata_cpu_rocket-0.0.post7130-py3-none-any.whl' and adding 'build/bdist.linux-x86_64/wheel' to it
  adding 'pythondata_cpu_rocket/__init__.py'
  adding 'pythondata_cpu_rocket/verilog/.gitignore'
  adding 'pythondata_cpu_rocket/verilog/README.md'
  adding 'pythondata_cpu_rocket/verilog/_upstream.rev'
  adding 'pythondata_cpu_rocket/verilog/update.sh'
  adding 'pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4DConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFull4QConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexFullConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2DConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux2QConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinux4Config.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxDConfig.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x0.1.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x2000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0x40.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.0xc000000.0.regmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.anno.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.behav_srams.v'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.d'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.dts'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.fir'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.graphml'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.memmap.json'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.plusArgs'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.rom.conf'
  adding 'pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexLinuxQConfig.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/SimDTM.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/TestDriver.v'
  adding 'pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v'
  adding 'pythondata_cpu_rocket-0.0.post7130.dist-info/LICENSE'
  adding 'pythondata_cpu_rocket-0.0.post7130.dist-info/METADATA'
  adding 'pythondata_cpu_rocket-0.0.post7130.dist-info/WHEEL'
  adding 'pythondata_cpu_rocket-0.0.post7130.dist-info/top_level.txt'
  adding 'pythondata_cpu_rocket-0.0.post7130.dist-info/RECORD'
  removing build/bdist.linux-x86_64/wheel
  Building wheel for pythondata-cpu-rocket (pyproject.toml): finished with status 'done'
  Created wheel for pythondata-cpu-rocket: filename=pythondata_cpu_rocket-0.0.post7130-py3-none-any.whl size=35157979 sha256=2e130cbfc58871e1f665b4a6c966d662b92ed30e2dc2b11efb13880ffb6b41df
  Stored in directory: /builddir/.cache/pip/wheels/69/ac/14/9264bed160851c149452b2be632335425c4d99077d8a3058c6
Successfully built pythondata-cpu-rocket
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.BCKiZ7
+ umask 022
+ cd /builddir/build/BUILD
+ '[' /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64 '!=' / ']'
+ rm -rf /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64
++ dirname /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64
+ mkdir -p /builddir/build/BUILDROOT
+ mkdir /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64
+ cd pythondata-cpu-rocket-0.0.post7130
++ ls /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pyproject-wheeldir/pythondata_cpu_rocket-0.0.post7130-py3-none-any.whl
++ sed -E 's/([^-]+)-([^-]+)-.+\.whl/\1==\2/'
++ xargs basename --multiple
+ specifier=pythondata_cpu_rocket==0.0.post7130
+ TMPDIR=/builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/.pyproject-builddir
+ /usr/bin/python3 -m pip install --root /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64 --no-deps --disable-pip-version-check --progress-bar off --verbose --ignore-installed --no-warn-script-location --no-index --no-cache-dir --find-links /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pyproject-wheeldir pythondata_cpu_rocket==0.0.post7130
Using pip 22.0.4 from /usr/lib/python3.9/site-packages/pip (python 3.9)
Looking in links: /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130/pyproject-wheeldir
Processing ./pyproject-wheeldir/pythondata_cpu_rocket-0.0.post7130-py3-none-any.whl
Installing collected packages: pythondata_cpu_rocket
Successfully installed pythondata_cpu_rocket-0.0.post7130
+ '[' -d /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/bin ']'
+ rm -f /builddir/build/BUILD/pyproject-ghost-distinfo
+ site_dirs=()
+ '[' -d /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages ']'
+ site_dirs+=("/usr/lib/python3.9/site-packages")
+ '[' /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib64/python3.9/site-packages '!=' /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages ']'
+ '[' -d /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib64/python3.9/site-packages ']'
+ for site_dir in ${site_dirs[@]}
+ for distinfo in /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64$site_dir/*.dist-info
+ echo '%ghost /usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info'
+ sed -i s/pip/rpm/ /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/INSTALLER
+ PYTHONPATH=/usr/lib/rpm/redhat
+ /usr/bin/python3 -B /usr/lib/rpm/redhat/pyproject_preprocess_record.py --buildroot /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64 --record /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/RECORD --output /builddir/build/BUILD/pyproject-record
+ rm -fv /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/RECORD
removed '/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/RECORD'
+ rm -fv /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/REQUESTED
removed '/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7130.dist-info/REQUESTED'
++ wc -l /builddir/build/BUILD/pyproject-ghost-distinfo
++ cut -f1 '-d '
+ lines=1
+ '[' 1 -ne 1 ']'
+ /usr/bin/python3 /usr/lib/rpm/redhat/pyproject_save_files.py --output-files /builddir/build/BUILD/pyproject-files --output-modules /builddir/build/BUILD/pyproject-modules --buildroot /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64 --sitelib /usr/lib/python3.9/site-packages --sitearch /usr/lib64/python3.9/site-packages --python-version 3.9 --pyproject-record /builddir/build/BUILD/pyproject-record --prefix /usr '*' +auto
+ /usr/lib/rpm/find-debuginfo.sh -j2 --strict-build-id -m -i --build-id-seed 0.0.post7130-1.el9 --unique-debug-suffix -0.0.post7130-1.el9.x86_64 --unique-debug-src-base pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 110000000 -S debugsourcefiles.list /builddir/build/BUILD/pythondata-cpu-rocket-0.0.post7130
find: 'debug': No such file or directory
+ /usr/lib/rpm/check-buildroot
+ /usr/lib/rpm/redhat/brp-ldconfig
+ /usr/lib/rpm/brp-compress
+ /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip
+ /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip
+ /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0
Bytecompiling .py files below /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9 using python3.9
+ /usr/lib/rpm/brp-python-hardlink
+ /usr/lib/rpm/redhat/brp-mangle-shebangs
Executing(%check): /bin/sh -e /var/tmp/rpm-tmp.OepyQ7
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ '[' '!' -f /builddir/build/BUILD/pyproject-modules ']'
+ PATH=/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/bin:/builddir/.local/bin:/builddir/bin:/usr/bin:/bin:/usr/sbin:/sbin:/usr/local/sbin
+ PYTHONPATH=/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib64/python3.9/site-packages:/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages
+ _PYTHONSITE=/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib64/python3.9/site-packages:/builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64/usr/lib/python3.9/site-packages
+ PYTHONDONTWRITEBYTECODE=1
+ /usr/bin/python3 -s /usr/lib/rpm/redhat/import_all_modules.py -f /builddir/build/BUILD/pyproject-modules -t
Check import: pythondata_cpu_rocket
+ RPM_EC=0
++ jobs -p
+ exit 0
Processing files: python3-pythondata-cpu-rocket-0.0.post7130-1.el9.noarch
Provides: python-pythondata-cpu-rocket = 0.0.post7130-1.el9 python3-pythondata-cpu-rocket = 0.0.post7130-1.el9 python3.9-pythondata-cpu-rocket = 0.0.post7130-1.el9 python3.9dist(pythondata-cpu-rocket) = 0^post7130 python3dist(pythondata-cpu-rocket) = 0^post7130
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: /usr/bin/sh python(abi) = 3.9
Obsoletes: python39-pythondata-cpu-rocket < 0.0.post7130-1.el9
Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64
Wrote: /builddir/build/SRPMS/pythondata-cpu-rocket-0.0.post7130-1.el9.src.rpm
Wrote: /builddir/build/RPMS/python3-pythondata-cpu-rocket-0.0.post7130-1.el9.noarch.rpm
Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.rCFaRx
+ umask 022
+ cd /builddir/build/BUILD
+ cd pythondata-cpu-rocket-0.0.post7130
+ /usr/bin/rm -rf /builddir/build/BUILDROOT/pythondata-cpu-rocket-0.0.post7130-1.el9.x86_64
+ RPM_EC=0
++ jobs -p
+ exit 0
Child return code was: 0