class OrigenDocHelpersDev::DUT
Public Class Methods
new(_options = {})
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# File lib/origen_doc_helpers_dev/dut.rb, line 104 def initialize(_options = {}) sub_block :sub_module, class_name: 'SubModule' # **The Long Name of the Reg** # # The MCLKDIV register is used to divide down the frequency of the HBOSCCLK input. If the MCLKDIV # register is set to value "N", then the output (beat) frequency of the clock divider is OSCCLK / (N+1). The # resulting beats are, in turn, counted by the PTIMER module to control the duration of Flash high-voltage # operations. # # This is just a test that paragraphs work. add_reg :mclkdiv, 0x0003, size: 16 do # **Oscillator (Hi)** - Firmware FMU clock source selection. (Note that in addition to this firmware-controlled bit, the # FMU clock source is also dependent on test and power control discretes). # # 0 | FMU clock is the externally supplied bus clock ipg_clk # 1 | FMU clock is the internal oscillator from the TFS hardblock bit 15, :osch, reset: 1 # **Mode Ready** - A Synchronized version of the *ftf_mode_ready[1:0]* output from the flash analog hard block. # See the TFL3 Hard Block Creation Guide for more details. # # 0 | Analog voltages have not reached target levels for the specified mode of operation # 1 | Analog voltages have reached target levels for the specified mode of operation bit 13..12, :mode_rdy, writable: false # **IFR and FW ECC Enable for LDM** - On / off control for UIFR, RIFR, and FW when reading with the MGATE's # Load Memory (LDM) instruction. The setting of this bit only makes a difference when reading with LDM, all other # MGATE reads from UIFR/RIFR will always have ECC disabled and reads from FW will have ECC enabled. # # 0 | ECC is disabled for UIFR, RIFR, and FW reads when using the LDM instruction # 1 | ECC is enabled for all UIFR, RIFR, and FW reads when using the LDM instruction bit 10, :eccen, reset: 1 # **MGATE Command Location Code** - A 2-bit code that tells the MGATE where to go for its instruction fetches # (location of command definitions). These bits are used to form different MGATE command request IDs from a # falling CCIF, one request ID for each of the possible locations of the MGATE executable. If this field is changed, # all subsequent command launches (falling CCIF) will execute from the new area. Note that the MGATE also has # a reset request ID. The reset request ID always targets the Boot Code and is unaffected by the CMDLOC setting. # # 00 | Execute from the Beginning of the MGRAM + 256B (the normal location) # 01 | Execute from the Beginning of the MGRAM # 10 | Execute from the Stack start at the end of MGRAM # 11 | Reserved bit 9..7, :cmdloc, reset: :undefined # **Clock Divider Bits** - DIV[7:0] must be set to effectively divide HBOSCCLK down to a known beat frequency # having acceptable resolution and dynamic range for timing high-voltage operations on the Flash hardblocks # during algorithms with timed events. Table 1-50 shows the range of timed events (i.e. pulse widths) that can be # achieved with 8-bit and 16-bit PTIMER loads for various input clock frequencies and clock divider settings. bit 6..2, :div, reset: :memory end # **Protection High** # # A simple register definition to test that reset values assigned to bytes # of a 32-bit register work reg :proth, 0x0024 do bits 31..24, :fprot7, reset: 0xFF bits 23..16, :fprot6, reset: 0xEE bits 15..8, :fprot5, reset: 0xDD bits 7..0, :fprot4, reset: 0x11 end # **Protection Low** # # A simple register definition to test that memory dependent bits display # correctly reg :protl, 0x0028 do bits 31..24, :fprot3, nvm_dep: true bits 23..16, :fprot2, reset: :memory bits 15..8, :fprot1, nvm_dep: true bits 7..0, :fprot0, nvm_dep: true end add_mode :default add_mode :low_power add_mode :high_performance # SMcG, removing as does not work with latest Origen, can be reintroduced # when the Origen spec API is stable # modes.each do |mode| # case mode # when :default # vdd_nom = 1.0.V # when :low_power # vdd_nom = 0.95.V # when :high_performance # vdd_nom = 1.05.V # end # spec :soc_vdd, mode do # symbol 'Vdd' # description 'Soc Core Power Supply' # min "#{vdd_nom} - 50.mV" # max "#{vdd_nom} + 50.mV" # audience :external # end # end # spec :soc_io_vdd do # symbol 'GVdd' # description 'Soc IO Power Supply' # min 1.35.v # max '1.50.v + 150.mv' # audience :external # end # spec :soc_pll_vdd do # symbol 'AVdd' # description 'Soc PLL Power Supply' # min :soc_vdd # max :soc_vdd # audience :external # end end