class Object
Public Instance Methods
address_width()
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 55 def address_width register_block.local_address_width end
array_size()
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# File lib/rggen/verilog/bit_field/type.rb, line 20 def array_size bit_field.array_size end
bit_field_read_data()
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# File lib/rggen/verilog/bit_field/type.rb, line 53 def bit_field_read_data register.bit_field_read_data[lsb, width] end
bit_field_read_mask()
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# File lib/rggen/verilog/bit_field/type.rb, line 41 def bit_field_read_mask register.bit_field_read_mask[lsb, width] end
bit_field_valid()
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# File lib/rggen/verilog/bit_field/type.rb, line 37 def bit_field_valid register.bit_field_valid end
bit_field_value()
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# File lib/rggen/verilog/bit_field/type.rb, line 57 def bit_field_value register.bit_field_value[lsb, width] end
bit_field_write_data()
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# File lib/rggen/verilog/bit_field/type.rb, line 49 def bit_field_write_data register.bit_field_write_data[lsb, width] end
bit_field_write_mask()
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# File lib/rggen/verilog/bit_field/type.rb, line 45 def bit_field_write_mask register.bit_field_write_mask[lsb, width] end
body_code(code)
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 87 def body_code(code) bit_field.generate_code(code, :bit_field, :top_down) end
bus_width()
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# File lib/rggen/verilog/register_block/protocol.rb, line 28 def bus_width configuration.bus_width end
byte_size()
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# File lib/rggen/verilog/register_block/protocol.rb, line 40 def byte_size register_block.byte_size end
clear_signal()
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# File lib/rggen/verilog/bit_field/type/rwc.rb, line 20 def clear_signal reference_bit_field || clear[loop_variables] end
clock()
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# File lib/rggen/verilog/bit_field/type.rb, line 29 def clock register_block.clock end
clock_or_reset?(declaration)
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 102 def clock_or_reset?(declaration) [clock.to_s, reset.to_s] .any? { |port_name| declaration.include?(port_name) } end
control_signal()
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# File lib/rggen/verilog/bit_field/type/rwe_rwl.rb, line 29 def control_signal reference_bit_field || control[loop_variables] end
control_signal_polarity()
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# File lib/rggen/verilog/bit_field/type/rwe_rwl.rb, line 25 def control_signal_polarity { rwe: '`RGGEN_ACTIVE_HIGH', rwl: '`RGGEN_ACTIVE_LOW' }[bit_field.type] end
define_accessor_for_initial_value()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 45 def define_accessor_for_initial_value define_singleton_method(:initial_value) do bit_field.initial_value? && initial_value_rhs || nil end end
enable_or_lock()
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# File lib/rggen/verilog/bit_field/type/rwe_rwl.rb, line 21 def enable_or_lock { rwe: 'enable', rwl: 'lock' }[bit_field.type] end
end_address()
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# File lib/rggen/verilog/register/type/external.rb, line 40 def end_address address = register.offset_address + register.byte_size - 1 hex(address, address_width) end
full_name()
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# File lib/rggen/verilog/bit_field/type.rb, line 8 def full_name bit_field.full_name('_') end
id_width_value()
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# File lib/rggen/verilog/register_block/protocol/axi4lite.rb, line 88 def id_width_value "((#{id_width} == 0) ? 1 : #{id_width})" end
initial_value()
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# File lib/rggen/verilog/bit_field/type.rb, line 24 def initial_value index = bit_field.initial_value_array? && bit_field.local_index || 0 macro_call('rggen_slice', [bit_field.initial_value, width, index]) end
initial_value_array_size()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 55 def initial_value_array_size bit_field.initial_value_array? && [bit_field.sequence_size] || nil end
initial_value_name()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 51 def initial_value_name "#{bit_field.full_name('_')}_initial_value".upcase end
initial_value_rhs()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 59 def initial_value_rhs if !bit_field.initial_value_array? sized_initial_value elsif bit_field.fixed_initial_value? merged_initial_values else repeat(bit_field.sequence_size, sized_initial_value) end end
local_address_width()
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# File lib/rggen/verilog/register_block/protocol.rb, line 32 def local_address_width register_block.local_address_width end
loop_size()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 82 def loop_size loop_variable = local_index loop_variable && { loop_variable => bit_field.sequence_size } end
loop_variables()
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# File lib/rggen/verilog/bit_field/type.rb, line 72 def loop_variables bit_field.loop_variables end
lsb()
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# File lib/rggen/verilog/bit_field/type.rb, line 12 def lsb bit_field.lsb(bit_field.local_index) end
macro_definition(code)
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 72 def macro_definition(code) template_path = File.join(__dir__, 'verilog_macros.erb') code << process_template(template_path) end
mask()
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# File lib/rggen/verilog/bit_field/type.rb, line 61 def mask reference_bit_field || fill_1(width) end
merged_initial_values()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 73 def merged_initial_values value = bit_field .initial_values .map.with_index { |v, i| v << (i * bit_field.width) } .inject(:|) hex(value, bit_field.width * bit_field.sequence_size) end
parameterized_initial_value?()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 41 def parameterized_initial_value? bit_field.initial_value? && !bit_field.fixed_initial_value? end
parameters()
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 86 def parameters register_block.declarations[:parameter] end
ports()
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 90 def ports register_block .declarations[:port] .yield_self(&method(:sort_port_declarations)) end
read_action()
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# File lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 23 def read_action { rc: '`RGGEN_READ_CLEAR', w0c: '`RGGEN_READ_DEFAULT', w1c: '`RGGEN_READ_DEFAULT', wc: '`RGGEN_READ_DEFAULT', woc: '`RGGEN_READ_NONE' }[bit_field.type] end
read_set?()
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# File lib/rggen/verilog/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb, line 21 def read_set? [:w0crs, :w1crs, :wcrs].include?(bit_field.type) end
reference_bit_field()
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# File lib/rggen/verilog/bit_field/type.rb, line 65 def reference_bit_field bit_field.reference? && bit_field .find_reference(register_block.bit_fields) .value(bit_field.local_indices, bit_field.reference_width) end
reference_or_value_in()
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# File lib/rggen/verilog/bit_field/type/ro.rb, line 17 def reference_or_value_in bit_field.reference? && reference_bit_field || value_in[loop_variables] end
register_access()
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# File lib/rggen/verilog/register/type.rb, line 22 def register_access register_block.register_access end
register_active()
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# File lib/rggen/verilog/register/type.rb, line 38 def register_active register_block.register_active[[register.index]] end
register_address()
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# File lib/rggen/verilog/register/type.rb, line 26 def register_address register_block.register_address end
register_read_data()
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# File lib/rggen/verilog/register/type.rb, line 50 def register_read_data register_block.register_read_data[[register.index]] end
register_ready()
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# File lib/rggen/verilog/register/type.rb, line 42 def register_ready register_block.register_ready[[register.index]] end
register_status()
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# File lib/rggen/verilog/register/type.rb, line 46 def register_status register_block.register_status[[register.index]] end
register_strobe()
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# File lib/rggen/verilog/register/type.rb, line 34 def register_strobe register_block.register_strobe end
register_valid()
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# File lib/rggen/verilog/register/type.rb, line 18 def register_valid register_block.register_valid end
register_value(offsets, lsb, width)
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 36 def register_value(offsets, lsb, width) index = register.index(offsets || register.local_indices) register_block.register_value[[index], lsb, width] end
register_write_data()
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# File lib/rggen/verilog/register/type.rb, line 30 def register_write_data register_block.register_write_data end
reset()
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# File lib/rggen/verilog/bit_field/type.rb, line 33 def reset register_block.reset end
set_signal()
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# File lib/rggen/verilog/bit_field/type/rws.rb, line 23 def set_signal reference_bit_field || set[loop_variables] end
sized_initial_value()
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 69 def sized_initial_value hex(bit_field.register_map.initial_value, bit_field.width) end
sort_port_declarations(declarations)
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 96 def sort_port_declarations(declarations) declarations .partition(&method(:clock_or_reset?)) .flatten end
start_address()
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# File lib/rggen/verilog/register/type/external.rb, line 36 def start_address hex(register.offset_address, address_width) end
target_feature_key(_configuration, bit_field)
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# File lib/rggen/verilog/bit_field/type.rb, line 78 def target_feature_key(_configuration, bit_field) type = bit_field.type target_features.key?(type) && type || (error "code generator for #{type} bit field type is not implemented") end
top_scope?()
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# File lib/rggen/verilog/register/verilog_top.rb, line 41 def top_scope? register_file.nil? end
total_registers()
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# File lib/rggen/verilog/register_block/protocol.rb, line 36 def total_registers register_block.files_and_registers.sum(&:count) end
trigger_value()
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# File lib/rggen/verilog/bit_field/type/w0trg_w1trg.rb, line 15 def trigger_value bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1) end
valid_type?(type)
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# File lib/rggen/verilog/register/type.rb, line 96 def valid_type?(type) target_features.key?(type) || type == :default end
value(offsets = nil, width = nil)
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# File lib/rggen/verilog/bit_field/verilog_top.rb, line 28 def value(offsets = nil, width = nil) value_lsb = bit_field.lsb(offsets&.last || local_index) value_width = width || bit_field.width register_value(offsets&.slice(0..-2), value_lsb, value_width) end
value_out_unmasked()
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# File lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 47 def value_out_unmasked (bit_field.reference? || nil) && value_unmasked[loop_variables] end
value_width()
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 63 def value_width register_block.registers.map(&:width).max end
variables()
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# File lib/rggen/verilog/register/verilog_top.rb, line 50 def variables register.declarations[:variable] end
verilog_module_body(code)
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 111 def verilog_module_body(code) { register_block: nil, register_file: 1 }.each do |kind, depth| register_block.generate_code(code, kind, :top_down, depth) end end
verilog_module_definition(code)
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# File lib/rggen/verilog/register_block/verilog_top.rb, line 77 def verilog_module_definition(code) code << module_definition(register_block.name) do |verilog_module| verilog_module.parameters parameters verilog_module.ports ports verilog_module.variables variables verilog_module.body(&method(:verilog_module_body)) end end
width()
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# File lib/rggen/verilog/bit_field/type.rb, line 16 def width bit_field.width end
write_action()
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# File lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 33 def write_action { rc: '`RGGEN_WRITE_NONE', w0c: '`RGGEN_WRITE_0_CLEAR', w1c: '`RGGEN_WRITE_1_CLEAR', wc: '`RGGEN_WRITE_CLEAR', woc: '`RGGEN_WRITE_CLEAR' }[bit_field.type] end
write_enable()
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# File lib/rggen/verilog/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 43 def write_enable bit_field.writable? && bin(1, 1) || bin(0, 1) end
write_once()
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# File lib/rggen/verilog/bit_field/type/rw_w1_wo_wo1.rb, line 19 def write_once [:w1, :wo1].include?(bit_field.type) && 1 || 0 end