class TdlTest
Public Class Methods
test0()
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# File lib/tdl/sdlimplement/test.rb, line 8 def self.test0 hash = YAML::load(File.open('resource.yml')) hash.delete('params') hash.delete('implement') # puts hash['Mac_1G()'] hash.each do |k,v| SdlImplModule.new(k,v) end # puts SdlImplModule.modules_hash('Mac_1G()') puts SdlImplModule.modules_hash('Mac_1G()').dependent end
test1()
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# File lib/tdl/sdlimplement/test.rb, line 22 def self.test1 hash = YAML::load(File.open('resource.yml')) hash.delete('params') hash.delete('implement') # puts hash['Mac_1G()'] hash.each do |k,v| SdlImplModule.new(k,v) end # puts SdlImplModule.modules_hash('Mac_1G()') sure_array = SdlImplModule.modules_hash('ModuleTempSensorTpu').dependent(sure:true) use_array = SdlImplModule.modules_hash('ModuleTempSensorTpu').dependent(sure:false,pool: sure_array.flatten ) dep_array = SdlImplModule.inspect_dependent_verb(0,use_array) File.open("tmp_log.yml",'w') do |f| f.puts dep_array end end
test2()
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# File lib/tdl/sdlimplement/test.rb, line 44 def self.test2 hash = YAML::load(File.open('resource.yml')) pm = SdlImplParam.new(hash['params']) # hash.delete('params') # hash.delete('implement') # puts hash['Mac_1G()'] hash.each do |k,v| SdlImplModule.new(k,v) if(k != 'params') && (k != 'implement') end SdlTopImplement.new("tmp_impl",__dir__,hash['implement']['modules'],hash['implement']['tb'],pm,'./pins.yml') end
test3()
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# File lib/tdl/sdlimplement/test.rb, line 58 def self.test3 SdlTopImplement.build("custom_200T_1221","./resource.yml") end
test_axi4_combin_wr_rd_batch()
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# File lib/tdl/axi4/bak/axi4_combin_wr_rd_batch_auto.rb, line 74 def self.test_axi4_combin_wr_rd_batch c0 = Clock.new(name:"axi4_combin_wr_rd_batch_clk",freqM:148.5) r0 = Reset.new(name:"axi4_combin_wr_rd_batch_rst_n",active:"low") wr_slaver = Axi4.new(name:"wr_slaver",clock:c0,reset:r0) rd_slaver = Axi4.new(name:"rd_slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_combin_wr_rd_batch( wr_slaver:wr_slaver, rd_slaver:rd_slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_data_convert()
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# File lib/tdl/axi4/bak/axi4_data_convert.rb, line 63 def self.test_axi4_data_convert c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") a0 = Axi4.new(name:"UP",clock:c0,reset:r0,mode:Axi4::BOTH,dsize:32) a1 = Axi4.new(name:"DOWN",clock:c0,reset:r0,mode:Axi4::ONLY_WRITE) a1.axi4_data_convert(up_stream:a0) puts_sv Axi4.inst,Axi4.draw end
test_axi4_direct()
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# File lib/tdl/axi4/bak/axi4_direct_auto.rb, line 74 def self.test_axi4_direct c0 = Clock.new(name:"axi4_direct_clk",freqM:148.5) r0 = Reset.new(name:"axi4_direct_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"BOTH_to_BOTH") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_direct( mode:mode, slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_direct_verb()
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# File lib/tdl/axi4/bak/axi4_direct_verb_auto.rb, line 66 def self.test_axi4_direct_verb c0 = Clock.new(name:"axi4_direct_verb_clk",freqM:148.5) r0 = Reset.new(name:"axi4_direct_verb_rst_n",active:"low") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_direct_verb( slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_long_to_axi4_wide()
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# File lib/tdl/axi4/bak/axi4_long_to_axi4_wide_auto.rb, line 66 def self.test_axi4_long_to_axi4_wide c0 = Clock.new(name:"axi4_long_to_axi4_wide_clk",freqM:148.5) r0 = Reset.new(name:"axi4_long_to_axi4_wide_rst_n",active:"low") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_long_to_axi4_wide( slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_long_to_axi4_wide_a1()
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# File lib/tdl/axi4/bak/axi4_long_to_axi4_wide_A1_auto.rb, line 74 def self.test_axi4_long_to_axi4_wide_a1 c0 = Clock.new(name:"axi4_long_to_axi4_wide_a1_clk",freqM:148.5) r0 = Reset.new(name:"axi4_long_to_axi4_wide_a1_rst_n",active:"low") partition = Parameter.new(name:"partition",value:"ON") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_long_to_axi4_wide_a1( partition:partition, slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_long_to_axi4_wide_verb()
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# File lib/tdl/axi4/bak/axi4_long_to_axi4_wide_verb_auto.rb, line 81 def self.test_axi4_long_to_axi4_wide_verb c0 = Clock.new(name:"axi4_long_to_axi4_wide_verb_clk",freqM:148.5) r0 = Reset.new(name:"axi4_long_to_axi4_wide_verb_rst_n",active:"low") pipe = Parameter.new(name:"pipe",value:"OFF") partition = Parameter.new(name:"partition",value:"ON") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) Axi4.axi4_long_to_axi4_wide_verb( pipe:pipe, partition:partition, slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_packet_fifo()
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# File lib/tdl/axi4/bak/axi4_packet_fifo_auto.rb, line 142 def self.test_axi4_packet_fifo c0 = Clock.new(name:"axi4_packet_fifo_clk",freqM:148.5) r0 = Reset.new(name:"axi4_packet_fifo_rst_n",active:"low") pipe = Parameter.new(name:"pipe",value:"OFF") depth = Parameter.new(name:"depth",value:4) mode = Parameter.new(name:"mode",value:"BOTH") axi_in = Axi4.new(name:"axi_in",clock:c0,reset:r0) axi_out = Axi4.new(name:"axi_out",clock:c0,reset:r0) up_stream = axi_in down_stream = axi_out Axi4.axi4_packet_fifo( pipe:pipe, depth:depth, mode:mode, axi_in:axi_in, axi_out:axi_out) puts_sv Tdl.inst,Tdl.draw end
test_axi4_partition_od()
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# File lib/tdl/axi4/bak/axi4_partition_od.rb, line 69 def self.test_axi4_partition_od c0 = Clock.new(name:"pix",freqM:148.5) r0 = Reset.new(name:"pix",active:"low") a0 = Axi4.new(name:"UP",clock:c0,reset:r0,mode:Axi4::BOTH,dsize:32) a1 = Axi4.new(name:"DOWN",clock:c0,reset:r0,mode:Axi4::ONLY_WRITE) a1.axi4_partition_od(up_stream:a0) puts_sv Axi4.inst,Axi4.draw end
test_axi4_pipe()
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# File lib/tdl/axi4/bak/axi4_pipe_auto.rb, line 114 def self.test_axi4_pipe c0 = Clock.new(name:"axi4_pipe_clk",freqM:148.5) r0 = Reset.new(name:"axi4_pipe_rst_n",active:"low") slaver = Axi4.new(name:"slaver",clock:c0,reset:r0) master = Axi4.new(name:"master",clock:c0,reset:r0) up_stream = slaver down_stream = master Axi4.axi4_pipe( slaver:slaver, master:master) puts_sv Tdl.inst,Tdl.draw end
test_axi4_to_native_for_ddr_ip_verb()
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# File lib/tdl/axi_stream/bak/axi4_to_native_for_ddr_ip_verb_auto.rb, line 59 def self.test_axi4_to_native_for_ddr_ip_verb c0 = Clock.new(name:"axi4_to_native_for_ddr_ip_verb_clk",freqM:148.5) r0 = Reset.new(name:"axi4_to_native_for_ddr_ip_verb_rst_n",active:"low") Parameter.new(name:"addr_width",value:27) Parameter.new(name:"data_width",value:256) Logic.new(name:"app_addr") Logic.new(name:"app_cmd") Logic.new(name:"app_en") Logic.new(name:"app_wdf_data") Logic.new(name:"app_wdf_end") Logic.new(name:"app_wdf_mask") Logic.new(name:"app_wdf_wren") Logic.new(name:"app_rd_data") Logic.new(name:"app_rd_data_end") Logic.new(name:"app_rd_data_valid") Logic.new(name:"app_rdy") Logic.new(name:"app_wdf_rdy") Logic.new(name:"init_calib_complete") Axi4.new(name:"axi_inf",clock:c0,reset:r0) Axi4.axi4_to_native_for_ddr_ip_verb(addr_width:addr_width,data_width:data_width,app_addr:app_addr,app_cmd:app_cmd,app_en:app_en,app_wdf_data:app_wdf_data,app_wdf_end:app_wdf_end,app_wdf_mask:app_wdf_mask,app_wdf_wren:app_wdf_wren,app_rd_data:app_rd_data,app_rd_data_end:app_rd_data_end,app_rd_data_valid:app_rd_data_valid,app_rdy:app_rdy,app_wdf_rdy:app_wdf_rdy,init_calib_complete:init_calib_complete,axi_inf:axi_inf) puts_sv Tdl.inst,Tdl.draw end
test_axi4_wr_auxiliary_gen_without_resp()
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# File lib/tdl/axi4/bak/__axi4_wr_auxiliary_gen_without_resp.rb, line 52 def self.test_axi4_wr_auxiliary_gen_without_resp c0 = Clock.new(name:"axi4_wr_auxiliary_gen_without_resp_clk",freqM:148.5) r0 = Reset.new(name:"axi4_wr_auxiliary_gen_without_resp_rst_n",active:"low") stream_en = Logic.new(name:"stream_en") id_add_len_in = AxiStream.new(name:"id_add_len_in",clock:c0,reset:r0) axi_wr_aux = Axi4.new(name:"axi_wr_aux",clock:c0,reset:r0) AxiStream.axi4_wr_auxiliary_gen_without_resp(stream_en:stream_en,id_add_len_in:id_add_len_in,axi_wr_aux:axi_wr_aux) puts_sv Tdl.inst,Tdl.draw end
test_axi_lite_master_empty()
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# File lib/tdl/axi_lite/bak/axi_lite_master_empty_auto.rb, line 55 def self.test_axi_lite_master_empty c0 = Clock.new(name:"axi_lite_master_empty_clk",freqM:148.5) r0 = Reset.new(name:"axi_lite_master_empty_rst_n",active:"low") lite = AxiLite.new(name:"lite",clock:c0,reset:r0) down_stream = lite AxiLite.axi_lite_master_empty(lite:lite) puts_sv Tdl.inst,Tdl.draw end
test_axi_lite_slaver_empty()
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# File lib/tdl/axi_lite/bak/axi_lite_slaver_empty_auto.rb, line 48 def self.test_axi_lite_slaver_empty c0 = Clock.new(name:"axi_lite_slaver_empty_clk",freqM:148.5) r0 = Reset.new(name:"axi_lite_slaver_empty_rst_n",active:"low") lite = AxiLite.new(name:"lite",clock:c0,reset:r0) up_stream = lite AxiLite.axi_lite_slaver_empty(lite:lite) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_auto.rb, line 80 def self.test_axi_stream_cache c0 = Clock.new(name:"axi_stream_cache_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache_35bit()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_35bit_auto.rb, line 80 def self.test_axi_stream_cache_35bit c0 = Clock.new(name:"axi_stream_cache_35bit_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_35bit_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache_35bit(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache_72_95bit_with_keep()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_72_95bit_with_keep_auto.rb, line 80 def self.test_axi_stream_cache_72_95bit_with_keep c0 = Clock.new(name:"axi_stream_cache_72_95bit_with_keep_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_72_95bit_with_keep_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache_72_95bit_with_keep(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache_b1()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_B1_auto.rb, line 80 def self.test_axi_stream_cache_b1 c0 = Clock.new(name:"axi_stream_cache_b1_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_b1_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache_b1(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache_mirror()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_mirror_auto.rb, line 80 def self.test_axi_stream_cache_mirror c0 = Clock.new(name:"axi_stream_cache_mirror_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_mirror_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache_mirror(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_cache_verb()
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# File lib/tdl/axi_stream/bak/axi_stream_cache_verb_auto.rb, line 80 def self.test_axi_stream_cache_verb c0 = Clock.new(name:"axi_stream_cache_verb_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_cache_verb_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_cache_verb(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_interconnect_s2m()
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# File lib/tdl/axi_stream/bak/__axi_stream_interconnect_S2M.rb, line 53 def self.test_axi_stream_interconnect_s2m c0 = Clock.new(name:"axi_stream_interconnect_s2m_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_interconnect_s2m_rst_n",active:"low") num = Parameter.new(name:"num",value:8) addr = Logic.new(name:"addr") s00 = AxiStream.new(name:"s00",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) AxiStream.axi_stream_interconnect_s2m(num:num,addr:addr,s00:s00,m00:m00) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_interconnect_s2m_with_keep()
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# File lib/tdl/axi_stream/bak/axi_stream_interconnect_S2M_with_keep.sv_auto.rb, line 54 def self.test_axi_stream_interconnect_s2m_with_keep c0 = Clock.new(name:"axi_stream_interconnect_s2m_with_keep_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_interconnect_s2m_with_keep_rst_n",active:"low") num = Parameter.new(name:"num",value:8) nsize = Parameter.new(name:"nsize",value:"NUM <= 2? 1 :") addr = Logic.new(name:"addr") s00 = AxiStream.new(name:"s00",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) AxiStream.axi_stream_interconnect_s2m_with_keep(num:num,nsize:nsize,addr:addr,s00:s00,m00:m00) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_long_fifo()
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# File lib/tdl/axi_stream/bak/axi_stream_long_fifo_auto.rb, line 83 def self.test_axi_stream_long_fifo c0 = Clock.new(name:"axi_stream_long_fifo_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_long_fifo_rst_n",active:"low") depth = Parameter.new(name:"depth",value:2) byte_depth = Parameter.new(name:"byte_depth",value:8192*2) axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_long_fifo(depth:depth,byte_depth:byte_depth,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_packet_fifo()
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# File lib/tdl/axi_stream/bak/axi_stream_packet_fifo_auto.rb, line 82 def self.test_axi_stream_packet_fifo c0 = Clock.new(name:"axi_stream_packet_fifo_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_packet_fifo_rst_n",active:"low") depth = Parameter.new(name:"depth",value:2 ) axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_packet_fifo(depth:depth,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_packet_fifo_with_info()
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# File lib/tdl/axi_stream/bak/axi_stream_packet_fifo_with_info_auto.rb, line 85 def self.test_axi_stream_packet_fifo_with_info c0 = Clock.new(name:"axi_stream_packet_fifo_with_info_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_packet_fifo_with_info_rst_n",active:"low") depth = Parameter.new(name:"depth",value:2) esize = Parameter.new(name:"esize",value:8) info_in = Logic.new(name:"info_in") info_out = Logic.new(name:"info_out") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_packet_fifo_with_info(depth:depth,esize:esize,info_in:info_in,info_out:info_out,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_partition()
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# File lib/tdl/axi_stream/bak/axi_stream_partition_auto.rb, line 83 def self.test_axi_stream_partition c0 = Clock.new(name:"axi_stream_partition_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_partition_rst_n",active:"low") valve = Logic.new(name:"valve") partition_len = Logic.new(name:"partition_len") req_new_len = Logic.new(name:"req_new_len") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_partition(valve:valve,partition_len:partition_len,req_new_len:req_new_len,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_stream_partition_a1()
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# File lib/tdl/axi_stream/bak/axi_stream_partition_A1_auto.rb, line 82 def self.test_axi_stream_partition_a1 c0 = Clock.new(name:"axi_stream_partition_a1_clk",freqM:148.5) r0 = Reset.new(name:"axi_stream_partition_a1_rst_n",active:"low") valve = Logic.new(name:"valve") partition_len = Logic.new(name:"partition_len") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axi_stream_partition_a1(valve:valve,partition_len:partition_len,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axi_streams_combin()
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# File lib/tdl/axi_stream/bak/axi_streams_combin_auto.rb, line 90 def self.test_axi_streams_combin c0 = Clock.new(name:"axi_streams_combin_clk",freqM:148.5) r0 = Reset.new(name:"axi_streams_combin_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"BOTH") cut_or_combin_body = Parameter.new(name:"cut_or_combin_body",value:"ON") dsize = Parameter.new(name:"dsize",value:8) new_body_len = Logic.new(name:"new_body_len") trigger_signal = Logic.new(name:"trigger_signal") head_inf = AxiStream.new(name:"head_inf",clock:c0,reset:r0) body_inf = AxiStream.new(name:"body_inf",clock:c0,reset:r0) end_inf = AxiStream.new(name:"end_inf",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) up_stream = body_inf down_stream = m00 AxiStream.axi_streams_combin(mode:mode,cut_or_combin_body:cut_or_combin_body,dsize:dsize,new_body_len:new_body_len,trigger_signal:trigger_signal,head_inf:head_inf,body_inf:body_inf,end_inf:end_inf,m00:m00) puts_sv Tdl.inst,Tdl.draw end
test_axi_streams_interconnect()
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# File lib/tdl/axi_stream/axi_stream_interconnect.rb, line 196 def self.test_axi_streams_interconnect c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") addr = Logic.new(name:'new_body_len') head_inf = AxiStream.new(name:"head_inf",clock:c0,reset:r0) body_inf = AxiStream.new(name:"body_inf",clock:c0,reset:r0) end_inf = AxiStream.new(name:"end_inf",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) m00.m2s_interconnect_addr = addr m00.<< head_inf,body_inf,end_inf puts_sv Tdl.inst,Tdl.draw end
test_axi_streams_s2m()
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# File lib/tdl/axi_stream/bak/axi_stream_S2M.rb, line 48 def self.test_axi_streams_s2m c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") addr = Logic.new(name:'new_body_len') head_inf = AxiStream.new(name:"head_inf",clock:c0,reset:r0) body_inf = AxiStream.new(name:"body_inf",clock:c0,reset:r0) end_inf = AxiStream.new(name:"end_inf",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) m00.axi_stream_s2m(addr, head_inf,body_inf,end_inf) puts_sv Tdl.inst,Tdl.draw end
test_axi_streams_scaler()
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# File lib/tdl/axi_stream/bak/axi_streams_scaler.rb, line 81 def self.test_axi_streams_scaler c0 = Clock.new(name:"axi_streams_scaler_clk",freqM:148.5) r0 = Reset.new(name:"axi_streams_scaler_rst_n",active:"low") Parameter.new(name:"mode",value:"BOTH") Parameter.new(name:"cut_or_combin_body",value:"ON") Parameter.new(name:"dsize",value:8) Logic.new(name:"new_body_len") AxiStream.new(name:"head_inf",clock:c0,reset:r0) AxiStream.new(name:"body_inf",clock:c0,reset:r0) AxiStream.new(name:"end_inf",clock:c0,reset:r0) AxiStream.new(name:"m00",clock:c0,reset:r0) up_stream = body_inf down_stream = m00 AxiStream.axi_streams_scaler(mode:mode,cut_or_combin_body:cut_or_combin_body,dsize:dsize,new_body_len:new_body_len,head_inf:head_inf,body_inf:body_inf,end_inf:end_inf,m00:m00) puts_sv Tdl.inst,Tdl.draw end
test_axis_append()
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# File lib/tdl/axi_stream/bak/axis_append_auto.rb, line 89 def self.test_axis_append c0 = Clock.new(name:"axis_append_clk",freqM:148.5) r0 = Reset.new(name:"axis_append_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"BOTH") dsize = Parameter.new(name:"dsize",value:8) head_field_len = Parameter.new(name:"head_field_len",value:16*8) head_field_name = Parameter.new(name:"head_field_name",value:"HEAD Filed") end_field_len = Parameter.new(name:"end_field_len",value:16*8) end_field_name = Parameter.new(name:"end_field_name",value:"END Filed") head_value = Logic.new(name:"head_value") end_value = Logic.new(name:"end_value") origin_in = AxiStream.new(name:"origin_in",clock:c0,reset:r0) append_out = AxiStream.new(name:"append_out",clock:c0,reset:r0) up_stream = origin_in down_stream = append_out AxiStream.axis_append(mode:mode,dsize:dsize,head_field_len:head_field_len,head_field_name:head_field_name,end_field_len:end_field_len,end_field_name:end_field_name,head_value:head_value,end_value:end_value,origin_in:origin_in,append_out:append_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_append_a1()
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# File lib/tdl/axi_stream/bak/axis_append_A1.rb, line 56 def self.test_axis_append_a1 c0 = Clock.new(name:"axis_append_a1_clk",freqM:148.5) r0 = Reset.new(name:"axis_append_a1_rst_n",active:"low") Parameter.new(name:"mode",value:"BOTH") Parameter.new(name:"dsize",value:8) Parameter.new(name:"head_field_len",value:16*8) Parameter.new(name:"head_field_name",value:"HEAD Filed") Parameter.new(name:"end_field_len",value:16*8) Parameter.new(name:"end_field_name",value:"END Filed") Logic.new(name:"enable") Logic.new(name:"head_value") Logic.new(name:"end_value") AxiStream.new(name:"origin_in",clock:c0,reset:r0) AxiStream.new(name:"append_out",clock:c0,reset:r0) up_stream = origin_in down_stream = append_out AxiStream.axis_append_a1(mode:mode,dsize:dsize,head_field_len:head_field_len,head_field_name:head_field_name,end_field_len:end_field_len,end_field_name:end_field_name,enable:enable,head_value:head_value,end_value:end_value,origin_in:origin_in,append_out:append_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_combin_with_fifo()
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# File lib/tdl/axi_stream/bak/axis_combin_with_fifo_auto.rb, line 88 def self.test_axis_combin_with_fifo c0 = Clock.new(name:"axis_combin_with_fifo_clk",freqM:148.5) r0 = Reset.new(name:"axis_combin_with_fifo_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"BOTH") cut_or_combin_body = Parameter.new(name:"cut_or_combin_body",value:"ON") new_body_len = Logic.new(name:"new_body_len") head_inf = AxiStream.new(name:"head_inf",clock:c0,reset:r0) body_inf = AxiStream.new(name:"body_inf",clock:c0,reset:r0) end_inf = AxiStream.new(name:"end_inf",clock:c0,reset:r0) m00 = AxiStream.new(name:"m00",clock:c0,reset:r0) up_stream = body_inf down_stream = m00 AxiStream.axis_combin_with_fifo(mode:mode,cut_or_combin_body:cut_or_combin_body,new_body_len:new_body_len,head_inf:head_inf,body_inf:body_inf,end_inf:end_inf,m00:m00) puts_sv Tdl.inst,Tdl.draw end
test_axis_connect_pipe()
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# File lib/tdl/axi_stream/bak/axis_connect_pipe_auto.rb, line 80 def self.test_axis_connect_pipe c0 = Clock.new(name:"axis_connect_pipe_clk",freqM:148.5) r0 = Reset.new(name:"axis_connect_pipe_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_connect_pipe(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_connect_pipe_a1()
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# File lib/tdl/axi_stream/bak/axis_connect_pipe_A1.sv_auto.rb, line 80 def self.test_axis_connect_pipe_a1 c0 = Clock.new(name:"axis_connect_pipe_a1_clk",freqM:148.5) r0 = Reset.new(name:"axis_connect_pipe_a1_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_connect_pipe_a1(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_connect_pipe_with_info()
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# File lib/tdl/axi_stream/bak/axis_connect_pipe_with_info_auto.rb, line 84 def self.test_axis_connect_pipe_with_info c0 = Clock.new(name:"axis_connect_pipe_with_info_clk",freqM:148.5) r0 = Reset.new(name:"axis_connect_pipe_with_info_rst_n",active:"low") ifsize = Parameter.new(name:"ifsize",value:32) info_in = Logic.new(name:"info_in") info_out = Logic.new(name:"info_out") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_connect_pipe_with_info(ifsize:ifsize,info_in:info_in,info_out:info_out,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_direct()
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# File lib/tdl/axi_stream/bak/axis_direct_auto.rb, line 80 def self.test_axis_direct c0 = Clock.new(name:"axis_direct_clk",freqM:148.5) r0 = Reset.new(name:"axis_direct_rst_n",active:"low") slaver = AxiStream.new(name:"slaver",clock:c0,reset:r0) master = AxiStream.new(name:"master",clock:c0,reset:r0) up_stream = slaver down_stream = master AxiStream.axis_direct(slaver:slaver,master:master) puts_sv Tdl.inst,Tdl.draw end
test_axis_filter()
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# File lib/tdl/axi_stream/bak/axis_filter_auto.rb, line 81 def self.test_axis_filter c0 = Clock.new(name:"axis_filter_clk",freqM:148.5) r0 = Reset.new(name:"axis_filter_rst_n",active:"low") button = Logic.new(name:"button") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_filter(button:button,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_length_fill()
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# File lib/tdl/axi_stream/bak/axis_length_fill_auto.rb, line 81 def self.test_axis_length_fill c0 = Clock.new(name:"axis_length_fill_clk",freqM:148.5) r0 = Reset.new(name:"axis_length_fill_rst_n",active:"low") length = Logic.new(name:"length") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_length_fill(length:length,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_length_split()
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# File lib/tdl/axi_stream/bak/axis_length_split_auto.rb, line 81 def self.test_axis_length_split c0 = Clock.new(name:"axis_length_split_clk",freqM:148.5) r0 = Reset.new(name:"axis_length_split_rst_n",active:"low") length = Logic.new(name:"length") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_length_split(length:length,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_length_split_with_addr()
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# File lib/tdl/axi_stream/bak/axis_length_split_with_addr_auto.rb, line 85 def self.test_axis_length_split_with_addr c0 = Clock.new(name:"axis_length_split_with_addr_clk",freqM:148.5) r0 = Reset.new(name:"axis_length_split_with_addr_rst_n",active:"low") addr_step = Parameter.new(name:"addr_step",value:1024 ) origin_addr = Logic.new(name:"origin_addr") length = Logic.new(name:"length") band_addr = Logic.new(name:"band_addr") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_length_split_with_addr(addr_step:addr_step,origin_addr:origin_addr,length:length,band_addr:band_addr,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_master_empty()
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# File lib/tdl/axi_stream/bak/axis_master_empty_auto.rb, line 55 def self.test_axis_master_empty c0 = Clock.new(name:"axis_master_empty_clk",freqM:148.5) r0 = Reset.new(name:"axis_master_empty_rst_n",active:"low") master = AxiStream.new(name:"master",clock:c0,reset:r0) down_stream = master AxiStream.axis_master_empty(master:master) puts_sv Tdl.inst,Tdl.draw end
test_axis_mirrors()
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# File lib/tdl/axi_stream/bak/_axis_mirrors.rb, line 93 def self.test_axis_mirrors c0 = Clock.new(name:"axis_mirrors_clk",freqM:148.5) r0 = Reset.new(name:"axis_mirrors_rst_n",active:"low") Parameter.new(name:"h",value:0) Parameter.new(name:"l",value:0) Parameter.new(name:"num",value:8) Parameter.new(name:"mode",value:"CDS_MODE") Logic.new(name:"condition_data") AxiStream.new(name:"axis_in",clock:c0,reset:r0) AxiStream.new(name:"axis_mirror",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_mirror AxiStream.axis_mirrors(h:h,l:l,num:num,mode:mode,condition_data:condition_data,axis_in:axis_in,axis_mirror:axis_mirror) puts_sv Tdl.inst,Tdl.draw end
test_axis_pkt_fifo_filter_keep()
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# File lib/tdl/axi_stream/bak/axis_pkt_fifo_filter_keep_auto.rb, line 82 def self.test_axis_pkt_fifo_filter_keep c0 = Clock.new(name:"axis_pkt_fifo_filter_keep_clk",freqM:148.5) r0 = Reset.new(name:"axis_pkt_fifo_filter_keep_rst_n",active:"low") depth = Parameter.new(name:"depth",value:2 ) axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_pkt_fifo_filter_keep(depth:depth,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_ram_buffer()
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# File lib/tdl/axi_stream/bak/axis_ram_buffer_auto.rb, line 85 def self.test_axis_ram_buffer c0 = Clock.new(name:"axis_ram_buffer_clk",freqM:148.5) r0 = Reset.new(name:"axis_ram_buffer_rst_n",active:"low") length = Parameter.new(name:"length",value:4096) wr_en = Logic.new(name:"wr_en") gen_en = Logic.new(name:"gen_en") gen_ready = Logic.new(name:"gen_ready") axis_wr_inf = AxiStream.new(name:"axis_wr_inf",clock:c0,reset:r0) axis_data_inf = AxiStream.new(name:"axis_data_inf",clock:c0,reset:r0) up_stream = axis_wr_inf down_stream = axis_data_inf AxiStream.axis_ram_buffer(length:length,wr_en:wr_en,gen_en:gen_en,gen_ready:gen_ready,axis_wr_inf:axis_wr_inf,axis_data_inf:axis_data_inf) puts_sv Tdl.inst,Tdl.draw end
test_axis_slaver_empty()
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# File lib/tdl/axi_stream/bak/axis_slaver_empty_auto.rb, line 48 def self.test_axis_slaver_empty c0 = Clock.new(name:"axis_slaver_empty_clk",freqM:148.5) r0 = Reset.new(name:"axis_slaver_empty_rst_n",active:"low") slaver = AxiStream.new(name:"slaver",clock:c0,reset:r0) up_stream = slaver AxiStream.axis_slaver_empty(slaver:slaver) puts_sv Tdl.inst,Tdl.draw end
test_axis_slaver_pipe()
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# File lib/tdl/axi_stream/bak/axis_slaver_pipe_auto.rb, line 80 def self.test_axis_slaver_pipe c0 = Clock.new(name:"axis_slaver_pipe_clk",freqM:148.5) r0 = Reset.new(name:"axis_slaver_pipe_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_slaver_pipe(axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_slaver_pipe_a1()
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# File lib/tdl/axi_stream/bak/axis_slaver_pipe_A1_auto.rb, line 82 def self.test_axis_slaver_pipe_a1 c0 = Clock.new(name:"axis_slaver_pipe_a1_clk",freqM:148.5) r0 = Reset.new(name:"axis_slaver_pipe_a1_rst_n",active:"low") depth = Parameter.new(name:"depth",value:1) axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_slaver_pipe_a1(depth:depth,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_to_axi4_wr()
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# File lib/tdl/axi4/bak/axis_to_axi4_wr_auto.rb, line 80 def self.test_axis_to_axi4_wr c0 = Clock.new(name:"axis_to_axi4_wr_clk",freqM:148.5) r0 = Reset.new(name:"axis_to_axi4_wr_rst_n",active:"low") addr = Logic.new(name:"addr") max_length = Logic.new(name:"max_length") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axi_wr = Axi4.new(name:"axi_wr",clock:c0,reset:r0) AxiStream.axis_to_axi4_wr( addr:addr, max_length:max_length, axis_in:axis_in, axi_wr:axi_wr) puts_sv Tdl.inst,Tdl.draw end
test_axis_to_data_inf()
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# File lib/tdl/axi_stream/bak/axis_to_data_inf_auto.rb, line 50 def self.test_axis_to_data_inf c0 = Clock.new(name:"axis_to_data_inf_clk",freqM:148.5) r0 = Reset.new(name:"axis_to_data_inf_rst_n",active:"low") data_out_inf = DataInf_C.new(name:"data_out_inf",clock:c0,reset:r0) axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) AxiStream.axis_to_data_inf(data_out_inf:data_out_inf,axis_in:axis_in) puts_sv Tdl.inst,Tdl.draw end
test_axis_uncompress()
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# File lib/tdl/axi_stream/bak/axis_uncompress_auto.rb, line 53 def self.test_axis_uncompress c0 = Clock.new(name:"axis_uncompress_clk",freqM:148.5) r0 = Reset.new(name:"axis_uncompress_rst_n",active:"low") asize = Parameter.new(name:"asize",value:8) lsize = Parameter.new(name:"lsize",value:8) axis_zip = AxiStream.new(name:"axis_zip",clock:c0,reset:r0) axis_unzip = AxiStream.new(name:"axis_unzip",clock:c0,reset:r0) AxiStream.axis_uncompress(asize:asize,lsize:lsize,axis_zip:axis_zip,axis_unzip:axis_unzip) puts_sv Tdl.inst,Tdl.draw end
test_axis_valve()
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# File lib/tdl/axi_stream/bak/axis_valve_auto.rb, line 81 def self.test_axis_valve c0 = Clock.new(name:"axis_valve_clk",freqM:148.5) r0 = Reset.new(name:"axis_valve_rst_n",active:"low") button = Logic.new(name:"button") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_valve(button:button,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_valve_with_pipe()
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# File lib/tdl/axi_stream/bak/axis_valve_with_pipe_auto.rb, line 81 def self.test_axis_valve_with_pipe c0 = Clock.new(name:"axis_valve_with_pipe_clk",freqM:148.5) r0 = Reset.new(name:"axis_valve_with_pipe_rst_n",active:"low") button = Logic.new(name:"button") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) up_stream = axis_in down_stream = axis_out AxiStream.axis_valve_with_pipe(button:button,axis_in:axis_in,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_axis_width_combin()
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# File lib/tdl/axi_stream/bak/axis_width_combin_auto.rb, line 80 def self.test_axis_width_combin c0 = Clock.new(name:"axis_width_combin_clk",freqM:148.5) r0 = Reset.new(name:"axis_width_combin_rst_n",active:"low") slim_axis = AxiStream.new(name:"slim_axis",clock:c0,reset:r0) wide_axis = AxiStream.new(name:"wide_axis",clock:c0,reset:r0) up_stream = slim_axis down_stream = wide_axis AxiStream.axis_width_combin(slim_axis:slim_axis,wide_axis:wide_axis) puts_sv Tdl.inst,Tdl.draw end
test_axis_width_convert()
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# File lib/tdl/axi_stream/bak/axis_width_convert_auto.rb, line 80 def self.test_axis_width_convert c0 = Clock.new(name:"axis_width_convert_clk",freqM:148.5) r0 = Reset.new(name:"axis_width_convert_rst_n",active:"low") in_axis = AxiStream.new(name:"in_axis",clock:c0,reset:r0) out_axis = AxiStream.new(name:"out_axis",clock:c0,reset:r0) up_stream = in_axis down_stream = out_axis AxiStream.axis_width_convert(in_axis:in_axis,out_axis:out_axis) puts_sv Tdl.inst,Tdl.draw end
test_axis_width_destruct()
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# File lib/tdl/axi_stream/bak/axis_width_destruct_auto.rb, line 80 def self.test_axis_width_destruct c0 = Clock.new(name:"axis_width_destruct_clk",freqM:148.5) r0 = Reset.new(name:"axis_width_destruct_rst_n",active:"low") wide_axis = AxiStream.new(name:"wide_axis",clock:c0,reset:r0) slim_axis = AxiStream.new(name:"slim_axis",clock:c0,reset:r0) up_stream = wide_axis down_stream = slim_axis AxiStream.axis_width_destruct(wide_axis:wide_axis,slim_axis:slim_axis) puts_sv Tdl.inst,Tdl.draw end
test_axis_wrapper_oled()
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# File lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb, line 51 def self.test_axis_wrapper_oled c0 = Clock.new(name:"axis_wrapper_oled_clk",freqM:148.5) r0 = Reset.new(name:"axis_wrapper_oled_rst_n",active:"low") Logic.new(name:"oled_sdin") Logic.new(name:"oled_sclk") Logic.new(name:"oled_dc") Logic.new(name:"oled_res") Logic.new(name:"oled_vbat") Logic.new(name:"oled_vdd") Logic.new(name:"trigger_toggle") AxiLite.new(name:"lite_ctrl_inf",clock:c0,reset:r0) AxiStream.new(name:"ctrl_inf",clock:c0,reset:r0) AxiLite.axis_wrapper_oled(oled_sdin:oled_sdin,oled_sclk:oled_sclk,oled_dc:oled_dc,oled_res:oled_res,oled_vbat:oled_vbat,oled_vdd:oled_vdd,trigger_toggle:trigger_toggle,lite_ctrl_inf:lite_ctrl_inf,ctrl_inf:ctrl_inf) puts_sv Tdl.inst,Tdl.draw end
test_check_stream_crc()
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# File lib/tdl/axi_stream/bak/check_stream_crc_auto.rb, line 48 def self.test_check_stream_crc c0 = Clock.new(name:"check_stream_crc_clk",freqM:148.5) r0 = Reset.new(name:"check_stream_crc_rst_n",active:"low") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) AxiStream.check_stream_crc(axis_in:axis_in) puts_sv Tdl.inst,Tdl.draw end
test_common_fifo()
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# File lib/tdl/data_inf/bak/common_fifo_auto.rb, line 59 def self.test_common_fifo c0 = Clock.new(name:"common_fifo_clk",freqM:148.5) r0 = Reset.new(name:"common_fifo_rst_n",active:"low") depth = Parameter.new(name:"depth",value:4) dsize = Parameter.new(name:"dsize",value:8) clock = Logic.new(name:"clock") rst_n = Logic.new(name:"rst_n") wdata = Logic.new(name:"wdata") wr_en = Logic.new(name:"wr_en") rdata = Logic.new(name:"rdata") rd_en = Logic.new(name:"rd_en") count = Logic.new(name:"count") empty = Logic.new(name:"empty") full = Logic.new(name:"full") DataInf.common_fifo(depth:depth,dsize:dsize,clock:clock,rst_n:rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,count:count,empty:empty,full:full) puts_sv Tdl.inst,Tdl.draw end
test_data_bind()
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# File lib/tdl/data_inf/bak/data_bind_auto.rb, line 52 def self.test_data_bind c0 = Clock.new(name:"data_bind_clk",freqM:148.5) r0 = Reset.new(name:"data_bind_rst_n",active:"low") num = Parameter.new(name:"num",value:2) data_in = DataInf_C.new(name:"data_in",clock:c0,reset:r0) data_out = DataInf_C.new(name:"data_out",clock:c0,reset:r0) DataInf_C.data_bind(num:num,data_in:data_in,data_out:data_out) puts_sv Tdl.inst,Tdl.draw end
test_data_c_direct()
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# File lib/tdl/data_inf/bak/data_c_direct_auto.rb, line 80 def self.test_data_c_direct c0 = Clock.new(name:"data_c_direct_clk",freqM:148.5) r0 = Reset.new(name:"data_c_direct_rst_n",active:"low") slaver = DataInf_C.new(name:"slaver",clock:c0,reset:r0) master = DataInf_C.new(name:"master",clock:c0,reset:r0) up_stream = slaver down_stream = master DataInf_C.data_c_direct(slaver:slaver,master:master) puts_sv Tdl.inst,Tdl.draw end
test_data_c_direct_mirror()
click to toggle source
# File lib/tdl/data_inf/bak/data_c_direct_mirror_auto.rb, line 80 def self.test_data_c_direct_mirror c0 = Clock.new(name:"data_c_direct_mirror_clk",freqM:148.5) r0 = Reset.new(name:"data_c_direct_mirror_rst_n",active:"low") slaver = DataInf_C.new(name:"slaver",clock:c0,reset:r0) master = DataInf_C.new(name:"master",clock:c0,reset:r0) up_stream = slaver down_stream = master DataInf_C.data_c_direct_mirror(slaver:slaver,master:master) puts_sv Tdl.inst,Tdl.draw end
test_data_c_tmp_cache()
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# File lib/tdl/data_inf/bak/data_c_tmp_cache_auto.rb, line 80 def self.test_data_c_tmp_cache c0 = Clock.new(name:"data_c_tmp_cache_clk",freqM:148.5) r0 = Reset.new(name:"data_c_tmp_cache_rst_n",active:"low") slaver = DataInf_C.new(name:"slaver",clock:c0,reset:r0) master = DataInf_C.new(name:"master",clock:c0,reset:r0) up_stream = slaver down_stream = master DataInf_C.data_c_tmp_cache(slaver:slaver,master:master) puts_sv Tdl.inst,Tdl.draw end
test_data_condition_mirror()
click to toggle source
# File lib/tdl/data_inf/bak/data_condition_mirror_auto.rb, line 86 def self.test_data_condition_mirror c0 = Clock.new(name:"data_condition_mirror_clk",freqM:148.5) r0 = Reset.new(name:"data_condition_mirror_rst_n",active:"low") h = Parameter.new(name:"h",value:0) l = Parameter.new(name:"l",value:0) condition_data = Logic.new(name:"condition_data") data_in = DataInf_C.new(name:"data_in",clock:c0,reset:r0) data_out = DataInf_C.new(name:"data_out",clock:c0,reset:r0) data_mirror = DataInf_C.new(name:"data_mirror",clock:c0,reset:r0) up_stream = data_in down_stream = data_out DataInf_C.data_condition_mirror(h:h,l:l,condition_data:condition_data,data_in:data_in,data_out:data_out,data_mirror:data_mirror) puts_sv Tdl.inst,Tdl.draw end
test_data_condition_valve()
click to toggle source
# File lib/tdl/data_inf/bak/data_condition_valve_auto.rb, line 85 def self.test_data_condition_valve c0 = Clock.new(name:"data_condition_valve_clk",freqM:148.5) r0 = Reset.new(name:"data_condition_valve_rst_n",active:"low") h = Parameter.new(name:"h",value:0) l = Parameter.new(name:"l",value:0) condition_button = Logic.new(name:"condition_button") condition_data = Logic.new(name:"condition_data") data_in = DataInf_C.new(name:"data_in",clock:c0,reset:r0) data_out = DataInf_C.new(name:"data_out",clock:c0,reset:r0) up_stream = data_in down_stream = data_out DataInf_C.data_condition_valve(h:h,l:l,condition_button:condition_button,condition_data:condition_data,data_in:data_in,data_out:data_out) puts_sv Tdl.inst,Tdl.draw end
test_data_connect_pipe()
click to toggle source
# File lib/tdl/data_inf/bak/data_connect_pipe.rb, line 70 def self.test_data_connect_pipe c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") d0 = DataInf.new(name:"D0",dsize:8) d1 = DataInf.new(name:"D1",dsize:8) d0.data_connect_pipe(up_stream:d1,clock:c0,reset:r0) puts_sv DataInf.inst,DataInf_C.inst,DataInf.draw,DataInf_C.draw end
test_data_connect_pipe_inf()
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# File lib/tdl/data_inf/bak/data_connect_pipe_inf_auto.rb, line 80 def self.test_data_connect_pipe_inf c0 = Clock.new(name:"data_connect_pipe_inf_clk",freqM:148.5) r0 = Reset.new(name:"data_connect_pipe_inf_rst_n",active:"low") indata = DataInf_C.new(name:"indata",clock:c0,reset:r0) outdata = DataInf_C.new(name:"outdata",clock:c0,reset:r0) up_stream = indata down_stream = outdata DataInf_C.data_connect_pipe_inf(indata:indata,outdata:outdata) puts_sv Tdl.inst,Tdl.draw end
test_data_inf_c_pipe_condition()
click to toggle source
# File lib/tdl/data_inf/bak/data_inf_c_pipe_condition_auto.rb, line 81 def self.test_data_inf_c_pipe_condition c0 = Clock.new(name:"data_inf_c_pipe_condition_clk",freqM:148.5) r0 = Reset.new(name:"data_inf_c_pipe_condition_rst_n",active:"low") and_condition = Logic.new(name:"and_condition") indata = DataInf_C.new(name:"indata",clock:c0,reset:r0) outdata = DataInf_C.new(name:"outdata",clock:c0,reset:r0) up_stream = indata down_stream = outdata DataInf_C.data_inf_c_pipe_condition(and_condition:and_condition,indata:indata,outdata:outdata) puts_sv Tdl.inst,Tdl.draw end
test_data_inf_cross_clk()
click to toggle source
# File lib/tdl/data_inf/bak/data_inf_cross_clk.rb, line 48 def self.test_data_inf_cross_clk c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") d0 = DataInf.new(name:"D0",dsize:8) d1 = DataInf.new(name:"D1",dsize:8) d0.data_inf_cross_clk(up_stream:d1,clock:c0,reset:r0) puts_sv DataInf.inst,DataInf_C.inst,DataInf.draw,DataInf_C.draw end
test_data_inf_interconnect()
click to toggle source
# File lib/tdl/data_inf/bak/data_inf_c_interconnect.rb, line 70 def self.test_data_inf_interconnect c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") d0 = DataInf.new(name:"D0",dsize:8) d1 = DataInf_C.new(name:"D1",dsize:8,clock:c0,reset:r0) d2 = DataInf.new(name:"D2",dsize:8) d1.<< d0,d2 puts_sv DataInf.inst,DataInf_C.inst,DataInf.draw,DataInf_C.draw end
test_data_inf_planer()
click to toggle source
# File lib/tdl/data_inf/bak/data_inf_planer.rb, line 62 def self.test_data_inf_planer c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") trigger = Logic.new(name:'trigger',dsize:9) d0 = DataInf_C.new(name:"D0",dsize:8,clock:c0,reset:r0) d1 = DataInf_C.new(name:"D1",dsize:8,clock:c0,reset:r0) # d0 = DataInf.new(name:"D0",dsize:8) # d1 = DataInf.new(name:"D1",dsize:8) d0.data_inf_planer(up_stream:d1,pack_data:trigger) # d0.data_inf_planer(up_stream:d1,pack_data:trigger,clock:c0,reset:r0) puts_sv DataInf.inst,DataInf_C.inst,DataInf.draw,DataInf_C.draw end
test_data_inf_ticktack()
click to toggle source
# File lib/tdl/data_inf/bak/data_inf_ticktack.rb, line 64 def self.test_data_inf_ticktack c0 = Clock.new(name:"clk",freqM:148.5) r0 = Reset.new(name:"rst_n",active:"low") trigger = Logic.new(name:'trigger',dsize:9) d0 = DataInf_C.new(name:"D0",dsize:8,clock:c0,reset:r0) d1 = DataInf_C.new(name:"D1",dsize:8,clock:c0,reset:r0) # d0 = DataInf.new(name:"D0",dsize:8) # d1 = DataInf.new(name:"D1",dsize:8) d0.data_inf_ticktack(down_stream:d1,index_data:trigger,compare_data:trigger) # d0.data_inf_planer(up_stream:d1,pack_data:trigger,clock:c0,reset:r0) puts_sv DataInf.inst,DataInf_C.inst,DataInf.draw,DataInf_C.draw end
test_data_mirrors()
click to toggle source
# File lib/tdl/data_inf/bak/_data_mirrors.rb, line 96 def self.test_data_mirrors c0 = Clock.new(name:"data_mirrors_clk",freqM:148.5) r0 = Reset.new(name:"data_mirrors_rst_n",active:"low") Parameter.new(name:"h",value:0) Parameter.new(name:"l",value:0) Parameter.new(name:"num",value:8) Parameter.new(name:"mode",value:"CDS_MODE") Logic.new(name:"condition_data") DataInf_C.new(name:"data_in",clock:c0,reset:r0) DataInf_C.new(name:"data_mirror",clock:c0,reset:r0) up_stream = data_in down_stream = data_mirror DataInf_C.data_mirrors(h:h,l:l,num:num,mode:mode,condition_data:condition_data,data_in:data_in,data_mirror:data_mirror) puts_sv Tdl.inst,Tdl.draw end
test_data_mirrors_verb()
click to toggle source
# File lib/tdl/data_inf/bak/data_mirrors_verb.sv_auto.rb, line 86 def self.test_data_mirrors_verb c0 = Clock.new(name:"data_mirrors_verb_clk",freqM:148.5) r0 = Reset.new(name:"data_mirrors_verb_rst_n",active:"low") h = Parameter.new(name:"h",value:0) l = Parameter.new(name:"l",value:0) num = Parameter.new(name:"num",value:8) mode = Parameter.new(name:"mode",value:"CDS_MODE") condition_data = Logic.new(name:"condition_data") data_in = DataInf_C.new(name:"data_in",clock:c0,reset:r0) data_mirror = DataInf_C.new(name:"data_mirror",clock:c0,reset:r0) up_stream = data_in down_stream = data_mirror DataInf_C.data_mirrors_verb(h:h,l:l,num:num,mode:mode,condition_data:condition_data,data_in:data_in,data_mirror:data_mirror) puts_sv Tdl.inst,Tdl.draw end
test_data_to_axis_inf()
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# File lib/tdl/axi_stream/bak/data_to_axis_inf_auto.rb, line 52 def self.test_data_to_axis_inf c0 = Clock.new(name:"data_to_axis_inf_clk",freqM:148.5) r0 = Reset.new(name:"data_to_axis_inf_rst_n",active:"low") mark_curr_data = Logic.new(name:"mark_curr_data") last_flag = Logic.new(name:"last_flag") data_slaver = DataInf_C.new(name:"data_slaver",clock:c0,reset:r0) axis_master = AxiStream.new(name:"axis_master",clock:c0,reset:r0) AxiStream.data_to_axis_inf(mark_curr_data:mark_curr_data,last_flag:last_flag,data_slaver:data_slaver,axis_master:axis_master) puts_sv Tdl.inst,Tdl.draw end
test_data_to_axis_inf_a1()
click to toggle source
# File lib/tdl/axi_stream/bak/data_to_axis_inf_A1.rb, line 40 def self.test_data_to_axis_inf_a1 c0 = Clock.new(name:"data_to_axis_inf_a1_clk",freqM:148.5) r0 = Reset.new(name:"data_to_axis_inf_a1_rst_n",active:"low") Logic.new(name:"last_flag") DataInf_C.new(name:"data_slaver",clock:c0,reset:r0) AxiStream.new(name:"axis_master",clock:c0,reset:r0) AxiStream.data_to_axis_inf_a1(last_flag:last_flag,data_slaver:data_slaver,axis_master:axis_master) puts_sv Tdl.inst,Tdl.draw end
test_data_uncompress()
click to toggle source
# File lib/tdl/data_inf/bak/data_uncompress_auto.rb, line 83 def self.test_data_uncompress c0 = Clock.new(name:"data_uncompress_clk",freqM:148.5) r0 = Reset.new(name:"data_uncompress_rst_n",active:"low") asize = Parameter.new(name:"asize",value:8) lsize = Parameter.new(name:"lsize",value:8) data_zip = DataInf_C.new(name:"data_zip",clock:c0,reset:r0) data_unzip = DataInf_C.new(name:"data_unzip",clock:c0,reset:r0) up_stream = data_zip down_stream = data_unzip DataInf_C.data_uncompress(asize:asize,lsize:lsize,data_zip:data_zip,data_unzip:data_unzip) puts_sv Tdl.inst,Tdl.draw end
test_data_valve()
click to toggle source
# File lib/tdl/data_inf/bak/data_valve_auto.rb, line 51 def self.test_data_valve c0 = Clock.new(name:"data_valve_clk",freqM:148.5) r0 = Reset.new(name:"data_valve_rst_n",active:"low") button = Logic.new(name:"button") data_in = DataInf_C.new(name:"data_in",clock:c0,reset:r0) data_out = DataInf_C.new(name:"data_out",clock:c0,reset:r0) DataInf_C.data_valve(button:button,data_in:data_in,data_out:data_out) puts_sv Tdl.inst,Tdl.draw end
test_datainf_c_master_empty()
click to toggle source
# File lib/tdl/axi_stream/bak/datainf_c_master_empty_auto.rb, line 50 def self.test_datainf_c_master_empty c0 = Clock.new(name:"datainf_c_master_empty_clk",freqM:148.5) r0 = Reset.new(name:"datainf_c_master_empty_rst_n",active:"low") DataInf_C.new(name:"master",clock:c0,reset:r0) down_stream = master DataInf_C.datainf_c_master_empty(master:master) puts_sv Tdl.inst,Tdl.draw end
test_datainf_c_slaver_empty()
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# File lib/tdl/axi_stream/bak/datainf_c_slaver_empty_auto.rb, line 43 def self.test_datainf_c_slaver_empty c0 = Clock.new(name:"datainf_c_slaver_empty_clk",freqM:148.5) r0 = Reset.new(name:"datainf_c_slaver_empty_rst_n",active:"low") DataInf_C.new(name:"slaver",clock:c0,reset:r0) up_stream = slaver DataInf_C.datainf_c_slaver_empty(slaver:slaver) puts_sv Tdl.inst,Tdl.draw end
test_datainf_master_empty()
click to toggle source
# File lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb, line 50 def self.test_datainf_master_empty c0 = Clock.new(name:"datainf_master_empty_clk",freqM:148.5) r0 = Reset.new(name:"datainf_master_empty_rst_n",active:"low") DataInf.new(name:"master",clock:c0,reset:r0) down_stream = master DataInf.datainf_master_empty(master:master) puts_sv Tdl.inst,Tdl.draw end
test_datainf_slaver_empty()
click to toggle source
# File lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb, line 43 def self.test_datainf_slaver_empty c0 = Clock.new(name:"datainf_slaver_empty_clk",freqM:148.5) r0 = Reset.new(name:"datainf_slaver_empty_rst_n",active:"low") DataInf.new(name:"slaver",clock:c0,reset:r0) up_stream = slaver DataInf.datainf_slaver_empty(slaver:slaver) puts_sv Tdl.inst,Tdl.draw end
test_dynamic_port_cfg()
click to toggle source
# File lib/tdl/axi_stream/bak/dynamic_port_cfg_auto.rb, line 49 def self.test_dynamic_port_cfg c0 = Clock.new(name:"dynamic_port_cfg_clk",freqM:148.5) r0 = Reset.new(name:"dynamic_port_cfg_rst_n",active:"low") Logic.new(name:"udp_port") Logic.new(name:"port_index") Logic.new(name:"valid") AxiStream.new(name:"tap_ex_udp_ctrl_inf",clock:c0,reset:r0) AxiStream.new(name:"tap_local_udp_ctrl_inf",clock:c0,reset:r0) AxiStream.new(name:"tap_broadcast_udp_inf",clock:c0,reset:r0) AxiStream.new(name:"send_inf",clock:c0,reset:r0) AxiStream.dynamic_port_cfg(udp_port:udp_port,port_index:port_index,valid:valid,tap_ex_udp_ctrl_inf:tap_ex_udp_ctrl_inf,tap_local_udp_ctrl_inf:tap_local_udp_ctrl_inf,tap_broadcast_udp_inf:tap_broadcast_udp_inf,send_inf:send_inf) puts_sv Tdl.inst,Tdl.draw end
test_dynnamic_addr_cfg()
click to toggle source
# File lib/tdl/axi_stream/bak/dynnamic_addr_cfg_auto.rb, line 47 def self.test_dynnamic_addr_cfg c0 = Clock.new(name:"dynnamic_addr_cfg_clk",freqM:148.5) r0 = Reset.new(name:"dynnamic_addr_cfg_rst_n",active:"low") Logic.new(name:"server_ip") Logic.new(name:"server_mac") AxiStream.new(name:"tap_local_udp_ctrl_inf",clock:c0,reset:r0) AxiStream.new(name:"tap_broadcast_udp_inf",clock:c0,reset:r0) AxiStream.new(name:"send_inf",clock:c0,reset:r0) AxiStream.dynnamic_addr_cfg(server_ip:server_ip,server_mac:server_mac,tap_local_udp_ctrl_inf:tap_local_udp_ctrl_inf,tap_broadcast_udp_inf:tap_broadcast_udp_inf,send_inf:send_inf) puts_sv Tdl.inst,Tdl.draw end
test_gen_big_field_table()
click to toggle source
# File lib/tdl/axi_stream/bak/gen_big_field_table_auto.rb, line 62 def self.test_gen_big_field_table c0 = Clock.new(name:"gen_big_field_table_clk",freqM:148.5) r0 = Reset.new(name:"gen_big_field_table_rst_n",active:"low") master_mode = Parameter.new(name:"master_mode",value:"OFF") dsize = Parameter.new(name:"dsize",value:8) field_len = Parameter.new(name:"field_len",value:16*8) field_name = Parameter.new(name:"field_name",value:"Big Filed") enable = Logic.new(name:"enable") value = Logic.new(name:"value") cm_tb = AxiStream.new(name:"cm_tb",clock:c0,reset:r0) down_stream = cm_tb AxiStream.gen_big_field_table(master_mode:master_mode,dsize:dsize,field_len:field_len,field_name:field_name,enable:enable,value:value,cm_tb:cm_tb) puts_sv Tdl.inst,Tdl.draw end
test_gen_origin_axis()
click to toggle source
# File lib/tdl/axi_stream/bak/gen_origin_axis_auto.rb, line 60 def self.test_gen_origin_axis c0 = Clock.new(name:"gen_origin_axis_clk",freqM:148.5) r0 = Reset.new(name:"gen_origin_axis_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"RANGE") enable = Logic.new(name:"enable") ready = Logic.new(name:"ready") length = Logic.new(name:"length") axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) down_stream = axis_out AxiStream.gen_origin_axis(mode:mode,enable:enable,ready:ready,length:length,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_gen_simple_axis()
click to toggle source
# File lib/tdl/axi_stream/bak/gen_simple_axis_auto.rb, line 61 def self.test_gen_simple_axis c0 = Clock.new(name:"gen_simple_axis_clk",freqM:148.5) r0 = Reset.new(name:"gen_simple_axis_rst_n",active:"low") mode = Parameter.new(name:"mode",value:"RANGE") trigger = Logic.new(name:"trigger") gen_en = Logic.new(name:"gen_en") length = Logic.new(name:"length") led = Logic.new(name:"led") axis_out = AxiStream.new(name:"axis_out",clock:c0,reset:r0) down_stream = axis_out AxiStream.gen_simple_axis(mode:mode,trigger:trigger,gen_en:gen_en,length:length,led:led,axis_out:axis_out) puts_sv Tdl.inst,Tdl.draw end
test_idata_pool_axi4()
click to toggle source
# File lib/tdl/axi4/bak/idata_pool_axi4_auto.rb, line 165 def self.test_idata_pool_axi4 c0 = Clock.new(name:"idata_pool_axi4_clk",freqM:148.5) r0 = Reset.new(name:"idata_pool_axi4_rst_n",active:"low") dsize = Parameter.new(name:"dsize",value:8) source_addr = Logic.new(name:"source_addr") size = Logic.new(name:"size") valid = Logic.new(name:"valid") ready = Logic.new(name:"ready") last_drop = Logic.new(name:"last_drop") data = Logic.new(name:"data") empty = Logic.new(name:"empty") wr_en = Logic.new(name:"wr_en") sewage_valve = Logic.new(name:"sewage_valve") axi_master = Axi4.new(name:"axi_master",clock:c0,reset:r0) down_stream = axi_master Axi4.idata_pool_axi4( dsize:dsize, source_addr:source_addr, size:size, valid:valid, ready:ready, last_drop:last_drop, data:data, empty:empty, wr_en:wr_en, sewage_valve:sewage_valve, axi_master:axi_master) puts_sv Tdl.inst,Tdl.draw end
test_independent_clock_fifo()
click to toggle source
# File lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb, line 60 def self.test_independent_clock_fifo c0 = Clock.new(name:"independent_clock_fifo_clk",freqM:148.5) r0 = Reset.new(name:"independent_clock_fifo_rst_n",active:"low") depth = Parameter.new(name:"depth",value:4) dsize = Parameter.new(name:"dsize",value:8) wr_clk = Logic.new(name:"wr_clk") wr_rst_n = Logic.new(name:"wr_rst_n") rd_clk = Logic.new(name:"rd_clk") rd_rst_n = Logic.new(name:"rd_rst_n") wdata = Logic.new(name:"wdata") wr_en = Logic.new(name:"wr_en") rdata = Logic.new(name:"rdata") rd_en = Logic.new(name:"rd_en") empty = Logic.new(name:"empty") full = Logic.new(name:"full") DataInf.independent_clock_fifo(depth:depth,dsize:dsize,wr_clk:wr_clk,wr_rst_n:wr_rst_n,rd_clk:rd_clk,rd_rst_n:rd_rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,empty:empty,full:full) puts_sv Tdl.inst,Tdl.draw end
test_jtag_to_axilite_wrapper()
click to toggle source
# File lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb, line 67 def self.test_jtag_to_axilite_wrapper c0 = Clock.new(name:"jtag_to_axilite_wrapper_clk",freqM:148.5) r0 = Reset.new(name:"jtag_to_axilite_wrapper_rst_n",active:"low") lite = AxiLite.new(name:"lite",clock:c0,reset:r0) AxiLite.jtag_to_axilite_wrapper( lite:lite) puts_sv Tdl.inst,Tdl.draw end
test_odata_pool_axi4()
click to toggle source
# File lib/tdl/axi4/bak/odata_pool_axi4_auto.rb, line 136 def self.test_odata_pool_axi4 c0 = Clock.new(name:"odata_pool_axi4_clk",freqM:148.5) r0 = Reset.new(name:"odata_pool_axi4_rst_n",active:"low") dsize = Parameter.new(name:"dsize",value:8) rd_clk = Logic.new(name:"rd_clk") rd_rst_n = Logic.new(name:"rd_rst_n") data = Logic.new(name:"data") empty = Logic.new(name:"empty") rd_en = Logic.new(name:"rd_en") source_addr = Logic.new(name:"source_addr") size = Logic.new(name:"size") valid = Logic.new(name:"valid") ready = Logic.new(name:"ready") last_drop = Logic.new(name:"last_drop") axi_master = Axi4.new(name:"axi_master",clock:c0,reset:r0) Axi4.odata_pool_axi4( dsize:dsize, rd_clk:rd_clk, rd_rst_n:rd_rst_n, data:data, empty:empty, rd_en:rd_en, source_addr:source_addr, size:size, valid:valid, ready:ready, last_drop:last_drop, axi_master:axi_master) puts_sv Tdl.inst,Tdl.draw end
test_odata_pool_axi4_a1()
click to toggle source
# File lib/tdl/axi4/bak/odata_pool_axi4_A1_auto.rb, line 94 def self.test_odata_pool_axi4_a1 c0 = Clock.new(name:"odata_pool_axi4_a1_clk",freqM:148.5) r0 = Reset.new(name:"odata_pool_axi4_a1_rst_n",active:"low") source_addr = Logic.new(name:"source_addr") size = Logic.new(name:"size") valid = Logic.new(name:"valid") ready = Logic.new(name:"ready") out_axis = AxiStream.new(name:"out_axis",clock:c0,reset:r0) axi_master = Axi4.new(name:"axi_master",clock:c0,reset:r0) Axi4.odata_pool_axi4_a1( source_addr:source_addr, size:size, valid:valid, ready:ready, out_axis:out_axis, axi_master:axi_master) puts_sv Tdl.inst,Tdl.draw end
test_parse_big_field_table()
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# File lib/tdl/axi_stream/bak/parse_big_field_table_auto.rb, line 90 def self.test_parse_big_field_table c0 = Clock.new(name:"parse_big_field_table_clk",freqM:148.5) r0 = Reset.new(name:"parse_big_field_table_rst_n",active:"low") dsize = Parameter.new(name:"dsize",value:8) field_len = Parameter.new(name:"field_len",value:16*8) field_name = Parameter.new(name:"field_name",value:"Big Filed") try_parse = Parameter.new(name:"try_parse",value:"OFF") enable = Logic.new(name:"enable") value = Logic.new(name:"value") out_valid = Logic.new(name:"out_valid") cm_tb_s = AxiStream.new(name:"cm_tb_s",clock:c0,reset:r0) cm_tb_m = AxiStream.new(name:"cm_tb_m",clock:c0,reset:r0) cm_mirror = AxiStream.new(name:"cm_mirror",clock:c0,reset:r0) up_stream = cm_tb_s down_stream = cm_tb_m AxiStream.parse_big_field_table(dsize:dsize,field_len:field_len,field_name:field_name,try_parse:try_parse,enable:enable,value:value,out_valid:out_valid,cm_tb_s:cm_tb_s,cm_tb_m:cm_tb_m,cm_mirror:cm_mirror) puts_sv Tdl.inst,Tdl.draw end
test_parse_big_field_table_a1()
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# File lib/tdl/axi_stream/bak/parse_big_field_table_A1_auto.rb, line 90 def self.test_parse_big_field_table_a1 c0 = Clock.new(name:"parse_big_field_table_a1_clk",freqM:148.5) r0 = Reset.new(name:"parse_big_field_table_a1_rst_n",active:"low") dsize = Parameter.new(name:"dsize",value:8) field_len = Parameter.new(name:"field_len",value:16*8) field_name = Parameter.new(name:"field_name",value:"Big Filed") try_parse = Parameter.new(name:"try_parse",value:"OFF") enable = Logic.new(name:"enable") value = Logic.new(name:"value") out_valid = Logic.new(name:"out_valid") cm_tb_s = AxiStream.new(name:"cm_tb_s",clock:c0,reset:r0) cm_tb_m = AxiStream.new(name:"cm_tb_m",clock:c0,reset:r0) cm_mirror = AxiStream.new(name:"cm_mirror",clock:c0,reset:r0) up_stream = cm_tb_s down_stream = cm_tb_m AxiStream.parse_big_field_table_a1(dsize:dsize,field_len:field_len,field_name:field_name,try_parse:try_parse,enable:enable,value:value,out_valid:out_valid,cm_tb_s:cm_tb_s,cm_tb_m:cm_tb_m,cm_mirror:cm_mirror) puts_sv Tdl.inst,Tdl.draw end
test_parse_big_field_table_a2()
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# File lib/tdl/axi_stream/bak/parse_big_field_table_A2_auto.rb, line 90 def self.test_parse_big_field_table_a2 c0 = Clock.new(name:"parse_big_field_table_a2_clk",freqM:148.5) r0 = Reset.new(name:"parse_big_field_table_a2_rst_n",active:"low") dsize = Parameter.new(name:"dsize",value:8) field_len = Parameter.new(name:"field_len",value:16*8) field_name = Parameter.new(name:"field_name",value:"Big Filed") try_parse = Parameter.new(name:"try_parse",value:"OFF") enable = Logic.new(name:"enable") value = Logic.new(name:"value") out_valid = Logic.new(name:"out_valid") cm_tb_s = AxiStream.new(name:"cm_tb_s",clock:c0,reset:r0) cm_tb_m = AxiStream.new(name:"cm_tb_m",clock:c0,reset:r0) cm_mirror = AxiStream.new(name:"cm_mirror",clock:c0,reset:r0) up_stream = cm_tb_s down_stream = cm_tb_m AxiStream.parse_big_field_table_a2(dsize:dsize,field_len:field_len,field_name:field_name,try_parse:try_parse,enable:enable,value:value,out_valid:out_valid,cm_tb_s:cm_tb_s,cm_tb_m:cm_tb_m,cm_mirror:cm_mirror) puts_sv Tdl.inst,Tdl.draw end
test_part_data_pair_map()
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# File lib/tdl/axi_stream/bak/part_data_pair_map_auto.rb, line 55 def self.test_part_data_pair_map c0 = Clock.new(name:"part_data_pair_map_clk",freqM:148.5) r0 = Reset.new(name:"part_data_pair_map_rst_n",active:"low") Parameter.new(name:"num",value:8) Parameter.new(name:"isize",value:8) Parameter.new(name:"osize",value:8) DataInf_C.new(name:"write_inf",clock:c0,reset:r0) DataInf_C.new(name:"ipart_inf",clock:c0,reset:r0) DataInf_C.new(name:"opart_inf",clock:c0,reset:r0) DataInf_C.new(name:"idel_inf",clock:c0,reset:r0) DataInf_C.new(name:"odel_inf",clock:c0,reset:r0) DataInf_C.new(name:"Oipart_inf",clock:c0,reset:r0) DataInf_C.new(name:"Oopart_inf",clock:c0,reset:r0) DataInf_C.new(name:"ierr_inf",clock:c0,reset:r0) DataInf_C.new(name:"oerr_inf",clock:c0,reset:r0) DataInf_C.part_data_pair_map(num:num,isize:isize,osize:osize,write_inf:write_inf,ipart_inf:ipart_inf,opart_inf:opart_inf,idel_inf:idel_inf,odel_inf:odel_inf,oipart_inf:oipart_inf,oopart_inf:oopart_inf,ierr_inf:ierr_inf,oerr_inf:oerr_inf) puts_sv Tdl.inst,Tdl.draw end
test_simple_video_gen_a2()
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# File lib/tdl/axi_stream/bak/simple_video_gen_A2.rb, line 42 def self.test_simple_video_gen_a2 c0 = Clock.new(name:"simple_video_gen_a2_clk",freqM:148.5) r0 = Reset.new(name:"simple_video_gen_a2_rst_n",active:"low") Parameter.new(name:"mode",value:"1080P@60") Parameter.new(name:"dsize",value:24) Logic.new(name:"enable") VideoInf.new(name:"inf",clock:c0,reset:r0) VideoInf.simple_video_gen_a2(mode:mode,dsize:dsize,enable:enable,inf:inf) puts_sv Tdl.inst,Tdl.draw end
test_stream_crc()
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# File lib/tdl/axi_stream/bak/stream_crc_auto.rb, line 49 def self.test_stream_crc c0 = Clock.new(name:"stream_crc_clk",freqM:148.5) r0 = Reset.new(name:"stream_crc_rst_n",active:"low") crc = Logic.new(name:"crc") axis_in = AxiStream.new(name:"axis_in",clock:c0,reset:r0) AxiStream.stream_crc(crc:crc,axis_in:axis_in) puts_sv Tdl.inst,Tdl.draw end
test_udp_server_bfm()
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# File lib/tdl/axi_stream/bak/udp_server_bfm_auto.rb, line 44 def self.test_udp_server_bfm c0 = Clock.new(name:"udp_server_bfm_clk",freqM:148.5) r0 = Reset.new(name:"udp_server_bfm_rst_n",active:"low") AxiStream.new(name:"tx_udp_inf",clock:c0,reset:r0) AxiStream.new(name:"rx_udp_inf",clock:c0,reset:r0) AxiStream.udp_server_bfm(tx_udp_inf:tx_udp_inf,rx_udp_inf:rx_udp_inf) puts_sv Tdl.inst,Tdl.draw end
test_udp_server_ctrl_bfm()
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# File lib/tdl/axi_stream/bak/udp_server_ctrl_bfm_auto.rb, line 44 def self.test_udp_server_ctrl_bfm c0 = Clock.new(name:"udp_server_ctrl_bfm_clk",freqM:148.5) r0 = Reset.new(name:"udp_server_ctrl_bfm_rst_n",active:"low") AxiStream.new(name:"tx_udp_inf",clock:c0,reset:r0) AxiStream.new(name:"rx_udp_inf",clock:c0,reset:r0) AxiStream.udp_server_ctrl_bfm(tx_udp_inf:tx_udp_inf,rx_udp_inf:rx_udp_inf) puts_sv Tdl.inst,Tdl.draw end
test_video_from_axi4()
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# File lib/tdl/VideoInf/video_from_axi4.rb, line 97 def self.test_video_from_axi4 c0 = Clock.new(name:"时钟",freqM:148.5) r0 = Reset.new(name:"复位",active:"low") p0 = Parameter.new(name:"P0",value:24) axi4_master = Axi4.new(name:"out",clock:c0,reset:r0,dsize:p0) data_slaver = VideoInf.new(name:"in",clock:c0,reset:r0,dsize:p0) Axi4.video_from_axi4(axi4_master:axi4_master,video_slaver:data_slaver,base_addr:"12'd0") puts_sv Tdl.inst,Tdl.draw Tdl.clear end
test_video_to_vdma()
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# File lib/tdl/axi_stream/bak/video_to_VDMA.rb, line 49 def self.test_video_to_vdma c0 = Clock.new(name:"video_to_vdma_clk",freqM:148.5) r0 = Reset.new(name:"video_to_vdma_rst_n",active:"low") Parameter.new(name:"mode",value:"LINE") Logic.new(name:"base_addr") VideoInf.new(name:"video_inf",clock:c0,reset:r0) Axi4.new(name:"axi_master",clock:c0,reset:r0) down_stream = axi_master Axi4.video_to_vdma(mode:mode,base_addr:base_addr,video_inf:video_inf,axi_master:axi_master) puts_sv Tdl.inst,Tdl.draw end
video_stream_2_axi_stream()
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# File lib/tdl/VideoInf/video_stream_2_axi_stream.rb, line 58 def self.video_stream_2_axi_stream c0 = Clock.new(name:"时钟",freqM:148.5) r0 = Reset.new(name:"复位",active:"low") axis_master = AxiStream.new(name:"out",clock:c0,reset:r0) data_in = VideoInf.new(name:"in",clock:c0,reset:r0) AxiStream.video_stream_2_axi_stream(axis_master:axis_master,video_slaver:data_in) puts_sv Tdl.inst,Tdl.draw end