class SdlModule
定义 位拼接方法
add clock domain
获取 引用的所有文件
迭代 本模块及本模块的子模块
有时候 sdlmodule 引用的是 HDL文件,为了能够 正常引用到 需要特殊处理
添加状态机
判断 是否被顶层引用
Attributes
create_tcl[R]
dont_gen_sv[RW]
ex_down_code[RW]
ex_param[RW]
ex_port[RW]
ex_up_code[RW]
head_import_packages[RW]
模块头部添加package引入
instance_and_children_module[RW]
instanced_and_parent_module[RW]
attr_accessor :ports attr_accessor :parent_modules,:children_modules
module_name[RW]
origin_sv[RW]
out_sv_path[RW]
path[RW]
real_sv_path[RW]
target_class[RW]
techbench[RW]
Public Class Methods
Main()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 22 def self.Main $__sdl_curr_self__ end
allmodule_name()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 9 def self.allmodule_name @@allmodule_name end
base_hdl_ref()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 391 def self.base_hdl_ref ## 基本接口引用 _base_refs = [] _base_refs << ['axi_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_inf.sv"))] _base_refs << ['axi_lite_inf', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_lite_inf.sv"))] _base_refs << ['axi_stream', File.expand_path(File.join(__dir__, "../../axi/interface_define/axi_stream_inf.sv"))] _base_refs << ['data_inf', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface.sv"))] _base_refs << ['data_inf_c', File.expand_path(File.join(__dir__, "../../axi/data_interface/data_interface_pkg.sv"))] _base_refs << ['axi_bfm_pkg', File.expand_path(File.join(__dir__, "../../axi/AXI_BFM/AXI_BFM_PKG.sv"))] _base_refs << ['cm_ram_inf', File.expand_path(File.join(__dir__, "../../tdl/rebuild_ele/cm_ram_inf.sv"))] _base_refs << ['Lite_Addr_Data_CMD', File.expand_path(File.join(__dir__, "../../axi/AXI_Lite/gen_axi_lite_ctrl.sv"))] _base_refs end
call_module(module_name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 13 def self.call_module(module_name) $__sdl_curr_self__.send(module_name) # main.send(module_name) end
echo_tracked_by_dve()
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 133 def self.echo_tracked_by_dve # Flag module root_path # rels = {} flags = [] _modules = [] _root_path = [] _signals = [] _max_name = 'module_name'.size _max_flag = 'FLAG'.size _max_signal = 'SIGNAL'.size self.tracked_by_dve.each do |sdlm, filter_block| __track_signals_hash__ = sdlm.track_signals_hash || Hash.new __track_signals_hash__.each do |flag, sub_hash| sub_hash.each do |ele, sub_filter_block| _root_refs = ele.path_refs(&filter_block) _root_refs.uniq! if sub_filter_block _root_refs.select! do |e| sub_filter_block.call(e) end end if _root_refs.size == 1 # rels[0] elsif _root_refs.size == 0 raise TdlError.new "#{ele.to_s} Cant find root ref" else raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_root_refs.join("\n")}\n" end flags << flag.to_s _modules << sdlm.module_name if sdlm.module_name.size > _max_name _max_name = sdlm.module_name.size end if flag.to_s.size > _max_flag _max_flag = flag.to_s.size end # _root_path << _root_refs[0] _root_path << File.expand_path(ele.belong_to_module.real_sv_path) _signals << ele.to_s if ele.to_s.size > _max_signal _max_signal = ele.to_s.size end end end end collect = ["[%s] %-#{_max_flag}s %#{_max_name+4}s %-#{_max_signal}s %s" % ['index', 'FLAG', 'MODULE-NAME', 'SIGNAL', 'belong_to_module']] flags.each_index do |index| collect << "[%5d] %-#{_max_flag}s %#{_max_name+4}s %-#{_max_signal}s %s" % [index+1, flags[index], _modules[index], _signals[index], _root_path[index]] end collect.join("\n") end
exist_module?(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 18 def self.exist_module?(name) @@allmodule_name.include? name.to_s end
gen_dev_wave_tcl(filepath=nil)
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 112 def self.gen_dev_wave_tcl(filepath=nil) ctcl_ss,ctcl_list,ctcl_bar = [],[],[] self.tracked_by_dve.each do |sdlm,filter_block| tcl_ss,tcl_list,tcl_bar = sdlm.gen_dev_wave_tcl ctcl_ss << tcl_ss ctcl_list << tcl_list ctcl_bar << tcl_bar end rel = TdlSpace.dve_tcl_temp(ctcl_ss.join("\n"), ctcl_list.join("\n"), ctcl_bar.join("\n") ) if filepath File.open(filepath,'w') do |f| f.puts rel end end rel end
gen_sv_module()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 19 def self.gen_sv_module @@allmodule.each do |e| e.gen_sv_module end end
new(name: "tdlmodule",out_sv_path: nil) { |self| ... }
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 121 def initialize(name: "tdlmodule",out_sv_path: nil) # $new_m = self # self.BindEleClassVars = PackClassVars.new # GlobalParam.PushTdlModule(self) @out_sv_path = out_sv_path def_main_method(name) @@allmodule << self @module_name = name @real_sv_path = File.join(@out_sv_path,"#{@module_name}.sv") if @out_sv_path @port_clocks = Hash.new @port_resets = Hash.new @port_params = Hash.new @port_logics = Hash.new @port_datainfs = Hash.new @port_datainf_c_s = Hash.new @port_videoinfs = Hash.new @port_axisinfs = Hash.new @port_axi4infs = Hash.new @port_axilinfs = Hash.new # @techbench = TechBench.new @sub_instanced = [] ## -------- @@ele_array.each do |e| head_str = "@#{e.to_s}" self.instance_variable_set("#{head_str}_collect",[]) self.instance_variable_set("#{head_str}_inst",[]) self.instance_variable_set("#{head_str}_draw",[]) self.instance_variable_set("#{head_str}_pre_inst_stack",[]) self.instance_variable_set("#{head_str}_post_inst_stack",[]) # tmp = e.new(name:"#{e.to_s}_NC") # tmp.ghost = true # self.instance_variable_set("#{head_str}_NC",tmp) end create_ghost if block_given? yield(self) end @instanced_and_parent_module ||= Hash.new @instance_and_children_module ||= Hash.new ## 记录当前模块被例化的 具体对象 @instances =[] end
tracked_by_dve()
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 14 def self.tracked_by_dve ## 收集添加有 dve track 的模块 @@__tracked_by_dve_hash__ ||= Hash.new ## key:sdlmodule, value:filter_block end
Public Instance Methods
<<(*args)
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 389 def <<(*args) str = "{<<{#{args.map{|e| e.to_s }.join(',')}}}" TdlSpace::ArrayChain.create(obj: str, belong_to_module: self) end
>>(*args)
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 384 def >>(*args) str = "{>>{#{args.map{|e| e.to_s }.join(',')}}}" TdlSpace::ArrayChain.create(obj: str, belong_to_module: self) end
Always(posedge: nil,negedge: nil,&block)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 185 def Always(posedge: nil,negedge: nil,&block) ClassHDL::Always(sdl_m: self,posedge: posedge,negedge: negedge,&block) end
Also aliased as: always
AlwaysComb(&block)
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# File lib/tdl/class_hdl/hdl_always_comb.rb, line 49 def AlwaysComb(&block) ClassHDL::AlwaysComb(self,&block) end
Always_comb(&block)
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# File lib/tdl/class_hdl/hdl_always_comb.rb, line 53 def Always_comb(&block) ClassHDL::AlwaysComb(self,&block) end
Also aliased as: always_comb
Always_ff(posedge: nil,negedge: nil,&block)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 191 def Always_ff(posedge: nil,negedge: nil,&block) ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge,negedge: negedge,&block) end
Assign(&block)
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# File lib/tdl/class_hdl/hdl_assign.rb, line 54 def Assign(&block) ClassHDL::Assign(self,&block) end
CASE(cond,&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 288 def CASE(cond,&block) new_op = ClassHDL::BlockCASE.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
CASEX(cond,&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 305 def CASEX(cond,&block) new_op = ClassHDL::BlockCASEX.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil) { |a| ... }
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 150 def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil) port_name_chk(name) pin,iostd = parse_pin_prop(pin_prop) if pin_prop a = Clock.new(name:name,freqM:freqM,port:port,dsize:dsize, belong_to_module: self) add_to_new_module("@port_clocks",a) if block_given? yield(a) end # define_method(name) do add_method_to_itgt(name,a) a end
CommonCFGReg()
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# File lib/tdl/elements/common_configure_reg.rb, line 109 def CommonCFGReg unless @Def_CommonCFGReg @Def_CommonCFGReg = InfPort.new(self,CommonCFGReg) class << @Def_CommonCFGReg def Def_CommonCFGReg_port_(name,dsize:8,asize:8,port: :master,dimension:[]) port_name_chk(name) a = CommonCFGReg.new(name:name,dsize:dsize,asize:asize,port:port.to_s,dimension:dimension) sdlmodule.add_to_new_module("@port_datainf_c_s",a) if block_given? yield(a) end StringBandItegration.add_method_to_itgt(name,a) a end end [:master,:slaver].each do |ty| @Def_CommonCFGReg.define_singleton_method(ty) do |name,dsize:8,asize: 8,dimension:[]| Def_CommonCFGReg_port_(name,dsize:dsize,asize: asize,port:ty,dimension:dimension) end end @Def_CommonCFGReg else @Def_CommonCFGReg end end
DEFAULT(&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 337 def DEFAULT(&block) new_op = ClassHDL::BlockCASEDEFAULT.new(self) ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
Def()
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def RootAssign(&block)
@aob ||= RootAssignObject.new(self) @aob.assign(&block)
end
# File lib/tdl/sdlmodule/sdlmodule_varible.rb, line 122 def Def @_defxp_ ||= DefXp.new(self) end
ELSE(&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 276 def ELSE(&block) new_op = ClassHDL::BlockELSE.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
ELSIF(cond,&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 259 def ELSIF(cond,&block) new_op = ClassHDL::BlockELSIF.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
FOR(var: nil, start: 0, stop: 8, step: 1,&block)
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# File lib/tdl/class_hdl/hdl_foreach.rb, line 80 def FOR(var: nil, start: 0, stop: 8, step: 1,&block) ClassHDL::AssignDefOpertor.with_normal_opertor do @@__for_index_cnt__ += 1 end new_op = ClassHDL::BlockFOR.new(self) ClassHDL::AssignDefOpertor.with_new_opertor do ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| # if cond.is_a? ClassHDL::OpertorChain # cond.slaver = true # end # ab.cond = cond ab.var = var ab.start = start ab.stop = stop ab.step = step ab.flag = var || "gvar_cc_#{@@__for_index_cnt__}".to_nq block.call(ab.flag) end end if ClassHDL::AssignDefOpertor.curr_assign_block.is_a?(ClassHDL::GenerateBlock) new_op.var_type = "genvar" else new_op.var_type = "integer" end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) ClassHDL::AssignDefOpertor.with_normal_opertor do @@__for_index_cnt__ -= 1 end return new_op end
FOREACH(cond,&block)
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# File lib/tdl/class_hdl/hdl_foreach.rb, line 54 def FOREACH(cond,&block) ClassHDL::AssignDefOpertor.with_normal_opertor do @@__foreach_index_cnt__ += 1 end new_op = ClassHDL::BlockFOREACH.new(self) ClassHDL::AssignDefOpertor.with_new_opertor do ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond ab.flag = "i#{@@__foreach_index_cnt__}".to_nq block.call(ab.flag) end end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) ClassHDL::AssignDefOpertor.with_normal_opertor do @@__foreach_index_cnt__ -= 1 end return new_op end
IF(cond,&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 242 def IF(cond,&block) new_op = ClassHDL::BlockIF.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
Initial(block_name=nil,&block)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 92 def Initial(block_name=nil,&block) ClassHDL::Initial(self,block_name,&block) end
Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) { |tmp| ... }
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 124 def Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) port_name_chk(name) pin,iostd = parse_pin_prop(pin_prop) if pin_prop # RedefOpertor.with_normal_operators do # tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' ) # add_to_new_module("@port_logics",tmp) # if block_given? # yield(tmp) # end # # define_method(name) do # add_method_to_itgt(name,tmp) # tmp # end ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do tmp = Logic.new(name:name,dsize:dsize,port:"inout",dimension:dimension,type: '' , belong_to_module: self) add_to_new_module("@port_logics",tmp) if block_given? yield(tmp) end add_method_to_itgt(name,tmp) tmp end end
Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 80 def Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) port_name_chk(name) pin,iostd = parse_pin_prop(pin_prop) if pin_prop # RedefOpertor.with_normal_operators do # tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension) # add_to_new_module("@port_logics",tmp) # add_method_to_itgt(name,tmp) # tmp # end ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do tmp = Logic.new(name:name,dsize:dsize,port:"input",dimension:dimension, belong_to_module: self) add_to_new_module("@port_logics",tmp) add_method_to_itgt(name,tmp) tmp end end
Instance(sdlmodule_name,name) { |inst_obj,self| ... }
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 498 def Instance(sdlmodule_name,name) ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do name = name.to_s unless name.to_s =~ /^[a-zA-Z]([a-zA-Z0-9]|_)*[a-zA-Z0-9]$/ raise TdlError.new("SdlModule Instance name ERROR: `#{name}`") end sdlmodule = SdlModule.call_module(sdlmodule_name) if self.module_name.eql? sdlmodule.module_name raise TdlError.new("SdlModule [#{@module_name}]cant instance itself ") end inst_obj = sdlmodule.instanced(name,self) inst_obj.belong_to_module = self add_children_modules(inst_obj: inst_obj,module_poit:sdlmodule) define_ele(name,inst_obj) @sub_instanced << inst_obj if block_given? yield inst_obj,self end inst_obj end end
Itgt_Instance(sdlmodule_name,stringbanditegration,&block)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 522 def Itgt_Instance(sdlmodule_name,stringbanditegration,&block) ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do unless stringbanditegration.is_a? StringBandItegration raise TdlError.new("Itgt_Instance is just used for StringBandItegration") end _inst_obj = Instance(sdlmodule_name,stringbanditegration.to_s,&block) # stringbanditegration.itgt.define_singleton_method(stringbanditegration.origin_str) do # _inst_obj # end StringBandItegration.add_method_to_itgt(stringbanditegration,_inst_obj) _inst_obj end end
NameSpaceAdd(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 238 def NameSpaceAdd(name) # @_add_to_new_module_vars ||= methods.map { |e| e.to_s } @_add_to_new_module_vars ||= [] @_base_methods ||= methods.map { |e| e.to_s } raise TdlError.new(" SdlModule[#{@module_name}] add signal error: same port or instance `#{name}` ") if (@_add_to_new_module_vars | @_base_methods ).include? name @_add_to_new_module_vars << name end
Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) { |tmp| ... }
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 97 def Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) port_name_chk(name) pin,iostd = parse_pin_prop(pin_prop) if pin_prop # RedefOpertor.with_normal_operators do # tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic') # add_to_new_module("@port_logics",tmp) # if block_given? # yield(tmp) # end # # define_method(name) do # add_method_to_itgt(name,tmp) # tmp # end ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do tmp = Logic.new(name:name,dsize:dsize,port:"output",dimension:dimension,type: 'logic', belong_to_module: self) add_to_new_module("@port_logics",tmp) if block_given? yield(tmp) end # define_method(name) do add_method_to_itgt(name,tmp) tmp end end
Parameter(name=:NAME,value=0,type:nil,show:true)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 62 def Parameter(name=:NAME,value=0,type:nil,show:true) # def Parameter(name=:NAME,value=0,type=nil,show=true) port_name_chk(name) if value.is_a? Float type = :real end tmp = Parameter.new(name:name.to_s,value:value,port:true,type:type,show:show, belong_to_module: self) add_to_new_module("@port_params",tmp) add_method_to_itgt(name,tmp) tmp end
Parameters(phash)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 74 def Parameters(phash) phash.each do |key,value| Parameter(name=key,value=value,type=nil) end end
Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 164 def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil) port_name_chk(name) pin,iostd = parse_pin_prop(pin_prop) if pin_prop a = Reset.new(name:name,active:active.to_s.downcase,port:port,dsize:dsize, belong_to_module: self) add_to_new_module("@port_resets",a) # define_method(name){ a } add_method_to_itgt(name,a) a end
StateMachine(name,clock: nil,reset: nil, &block)
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# File lib/tdl/sdlmodule/sdlmodule_varible.rb, line 157 def StateMachine(name,clock: nil,reset: nil, &block) MainStateMachine(name,:clock => clock,:reset => reset,:belong_to_module => self,&block) end
TrackInf()
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# File lib/tdl/elements/track_inf.rb, line 137 def TrackInf unless @Def_TrackInf @Def_TrackInf = InfPort.new(self,TrackInf) class << @Def_TrackInf def Def_TrackInf_port_(name,dsize:8,tsize:1,enable:"1'b1".to_nq,port: :master,dimension:[]) port_name_chk(name) a = TrackInf.new(name:name,dsize:dsize,tsize:tsize,enable:enable,port:port.to_s,dimension:dimension) sdlmodule.add_to_new_module("@port_datainf_c_s",a) if block_given? yield(a) end StringBandItegration.add_method_to_itgt(name,a) a end end [:master,:slaver].each do |ty| @Def_TrackInf.define_singleton_method(ty) do |name,dsize:8,tsize: 1,enable:"1'b1".to_nq,dimension:[]| Def_TrackInf_port_(name,dsize:dsize,tsize: tsize,enable:enable,port:ty,dimension:dimension) end end @Def_TrackInf else @Def_TrackInf end end
TryDef()
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# File lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb, line 116 def TryDef @_trydefxp_ ||= TryDefXp.new(self) end
WHEN(*cond,&block)
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# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 322 def WHEN(*cond,&block) new_op = ClassHDL::BlockCASEWHEN.new(self) ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond block.call end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
__contain_hdl__(recreate,*hdl_names)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 512 def __contain_hdl__(recreate,*hdl_names) hdl_names = hdl_names.map do |e| if e.include?("/") || e.include?("\\") e else ee = find_first_hdl_path(e) if recreate && !ee raise TdlError.new("Cant find #{e} in tdl_paths") end ee || e end end unless recreate @__contain_hdl__ ||= [] @__contain_hdl__ += hdl_names else @__contain_hdl__ = hdl_names end @__contain_hdl__.uniq! @__contain_hdl__ end
__ref_children_modules__()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 370 def __ref_children_modules__ curr_refs = [] @_import_packages_ ||= [] curr_refs << @_import_packages_ instance_and_children_module.values.each do |pm| curr_refs << [pm, pm.__ref_children_modules__()] end return curr_refs end
add_children_modules(inst_obj:nil,module_poit:nil)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 546 def add_children_modules(inst_obj:nil,module_poit:nil) # inst_name = inst_name.to_s @instance_and_children_module ||= Hash.new @instance_and_children_module[inst_obj] = module_poit module_poit.add_parent_modules(inst_obj:inst_obj,module_poit:self) end
add_parent_modules(inst_obj:nil,module_poit:nil)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 555 def add_parent_modules(inst_obj:nil,module_poit:nil) # inst_name = inst_name.to_s @instanced_and_parent_module ||= Hash.new @instanced_and_parent_module[inst_obj] = module_poit end
add_to_dve_wave(flag: :default,base_ele: nil,&block)
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 18 def add_to_dve_wave(flag: :default,base_ele: nil,&block) @__track_signals_hash__ ||=Hash.new @__track_signals_hash__[flag] ||= Hash.new if @__track_signals_hash__[flag].has_key?(base_ele) raise TdlError.new(" `#{module_name}.#{base_ele.to_s}` Cant be tracked again!!!") end @__track_signals_hash__[flag][base_ele] = block unless base_ele.is_a?(AxiTdl::SdlModuleActiveBaseElm) raise TdlError.new(" `#{base_ele.to_s}<class #{base_ele.class}>` is not AxiTdl::SdlModuleActiveBaseElm !!! ") end end
add_to_new_module(variable="@port_params",new_var)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 22 def add_to_new_module(variable="@port_params",new_var) _vars = self.instance_variable_get(variable) # get hash define_ele(new_var) ## 给sdlmodule 定义方法,方法名为 new_var.name ,返回new_var对象 @ports ||=Hash.new _vars[new_var.name] = new_var @ports[new_var.name] = new_var unless new_var.is_a? Parameter new_var.belong_to_module = self add_new_after_inst(new_var) ## 当在sdlmodule里面例化 子sdlmodule时可以通过child_sdlmodule_inst[:key] 访问 子模块的port return new_var end
all_ref_sdlmodules(&block)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 490 def all_ref_sdlmodules(&block) sdlms = instance_and_children_module.values.uniq sdlms = sdlms.map do |e| if e.instance_and_children_module.any? e.all_ref_sdlmodules(&block) else e end end sdlms = sdlms.unshift(self) sdlms = sdlms.flatten sdlms.map(&block) end
always_ff(*args,&block)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 195 def always_ff(*args,&block) if args[0].is_a? Hash return Always(**args[0],&block) end posedge_list = [] negedge_list = [] args.each do |e| if e.is_a? ClassHDL::ClassPosedge posedge_list << e elsif e.is_a? ClassHDL::ClassNegedge negedge_list << e end end ClassHDL::AlwaysFF(sdl_m: self,posedge: posedge_list,negedge: negedge_list,&block) end
always_sim(posedge: nil,negedge: nil,&block)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 213 def always_sim(posedge: nil,negedge: nil,&block) ClassHDL::AlwaysSIM(sdl_m: self,posedge: posedge,negedge: negedge,&block) end
assert(cond,formats=false,*argsx,&block)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 100 def assert(cond,formats=false,*argsx,&block) unless formats return assert_old(cond,nil,&block) end if formats.is_a?(String) && argsx.empty? return assert_old(cond,argv_str=formats,&block) end new_op = ClassHDL::BlocAssertIF.new(self) ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond if block_given? block.call else assert_format_error([formats],argsx) end end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) return new_op end
assert_error(argv_str)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 155 def assert_error(argv_str) ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{argv_str}\")".to_nq], self)) ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self)) end
assert_format_error(formats=[],args=[])
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# File lib/tdl/class_hdl/hdl_initial.rb, line 160 def assert_format_error(formats=[],args=[]) ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$error(\"#{formats.join(' ')}\",#{args.map{|s| s.to_s}.join(',')})".to_nq], self)) ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new(["$stop".to_nq], self)) end
assert_old(cond,argv_str=nil,&block)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 127 def assert_old(cond,argv_str=nil,&block) new_op = ClassHDL::BlocAssertIF.new(self) # if ClassHDL::AssignDefOpertor.curr_assign_block.is_a? ClassHDL::BlockIF # new_op.slaver = true # end ClassHDL::AssignDefOpertor.with_new_assign_block(new_op) do |ab| if cond.is_a? ClassHDL::OpertorChain cond.slaver = true end ab.cond = cond if block_given? block.call else if argv_str assert_error(argv_str) end end end ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(new_op) # unless argv_str # assert_error(argv_str) # end return new_op end
bits(arg)
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 404 def bits(arg) str = "$bits(#{arg.to_s})" TdlSpace::ArrayChain.create(obj: str, belong_to_module: self) end
build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
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end
# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 83 def build_module(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"") # Tdl.Puts pagination(module_name) Tdl.Build_SdlModule_Puts(module_name) ex_param = ex_param.to_s unless ex_param ex_port = ex_port.to_s unless ex_port ex_up_code = ex_up_code.to_s unless ex_up_code ex_down_code = ex_down_code.to_s unless ex_down_code # gen_auto_method # auto generate class method for interface # draw = Tdl.inst + Tdl.draw instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec post_str = post_inst_stack_call() unless post_str.strip.empty? post_str = pagination("ROOT REF") + post_str end draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str unless ex_up_code.empty? ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n" end unless ex_down_code.empty? ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n" end # str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n" # unless GlobalParam.sim module_name_str = @module_name # else # module_name_str = @module_name+"_sim" # end unless head_import_packages str = module_head+"module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths else head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('') str = module_head+"module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths end create_vivado_tcl if @create_tcl create_constraints_file if @create_sdc return str end
build_module_verb(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"")
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 133 def build_module_verb(ex_param:"",ex_port:"",ex_up_code:"",ex_down_code:"") #return [ head, body] # Tdl.Puts pagination(module_name) Tdl.Build_SdlModule_Puts(module_name) ex_param = ex_param.to_s unless ex_param ex_port = ex_port.to_s unless ex_port ex_up_code = ex_up_code.to_s unless ex_up_code ex_down_code = ex_down_code.to_s unless ex_down_code # gen_auto_method # auto generate class method for interface # draw = Tdl.inst + Tdl.draw instance_draw_str = instance_draw # It must run before vars_define_inst,because some signals define when inst vars_exec_inst_str = vars_exec_inst # It must run before vars_define_inst,because some signals define when vars exec post_str = post_inst_stack_call() unless post_str.strip.empty? post_str = pagination("ROOT REF") + post_str end draw = pagination("define") + vars_define_inst + pagination("instance") + instance_draw_str + pagination("expression") + vars_exec_inst_str + post_str unless ex_up_code.empty? ex_up_code = "\n//------>> EX CODE <<-------------------\n" + ex_up_code + "//------<< EX CODE >>-------------------\n" end unless ex_down_code.empty? ex_down_code = "//------>> EX CODE <<-------------------\n" + ex_down_code + "//------<< EX CODE >>-------------------\n" end # str = module_head+"module #{@module_name}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + gen_lite_str() + draw + ex_down_code + "\nendmodule\n" # unless GlobalParam.sim module_name_str = @module_name # else # module_name_str = @module_name+"_sim" # end unless head_import_packages str = "module #{module_name_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths else head_import_pkgs_str = head_import_packages.map{|e| "import #{e}::*;" }.join('') str = "module #{module_name_str} #{head_import_pkgs_str}" + build_params(ex_param) + build_ports(ex_port) + ex_up_code + draw + ex_down_code + "\nendmodule\n" + add_sub_module_file_paths end create_vivado_tcl if @create_tcl create_constraints_file if @create_sdc # return str return [module_head_verb, str] end
call_instance(name)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 561 def call_instance(name) method(name).call end
children_inst_tree(collect=[]) { |dc| ... }
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子 [self,[C0, [C1,] C3]]
# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 610 def children_inst_tree(collect=[],&block) rels = [] # parent_rels = [] @sub_instanced.each do |sm| dc = collect.dup if sm.origin.instance_and_children_module.empty? dc << sm rels << dc yield dc if block_given? else dc << sm sm.origin.children_inst_tree(dc,&block) end end rels end
clog2(arg)
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 399 def clog2(arg) str = "$clog2(#{arg.to_s})" TdlSpace::ArrayChain.create(obj: str, belong_to_module: self) end
contain_hdl(*hdl_names)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 508 def contain_hdl(*hdl_names) __contain_hdl__(false,*hdl_names) end
debugLogic()
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# File lib/tdl/sdlmodule/sdlmodule_arraychain.rb, line 305 def debugLogic TdlSpace::DefDebugLogicArrayChain.new(self) end
def_struct(&block)
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# File lib/tdl/class_hdl/hdl_struct.rb, line 195 def def_struct(&block) return ClassHDL::DefStruct.new(self,block) end
define_ele(name,obj=nil) { |obj| ... }
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private
# File lib/tdl/sdlmodule/sdlmodule.rb, line 223 def define_ele(name,obj=nil) if name.is_a? BaseElm obj = name name = obj.name end name = name.to_s NameSpaceAdd(name) self.define_singleton_method(name) do |&block| if block_given? yield obj end obj end end
enum(*args)
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定义状态机
# File lib/tdl/class_hdl/hdl_block_ifelse.rb, line 348 def enum(*args) return ClassHDL::EnumStruct.new(self,*args) end
function(return_type=nil)
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def _core_function(name,*argvs,&block)
ClassHDL::Function(self,name,*argvs,&block)
end
# File lib/tdl/class_hdl/hdl_function.rb, line 273 def function(return_type=nil) ClassHDL.disable_SdlModule_port ClassHDL.new_def_SdlModule_port return ClassHDL::DefFunction.new(self,return_type) end
gen_dev_wave_tcl()
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 45 def gen_dev_wave_tcl ## 返回一个[] return ['','',''] unless TopModule.sim dve_tcl_hash = {} track_signals_hash.each do |flag, base_ele_bhash| base_elms = [] intf_elms = [] intf_elms_name = [] base_ele_bhash.each do |ele, sub_filter_block| _ref_paths = ele.path_refs(&@__track_filter_block__) _ref_paths.uniq! if sub_filter_block _ref_paths = _ref_paths.select do |e| sub_filter_block.call(e) end end if _ref_paths.size == 1 # rels[0] elsif _ref_paths.size == 0 raise TdlError.new "#{ele.to_s} Cant find root ref" else raise TdlError.new "#{ele.to_s} Find multi root refs \n#{_ref_paths.join("\n")}\n" end if ele.is_a?(BaseElm) || ele.is_a?(ClassHDL::EnumStruct) || ele.is_a?(ClassHDL::StructVar) base_elms << _ref_paths[0].sub("$root.","Sim:") elsif ele.is_a? TdlSpace::TdlBaseInterface if ele.modport_type base_elms << _ref_paths[0].sub("$root.","Sim:") else intf_elms << _ref_paths[0].sub("$root.","Sim:") intf_elms_name << ele.inst_name end end end dve_tcl_hash[flag] = [base_elms, intf_elms,intf_elms_name] end add_ss = [] add_list = [] add_bar = [] dve_tcl_hash.each do |flag, ary| add_ss << TdlSpace.dev_signals_to_tcl(flag: "#{module_name}_#{flag}", signals: ary[0] ) add_list << TdlSpace.gui_list_add_group(flag: "Group2_#{module_name}_#{flag}") ary[1].each_index do |index| add_ss << TdlSpace.dev_interface_to_tcl(flag: "#{module_name}_#{flag}", iname: ary[2][index] ,signals: [ ary[1][index] ]) add_list << TdlSpace.gui_list_add_group(flag: "#{module_name}_#{flag}|#{ary[2][index]}") end add_bar << TdlSpace.gui_list_set_insertion_bar(flag: "#{module_name}_#{flag}") end # TdlSpace.dve_tcl_temp(add_ss.join("\n"), add_list.join("\n"), add_bar.join("\n") ) return [add_ss.join("\n"), add_list.join("\n"), add_bar.join("\n")] end
gen_sv_module()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 49 def gen_sv_module # @out_sv_path ||= File.dirname(File.expand_path(__FILE__)) return if (@origin_sv || @dont_gen_sv) pre_inst_stack_call @out_sv_path ||= '..\..\tdl\test_sdlmodule' if File.exist?(File.join(@out_sv_path,"#{module_name}.sv")) old_str = File.open(File.join(@out_sv_path,"#{module_name}.sv")).read.sub(/\/\*.*?\*\//m,"").gsub(/\/\/.*/,"").sub(/^`timescale .*/,"").strip head_str,body_str = build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code) new_str = head_str+body_str if body_str.gsub(/\/\/.*/,"").strip != old_str File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f| f.print new_str end end else File.open(File.join(@out_sv_path,"#{module_name}.sv"),"w") do |f| f.print build_module_verb(ex_param:ex_param,ex_port:ex_port,ex_up_code:ex_up_code,ex_down_code:ex_down_code).join("") end end end
generate(*args,&block)
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# File lib/tdl/class_hdl/hdl_generate.rb, line 147 def generate(*args,&block) head_str = "" index = 0 @__generate_blocks__ ||= [] tmp_sm = ClassHDL::GenerateBlock.new(self) kk_args = [] @__generate_blocks__ << tmp_sm tmp_sm.block_index = @__generate_blocks__.size tmp_sm.module_name = "generate_block_#{tmp_sm.block_index}" if args.empty? inst_obj = tmp_sm.instanced("genblk#{tmp_sm.block_index}",tmp_sm) else inst_obj = tmp_sm.instanced("genblk#{tmp_sm.block_index}[0]",tmp_sm) ## 只取第一个 end inst_obj.belong_to_module = tmp_sm add_children_modules(inst_obj:inst_obj ,module_poit: tmp_sm) args.each_index do |e| new_op = ClassHDL::OpertorChain.new(nil, self) new_op.tree.push(["KK#{e}".to_nq]) kk_args << new_op end ClassHDL::AssignDefOpertor.with_new_assign_block(ClassHDL::HDLAssignGenerateBlock.new(self) ) do ClassHDL::AssignDefOpertor.with_rollback_opertors(:new) do tmp_sm.instance_exec(*kk_args,&block) end end str = (tmp_sm.instance_draw + tmp_sm.vars_exec_inst) gstr = generate_block_inst_iterate(str,args) head_str = "generate\n" end_str = "endgenerate\n" self.Logic_inst << head_str+gstr+end_str end
genvar()
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# File lib/tdl/sdlmodule/sdlmodule_arraychain.rb, line 309 def genvar TdlSpace::DefGenVar.new(self) end
has_inward_inst?(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 38 def has_inward_inst?(name) @_add_to_new_module_vars.include? name.to_s end
has_signal?(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 34 def has_signal?(name) @_add_to_new_module_vars.include? name.to_s end
implicit_inst_module_method_missing(method,*args,&block)
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例化模块
@@_method_missing_sub_methds ||= [] @@_method_missing_sub_methds << 'implicit_inst_module_method_missing'
# File lib/tdl/class_hdl/hdl_module_def.rb, line 128 def implicit_inst_module_method_missing(method,*args,&block) unless $__sdl_curr_self__.respond_to?(method) # super ##打通 ITGT 和 module 的方法调用 if $_implicit_curr_itgt_.slast && $_implicit_curr_itgt_.slast.respond_to?(method) return $_implicit_curr_itgt_.slast.send(method,*args) else return false end end return ClassHDL::ImplicitInstModule.new(method,self) end
initial(block_name=nil,&block)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 96 def initial(block_name=nil,&block) ClassHDL::Initial(self,block_name,&block) end
initial_exec(str)
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# File lib/tdl/class_hdl/hdl_initial.rb, line 165 def initial_exec(str) ClassHDL::AssignDefOpertor.curr_assign_block.opertor_chains.push(ClassHDL::OpertorChain.new([str.to_s.to_nq], self)) end
Also aliased as: always_sim_exec
inout(args={})
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 376 def inout(args={}) return ClassHDL::ImplicitPortInout.new(self,args) end
input(args={})
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例化 input output
# File lib/tdl/class_hdl/hdl_module_def.rb, line 368 def input(args={}) return ClassHDL::ImplicitPortInput.new(self,args) end
instance_draw()
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private
# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 540 def instance_draw @sub_instanced.map do |e| e.inst_draw end.join("\n") end
instanced(name,parent_module)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 443 def instanced(name,parent_module) @ports ||= Hash.new # [@port_clocks , @port_resets , @port_logics , @port_datainfs , @port_datainf_c_s , @port_videoinfs , @port_axisinfs , @port_axi4infs , @port_axilinfs].each do |e| # @ports = @ports.merge e # end # @ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs) @instance_cnt ||= 0 inst_p = SdlInst.new(origin:self,name:name) @instances ||= [] @instances << inst_p @port_params.each do |k,v| inst_p.inst_param_hash[k.to_s] = nil end @ports.each do |k,v| inst_p.inner_port_hash[k.to_s] = v if v.is_a? SignalElm dele = DefaultProc.new do new_ele = v.copy(belong_to_module:parent_module) # new_ele.belong_to_module = parent_module new_ele.name = "#{name}_#{v.name}" new_ele end else dele = NqString.new("") end inst_p.inst_port_hash[k.to_s] = dele end @instance_cnt += 1 inst_p end
inward_inst(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 30 def inward_inst(name) method(name).call end
localparam()
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# File lib/tdl/class_hdl/hdl_parameter.rb, line 59 def localparam a = HDLClass::ImplicitInstParam.new(self) a.local = true return a end
logic()
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# File lib/tdl/sdlmodule/sdlmodule_arraychain.rb, line 301 def logic TdlSpace::DefLogicArrayChain.new(self) end
logic_bind_(*args)
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 394 def logic_bind_(*args) str = "{#{args.map{|e| e.to_s }.join(',')}}" TdlSpace::ArrayChain.create(obj: str, belong_to_module: self) end
macro_add_vcs()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 345 def macro_add_vcs @_head_macro_ ||=[] @_head_macro_ << "`include \"define_macro.sv\" " end
macro_def()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 339 def macro_def @_head_macro_ ||=[] @_head_macro_ << "`timescale 1ns/1ps" @_head_macro_.reverse.join("\n") end
method_missing(method,*args,&block)
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例化模块
Calls superclass method
# File lib/tdl/sdlmodule/sdlmodule.rb, line 298 def method_missing(method,*args,&block) rel = nil ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do @@_method_missing_sub_methds ||= [] @@_method_missing_sub_methds.each do |me| rel = self.send(me,method,*args,&block) if rel rel end end ## 最后才调用阴性例化模块 rel = implicit_inst_module_method_missing(method,*args,&block) if rel rel else super end end return rel end
negedge(origin=nil)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 179 def negedge(origin=nil) rel = ClassHDL::ClassNegedge.new(self) rel.origin = origin return rel end
output(args={})
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# File lib/tdl/class_hdl/hdl_module_def.rb, line 372 def output(args={}) return ClassHDL::ImplicitPortOutput.new(self,args) end
parameter()
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# File lib/tdl/class_hdl/hdl_parameter.rb, line 53 def parameter return HDLClass::ImplicitInstParam.new(self) end
Also aliased as: param
parents_inst_tree(collect=[]) { |dc| ... }
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获取模块的树状结构 父 [self,[ [P0,inst-name], [P1,] [P3, inst-name]] ]
# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 571 def parents_inst_tree(collect=[],&block) rels = [] # parent_rels = [] @instanced_and_parent_module.each do |k,v| # ## 获取generate tree # if v.is_a? ClassHDL::GenerateBlock # dc = collect.dup # dc << v # dc << v.belong_to_module # v.parents_inst_tree(dc,&block) # elsif v.is_a? ClassHDL::ClearGenerateSlaverBlock # dc = collect.dup # dc << v.belong_to_module # dc << v.belong_to_module.belong_to_module # v.parents_inst_tree(dc,&block) # end # v.instance_variable_get("@sub_instanced").each do |sm| v.instance_and_children_module.each do |ck,cv| sm = ck dc = collect.dup if sm.origin == self # rels << sm if v.instanced_and_parent_module.empty? dc << sm dc << v rels << dc yield dc if block_given? else dc << sm unless cv.is_a?(ClassHDL::ClearGenerateSlaverBlock) v.parents_inst_tree(dc,&block) end end end end rels end
path_refs() { |new_name| ... }
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获取信号的绝对路径
# File lib/tdl/sdlmodule/sdlmodule.rb, line 434 def path_refs(&block) collects = [] if self != TopModule.current.techbench @instances.each do |it| it.origin.parents_inst_tree do |tree| ll = ["$root"] rt = tree.reverse rt.each_index do |index| if rt[index].respond_to? :module_name ll << rt[index].module_name else ll << rt[index].inst_name end end # ll << it.inst_name new_name = ll.join('.').to_nq if block_given? if yield(new_name) collects << new_name end else collects << new_name end end end else collects = ["$root.#{self.module_name}".to_nq] end collects end
port()
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端口定义
# File lib/tdl/class_hdl/hdl_ex_defarraychain.rb, line 225 def port # return ClassHDL::PortDefChain.new(self) return TdlSpace::DefPortArrayChain.new(self) end
posedge(origin=nil)
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# File lib/tdl/class_hdl/hdl_always_ff.rb, line 173 def posedge(origin=nil) rel = ClassHDL::ClassPosedge.new(self) rel.origin = origin return rel end
pretty_ref_hdl_moduls_echo()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 405 def pretty_ref_hdl_moduls_echo index = 1 _indexs = [] _names = [] _paths = [] max_size = 0 ref_modules.each do |e| _indexs << index _names << e.module_name _paths << File.expand_path(e.real_sv_path) index += 1 if e.module_name.size > max_size max_size = e.module_name.size end end puts(pagination(" Modules of <#{module_name}> reference")) # fstr = "[%#{index.to_s.size}d] %-#{ _names.map do |e| e.size end.max }s %s" fstr = "[%#{index.to_s.size}d] %-#{ max_size }s %s" (index-1).times do |xi| puts (fstr % [_indexs[xi], _names[xi], _paths[xi]]) end end
ref_modules()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 383 def ref_modules curr_refs = __ref_children_modules__.flatten.uniq.reject do |e| e.is_a?(ClassHDL::ClearSdlModule) end curr_refs << self end
require_hdl(*hdl_path)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 536 def require_hdl(*hdl_path) hdl_path.each do |hp| __require_hdl__(hp,self) end end
require_package(tdl_package_str,ex_code=true)
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# File lib/tdl/class_hdl/hdl_package.rb, line 168 def require_package(tdl_package_str,ex_code=true) # puts tdl_package if SdlModule.exist_module?(tdl_package_str) && SdlModule.call_module(tdl_package_str).instance_of?(ClassHDL::SdlPackage) tdl_package = SdlModule.call_module(tdl_package_str) @_import_packages_ ||= [] @_import_packages_ << tdl_package if ex_code self.ex_up_code ||= '' self.ex_up_code += "import #{tdl_package.module_name}::*;\n" end else raise TdlError.new("Dont have packge #{tdl_package_str}") end define_singleton_method(tdl_package_str) do SdlModule.call_module(tdl_package_str) end ## 替换掉 package 里面 DefStruct 指向的 sdlmodule metac = tdl_package.instance_variable_get("@_struct_meta_collect_") || [] metac.each do |e| e.sdlm = self end end
root_ref(&block)
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定义获取 信号的绝对路径
# File lib/tdl/sdlmodule/sdlmodule.rb, line 466 def root_ref(&block) ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do rels = path_refs(&block) if block_given? sst = "block given" else sst = "no block" end if rels.size == 1 rels[0] elsif rels.size == 0 raise TdlError.new "#{module_name} Cant find root ref {#{sst}}" else raise TdlError.new "#{module_name} Find multi root refs {#{sst}} \n#{rels.join("\n")}\n" end end end
rubyOP(&block)
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# File lib/tdl/class_hdl/hdl_redefine_opertor.rb, line 506 def rubyOP(&block) ClassHDL::AssignDefOpertor.with_rollback_opertors(:old,&block ) end
same_clock_domain(*vars)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 327 def same_clock_domain(*vars) objs = vars.map do |c| ## interface if c.respond_to?(:clock) && c.clock.respond_to?(:freqM) c.clock.freqM ## Clock elsif c.is_a?(Clock) c.freqM else ## other nil end end.uniq.compact if objs.size > 1 raise TdlError.new " dont same clock domain" end ## verification in HDL objs_clks = vars.map do |c| ## interface if c.respond_to?(:clock) if c.dimension && c.dimension.any? c.clock else c.clock end ## Clock elsif c.is_a?(Clock) c else ## other c end end Clock.same_clock(self, *objs_clks) end
show_ports()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 250 def show_ports puts pagination("clock") hash_show @port_clocks puts pagination("reset") hash_show @port_resets puts pagination("parameter") hash_show @port_params puts pagination("logic") hash_show @port_logics puts pagination("datainf") hash_show @port_datainfs puts pagination("datainf_c") hash_show @port_datainf_c_s puts pagination("videoinf") hash_show @port_videoinfs puts pagination("axistream") hash_show @port_axisinfs puts pagination("axi4") hash_show @port_axi4infs puts pagination("axilite") hash_show @port_axilinfs end
signal(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 26 def signal(name) method(name).call end
top_module_ref?()
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# File lib/tdl/sdlmodule/top_module.rb, line 513 def top_module_ref? if self == TopModule.current.techbench return true end instanced_and_parent_module.values.each do |pm| if pm.is_a?(TopModule) return true else if pm.instanced_and_parent_module.any? if pm.top_module_ref? return true end end end end return false end
top_tb_ref?()
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# File lib/tdl/sdlmodule/top_module.rb, line 531 def top_tb_ref? return false unless TopModule.current if self == TopModule.current.techbench return true end instanced_and_parent_module.values.each do |pm| if pm == TopModule.current.techbench ##pm.is_a?(TechBenchModule) return true else if pm.instanced_and_parent_module.any? if pm.top_tb_ref? return true end end end end return false end
track_signals_hash()
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 33 def track_signals_hash @__track_signals_hash__ ||=Hash.new unless @__dve_track_flag__ @__track_signals_hash__ else rel = {} rel[@__dve_track_flag__] = @__track_signals_hash__[@__dve_track_flag__] rel end end
tracked_by_dve(flag:nil, &filter_block)
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attr_accessor :dve_wave_signals
# File lib/tdl/sdlmodule/test_unit_module.rb, line 4 def tracked_by_dve(flag:nil, &filter_block) ## 被dve track @@__tracked_by_dve_hash__ ||= Hash.new # if @@__tracked_by_dve_hash__.has_key?(self) # raise TdlError.new(" `#{module_name}` Cant be tracked again!!!") # end @@__tracked_by_dve_hash__[self] = filter_block @__track_filter_block__ = filter_block @__dve_track_flag__ = flag end
try_call_ele(name)
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# File lib/tdl/sdlmodule/bak/sdlmodule_varible_ex.rb, line 107 def try_call_ele(name) # puts SdlModule.allmodule_name if @_add_to_new_module_vars.include?(name.to_s) method(name).call else nil end end
urandom_range(a,b)
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# File lib/tdl/class_hdl/hdl_random.rb, line 16 def urandom_range(a,b) return "$urandom_range(#{a},#{b})".to_nq end
var_common(a) { |a| ... }
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# File lib/tdl/sdlmodule/sdlmodule_varible.rb, line 126 def var_common(a,&block) class_v = a.class unless self.instance_variable_get("@#{class_v}_collect") self.instance_variable_set("@#{class_v}_collect",[]) end unless self.instance_variable_get("@#{class_v}_id") self.instance_variable_set("@#{class_v}_id",1) end a.id = self.instance_variable_get("@#{class_v}_id") self.instance_variable_set("@#{class_v}_id",a.id+1) a.belong_to_module = self self.instance_variable_get("@#{class_v}_collect") << a define_ele(a) if block_given? yield(a) end a end
vars_define_inst()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 171 def vars_define_inst vars = [] @@ele_array.each do |e| head_str = "@#{e.to_s}" vars += self.instance_variable_get("#{head_str}_collect") end ele_str = [] (self.instance_variable_get("@__element_collect__") || [] ).each do |e| rel = e._inner_inst if rel ele_str << rel end end vars_inst = vars.map{ |v| v.inst } var_str = vars_inst.join("\n") var_str +"\n"+ ele_str.join("\n") end
vars_exec_inst()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 193 def vars_exec_inst vars_inst = [] vars_draw = [] @@ele_array.each do |e| head_str = "@#{e.to_s}" vars_inst |= self.instance_variable_get("#{head_str}_inst") vars_draw |= self.instance_variable_get("#{head_str}_draw") end vars_inst_str = vars_inst.map do |e| if e.is_a? String e elsif e.is_a? Proc e.call end end.join("\n") vars_draw_str = vars_draw.map do |e| if e.is_a? String e elsif e.is_a? Proc e.call end end.join("\n") vars_inst_str + vars_draw_str end
vcs_string(total=64,local=false)
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# File lib/tdl/class_hdl/hdl_parameter.rb, line 65 def vcs_string(total=64,local=false) a = HDLClass::ImplicitInstParam.new(self) self.macro_add_vcs a.vcs_string = total a.local = local return a end
verify()
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# File lib/tdl/class_hdl/hdl_verify.rb, line 133 def verify vinst = ClassHDL::Verify.new(self) end
Private Instance Methods
add_method_to_itgt(stringbanditegration,obj)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 56 def add_method_to_itgt(stringbanditegration,obj) StringBandItegration.add_method_to_itgt(stringbanditegration,obj) end
add_new_after_inst(baseele)
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# File lib/tdl/sdlmodule/sdlmodule_instance.rb, line 481 def add_new_after_inst(baseele) @instanced_and_parent_module ||= Hash.new if baseele.is_a? Parameter instanced_and_parent_module.each do |k_inst,v_module| v_module.method(k_inst.inst_name).call.inst_param_hash[baseele.name.to_s] = nil end else instanced_and_parent_module.each do |k_inst,v_module| v_module.method(k_inst.inst_name).call.inner_port_hash[baseele.name.to_s] = baseele v_module.method(k_inst.inst_name).call.inst_port_hash[baseele.name.to_s] = NqString.new("") end end end
add_sub_module_file_paths()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 330 def add_sub_module_file_paths "" end
align_tt(max_len,tt,tap=1)
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 274 def align_tt(max_len,tt,tap=1) tt+" "*(max_len+tap-tt.length) end
build_params(ex_str="")
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 236 def build_params(ex_str="") "Draw Parameters of sv module" str = [] max_len = 0 @port_params.each do |k,v| if v.port_length > max_len max_len = v.port_length; end end @port_params.each do |k,v| str << " " + v.inst_port(max_len-v.port_length) end unless ex_str.empty? head_tap = '//------>> EX PARAMETER <<-------------------'+"\n" end_tap = "\n//------<< EX PARAMETER >>-------------------"+"\n" else head_tap = "" end_tap = "" end if str.empty? if ex_str.empty? return "" else # ex_str.gsub!(/,\s*$/m,"") return "#(\n" + head_tap + ex_str + end_tap + "\n)" end else # if (ex_str !~ /,\s*$/m) # ex_str = ex_str + ",\n" unless ex_str.empty? # end "#(\n" + head_tap + ex_str + end_tap + str.join(",\n")+"\n)" end end
build_ports(ex_str="")
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 278 def build_ports(ex_str="") "Draw Ports of sv module" "<T0> type.[.]... <T1>name <T2> Array" str = [] # ports = (@port_clocks + @port_resets + @port_logics + @port_datainfs + @port_datainf_c_s + @port_videoinfs + @port_axisinfs + @port_axi4infs + @port_axilinfs) t0 = [] t1 = [] t2 = [] @ports ||= Hash.new @ports.each do |k,v| tmp = v.inst_port t0 << tmp[0] t1 << tmp[1] t2 << tmp[2] end max_len_t0 = t0.map { |e| e.length }.max max_len_t1 = t1.map { |e| e.length }.max max_len_t2 = t2.map { |e| e.length }.max t0.each_index do |index| str << " "+align_tt(max_len_t0,t0[index])+align_tt(max_len_t1,t1[index])+align_tt(max_len_t2,t2[index]) end str = str.map { |e| e.rstrip }.join(",\n") unless ex_str.empty? head_tap = '//------>> EX PORT <<-------------------'+"\n" end_tap = "\n//------<< EX PORT >>-------------------"+"\n" else head_tap = "" end_tap = "" end if str.empty? if ex_str.empty? return "();" else # ex_str.gsub!(/,\s*$/m,"") return "(\n" + head_tap + ex_str + end_tap + "\n);\n" end else ex_str = ex_str.rstrip if ex_str[ex_str.length] != "," && !ex_str.empty? ex_str = ex_str + ",\n" end "(\n" + head_tap + ex_str + end_tap + str+"\n);\n" end end
create_ghost()
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 71 def create_ghost @@ele_array.each do |e| head = e.to_s if e.is_a? String next end tmp = e.new(name:"#{head}_NC",belong_to_module: self) tmp.belong_to_module = self tmp.ghost = true instance_variable_set("@#{head}_NC",tmp) class << tmp def signal @_id_ ||= 0 str = @_id_.to_s @_id_ += 1 str end end end end
def_main_method(name)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 44 def def_main_method(name) name = name.to_s unless name =~ /^[a-zA-Z]([a-zA-Z0-9]|_)*[a-zA-Z0-9]$/ raise TdlError.new("SdlModule name ERROR: `#{name}`") end if @@allmodule_name.include? name tm = SdlModule.call_module(name) raise TdlError.new("sdlmodule[#{name}]<#{path}> already be created before PATH[#{tm.path.to_s}]") end @@allmodule_name << name $__sdl_curr_self__.instance_variable_set("@#{name}",self) # main.instance_variable_set("@#{name}",self) $__sdl_curr_self__.define_singleton_method(name) do # main.define_singleton_method(name) do self.instance_variable_get("@#{name}") end end
generate_block_inst(arg=[0,8],index=0,body_str="")
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# File lib/tdl/class_hdl/hdl_generate.rb, line 198 def generate_block_inst(arg=[0,8],index=0,body_str="") if arg.respond_to?(:first) && arg.respond_to?(:last) start = arg.first stop = arg.last else start = 0 stop = arg end if start.is_a?(Integer) && stop.is_a?(Integer) if start < stop flag = "<" else flag = ">" end else flag = "<" end head_str = "for(genvar KK#{index}=#{start};KK#{index} #{flag} #{stop};KK#{index}#{flag=="<" ? '++' : '--'})begin\n" gbody_str = body_str.gsub(/^./){ |m| " #{m}"} return head_str+gbody_str+"end\n" end
generate_block_inst_iterate(body_str,args)
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# File lib/tdl/class_hdl/hdl_generate.rb, line 187 def generate_block_inst_iterate(body_str,args) index = args.size-1 bstr = body_str args.reverse.each do |arg| bstr = generate_block_inst(arg,index=index,bstr) index -= 1 end return bstr end
hash_show(hash)
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# File lib/tdl/sdlmodule/sdlmodule.rb, line 275 def hash_show(hash) hash.each do |k,v| puts "#{k} CLASS:#{v.class} " end end
head_class()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 217 def head_class case(@target_class.to_s) when "AxiStream" '(* axi_stream = "true" *)' when "Axi4" '(* axi4 = "true" *)' when "AxiLite" '(* axi_lite = "true" *)' when "VideoInf" '(* videoinf = "true" *)' when "DataInf" '(* data_inf = "true" *)' when "DataInf_C" '(* data_inf_c = "true" *)' else @target_class.to_s end end
module_head()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 203 def module_head %Q{#{$__sdlmodule_head_logo__} #{macro_def} #{head_class} } end
module_head_verb()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 210 def module_head_verb %Q{#{$__sdlmodule_head_logo__.sub(/created:.*/, "created: #{Time.now()}")} #{macro_def} #{head_class} } end
old_module_head()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 187 def old_module_head %Q{/********************************************** _______________________________________ ___________ Cook Darwin __________ _______________________________________ descript: author : Cook.Darwin Version: VERA.0.0 created: #{Time.now()} madified: ***********************************************/ #{macro_def} #{head_class} } end
parse_pin_prop(prop=nil)
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port_name_chk(name)
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# File lib/tdl/sdlmodule/sdlmodule_port_define.rb, line 43 def port_name_chk(name) if name.is_a?( String )|| name.is_a?( Symbol) return else raise TdlError.new("Port of #{@module_name} must be defined in String or Symbol") end end
post_inst_stack_call()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 36 def post_inst_stack_call str = '' @@ele_array.each do |e| head_str = "#{e.to_s}" method("#{head_str}_post_inst_stack").call.each do |proc| str += proc.call end end str end
pre_inst_stack_call()
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# File lib/tdl/sdlmodule/sdlmodule_draw.rb, line 27 def pre_inst_stack_call @@ele_array.each do |e| head_str = "#{e.to_s}" method("#{head_str}_pre_inst_stack").call.each do |proc| proc.call end end end