class ClassHDL::ImplicitPortBase

Attributes

_struct_q[RW]
chain[RW]
sdlm[RW]
speciel_type[RW]
sub_type[RW]

Public Class Methods

new(sdlm,args={}) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 170
def initialize(sdlm,args={})
    @chain = []
    @sdlm = sdlm
    unless @sdlm 
        raise TdlError.new("ImplicitPortBase<#{args.to_s}> dont have belong_to_module")
    end
    @up_args = args
end

Public Instance Methods

-(name) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 193
def - (name)
    if name !~ /\w+/
        raise TDLError.new("PORT #{name} Illegle ")
    end

    if name.is_a? StringBandItegration
        raise TDLError.new("简化定义模式不允许传入 StringBandItegration 类型")
    end

    args = @up_args
    # @sdlm.Input(method,dsize:args[:dsize] || 1,dimension:args[:dimension]||[],pin:args[:pin]||[],iostd:args[:iostd]||[],pin_prop:args[:pin_prop])
    if $_implicit_curr_itgt_.slast
        name = name.to_inp($_implicit_curr_itgt_.last)
    end

    ## >>>>当使用 chain 定义时忽略 args dimension<<<
    ## 修改成当为struct时 需要不同处理方式
    
    if @chain.any? 
        unless @_struct_q
            args[:dsize] = @chain.last
            if @chain[1]
                args[:dimension] = @chain[0,@chain.size-1]
            end
        else 
            args[:dimension] = @chain
        end
    end

    sdlm_port(name,args)
end
[](*a) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 286
def [](*a)
    if a.empty?
        raise TdlError.new("参数不能为空")
    end
    # @chain ||= []
    new_dla = self.class.new(@sdlm,@up_args)
    new_dla.chain = @chain + a
    ## 继承
    new_dla._struct_q = _struct_q
    new_dla.speciel_type = speciel_type
    new_dla.sub_type = sub_type
    new_dla
end
add_struct_method(obj) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 300
def add_struct_method(obj)
    if sub_type.is_a? StructMeta
        @sub_type.struct_slots.each do |e|
            obj.define_singleton_method(e.name) do 
                TdlSpace::ArrayChain.create(obj: "#{obj.name}.#{e.name}".to_nq, belong_to_module: obj.belong_to_module)
            end
        end
    end
end
clock(*args) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 225
def clock(*args)
    if args.any?
        if args[0].is_a? Hash 
            @clock_freqM = args[0][:freqM]
        else 
            @clock_freqM = args[0]
        end 
    else  
        @clock_freqM = nil
    end
    return self
end
logic() click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 183
def logic 
    @speciel_type = 'logic'
    return self
end
method_missing(method,*args,&block) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 251
def method_missing(method,*args,&block)
    ## 检查是否有用户定义的类型数据
    if @sdlm.respond_to?(method)
        if @sdlm.send(method).is_a?(EnumStruct)
            self.speciel_type = @sdlm.send(method).typedef_name
            self.sub_type = @sdlm.send(method)  ## 针对struct 内元素
            self
        elsif @sdlm.send(method).is_a?(StructMeta)
            self.speciel_type = @sdlm.send(method).name
            self.sub_type = @sdlm.send(method) ## 针对struct 内元素
            self
        else 
            ## 判断 是否是头部引入的包
            ##  input.<package_name> 返回自身calss
            # if method.to_s.eql? @sdlm.head_import_package.to_s
            if @sdlm.head_import_packages.map{ |e| e.to_s }.include?(method.to_s )
                package_name = method.to_s
                return ImplicitPortBasePackage.new(self,package_name)
            else 
                ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
                    args = args[0] || {}
                    @up_args = @up_args.merge(args)
                    self.-(method)
                end
            end
        end
    else 
        ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do 
            args = args[0] || {}
            @up_args = @up_args.merge(args)
            self.-(method)
        end
    end
end
reset(*args) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 238
def reset(*args)
    if args.any?
        if args[0].is_a? Hash 
            @reset_active = args[0][:active]
        else 
            @reset_active = args[0]
        end 
    else  
        @reset_active = nil
    end
    return self
end
sdlm_port(method=nil,args={}) click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 179
def sdlm_port(method=nil,args={})
    raise TDLError.new "ImplicitPortBase slot <#{method}>"
end
wire() click to toggle source
# File lib/tdl/class_hdl/hdl_module_def.rb, line 188
def wire 
    @speciel_type = 'wire'
    return self 
end