class Logic
class Logic
#定义取反
define_method("!") do "!#{signal}" end
end
Constants
- INOUT
- INPUT
- OP_SYMBOLS
- OUTPUT
- Synth_REP
parse text for autogen method and constant ###
Attributes
clock[RW]
@@logic_expression = [] @@logic_expression_def = [] @@logic_expression_record = []
@@condition_expression = []
dimension[R]
dsize[RW]
attr_reader :dsize
ghost[RW]
attr_reader :dsize
id[RW]
attr_reader :dsize
name[RW]
attr_reader :dsize
port[R]
reset[RW]
@@logic_expression = [] @@logic_expression_def = [] @@logic_expression_record = []
@@condition_expression = []
type[RW]
attr_reader :dsize
Public Class Methods
exp_element(b)
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# File lib/tdl/Logic/logic_main.rb, line 165 def self.exp_element(b) if b.is_a? Proc b.call else b.to_s end end
new(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic",belong_to_module: nil) { || ... }
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# File lib/tdl/elements/logic.rb, line 24 def initialize(name:"tmp",dsize:1,port: false,default: nil,msb_high: true,dimension: [],type: "logic",belong_to_module: nil) @name = name # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Logic.id @dsize = dsize @port = port @default = default # @msb_high = msb_high @dimension = dimension @type = type # raise TdlError.new("#{name} DATA ERROR") unless dsize.is_a? Fixnum # raise TdlError.new("STOP") if @id == 10 name_legal?(name) if block_given? yield end @belong_to_module = belong_to_module unless @belong_to_module raise TdlError.new("Logic<#{@name}> be not belong_to_module") end end
parse_ports(port_str)
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Calls superclass method
SignalElm::parse_ports
# File lib/tdl/elements/logic.rb, line 286 def self.parse_ports(port_str) rh = super.parse_ports(port_str) rh[:type] = Logic return rh end
Public Instance Methods
Initial() { |self| ... }
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# File lib/tdl/bfm/logic_initial_block.rb, line 4 def Initial(&block) @_lg_init_tap_cnt_ = 1 @_init_exec_stack = [] yield(self) str = initial_block(@_init_exec_stack.join()) # Logic.add_ex_expression(lambda { str }) belong_to_module.Logic_draw << str end
[](a,b=nil)
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# File lib/tdl/elements/logic.rb, line 57 def [](a,b=nil) # if dimension.empty? # if a.eql?(:all) # square = "" # elsif b # square = "[#{a}:#{b}]" # else # square = "[#{a}]" # end # if @port # NqString.new("#{@name.to_s}#{square}") # else # NqString.new("#{name}#{square}") # end # else if a.is_a? ClassHDL::OpertorChain a.slaver = true end if b.is_a? ClassHDL::OpertorChain b.slaver = true end ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module) end end
[]=(a,b=nil,c)
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# File lib/tdl/elements/logic.rb, line 88 def []=(a,b=nil,c) if a.is_a? ClassHDL::OpertorChain a.slaver = true end if b.is_a? ClassHDL::OpertorChain b.slaver = true end # b = a unless b if c.is_a? Logic cstr = c.signal elsif c.is_a? String cstr = c else "" end lbd = "assign #{self.[](a,b)} = #{cstr};" # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.pre_inst << lambda do # lbd # end belong_to_module.Logic_draw << lbd return lbd end
active()
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# File lib/tdl/elements/logic.rb, line 53 def active "low" end
broaden_and_cross_clk(phase: "POSITIVE",len:4,lat:2,wclk: nil,rreset: "1'b1".to_nq,rclk: nil,wreset: "1'b1".to_nq,name: nil)
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# File lib/tdl/Logic/logic_latency.rb, line 80 def broaden_and_cross_clk(phase: "POSITIVE",len:4,lat:2,wclk: nil,rreset: "1'b1".to_nq,rclk: nil,wreset: "1'b1".to_nq,name: nil) if wclk.nil? || rclk.nil? raise TdlError.new("\n #{self.to_s} BROADEN_AND_CROSS_CLK <clock = nil> \n") end new_l = belong_to_module.Def().logic(name:name || "broaden_and_cross_clk_#{globle_random_name_flag()}",dsize:1) large_name_len(phase,len,wclk,wreset,rclk,rreset) body = " broaden_and_cross_clk #( .PHASE (#{align_signal(phase)}), //POSITIVE NEGATIVE .LEN (#{align_signal(len)}), .LAT (#{align_signal(lat)}) )#{new_l.signal}_inst_#{globle_random_name_flag()}( /* input */ .rclk (#{align_signal(rclk,q_mark=false)}), /* input */ .rd_rst_n (#{align_signal(rreset,q_mark=false)}), /* input */ .wclk (#{align_signal(wclk,q_mark=false)}), /* input */ .wr_rst_n (#{align_signal(wreset,q_mark=false)}), /* input */ .d (#{align_signal(self,q_mark=false)}), /* output */ .q (#{align_signal(new_l,q_mark=false)}) ); " belong_to_module.Logic_draw << page(tag:"BROADEN_AND_CROSS_CLK",body:body) return new_l end
copy(name:@name.to_s,dsize:@dsize,port:@port,default:@default,msb_high:@msb_high,dimension:@dimension,type:@type,belong_to_module:@belong_to_module)
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# File lib/tdl/elements/logic.rb, line 48 def copy(name:@name.to_s,dsize:@dsize,port:@port,default:@default,msb_high:@msb_high,dimension:@dimension,type:@type,belong_to_module:@belong_to_module) append_name = name_copy(name) belong_to_module.Def.logic(name:append_name,dsize:dsize,port:port,default:default,msb_high:msb_high,dimension:dimension,type:type) end
cross_clock(clock:nil,name: false)
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# File lib/tdl/Logic/logic_latency.rb, line 48 def cross_clock(clock:nil,name: false) raise TdlError.new("\n #{signal} CROSS CLOCK <clock = nil> \n") unless clock # new_l = Logic.new(name:"#{signal(square:false)}_cc",dsize:self.dsize) new_l = nil ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do unless name new_l = belong_to_module.Def.logic(name:"#{signal(square:false)}_cc",dsize:self.dsize) else new_l = belong_to_module.Def.logic(name: name.to_s ,dsize:self.dsize) end str = %Q{ //----->> #{signal} cross clock <<------------------ cross_clk_sync #( .LAT (2 ), .DSIZE (#{dsize}) )#{signal(square:false)}_cross_clk_#{name ? name.to_s : '' }inst( /* input */ .clk (#{align_signal(clock)}), /* input */ .rst_n (#{align_signal("1'b1")}), /* input [DSIZE-1:0] */ .d (#{align_signal(self)}), /* output[DSIZE-1:0] */ .q (#{align_signal(new_l)}) ); //-----<< #{signal} cross clock >>------------------ } # @@logic_expression << lambda{ str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ str } belong_to_module.Logic_draw << str end return new_l end
destruct_to(*args)
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# File lib/tdl/elements/logic.rb, line 248 def destruct_to(*args) m = args.map do |e| align_signal(e) end # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.inst_stack += "\nassign #{signal} = {#{m.join(',')}};\n" belong_to_module.Logic_draw << "\nassign {#{m.join(',')}} = #{signal};\n" end
exp_element(b)
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def signal_proc(a)
if a.is_a? Proc a.call else a.to_s end
end
# File lib/tdl/Logic/logic_main.rb, line 157 def exp_element(b) if b.is_a? Proc b.call else b.to_s end end
falling(cnt:1,clock:nil,reset:nil)
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# File lib/tdl/Logic/logic_edge.rb, line 47 def falling(cnt:1,clock:nil,reset:nil) @logic_expression_record ||= Hash.new @clock = clock if clock @reset = reset if reset head_str = "" end_str = "" str = "" # RedefOpertor.with_normal_operators do ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do head_str = "\n//====>>>> #{signal} FEDGE <<<<#{"="*(60-6-signal.length)}\n" end_str = "//----<<<< #{signal} FEDGE >>>>#{"-"*(60-6-signal.length)}\n" # end # @@logic_expression << lambda{ head_str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str } belong_to_module.Logic_draw << head_str inst_edge(@clock,@reset) if cnt>1 inst_fall_edge_cnt(cnt-1) str = inst_cnt_edge_signal(cnt-1,:fall) else str = "#{signal}_falling" end # @@logic_expression << lambda{ end_str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str } belong_to_module.Logic_draw << end_str end return str.to_nq end
force_nege_index(bool=true)
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# File lib/tdl/elements/logic.rb, line 143 def force_nege_index(bool=true) @nege_index = bool end
init_assign(value)
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# File lib/tdl/bfm/logic_initial_block.rb, line 13 def init_assign(value) vstr = RedefOpertor.with_normal_operators do with_new_align(0) do align_signal(value,q_mark=false) end end @_init_exec_stack << "#{logic_init_tap}#{signal} = #{vstr};\n" end
init_exec(str)
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# File lib/tdl/bfm/logic_initial_block.rb, line 22 def init_exec(str) @_init_exec_stack << "#{logic_init_tap}#{str};\n" end
inst()
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# File lib/tdl/elements/logic.rb, line 147 def inst # if (@port != :origin) # lname = "#{name}_id#{@id}" # else # lname = @name.to_s # end lname = @name.to_s unless @ghost if dsize.eql?(1) && dimension.empty? str = "#{@type} #{lname}#{@default ? " = #{align_signal(@default)};" : ";"}" else if (@dsize.is_a? Numeric) && @dsize < 0 str = "#{@type} [0:#{(-@dsize-1)}] #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}" elsif @nege_index str = "#{@type} [0:#{@dsize}-1] #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}" else str = "#{@type} [#{@dsize}-1:0] #{lname}#{array_inst} #{@default ? " = #{align_signal(@default)};" : ";"}" end end else str = "" end str end
inst_port()
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# File lib/tdl/elements/logic.rb, line 187 def inst_port if dsize.eql? 1 n = " #{@type}" else n = " #{@type}[#{(@dsize-1)}:0]" end return [@port.to_s + n, @name.to_s,array_inst] end
latency(count:1,clock:nil,reset:nil)
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# File lib/tdl/Logic/logic_latency.rb, line 3 def latency(count:1,clock:nil,reset:nil) unless clock sclk = @__clock__ else sclk = clock end unless reset srst = @__reset__ else srst = reset end unless sclk raise TdlError.new("latency clock is nil") end unless srst raise TdlError.new('latency reset is nil') end # new_l = Logic.new(name:" #{signal(square:false)}_lat",dsize:self.dsize) new_l = belong_to_module.Def.logic(name:"#{signal(square:false)}_lat",dsize:self.dsize) str = %Q{ //----->> #{signal} LAST DELAY <<------------------ latency #( .LAT (#{count}), .DSIZE (#{dsize}) )#{signal(square:false)}_lat#{count}_inst( #{sclk}, #{srst}, #{signal}, #{new_l.signal} ); //-----<< #{signal} LAST DELAY >>------------------ } # @@logic_expression << lambda{ str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ str } belong_to_module.Logic_draw << str return new_l end
merge_from(*args)
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def self.clear
@@id = 1 @@inst_stack = [] @@ports = [] @@nc = self.new BaseElm.recfg_nc(@@nc)
end
# File lib/tdl/elements/logic.rb, line 240 def merge_from(*args) m = args.map do |e| align_signal(e) end # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.inst_stack += "\nassign #{signal} = {#{m.join(',')}};\n" belong_to_module.Logic_draw << "\nassign #{signal} = {#{m.join(',')}};\n" end
port_length()
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# File lib/tdl/elements/logic.rb, line 173 def port_length if dsize.eql? 1 n = "" else if @dsize.is_a? Numeric n = "[#{(@dsize.abs-1)}:0]" else n = "[#{(@dsize.to_s-1)}:0]" end end (@port.to_s + n + " ").length end
raising(cnt:1,clock:nil,reset: 1.b1 )
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# File lib/tdl/Logic/logic_edge.rb, line 4 def raising(cnt:1,clock:nil,reset: 1.b1 ) # if cnt==1 && clock == nil && reset==nil && @raising_record # return @raising_record # end @logic_expression_record ||= Hash.new str = "" # RedefOpertor.with_normal_operators do @clock = clock if clock @reset = reset if reset head_str = "" end_str = "" # RedefOpertor.with_normal_operators do ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do head_str = "\n//====>>>> #{signal} RAISING EDGE <<<<#{"="*(60-6-signal.length)}\n" end_str = "\n//----<<<< #{signal} RAISING EDGE >>>>#{"-"*(60-6-signal.length)}\n" # @@logic_expression << lambda{ head_str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ head_str } belong_to_module.Logic_draw << head_str inst_edge(@clock,@reset) if cnt>1 inst_raise_edge_cnt(cnt-1) str = inst_cnt_edge_signal(cnt-1,:raise) else str = "#{signal}_raising" end # @@logic_expression << lambda{ end_str } # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda{ end_str } belong_to_module.Logic_draw << end_str end # if cnt==1 && clock == nil && reset==nil # @raising_record = str.to_nq # end return str.to_nq end
repeat(num=0) { || ... }
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# File lib/tdl/bfm/logic_initial_block.rb, line 26 def repeat(num=0,&block) if num > 0 @_init_exec_stack << "#{logic_init_tap}repeat(#{num.to_s}) begin\n" else @_init_exec_stack << "#{logic_init_tap}forever begin\n" end @_lg_init_tap_cnt_ += 1 yield @_lg_init_tap_cnt_ -= 1 @_init_exec_stack << "#{logic_init_tap}end\n" end
signal(h:nil,l:0,square:true)
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# File lib/tdl/elements/logic.rb, line 114 def signal(h:nil,l:0,square:true) if h.is_a? Numeric if @dsize.is_a?(Numeric) && (h > @dsize-1) h = @dsize - 1 end h = h elsif @dsize.is_a? Numeric h = (@dsize.abs-1) else h = "#{@dsize}-1" end if @port NqString.new (@name.to_s) elsif !square || @dimension.any? NqString.new("#{name}") elsif dsize.eql? 1 NqString.new("#{name}") else NqString.new("#{name}[#{h}:#{l}]") end end
to_s()
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# File lib/tdl/elements/logic.rb, line 137 def to_s ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do signal(square:false) end end
to_sim_source_coe(data: (0...100).to_a, posedge: nil ,negedge: nil ,loop_coe: true)
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# File lib/tdl/exlib/logic_verify.rb, line 58 def to_sim_source_coe(data: (0...100).to_a, posedge: nil ,negedge: nil ,loop_coe: true) raise TdlError.new(" posedge negedge both nil") unless (posedge || negedge ) # raise TdlError.new "file cant be empty" unless file file = File.join(AxiTdl::TDL_PATH,"./auto_script/tmp/","#{self.name}_#{globle_random_name_flag}.coe") _len = 1000 ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do require_hdl 'logic_sim_model.sv' itr = AxiTdl::LogicVerify::Iteration.new(length: data.size, data: data ) File.open(file,'w') do |f| f.puts itr.coe end _len = itr.context.size end @belong_to_module.instance_exec(self,_len, posedge || 1.b0 , negedge || 1.b0 ,file, loop_coe) do |_self,_len,next_at_posedge_of,next_at_negedge_of,file,loop_coe| Instance(:logic_sim_model, "#{_self.name}_sim_model_inst") do |h| h.param.LOOP (loop_coe ? "TRUE" : "FALSE") h.param.DSIZE _self.dsize h.param.RAM_DEPTH _len h.input.next_at_negedge_of next_at_negedge_of h.input.next_at_posedge_of next_at_posedge_of h.input.load_trigger 1.b0 h.input[32].total_length _len h.input[512*8].mem_file File.expand_path(file) h.output['DSIZE'].data _self end end end
Private Instance Methods
initial_block(str)
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# File lib/tdl/bfm/logic_initial_block.rb, line 44 def initial_block(str) @_init_index_ ||=0 " initial begin:#{signal(square:false)}_INIT_BLOCK_#{@_init_index_ += 1} #{str} end " end
inst_cnt_edge_signal(cnt=1,type=:raise)
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# File lib/tdl/Logic/logic_edge.rb, line 82 def inst_cnt_edge_signal(cnt=1,type=:raise) return "#{signal}_#{cnt}_#{type}" if @logic_expression_record["#{cnt}_#{type}"] # @@logic_expression_def << lambda {"logic #{signal}_#{cnt}_#{type};"} # @@logic_expression << lambda { # " # assign #{signal}_#{cnt}_#{type} = #{signal}_edge_#{type}_cnt==#{cnt}; # "} # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression_def << lambda {"logic #{signal}_#{cnt}_#{type};"} belong_to_module.Logic_inst << "logic #{signal}_#{cnt}_#{type};" # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda { # " # assign #{signal}_#{cnt}_#{type} = #{signal}_edge_#{type}_cnt==#{cnt}; # "} belong_to_module.Logic_draw << "assign #{signal}_#{cnt}_#{type} = #{signal}_edge_#{type}_cnt==#{cnt};" return "#{signal}_#{cnt}_#{type}" end
inst_edge(clock,reset)
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# File lib/tdl/Logic/logic_edge.rb, line 100 def inst_edge(clock,reset) return "" if @logic_expression_record[:inst_edge] raise TdlError.new("#{@name} DSIZE[#{@dsize}] dont eq 1 ") unless @dsize == 1 # @@logic_expression_def << lambda { # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression_def << lambda { # " # logic #{signal}_raising; # logic #{signal}_falling; # "} # belong_to_module.Logic_inst << lambda { # " # logic #{signal}_raising; # logic #{signal}_falling; # "} belong_to_module.Def().logic(name:"#{signal}_raising") belong_to_module.Def().logic(name:"#{signal}_falling") # @@logic_expression << lambda { # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda { belong_to_module.Logic_draw << lambda { large_name_len("0"*36) " edge_generator #{signal}edge_generator_inst( /* input */ .clk (#{align_signal(clock,q_mark=false)}), /* input */ .rst_n (#{align_signal(reset,q_mark=false)}), /* input */ .in (#{align_signal(signal,q_mark=false)}), /* output */ .raising (#{align_signal(signal+"_raising",q_mark=false)}), /* output */ .falling (#{align_signal(signal+"_falling",q_mark=false)}) );"} return "" end
inst_edge_cnt(cnt=1,type=:raise)
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# File lib/tdl/Logic/logic_edge.rb, line 152 def inst_edge_cnt(cnt=1,type=:raise) clock_tri = "" rst_tri = "" rst_assign = "if(0)" with_new_align(0) do clock_tri = "posedge #{align_signal(@clock,q_mark=false)}" if @reset if ((@reset.respond_to?(:active)) && (@reset.active.downcase.eql? "high")) rst_tri = ",posedge #{align_signal(@reset,q_mark=false)}" rst_assign = "if(#{align_signal(@reset,q_mark=false)})" else rst_tri = ",negedge #{align_signal(@reset,q_mark=false)}" rst_assign = "if(~#{align_signal(@reset,q_mark=false)})" end else rst_tri = "" rst_assign = "if(0)" end end # @@logic_expression_def << lambda { # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression_def << lambda { belong_to_module.Logic_inst << lambda { " logic [#{cnt.clog2}-1:0] #{signal}_edge_#{type}_cnt; "} # @@logic_expression << lambda { # GlobalParam.CurrTdlModule.BindEleClassVars.Logic.expression << lambda { belong_to_module.Logic_draw << lambda { " always@(#{clock_tri}#{rst_tri}) #{rst_assign} #{signal}_edge_#{type}_cnt <= '0; else begin if(#{type==:raise ? "#{signal}_raising" : "#{signal}_falling"})begin if(#{signal}_edge_#{type}_cnt == '1) #{signal}_edge_#{type}_cnt <= #{signal}_edge_#{type}_cnt; else #{signal}_edge_#{type}_cnt <= #{signal}_edge_#{type}_cnt + 1'b1; end else #{signal}_edge_#{type}_cnt <= #{signal}_edge_#{type}_cnt; end "} end
inst_fall_edge_cnt(cnt=1)
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# File lib/tdl/Logic/logic_edge.rb, line 146 def inst_fall_edge_cnt(cnt=1) count = cnt if count==nil || cnt > count return "" if @logic_expression_record[:inst_fall_edge_cnt] inst_edge_cnt(count,:fall) end
inst_raise_edge_cnt(cnt=1)
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# File lib/tdl/Logic/logic_edge.rb, line 140 def inst_raise_edge_cnt(cnt=1) count = cnt if count==nil || cnt > count return "" if @logic_expression_record[:inst_raise_edge_cnt] inst_edge_cnt(count,:raise) end
logic_init_tap()
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# File lib/tdl/bfm/logic_initial_block.rb, line 40 def logic_init_tap "#{' '*@_lg_init_tap_cnt_}" end
raising_edge(cnt=1)
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# File lib/tdl/Logic/logic_edge.rb, line 132 def raising_edge(cnt=1) if cnt==1 return "#{signal}_raising" else end end