/********************************************** _ _ Cook Darwin __

_ descript: author : Cook.Darwin Version: VERA.0.0 created: 2021-05-04 20:03:33 +0800 madified: ***********************************************/ `timescale 1ns/1ps

module simple_assign_test (); //========================================================================== //——– define ———————————————————- logic [1-1:0] tmp0[2-1:0] ; logic tmp1; data_inf_c #(.DSIZE(8),.FreqM(101)) a_inf (.clock(dclk),.rst_n(drstn)) ; data_inf_c #(.DSIZE(8),.FreqM(101)) c_inf [2:0][7:0] (.clock(dclk),.rst_n(drstn)) ; //========================================================================== //——– instance ——————————————————–

//========================================================================== //——– expression —————————————————— assign tmp1 = tmp0&“FALSE” &&(c_inf.data==3 ||a_inf.valid|1'b0);

endmodule