class InfElm
Attributes
dimension[RW]
Public Class Methods
inherited(subclass)
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# File lib/tdl/elements/originclass.rb, line 313 def self.inherited(subclass) unless @@child.include? subclass @@child << subclass if subclass != CLKInfElm end end
new(dimension:[])
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# File lib/tdl/elements/originclass.rb, line 429 def initialize(dimension:[]) @instance_draw_stack = [] @correlation_proc = "" @dimension = dimension end
parse_ports(port_array=nil,rep,inf_name,up_stream_rep) { |h| ... }
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def left_port_length()
("/* #{@inf_name}." + @port.to_s + " */ ").length
end
def right_port_length
(".#{@name.to_s} ").length
end
def ex_port(left_align_len = 7,right_align_len = 7)
if left_align_len >= left_port_length sub_left_len = left_align_len - left_port_length else sub_left_len = 0 end if right_align_len >= right_port_length sub_right_len = right_align_len - right_port_length else sub_right_len = 0 end if @port ("/* #{@inf_name}." + @port.to_s + " "*sub_left_len + "*/ " + "."+@name.to_s + " "*sub_right_len) end
end
# File lib/tdl/elements/originclass.rb, line 359 def self.parse_ports(port_array=nil,rep,inf_name,up_stream_rep) ports = [] del_ports = [] if port_array ports = port_array.map do |e| me = e.match(rep) if me del_ports << e h = Hash.new h[:type] = AxiLite h[:modport] = me["modport"].downcase if h[:modport]=="master" h[:way] = :to_down elsif h[:modport]=="slaver" h[:way] = :from_up else h[:way] = :mirror end h[:name] = me["name"].downcase h[:origin_name] = me["name"] h[:vector] = me["vector"] if me["vector"] if me["ud_name"] h[:up_down] = me["ud_name"] =~ up_stream_rep ? "up_stream" : "down_stream" else h[:up_down] = "nil" end ## port_left_len = 4+"#{inf_name}.#{h[:modport]}".length+6 port_right_len = 4+h[:origin_name].length h[:port_left_len] = port_left_len h[:port_right_len] = port_right_len h[:inst_ex_port] = lambda {|left,right| if left >= port_left_len ll = left - port_left_len else ll = 1 end if right >= port_right_len rl = right - port_right_len else rl = 1 end "/* #{inf_name}.#{h[:modport]}" + " "*ll+ "*/ " + ".#{h[:origin_name]}"+" "*rl + " (\#{align_signal(#{h[:name]},q_mark=false)})" } yield h ## h else nil end end end # puts port_array,"=====",del_ports return_ports = port_array - del_ports return return_ports end
same_name_socket(way,mix,inf_array,base_new_inf=nil,belong_to_module=nil)
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# File lib/tdl/elements/originclass.rb, line 460 def self.same_name_socket(way,mix,inf_array,base_new_inf=nil,belong_to_module=nil) # return inf_array unless inf_array.is_a? Array unless inf_array.is_a? Array return inf_array if inf_array.respond_to?(:dimension) && inf_array.dimension.any? inf_array = [inf_array] end return nil if inf_array.empty? return inf_array[0] if (inf_array.length == 1 && mix.eql?(true)) unless base_new_inf unless inf_array[0].is_a? String new_inf = inf_array[0].copy() else new_inf = self.string_copy_inf(inf_array[0],belong_to_module) end else new_inf = base_new_inf end unless mix # new_inf = DataInf_C.new(copy_inf:data_c_array[0],dimension:[data_c_array.length]) new_inf.dimension = [inf_array.length] inf_array.each_index do |index| # DataInf_C.data_c_direct(slaver:data_c_array[index],master:new_data_c.signal(index)) if way == :to_down inf_array[index].direct(slaver:new_inf.signal(index)) elsif way == :from_up self.direct(master:new_inf.signal(index),slaver:inf_array[index],belong_to_module:belong_to_module) elsif way == :mirror self.data_c_direct_mirror(master:new_inf.signal(index),slaver:inf_array[index],belong_to_module:belong_to_module) else raise TdlError.new("\nASSIGN Array to port that dont support SAME_NAME_SOCKET\n") end # puts new_inf.signal(index),inf_array[index].signal end else new_inf.<<(*inf_array) end # puts new_data_c.signal return new_inf end
subclass()
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# File lib/tdl/elements/originclass.rb, line 319 def self.subclass @@child end
Public Instance Methods
[](a,b=false)
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# File lib/tdl/elements/originclass.rb, line 446 def [](a,b=false) if a.is_a? ClassHDL::OpertorChain a.slaver = true end if b.is_a? ClassHDL::OpertorChain b.slaver = true end return signal if @dimension.empty? TdlSpace::ArrayChain.create(obj: self,lchain: a, end_slice: b, belong_to_module: belong_to_module) end
dimension_num(e)
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# File lib/tdl/elements/originclass.rb, line 524 def dimension_num(e) if e.is_a? Array return e.size else if e.respond_to?(:dimension) && e.dimension.any? return e.dimension.last else return 1 end end end
draw()
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# File lib/tdl/elements/originclass.rb, line 435 def draw @instance_draw_stack.each do |each_inst| if each_inst.is_a? Proc @correlation_proc += each_inst.call elsif each_inst.is_a? String @correlation_proc += each_inst end end end
inst_port()
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# File lib/tdl/elements/originclass.rb, line 327 def inst_port return ["#{@inf_name}." + @port.to_s, @name.to_s,array_inst] end
port_length()
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# File lib/tdl/elements/originclass.rb, line 323 def port_length() ("#{@inf_name}." + @port.to_s + " ").length end
signal(index=nil)
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重覆盖掉
# File lib/tdl/class_hdl/hdl_redefine_opertor.rb, line 597 def signal(index=nil) #array interface # large_name_len("") ClassHDL::AssignDefOpertor.with_rollback_opertors(:old) do with_new_align(0) do if @dimension.any? && index if index.is_a? String sq = "[#{index}]" NqString.new("#{@name}#{sq}") # NqString.new("#{@name}") else NqString.new("#{@name}[#{align_signal(index)}]") end else NqString.new("#{@name}") end end end end
Private Instance Methods
generate_chains(name,rv=false)
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# File lib/tdl/elements/originclass.rb, line 544 def generate_chains(name,rv=false) str = [] index = 0 dimension.each do |e| str << "#{' '*index}for(genvar KK#{index}=0;KK#{index}<#{e};KK#{index}++)begin" index += 1 end ti = (0...dimension.length).to_a.map{|e| "[KK#{e}]"}.join('') unless rv str << "#{' '*index}assign #{signal}_#{name}#{ti} = #{signal}#{ti}.#{name};" else str << "#{' '*index}assign #{signal}#{ti}.#{name} = #{signal}_#{name}#{ti};" end dimension.each do |e| index -= 1 str << "#{' '*index}end" end return str.join("\n") end
generate_inf_to_signals(name,width=1,rv=false)
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Array Chain
# File lib/tdl/elements/originclass.rb, line 538 def generate_inf_to_signals(name,width=1,rv=false) rel = belong_to_module.Def().logic(name: "#{signal}_#{name}",dsize: width,dimension: dimension) belong_to_module.DataInf_C_inst << "generate\n"+generate_chains(name,rv=rv)+"\nendgenerate\n" return rel end