class Reset

require_relative “./tdlerror” require_relative “./basefunc”

Attributes

active[R]
dsize[RW]
ghost[RW]
id[RW]
name[R]
port[RW]

Public Class Methods

new(name:"system_rst",active:"LOW",port:false,dsize:1, belong_to_module: nil) click to toggle source
# File lib/tdl/elements/Reset.rb, line 8
def initialize(name:"system_rst",active:"LOW",port:false,dsize:1, belong_to_module: nil)
    name_legal?(name)
    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.Reset.id
    @dsize = dsize
    @name = name
    @port = port
    @active = active.to_s.downcase
    if @active.eql?("low") && @active.eql?("high")
        raise TdlError.new("RESET ACTIVE PARA #{@active} ERROR")
    end
    @belong_to_module = belong_to_module
    unless @belong_to_module 
        raise TdlError.new("Reset<#{name}> dnot have belong_to_module")
    end
end
parse_ports(port_str) click to toggle source

def self.NC

GlobalParam.CurrTdlModule.BindEleClassVars.Reset.nc

end

def self.nc_create

Reset.new(name:"nc_rst",active:"LOW")

end

parse text for autogen method and constant ###
Calls superclass method SignalElm::parse_ports
# File lib/tdl/elements/Reset.rb, line 142
def self.parse_ports(port_str)
    rh = super.parse_ports(port_str)
    rh[:type]   = Reset
    return rh
end

Public Instance Methods

high_signal() click to toggle source
# File lib/tdl/elements/Reset.rb, line 89
def high_signal
    if(active.eql? "low")
        NqString.new("~").concat signal
    else
        signal
    end
end
inst_port() click to toggle source

def port_length

(@port.to_s + " ").length

end

# File lib/tdl/elements/Reset.rb, line 40
def inst_port

    # if @port
    #     (@port.to_s + " " + " "*sub_len + @name.to_s)
    # end

    if dsize.eql? 1
        n = ""
    else
        n = "[#{(@dsize-1)}:0]"
    end

    return [@port.to_s+n,@name.to_s,""]
end
low_signal() click to toggle source

def left_port_length

("/*  input" + " */ ").length

end

def right_port_length

(".#{@name.to_s} ").length

end

def ex_port(left_align_len = 7,right_align_len = 7)

if left_align_len >=  left_port_length
    sub_left_len = left_align_len -  left_port_length
else
    sub_left_len = 0
end

if right_align_len >=  right_port_length
    sub_right_len = right_align_len -  right_port_length
else
    sub_right_len = 0
end

if @port
    ("/*  input" + " "*sub_left_len + "*/ " + "."+@name.to_s + " "*sub_right_len)
end

end

# File lib/tdl/elements/Reset.rb, line 81
def low_signal
    if(active.eql? "low")
        signal
    else
        NqString.new("~").concat signal
    end
end
to_sim_source(ns=100) click to toggle source
# File lib/tdl/exlib/clock_reset_verify.rb, line 17
def to_sim_source(ns=100)
    
    @belong_to_module.instance_exec(self,ns) do |_self,ns|
        _xxx = (_self.active == 'low') ? 1.b0 : 1.b1 

        Initial do 
            _self   <= _xxx
            initial_exec("#(#{ns}ns)")
            _self   <= ~_self
        end
    end
end