class TopModule
添加 itegration verb
添加 missing
Attributes
constraint[RW]
implicit_itgt_collect[RW]
sim[RW]
techbench[RW]
vcs_path[RW]
vcs path
Public Class Methods
contain_hdl(*hdl_paths)
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# File lib/tdl/auto_script/import_hdl.rb, line 43 def TopModule.contain_hdl(*hdl_paths) hdl_paths.each do |hdl_path| rel = find_first_hdl_path(hdl_path) unless rel return nil end unless $__contain_hdl__.include? rel $__contain_hdl__ << rel end end end
current()
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# File lib/tdl/sdlmodule/top_module.rb, line 29 def self.current @@curr_top_module end
define_global(name,default_value)
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def self.recur_ref(sdlmodule,collect_str)
if sdlmodule.is_a? TopModule @@root_ref_array << "$root.#{sdlmodule.techbench.module_name}.#{sdlmodule.instanced_and_parent_module.keys.first}.#{collect_str}" else return nil unless sdlmodule.instanced_and_parent_module sdlmodule.instanced_and_parent_module.each do |k_inst,v_module| next_collect_str = "#{k_inst}.#{collect_str}" self.recur_ref(v_module,next_collect_str) end end
end
# File lib/tdl/sdlmodule/top_module.rb, line 328 def self.define_global(name,default_value) # RedefOpertor.with_normal_operators do self.class_variable_set("@@#{name.to_s}",default_value) self.define_singleton_method(name.to_s) do self.class_variable_get("@@#{name.to_s}") end self.define_singleton_method("#{name.to_s}=") do |a| self.class_variable_set("@@#{name.to_s}",a) end # end end
method_missing(method,*args,&block)
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# File lib/tdl/sdlmodule/top_module.rb, line 417 def self.method_missing(method,*args,&block) sdlm = TopModule.new(name: method,out_sv_path: args[0]) @@package_names ||= [] sdlm.head_import_packages = [] sdlm.head_import_packages += @@package_names @@package_names.each do |e| sdlm.require_package(e,false) if e end @@package_names = [] sdlm.instance_exec(&block) if args[0] && File.exist?(args[0]) # sdlm.gen_sv_module sdlm.gen_sv_module_verb unless sdlm.vcs_path # sdlm.test_unit.gen_dve_tcl(File.join(args[0],"dve.tcl")) SdlModule.gen_dev_wave_tcl File.join(args[0],"dve.tcl") else # sdlm.test_unit.gen_dve_tcl(File.join(sdlm.vcs_path,"dve.tcl")) SdlModule.gen_dev_wave_tcl File.join(sdlm.vcs_path,"dve.tcl") end sdlm.create_xdc ## 全局contain_hdl 引入到 TopModule sdlm.contain_hdl(*$__contain_hdl__) else sdlm.origin_sv = true end sdlm end
new(name:"tdlmodule",out_sv_path:nil)
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Calls superclass method
SdlModule::new
# File lib/tdl/sdlmodule/top_module.rb, line 6 def initialize(name:"tdlmodule",out_sv_path:nil) @@curr_top_module = self # set sim env @sim = TopModule.sim @out_sv_path = out_sv_path # console_argvs # TopModule.sim = @sim @constraint = ConstraintsVerb.new if @sim rewrite_to_warning(out_sv_path,"#{name}.sv") name = "#{name}_sim" else rewrite_to_warning(out_sv_path,"#{name}_sim.sv") end @techbench = TechBenchModule.new(name:"tb_#{name}",out_sv_path:out_sv_path) rtl_top_module = super(name:name,out_sv_path:out_sv_path) @techbench.Instance(name,"rtl_top") rtl_top_module end
with_package(*args)
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定义模块时添加 package
# File lib/tdl/sdlmodule/top_module.rb, line 451 def self.with_package(*args) @@package_names += args return self end
Public Instance Methods
Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil)
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Calls superclass method
SdlModule#Clock
# File lib/tdl/sdlmodule/top_module.rb, line 203 def Clock(name,freqM:100,port: :input,pin:[],iostd:[],dsize:1,pin_prop:nil) pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop a = super(name,port:port,freqM:freqM,pin:pin,iostd:iostd,dsize:dsize,pin_prop:pin_prop) @constraint.add_property(a,pin,iostd,pulltype,drive) a end
Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
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Calls superclass method
SdlModule#Inout
# File lib/tdl/sdlmodule/top_module.rb, line 196 def Inout(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd) @constraint.add_property(a,pin,iostd,pulltype,drive) a end
Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
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Calls superclass method
SdlModule#Input
# File lib/tdl/sdlmodule/top_module.rb, line 182 def Input(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd,pin_prop:pin_prop) @constraint.add_property(a,pin,iostd,pulltype,drive) a end
Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil)
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Calls superclass method
SdlModule#Output
# File lib/tdl/sdlmodule/top_module.rb, line 189 def Output(name,dsize:1,dimension:[],pin:[],iostd:[],pin_prop:nil) pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop a = super(name,dsize:dsize,dimension:dimension,pin:pin,iostd:iostd,pin_prop:pin_prop) @constraint.add_property(a,pin,iostd,pulltype,drive) a end
Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil)
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Calls superclass method
SdlModule#Reset
# File lib/tdl/sdlmodule/top_module.rb, line 210 def Reset(name,port: :input,active:"low",pin:[],iostd:[],dsize:1,pin_prop:nil) pin,iostd,pulltype,drive = parse_pin_prop(pin_prop) if pin_prop a = super(name,port:port,active:active,pin:pin,iostd:iostd,dsize:dsize,pin_prop:pin_prop) @constraint.add_property(a,pin,iostd,pulltype,drive) a end
add_itegration(itgt_class,nickname:nil,param:{},pins_map:{},implicit:false)
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# File lib/tdl/sdlmodule/top_module.rb, line 356 def add_itegration(itgt_class,nickname:nil,param:{},pins_map:{},implicit:false) @_itgt_collect_ ||= [] if pins_map.is_a? Hash pins_map_f = pins_map else pins_map_f = self.pins[pins_map.to_s] || {} end ist = Kernel.const_get(itgt_class).new(nickname,pins_map_f,self) @_itgt_collect_ << ist unless implicit # ist.top_module = self param.each do |k,v| ist.send("#{k}=",v) end ## 加入新的itgt时,自动link itgt # ist.link_eval # puts "------------------" # ist.names_pool_inst ## 如果itgt没有上级 link 和 不是隐性添加 则直接例化 # if nickname != "implicit" col = ist.class.get_itgt_var('itegration_link_collect',[]) if col && col.empty? ist.inst unless ist.init_inst ist.init_inst = true ist.inst_index = 0 end # end # ist.inst return ist end
add_test_unit(*args)
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 324 def add_test_unit(*args) @_test_unit_collect_ ||= [] @_test_unit_collect_ = @_test_unit_collect_ + args end
console_argvs()
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# File lib/tdl/sdlmodule/top_module.rb, line 64 def console_argvs # hash = Parser.parse(ARGV) hash = $argvs_hash if hash[:sim] @sim = hash[:sim] end bi = Proc.new do bp = File.join(@out_sv_path,"program_files/") Dir.mkdir(bp) unless File.exist? bp bp end if hash[:gold] @constraint.image(type: :gold,next_addr:hash[:next_cfg_addr],bitpath:bi.call) elsif hash[:update] @constraint.image(type: :update,bitpath:bi.call) end end
create_add_file_tcl()
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# File lib/tdl/sdlmodule/top_module.rb, line 226 def create_add_file_tcl return if @sim fname = "#{module_name}_add_files.tcl" fname = File.join(@out_sv_path,fname) File.open(fname,'w') do |f| f.puts("add_files \\") # f.puts Tdl.all_file_paths.map{ |e| e[1].gsub("\\",'/') }.join("\\\n") f.puts Tdl.all_file_paths.map{ |k,v| v.gsub("\\",'/') }.join("\\\n") end end
create_xdc()
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# File lib/tdl/sdlmodule/top_module.rb, line 217 def create_xdc return if @sim fname = "#{module_name}_constraints.xdc" fname = File.join(@out_sv_path,fname) File.open(fname,'w') do |f| f.puts @constraint.xds end end
gen_sv_module()
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Calls superclass method
SdlModule::gen_sv_module
# File lib/tdl/sdlmodule/top_module.rb, line 115 def gen_sv_module if @sim Tdl.Puts "INFO: JUST GEN SV[#{@module_name}] FOR SIM " else Tdl.Puts "INFO: JUST GEN TechBench Modules,NO SIM" end super # @techbench.gen_sv_module # exec auto gen sub TechBenchModule TechBenchModule.gen_sv_module end
gen_sv_module_verb()
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# File lib/tdl/sdlmodule/top_module.rb, line 170 def gen_sv_module_verb mix_itegrations ## 添加测试用例 实例化 _exec_add_test_unit() if TopModule.sim gen_sv_module end
index_inst()
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# File lib/tdl/sdlmodule/top_module.rb, line 396 def index_inst curr_collect = (implicit_itgt_collect || []) | @_itgt_collect_ curr_collect.each do |e| if e.init_inst e.cal_inst_index(0) end end curr_collect = curr_collect.sort { |a, b| a.inst_index <=> b.inst_index } curr_collect.each {|e| e.inst unless e.init_inst } end
itgt_collect()
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attr_accessor :cal_inst_index_proc
# File lib/tdl/sdlmodule/top_module.rb, line 352 def itgt_collect @_itgt_collect_ end
link_eval()
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# File lib/tdl/sdlmodule/top_module.rb, line 388 def link_eval @_itgt_collect_ ||= [] @_itgt_collect_.each do |i| i.link_eval end end
load_pins(pins_file)
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# File lib/tdl/sdlmodule/top_module.rb, line 37 def load_pins(pins_file) pins_params = YAML::load(File.open(pins_file)) pins_params = recur_pins_hash(pins_params) pins_params.define_singleton_method("[]") do |index| pins_params.fetch(index.to_s) end @pins_params = pins_params end
mix_itegrations()
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# File lib/tdl/sdlmodule/top_module.rb, line 128 def mix_itegrations ## 执行动态link itgt # puts implicit_itgt_collect self.link_eval self.index_inst # if implicit_itgt_collect # ## 执行 itgt inst # implicit_itgt_collect.reverse.each do |itgt| # itgt.inst unless itgt.init_inst # end # end # # ## 执行 itgt inst # @_itgt_collect_.each do |itgt| # itgt.inst unless itgt.init_inst # end ## 执行 itegration_verb 里面的silence @_itgt_collect_.each do |itgt| itgt.silence_procs_run if itgt.respond_to?('silence_procs_run') end if implicit_itgt_collect ## 执行 itegration_verb 里面的silence implicit_itgt_collect.each do |itgt| itgt.silence_procs_run if itgt.respond_to?('silence_procs_run') end end ## 生成 itgt下的子模块文件 # @_itgt_collect_.each do |itgt| # itgt.gen_children_modules() # end # if implicit_itgt_collect # ## 执行 itegration_verb 里面的silence # implicit_itgt_collect.each do |itgt| # itgt.gen_children_modules() # end # end end
parse_pin_prop(prop=nil)
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# File lib/tdl/sdlmodule/top_module.rb, line 178 def parse_pin_prop(prop=nil) return [prop["pins"],prop["iostd"],prop["pulltype"],prop["drive"]] end
pins()
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# File lib/tdl/sdlmodule/top_module.rb, line 33 def pins @pins_params end
recur_pins_hash(hash)
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# File lib/tdl/sdlmodule/top_module.rb, line 49 def recur_pins_hash(hash) new_hash = {} hash.each do |k,v| if v.is_a? Hash hash[k] = recur_pins_hash(v) else if v.is_a?(String) && v=~/\s/ hash[k] = v.split(/\s+/) end end new_hash[k.to_sym] = hash[k] end return hash.merge(new_hash) end
rewrite_to_warning(path,file_name)
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# File lib/tdl/sdlmodule/top_module.rb, line 84 def rewrite_to_warning(path,file_name) unless path _out_sv_path = './' else _out_sv_path = path end path_file_name = File.join(_out_sv_path,file_name) return unless File.exist? path_file_name basename = File.basename(path_file_name,'.sv') File.open(path_file_name,'w') do |f| str = " `timescale 1ns/1ps module #{basename}(); initial begin #(1us); $warning(\"Check TopModule.sim,please!!!\"); $stop; end endmodule\n" f.puts str end end
sim_test_hash()
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# File lib/tdl/exlib/sdlmodule_sim.bak.rb, line 340 def sim_test_hash TdlSimTest::TdlBaseTestUnit.test_unit_hash end
sim_test_hash=(hash)
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# File lib/tdl/exlib/sdlmodule_sim.bak.rb, line 333 def sim_test_hash=(hash) return nil unless TopModule.sim rel = TdlSimTest::TdlBaseTestUnit.test_unit_hash || {} TdlSimTest::TdlBaseTestUnit.test_unit_hash = rel.merge(hash) return TdlSimTest::TdlBaseTestUnit.test_unit_hash end
Private Instance Methods
_exec_add_test_unit()
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# File lib/tdl/sdlmodule/test_unit_module.rb, line 331 def _exec_add_test_unit @_test_unit_collect_ ||= [] args = @_test_unit_collect_ ## 例化需要的itgt test unit # ItegrationVerb.test_unit_inst ItegrationVerb.test_unit_inst do |name| args.include? name.to_s end self.techbench.instance_exec(args) do |args| index = 0 last_index = 0 logic.string - 'test_unit_region' logic[args.size] - 'unit_pass_u' logic[args.size] - 'unit_pass_d' nqq = args.size <= 1 args.each do |tu| if tu.is_a? SdlModule _inst_name_ = tu.module_name else _inst_name_ = tu.to_s end # puts _inst_name_ # puts SdlModule.call_module(_inst_name_).class tu_inst = Instance(_inst_name_,"test_unit_#{index}") do |h| h.input.from_up_pass (nqq ? unit_pass_u : unit_pass_u[index]) h.output.logic.to_down_pass (nqq ? unit_pass_d : unit_pass_d[index]) end tu_inst.origin.be_instanced_by_sim # TdlTestUnit.collect_unit tu_inst # TopModule.current.test_unit.collect_unit tu_inst ## 添加dve wave 信号 # TopModule.current.test_unit.dve_wave(name: _inst_name_, signals: tu_inst.origin.dve_wave_signals ) if index == 0 Assign do unless nqq unit_pass_u[index] <= 1.b1 else unit_pass_u <= 1.b1 end end else Assign do unit_pass_u[index] <= unit_pass_d[last_index] end end last_index = index index += 1 end end end