class DataInf
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'
require_relative “./tdlerror” require_relative “./clock” require_relative “./Reset” require_relative “./logic” require_relative “./basefunc”
Constants
- PORT_REP
- Synth_REP
parse text for autogen method and constant ###
- UP_STREAM_REP
Attributes
Public Class Methods
# File lib/tdl/Logic/clock_rst_verb_auto.rb, line 74 def self.clock_rst_verb( active:1, period_cnt:0, rst_hold:5, freqm:100, clock:"clock", rst_x:"rst_x", belong_to_module:nil ) return_stream = nil belong_to_module.DataInf_NC._clock_rst_verb( active:active, period_cnt:period_cnt, rst_hold:rst_hold, freqm:freqm, clock:clock, rst_x:rst_x) return return_stream end
# File lib/tdl/data_inf/bak/common_fifo_auto.rb, line 45 def self.common_fifo(depth:4,dsize:8,clock:"clock",rst_n:"rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",count:"count",empty:"empty",full:"full") return_stream = nil DataInf.NC._common_fifo(depth:depth,dsize:dsize,clock:clock,rst_n:rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,count:count,empty:empty,full:full) return return_stream end
# File lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb, line 29 def self.datainf_master_empty(master:"master",down_stream:nil) return_stream = nil if down_stream.is_a? DataInf down_stream.datainf_master_empty(master:master,down_stream:down_stream) elsif master.is_a? DataInf master.datainf_master_empty(master:master,down_stream:down_stream) else NC.datainf_master_empty(master:master,down_stream:down_stream) end return return_stream end
# File lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb, line 29 def self.datainf_slaver_empty(slaver:"slaver",up_stream:nil) return_stream = nil NC._datainf_slaver_empty(slaver:slaver,up_stream:up_stream) return return_stream end
# File lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb, line 46 def self.independent_clock_fifo(depth:4,dsize:8,wr_clk:"wr_clk",wr_rst_n:"wr_rst_n",rd_clk:"rd_clk",rd_rst_n:"rd_rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",empty:"empty",full:"full") return_stream = nil DataInf.NC._independent_clock_fifo(depth:depth,dsize:dsize,wr_clk:wr_clk,wr_rst_n:wr_rst_n,rd_clk:rd_clk,rd_rst_n:rd_rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,empty:empty,full:full) return return_stream end
def self.NC
GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.nc
end
def self.nc_create
DataInf.new(name:"implicit",dsize:1)
end
# File lib/tdl/elements/data_inf.rb, line 152 def self.master_empty(*ms) ms.each do |e| self.datainf_master_empty(master:e) end end
# File lib/tdl/Logic/mdio_model_auto.rb, line 58 def self.mdio_model( reset:"reset", mdio:"mdio", mdc:"mdc", belong_to_module:nil ) return_stream = nil belong_to_module.DataInf_NC._mdio_model( reset:reset, mdio:mdio, mdc:mdc) return return_stream end
InfElm::new
# File lib/tdl/elements/data_inf.rb, line 11 def initialize(name:"data_inf",dsize:8,port:false,dimension:[]) name_legal?(name) super() @port = port @dsize = dsize @name = name # @id = GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.id # @correlation_proc = "" @_to_data_inf_c = "" # if @port # GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.ports << self # else # GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.inst_stack << method(:inst).to_proc # end @interconnect_up_streams = [] @interconnect_idsize = 1 # GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.draw_stack << method(:draw).to_proc end
# File lib/tdl/elements/data_inf.rb, line 179 def self.parse_ports(port_array=nil) rep = /(?<up_down>\(\*\s+(?<ud_name>data_up|data_down|up_stream|down_stream)\s*=\s*"true"\s+\*\))?\s*(data_inf\.)(?<modport>master|slaver|mirror)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m up_stream_rep = /data_up/ InfElm.parse_ports(port_array,rep,"data_inf",up_stream_rep) do |h| h[:type] = DataInf yield h end end
# File lib/tdl/elements/data_inf.rb, line 158 def self.slaver_empty(*ss) ss.each do |e| self.datainf_slaver_empty(slaver:e) end end
Public Instance Methods
# File lib/tdl/data_inf/bak/data_inf_interconnect.rb, line 6 def <<(*up_streams) unless @interconnect_up_streams.empty? suit_type = @interconnect_up_streams.first else suit_type = up_streams.reject { |e| (e.is_a? Clock) || (e.is_a? Reset) || (e.is_a? DataInf_C)}.first suit_type = self unless suit_type end up_streams.each do |e| if (e.is_a? DataInf) || (e.is_a? DataInf_C) if (suit_type.is_a? DataInf) if e.is_a? DataInf_C @interconnect_up_streams << e.to_data_inf() else @interconnect_up_streams << e end else raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR") end elsif e.is_a? Hash if suit_type.is_a? Hash if e[:inf].is_a? DataInf_C @interconnect_up_streams << {:inf=>e[:inf].to_data_inf(),:id=>e[:id]} else @interconnect_up_streams << e end @interconnect_idsize = e[:id].dsize if e[:id].dsize > @interconnect_idsize else raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR") end elsif e.is_a? Clock @interconnect_clock = e elsif e.is_a? Reset if e.active != 'low' @interconnect_reset = "~"+e.signal else @interconnect_reset = e end else raise TdlError.new("DATA INF INTERCONNECT UP_STREAMS ERROR") end end end
# File lib/tdl/Logic/clock_rst_verb_auto.rb, line 9 def _clock_rst_verb( active:1, period_cnt:0, rst_hold:5, freqm:100, clock:"clock", rst_x:"rst_x" ) Tdl.add_to_all_file_paths('clock_rst_verb','../../github/public_atom_modules/sim/clock_rst_verb.sv') # GlobalParam.CurrTdlModule.add_to_all_file_paths(['clock_rst_verb','../../github/public_atom_modules/sim/clock_rst_verb.sv']) return_stream = self belong_to_module.DataInf_draw << _clock_rst_verb_draw( active:active, period_cnt:period_cnt, rst_hold:rst_hold, freqm:freqm, clock:clock, rst_x:rst_x) return return_stream end
# File lib/tdl/data_inf/bak/common_fifo_auto.rb, line 9 def _common_fifo(depth:4,dsize:8,clock:"clock",rst_n:"rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",count:"count",empty:"empty",full:"full") Tdl.add_to_all_file_paths(['common_fifo','../../axi/common_fifo/common_fifo.sv']) return_stream = self @instance_draw_stack << lambda { _common_fifo_draw(depth:depth,dsize:dsize,clock:clock,rst_n:rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,count:count,empty:empty,full:full) } return return_stream end
# File lib/tdl/data_inf/bak/common_fifo_auto.rb, line 23 def _common_fifo_draw(depth:4,dsize:8,clock:"clock",rst_n:"rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",count:"count",empty:"empty",full:"full") large_name_len(depth,dsize,clock,rst_n,wdata,wr_en,rdata,rd_en,count,empty,full) " // FilePath:::../../axi/common_fifo/common_fifo.sv common_fifo#( .DEPTH (#{align_signal(depth)}), .DSIZE (#{align_signal(dsize)}) ) common_fifo_#{signal}_inst( /* input */ .clock (#{align_signal(clock,q_mark=false)}), /* input */ .rst_n (#{align_signal(rst_n,q_mark=false)}), /* input [DSIZE-1:0]*/ .wdata (#{align_signal(wdata,q_mark=false)}), /* input */ .wr_en (#{align_signal(wr_en,q_mark=false)}), /* output [DSIZE-1:0]*/ .rdata (#{align_signal(rdata,q_mark=false)}), /* input */ .rd_en (#{align_signal(rd_en,q_mark=false)}), /* output [CSIZE-1:0]*/ .count (#{align_signal(count,q_mark=false)}), /* output */ .empty (#{align_signal(empty,q_mark=false)}), /* output */ .full (#{align_signal(full,q_mark=false)}) ); " end
# File lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb, line 9 def _datainf_slaver_empty(slaver:"slaver",up_stream:nil) return_stream = self slaver = up_stream if up_stream $_draw = lambda { _datainf_slaver_empty_draw(slaver:slaver,up_stream:up_stream) } @correlation_proc += $_draw.call return return_stream end
# File lib/tdl/axi_stream/bak/datainf_slaver_empty_auto.rb, line 20 def _datainf_slaver_empty_draw(slaver:"slaver",up_stream:nil) large_name_len(slaver) " datainf_slaver_empty datainf_slaver_empty_#{signal}_inst( /* data_inf.slaver*/ .slaver (#{align_signal(slaver,q_mark=false)}) ); " end
# File lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb, line 9 def _independent_clock_fifo(depth:4,dsize:8,wr_clk:"wr_clk",wr_rst_n:"wr_rst_n",rd_clk:"rd_clk",rd_rst_n:"rd_rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",empty:"empty",full:"full") Tdl.add_to_all_file_paths(['independent_clock_fifo','../../axi/common_fifo/independent_clock_fifo.sv']) return_stream = self @instance_draw_stack << lambda { _independent_clock_fifo_draw(depth:depth,dsize:dsize,wr_clk:wr_clk,wr_rst_n:wr_rst_n,rd_clk:rd_clk,rd_rst_n:rd_rst_n,wdata:wdata,wr_en:wr_en,rdata:rdata,rd_en:rd_en,empty:empty,full:full) } return return_stream end
# File lib/tdl/data_inf/bak/independent_clock_fifo_auto.rb, line 23 def _independent_clock_fifo_draw(depth:4,dsize:8,wr_clk:"wr_clk",wr_rst_n:"wr_rst_n",rd_clk:"rd_clk",rd_rst_n:"rd_rst_n",wdata:"wdata",wr_en:"wr_en",rdata:"rdata",rd_en:"rd_en",empty:"empty",full:"full") large_name_len(depth,dsize,wr_clk,wr_rst_n,rd_clk,rd_rst_n,wdata,wr_en,rdata,rd_en,empty,full) " // FilePath:::../../axi/common_fifo/independent_clock_fifo.sv independent_clock_fifo#( .DEPTH (#{align_signal(depth)}), .DSIZE (#{align_signal(dsize)}) ) independent_clock_fifo_#{signal}_inst( /* input */ .wr_clk (#{align_signal(wr_clk,q_mark=false)}), /* input */ .wr_rst_n (#{align_signal(wr_rst_n,q_mark=false)}), /* input */ .rd_clk (#{align_signal(rd_clk,q_mark=false)}), /* input */ .rd_rst_n (#{align_signal(rd_rst_n,q_mark=false)}), /* input [DSIZE-1:0]*/ .wdata (#{align_signal(wdata,q_mark=false)}), /* input */ .wr_en (#{align_signal(wr_en,q_mark=false)}), /* output [DSIZE-1:0]*/ .rdata (#{align_signal(rdata,q_mark=false)}), /* input */ .rd_en (#{align_signal(rd_en,q_mark=false)}), /* output */ .empty (#{align_signal(empty,q_mark=false)}), /* output */ .full (#{align_signal(full,q_mark=false)}) ); " end
# File lib/tdl/Logic/mdio_model_auto.rb, line 9 def _mdio_model( reset:"reset", mdio:"mdio", mdc:"mdc" ) Tdl.add_to_all_file_paths('mdio_model','../../repository/ethernet_protocol/model/mdio_model.sv') # GlobalParam.CurrTdlModule.add_to_all_file_paths(['mdio_model','../../repository/ethernet_protocol/model/mdio_model.sv']) return_stream = self belong_to_module.DataInf_draw << _mdio_model_draw( reset:reset, mdio:mdio, mdc:mdc) return return_stream end
# File lib/tdl/data_inf/bak/data_inf_interconnect.rb, line 81 def a_interconnect_draw(prio:"OFF") clock = @interconnect_clock reset = @interconnect_reset num = @interconnect_up_streams.length large_name_len(num,prio,clock,reset,"sub_#{signal}") sub_inst + "data_inf_interconnect_M2S_noaddr #( .NUM (#{align_signal(num)}), .PRIO (#{align_signal(prio)}) )data_inf_interconnect_M2S_noaddr_#{signal}_inst( /* input */ .clock (#{align_signal(clock)}), /* input */ .rst_n (#{align_signal(reset)}), /* data_inf.slaver */ .s00 (#{align_signal("sub_#{signal}",false)}),//[NUM-1:0], /* data_inf.master */ .m00 (#{align_signal(self)}) );" end
# File lib/tdl/data_inf/bak/data_inf_interconnect.rb, line 98 def b_interconnect_draw(prio:"OFF") idsize= @interconnect_idsize clock = @interconnect_clock reset = @interconnect_reset num = @interconnect_up_streams.length large_name_len(num,prio,clock,reset,"sub_#{signal}",@interconnect_mid) sub_inst + "data_inf_interconnect_M2S_with_id_noaddr #( .NUM (#{align_signal(num)}), .IDSIZE (#{align_signal(idsize)}), .PRIO (#{align_signal(prio)}) )data_inf_interconnect_M2S_with_id_noaddr_#{signal}_inst( /* input */ .clock (#{align_signal(clock)}), /* input */ .rst_n (#{align_signal(reset)}), /* input [IDSIZE-1:0] */ .sid (#{align_signal("#{signal}_sid",false)})//[NUM-1:0], /* output[IDSIZE-1:0] */ .mid (#{align_signal(@interconnect_mid)})//, /* data_inf.slaver */ .s00 (#{align_signal("sub_#{signal}",false)}),//[NUM-1:0], /* data_inf.master */ .m00 (#{align_signal(self)}) );" end
# File lib/tdl/elements/data_inf.rb, line 169 def branch(name:@name,dsize:@dsize) a = copy(name:name,dsize:dsize) self << a return a end
# File lib/tdl/elements/data_inf.rb, line 164 def copy(name:@name.to_s,dsize:"#{signal}.DSIZE") append_name = name_copy(name) belong_to_module.Def.datainf(name:append_name,dsize:dsize) end
# File lib/tdl/data_inf/bak/data_connect_pipe.rb, line 49 def data_connect_pipe(clock:nil,reset:nil,up_stream:nil,down_stream:nil) if down_stream && !up_stream down_stream.data_connect_pipe(clock:clock,reset:reset,up_stream:self,down_stream:nil) return down_stream end down_stream = self if up_stream.is_a? DataInf up_stream_c = up_stream.to_data_inf_c(clock:clock,reset:reset) else up_stream_c = up_stream end down_stream_c = self.from_data_inf_c(clock:clock,reset:reset) down_stream_c.data_connect_pipe(up_stream:up_stream_c) return up_stream end
# File lib/tdl/data_inf/bak/data_inf_cross_clk.rb, line 30 def data_inf_cross_clk(clock:nil,reset:nil,up_stream:nil,down_stream:nil) if down_stream && !up_stream down_stream.data_inf_cross_clk(up_stream:self,down_stream:down_stream,clock:clock,reset:reset) return down_stream end down_stream = self down_stream.from_data_inf_c(clock:clock,reset:reset).data_inf_cross_clk(up_stream:up_stream.to_data_inf_c(clock:clock,reset:reset)) return up_stream end
# File lib/tdl/data_inf/bak/data_inf_planer.rb, line 7 def data_inf_planer(latency:3,clock:nil,reset:nil,pack_data:nil,up_stream:nil,down_stream:nil) if down_stream && !up_stream down_stream.data_inf_planer(latency:latency,clock:clock,reset:reset,pack_data:pack_data,up_stream:self,down_stream:down_stream) return down_stream end down_stream = self if (reset.is_a? Reset) && (reset.active != 'low') reset_str = "~"+reset.signal else reset_str = reset; end $_draw = lambda { data_inf_planer_draw(latency:latency,clock:clock,reset:reset_str,pack_data:pack_data,up_stream:up_stream,down_stream:down_stream) } @correlation_proc +=$_draw.call return self end
# File lib/tdl/data_inf/bak/data_inf_planer.rb, line 27 def data_inf_planer_draw(latency:3,clock:nil,reset:nil,pack_data:nil,up_stream:nil,down_stream:self) large_name_len(latency,"#{signal}.DSIZE",up_stream,down_stream) "data_inf_planer #( .LAT (#{align_signal(latency)}), .DSIZE (#{align_signal("#{signal}.DSIZE",false)}) )data_inf_planer_#{signal}_inst( /* input */ .clock (#{align_signal(clock)}), /* input */ .rst_n (#{align_signal(reset)}), /* input [DSIZE-1:0]*/ .pack_data (#{align_signal(pack_data)}), /* data_inf.slaver */ .slaver (#{align_signal(up_stream)}), /* data_inf.master */ .master (#{align_signal(down_stream)}) //{pack_data,slaver.data} );" end
# File lib/tdl/data_inf/bak/data_inf_ticktack.rb, line 6 def data_inf_ticktack(sub_hbit:@dsize-1,sub_lbit:0,mode:"COMPARE:<",index_data:nil,compare_data:nil,up_stream:nil,down_stream:self,clock:nil,reset:nil) if down_stream && !up_stream down_stream.data_inf_planer(sub_hbit:sub_hbit,sub_lbit:sub_lbit,mode:mode,index_data:index_data,compare_data:compare_data,up_stream:self,down_stream:down_stream,clock:clock,reset:reset) return down_stream end down_stream = self if (reset.is_a? Reset) && (reset.active != 'low') reset_str = "~"+reset.signal else reset_str = reset; end $_draw = lambda { data_inf_ticktack_draw(sub_hbit:sub_hbit,sub_lbit:sub_lbit,mode:mode,index_data:index_data,compare_data:compare_data,up_stream:self,down_stream:down_stream,clock:clock,reset:reset_str) } @correlation_proc +=$_draw.call return self end
# File lib/tdl/data_inf/bak/data_inf_ticktack.rb, line 26 def data_inf_ticktack_draw(sub_hbit:@dsize-1,sub_lbit:0,mode:"COMPARE:<",index_data:nil,compare_data:nil,up_stream:nil,down_stream:self,clock:nil,reset:nil) large_name_len(sub_hbit,sub_lbit,mode,index_data,compare_data,up_stream,down_stream,clock,reset) "data_inf_ticktack #( .DSIZE (#{signal}.DSIZE), .SUB_HBIT (#{align_signal(sub_hbit)}), .SUB_LBIT (#{align_signal(sub_lbit)}), .MODE (#{align_signal(mode)}), //COMPARE:< COMPARE:> COMPARE:<= COMPARE:>= COMPARE:== COMPARE:!= ,INDEX .ISIZE (#{align_signal(index_data.dsize)}) // ONLY INDEX MODE )data_inf_ticktack_#{signal}_inst( /* input */ .clock (#{align_signal(clock)}), /* input */ .rst_n (#{align_signal(reset)}), /* input [DSIZE-1:0] */ .compare_data (#{align_signal(compare_data)}), /* input [ISIZE-1:0] */ .index_data (#{align_signal(index_data)}), /* data_inf.slaver */ .slaver (#{align_signal(up_stream)}), /* data_inf.master */ .master (#{align_signal(down_stream)}) );" end
# File lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb, line 9 def datainf_master_empty(master:"master",down_stream:nil) return_stream = self master = self $_draw = lambda { datainf_master_empty_draw(master:master,down_stream:down_stream) } @correlation_proc += $_draw.call return return_stream end
# File lib/tdl/axi_stream/bak/datainf_master_empty_auto.rb, line 20 def datainf_master_empty_draw(master:"master",down_stream:nil) large_name_len(master) " datainf_master_empty datainf_master_empty_#{signal}_inst( /* data_inf.master*/ .master (#{align_signal(master,q_mark=false)}) ); " end
# File lib/tdl/elements/data_inf.rb, line 110 def from_data_inf_c(clock:nil,reset:nil) new_obj = belong_to_module.Def.datainf_c(name:@name+"_c",clock:clock,reset:reset,dsize:@dsize) belong_to_module.DataInf_C_draw << from_data_inf_c_draw(up_stream:new_obj,down_stream:self) return new_obj end
# File lib/tdl/elements/data_inf.rb, line 116 def from_data_inf_c_draw(up_stream:nil,down_stream:nil) large_name_len(up_stream,down_stream) "data_inf_B2A data_inf_B2A_#{signal}_inst ( /* data_inf_c.slaver */ .slaver (#{align_signal(up_stream)}), /* data_inf.master */ .master (#{align_signal(down_stream)}) );" end
def signal
if @port NqString.new(@name.to_s) else # "data_#{name}_#{@id}_inf" NqString.new("#{@name}_#{@id}_inf") end
end
# File lib/tdl/elements/data_inf.rb, line 40 def inst return "" if @ghost "data_inf #(.DSIZE(#{dsize.abs})) #{signal} ();" end
def port_length
("data_inf." + @port.to_s + " ").length
end
# File lib/tdl/elements/data_inf.rb, line 49 def inst_port # if @port # ("data_inf." + @port.to_s + " " + " "*sub_len + @name.to_s) # end return ["data_inf." + @port.to_s,@name.to_s,array_inst] end
# File lib/tdl/data_inf/bak/data_inf_interconnect.rb, line 61 def sub_direct str = "" for i in 0...(@interconnect_up_streams.length) if @interconnect_up_streams[i].is_a? DataInf up_stream = @interconnect_up_streams[i] else up_stream = @interconnect_up_streams[i][:inf] sid = @interconnect_up_streams[i][:id] end str += " #{sid ? "assign #{signal}_sid[#{i}] = #{sid.signal};" : ""} assign sub_#{signal}[#{i}].valid = #{up_stream.signal}.valid; assign sub_#{signal}[#{i}].data = #{up_stream.signal}.data; assign #{up_stream.signal}.ready = sub_#{signal}[#{i}].ready; " end return str end
# File lib/tdl/data_inf/bak/data_inf_interconnect.rb, line 50 def sub_inst return '' if @interconnect_up_streams.empty? if @interconnect_up_streams.first.is_a? Hash id_str = "logic [#{signal}.DSIZE-1:0] #{signal}_sid [#{@interconnect_up_streams.length-1}:0];\n" else id_str = "" end id_str+"data_inf #(.DSIZE(#{dsize})) sub_#{signal} [#{@interconnect_up_streams.length-1}:0]();\n"+sub_direct end
def self.inst
GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.inst_stack.map { |e| e.call }.join("")
end
def self.draw
str = "" GlobalParam.CurrTdlModule.BindEleClassVars.DataInf.draw_stack.each do |e| str += e.call end return str
end
# File lib/tdl/elements/data_inf.rb, line 96 def to_data_inf_c(clock:nil,reset:nil) new_obj = belong_to_module.Def.datainf_c(name:@name+"_c",clock:clock,reset:reset,dsize:@dsize) belong_to_module.DataInf_C_draw << to_data_inf_c_draw(up_stream:self,down_stream:new_obj) return new_obj end
# File lib/tdl/elements/data_inf.rb, line 102 def to_data_inf_c_draw(up_stream:nil,down_stream:nil) large_name_len(up_stream,down_stream) "data_inf_A2B data_inf_A2B_#{signal}_inst ( /* data_inf.slaver */ .slaver (#{align_signal(up_stream)}), /* data_inf_c.master */ .master (#{align_signal(down_stream)}) );" end
super(port_array,rep,"data_inf",up_stream_rep) do |h| h[:type] = DataInf yield h end
end
# File lib/tdl/rebuild_ele/data_inf.rb, line 23 def vld_rdy valid.concat(" && ").concat(ready) end
Private Instance Methods
# File lib/tdl/Logic/clock_rst_verb_auto.rb, line 40 def _clock_rst_verb_draw( active:1, period_cnt:0, rst_hold:5, freqm:100, clock:"clock", rst_x:"rst_x" ) large_name_len( active, period_cnt, rst_hold, freqm, clock, rst_x ) instance_name = "clock_rst_verb_#{signal}_inst" " // FilePath:::../../github/public_atom_modules/sim/clock_rst_verb.sv clock_rst_verb#( .ACTIVE (#{align_signal(active)}), .PERIOD_CNT (#{align_signal(period_cnt)}), .RST_HOLD (#{align_signal(rst_hold)}), .FreqM (#{align_signal(freqm)}) ) #{instance_name}( /* output */ .clock (#{align_signal(clock,q_mark=false)}), /* output */ .rst_x (#{align_signal(rst_x,q_mark=false)}) ); " end
# File lib/tdl/Logic/mdio_model_auto.rb, line 34 def _mdio_model_draw( reset:"reset", mdio:"mdio", mdc:"mdc" ) large_name_len( reset, mdio, mdc ) instance_name = "mdio_model_#{signal}_inst" " // FilePath:::../../repository/ethernet_protocol/model/mdio_model.sv mdio_model #{instance_name}( /* input */ .reset (#{align_signal(reset,q_mark=false)}), /* inout */ .mdio (#{align_signal(mdio,q_mark=false)}), /* input */ .mdc (#{align_signal(mdc,q_mark=false)}) ); " end