class AxiLite

2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'

2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'

2018-05-04 14:40:11 +0800 require_relative “.././tdl” require_relative '....tdltdl'

require_relative “./tdlerror” require_relative “./clock” require_relative “./Reset” require_relative “./logic” require_relative “./basefunc” require_relative “./axi_stream/axi_stream_lib”

require_relative 'ele'

Constants

BOTH
INTERFACE_S_SIGNALS
INTERFACE_VECTOR_SIGNALS
LastModuleInstName
MACRO
ONLY_READ
ONLY_WRITE
PORT_REP

def initialize(name:“axi4”,clock:nil,reset:nil,dsize:8,idsize:1,asize:8,lsize:8,mode:BOTH,port:false,addr_step:1.0,dimension:[],freqM:nil,belong_to_module: nil)

super belong_to_module
self.inst_name = name 
self.clock = clock 
self.reset = reset 
self.dsize = dsize 
self.idsize = idsize
self.asize = asize 
self.lsize = lsize
self.mode = mode 
self.modport_type = port
self.addr_step = addr_step
self.dimension = dimension
self.freqM = freqM

end

Synth_REP

parse text for autogen method and constant ###

UP_STREAM_REP

Attributes

asize[RW]
dsize[RW]
ghost[RW]
id[RW]
mode[RW]
name[RW]
port[RW]

Public Class Methods

axi_lite_master_empty( lite:"lite", down_stream:nil, belong_to_module:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_master_empty_auto.rb, line 57
def self.axi_lite_master_empty(
    lite:"lite",
    down_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [lite].first.belong_to_module unless belong_to_module
    
    
    
    if down_stream.is_a? AxiLite
        down_stream.axi_lite_master_empty(
            lite:lite,
            down_stream:down_stream)
    elsif lite.is_a? AxiLite
        lite.axi_lite_master_empty(
            lite:lite,
            down_stream:down_stream)
    else
        belong_to_module.AxiLite_NC.axi_lite_master_empty(
            lite:lite,
            down_stream:down_stream)
    end
    return return_stream
end
axi_lite_slaver_empty( lite:"lite", up_stream:nil, belong_to_module:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb, line 51
def self.axi_lite_slaver_empty(
    lite:"lite",
    up_stream:nil,
    belong_to_module:nil
    )
    return_stream = nil
    belong_to_module = [lite].first.belong_to_module unless belong_to_module
    
    
    belong_to_module.AxiLite_NC._axi_lite_slaver_empty(
        lite:lite,
        up_stream:up_stream)
    return return_stream
end
axis_wrapper_oled(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf") click to toggle source
# File lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb, line 37
def self.axis_wrapper_oled(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf")
    return_stream = nil
    
    
    NC._axis_wrapper_oled(oled_sdin:oled_sdin,oled_sclk:oled_sclk,oled_dc:oled_dc,oled_res:oled_res,oled_vbat:oled_vbat,oled_vdd:oled_vdd,trigger_toggle:trigger_toggle,lite_ctrl_inf:lite_ctrl_inf,ctrl_inf:ctrl_inf)
    return return_stream
end
jtag_to_axilite_wrapper( lite:"lite" ) click to toggle source
# File lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb, line 50
def self.jtag_to_axilite_wrapper(
    lite:"lite"
)
    return_stream = nil
    
    
    AxiLite.NC._jtag_to_axilite_wrapper(
        lite:lite)
    return return_stream
end
leave_empty(curr_type: :master,dsize:8,asize:32,clock:Clock.NC,reset:Reset.NC) click to toggle source
# File lib/tdl/elements/axi_lite.rb, line 233
def self.leave_empty(curr_type: :master,dsize:8,asize:32,clock:Clock.NC,reset:Reset.NC)
    nc = AxiLite.new(name:"empty",clock:clock,reset:reset,dsize:dsize,asize:asize,mode:BOTH,port:false)

    if curr_type.to_sym == :slaver
        self.axi_lite_master_empty(lite:nc)
    elsif curr_type.to_sym == :master
        self.axi_lite_slaver_empty(lite:nc)
    else
        raise TdlError.new("\n\n Axi Lite don't has this type << #{type} >> \n\n")
    end

    return nc
end
nc_create() click to toggle source

def @@nc.signal

id = @@nc.instance_variable_get("@_id")
@@nc.instance_variable_set("@_id",id+1).to_s

end

# File lib/tdl/elements/axi_lite.rb, line 123
def self.nc_create
    AxiLite.new(name:"implicit",dsize:1,clock:Clock.NC,reset:Reset.NC)
end
new(name:"axi_lite",clock:nil,reset:nil,dsize:8,asize:8,mode:BOTH,port:false,freqM:nil) click to toggle source
Calls superclass method CLKInfElm::new
# File lib/tdl/elements/axi_lite.rb, line 18
def initialize(name:"axi_lite",clock:nil,reset:nil,dsize:8,asize:8,mode:BOTH,port:false,freqM:nil)
    name_legal?(name)
    super(clock:clock,reset:reset,freqM:freqM)
    @inf_name = "axi_lite_inf"
    @name = name
    @dsize = dsize
    @asize = asize
    @mode = mode
    @port = port

    # @id = GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.id
    # @correlation_proc = ""
    # if @port
    #     GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.ports << self
    # else
    #     GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.inst_stack << method(:inst).to_proc
    # end
    # @interconnect_up_streams = []
    # GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.draw_stack << method(:draw).to_proc
end
parse_ports(port_array=nil) { |h| ... } click to toggle source
Calls superclass method InfElm::parse_ports
# File lib/tdl/elements/axi_lite.rb, line 131
def self.parse_ports(port_array=nil)
    rep = /(?<up_down>\(\*\s+(?<ud_name>axil_up|axil_down)\s*=\s*"true"\s+\*\))?\s*(axi_lite_inf\.)(?<modport>master|slaver|master_rd|slaver_rd|master_wr|slaver_wr)\s+(?<name>\w+)\s*(?<vector>\[.*?\])?/m
    up_stream_rep = /axil_up/

    super(port_array,rep,"axi_lite_inf",up_stream_rep) do |h|
        h[:type]   = AxiLite
        yield h
    end
end

Public Instance Methods

EvalList(trigger:"1'b1",done:"",&block) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 4
def EvalList(trigger:"1'b1",done:"",&block)
    Tdl.add_to_all_file_paths('gen_axi_lite_ctrl','..\..\axi\AXI_Lite\gen_axi_lite_ctrl.sv')
    Tdl.add_to_all_file_paths('gen_axi_lite_ctrl_verc','..\..\axi\AXI_Lite\gen_axi_lite_ctrl_verc.sv')
    @__cmds__ = []
    with_main_funcs(
        {
            LITE_WR:method(:cmd_wr_exec),
            LITE_RD_MEET:method(:cmd_read_meet_exec),
            LITE_RD_MEET_KEEP:method(:cmd_read_meet_keep_exec),
            LITE_RD:method(:cmd_read_exec)
        },&block)

    belong_to_module.AxiLite_draw << cmd_list_draw(@__cmds__.length,trigger,done,render_cmds)
end
EvalListStep(clken:nil,trigger:"1'b1",done:"",&block) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 109
def EvalListStep(clken:nil,trigger:"1'b1",done:"",&block)
    raise TdlError.new("\n LITE Eval List <<clken>> must privoded\n") unless clken
    Tdl.add_to_all_file_paths(['gen_axi_lite_ctrl','..\..\axi\AXI_Lite\gen_axi_lite_ctrl.sv'])
    Tdl.add_to_all_file_paths(['gen_axi_lite_ctrl_verc','..\..\axi\AXI_Lite\gen_axi_lite_ctrl_C1.sv'])
    @__cmds__ = []
    with_main_funcs(
        {
            LITE_WR:method(:cmd_wr_exec),
            LITE_RD_MEET:method(:cmd_read_meet_exec),
            LITE_RD_MEET_KEEP:method(:cmd_read_meet_keep_exec),
            LITE_RD:method(:cmd_read_exec)
        },&block)
    @_step_clken_ = clken
    belong_to_module.AxiLite_draw << cmd_list_draw_step(@__cmds__.length,trigger,done,render_cmds)
end
__inf_signal__(name) click to toggle source
# File lib/tdl/elements/axi_lite.rb, line 148
def __inf_signal__(name)
    raise TdlError.new("\nARRAY Don't have '#{name}'\n") unless @dimension.empty?
    # puts "--------------"
    # puts $new_m.instance_variable_get("@port_axisinfs")
    # puts "============="
    NqString.new(signal.concat ".#{name}")
    # signal.concat ".#{name}"
end
_axi_data(name,h=nil,l=nil) click to toggle source

def vld_rdy

axis_tvalid.concat(" && ").concat(axis_tready)

end

def vld_rdy_last

axis_tvalid.concat(" && ").concat(axis_tready).concat(" && ").concat(axis_tlast)

end

# File lib/tdl/elements/axi_lite.rb, line 194
def _axi_data(name,h=nil,l=nil)
    raise TdlError.new("\nARRAY Don't have '#{name}'") unless @dimension.empty?

    if h.is_a? Range
        l = h.to_a.min
        h = h.to_a.max
    end

    if h
        if l
            sqr = "[#{h.to_s}:#{l.to_s}]"
        else
            sqr = "[#{h.to_s}]"
        end
    else
        sqr = ""
    end
    signal.concat(".#{name}").concat(sqr)
end
_axi_lite_slaver_empty( lite:"lite", up_stream:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb, line 9
def _axi_lite_slaver_empty(
    lite:"lite",
    up_stream:nil
)

    Tdl.add_to_all_file_paths('axi_lite_slaver_empty','../../axi/AXI_Lite/axi_lite_slaver_empty.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi_lite_slaver_empty','../../axi/AXI_Lite/axi_lite_slaver_empty.sv'])
    return_stream = self
    
    lite = AxiLite.same_name_socket(:from_up,mix=true,lite,nil,belong_to_module) unless lite.is_a? String
    
    lite = up_stream if up_stream
    


    belong_to_module.AxiLite_draw << _axi_lite_slaver_empty_draw(
        lite:lite,
        up_stream:up_stream)
    return return_stream
end
_axis_wrapper_oled(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf") click to toggle source
# File lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb, line 9
def _axis_wrapper_oled(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf")
    return_stream = self
    
    
    

    $_draw = lambda { _axis_wrapper_oled_draw(oled_sdin:oled_sdin,oled_sclk:oled_sclk,oled_dc:oled_dc,oled_res:oled_res,oled_vbat:oled_vbat,oled_vdd:oled_vdd,trigger_toggle:trigger_toggle,lite_ctrl_inf:lite_ctrl_inf,ctrl_inf:ctrl_inf) }
    @correlation_proc += $_draw.call
    return return_stream
end
_axis_wrapper_oled_draw(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf") click to toggle source
# File lib/tdl/axi_stream/bak/axis_wrapper_oled_auto.rb, line 20
    def _axis_wrapper_oled_draw(oled_sdin:"oled_sdin",oled_sclk:"oled_sclk",oled_dc:"oled_dc",oled_res:"oled_res",oled_vbat:"oled_vbat",oled_vdd:"oled_vdd",trigger_toggle:"trigger_toggle",lite_ctrl_inf:"lite_ctrl_inf",ctrl_inf:"ctrl_inf")
        large_name_len(oled_sdin,oled_sclk,oled_dc,oled_res,oled_vbat,oled_vdd,trigger_toggle,lite_ctrl_inf,ctrl_inf)
"
axis_wrapper_oled axis_wrapper_oled_#{signal}_inst(
/*  output               */ .oled_sdin      (#{align_signal(oled_sdin,q_mark=false)}),
/*  output               */ .oled_sclk      (#{align_signal(oled_sclk,q_mark=false)}),
/*  output               */ .oled_dc        (#{align_signal(oled_dc,q_mark=false)}),
/*  output               */ .oled_res       (#{align_signal(oled_res,q_mark=false)}),
/*  output               */ .oled_vbat      (#{align_signal(oled_vbat,q_mark=false)}),
/*  output               */ .oled_vdd       (#{align_signal(oled_vdd,q_mark=false)}),
/*  input                */ .trigger_toggle (#{align_signal(trigger_toggle,q_mark=false)}),
/*  axi_lite_inf.slaver  */ .lite_ctrl_inf  (#{align_signal(lite_ctrl_inf,q_mark=false)}),
/*  axi_stream_inf.slaver*/ .ctrl_inf       (#{align_signal(ctrl_inf,q_mark=false)})
);
"
    end
_jtag_to_axilite_wrapper( lite:"lite" ) click to toggle source
# File lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb, line 9
def _jtag_to_axilite_wrapper(
    lite:"lite"
)

    # Tdl.add_to_all_file_paths(['jtag_to_axilite_wrapper','../../axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv'])
    GlobalParam.CurrTdlModule.add_to_all_file_paths(['jtag_to_axilite_wrapper','../../axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv'])
    return_stream = self
    
    lite = AxiLite.same_name_socket(:to_down,mix=true,lite) unless lite.is_a? String
    
    
    

    # @instance_draw_stack << lambda { _jtag_to_axilite_wrapper_draw(
    #    lite:lite,
        #thash:GlobalParam.CurrHash) }
    @instance_draw_stack << _jtag_to_axilite_wrapper_draw(
        lite:lite,
        thash:GlobalParam.CurrHash)
    return return_stream
end
_jtag_to_axilite_wrapper_draw( lite:"lite", thash:nil ) click to toggle source
# File lib/tdl/axi_lite/bak/jtag_to_axilite_wrapper_auto.rb, line 31
    def _jtag_to_axilite_wrapper_draw(
        lite:"lite",
        thash:nil
    )

        large_name_len(
            lite
        )
        instance_name = "jtag_to_axilite_wrapper_#{signal}_inst"
        thash.instance_name = instance_name if thash
        GlobalParam.LastModuleInstName = instance_name 
"
// FilePath:::../../axi/AXI_Lite/common_configure_reg_interface/jtag_to_axilite_wrapper.sv
jtag_to_axilite_wrapper #{instance_name}(
/*  axi_lite_inf.master*/ .lite (#{align_signal(lite,q_mark=false)})
);
"
    end
axi_lite_master_empty( lite:"lite", down_stream:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_master_empty_auto.rb, line 9
def axi_lite_master_empty(
    lite:"lite",
    down_stream:nil
)

    Tdl.add_to_all_file_paths('axi_lite_master_empty','../../axi/AXI_Lite/axi_lite_master_empty.sv')
    # GlobalParam.CurrTdlModule.add_to_all_file_paths(['axi_lite_master_empty','../../axi/AXI_Lite/axi_lite_master_empty.sv'])
    return_stream = self
    
    lite = AxiLite.same_name_socket(:to_down,mix=true,lite,nil,belong_to_module) unless lite.is_a? String
    
    
    unless self.eql? belong_to_module.AxiLite_NC
        lite = self
    else
        if down_stream
            lite = down_stream
        end
    end


    belong_to_module.AxiLite_draw << axi_lite_master_empty_draw(
        lite:lite,
        down_stream:down_stream)
    return return_stream
end
cmd_exec(type: :write,addr:0,data:0,keep:nil) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 47
def cmd_exec(type: :write,addr:0,data:0,keep:nil)
    if keep
        @__cmds__ << [type,addr,data,keep]
    else
        @__cmds__ << [type,addr,data]
    end
end
cmd_list_draw(num,up_trigger,domn_trigger,ex_str) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 19
    def cmd_list_draw(num,up_trigger,domn_trigger,ex_str)
        large_name_len(num,up_trigger,domn_trigger,self)
"
logic [#{signal}.DSIZE-1:0]  lite_rdata_#{signal};
generate
begin:LITE_CMD_#{signal}
Lite_Addr_Data_CMD #(
    .ASIZE      (#{signal}.ASIZE),
    .DSIZE      (#{signal}.DSIZE)
)addrdatac_#{signal} [#{num.to_s}-1:0] ();

// FilePath::: ../../axi/AXI_Lite/gen_axi_lite_ctrl_verc.sv
gen_axi_lite_ctrl_verc #(
    .NUM        (#{num.to_s})
)gen_axi_lite_ctrl_inst_#{signal}(
/*    input                     */  .from_up_trigger    (#{align_signal(up_trigger  ,q_mark=false)}),
/*    output logic              */  .to_domn_trigger    (#{align_signal(domn_trigger,q_mark=false)}),
/*    axi_lite_inf.master       */  .lite               (#{align_signal(self)}),
/*    Lite_Addr_Data_CMD.slaver */  .addrdatac          (addrdatac_#{signal}),
/*    output logic []           */  .lite_rdata         (lite_rdata_#{signal})
);

#{ex_str}
end
endgenerate
"
    end
cmd_list_draw_step(num,up_trigger,domn_trigger,ex_str) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 125
    def cmd_list_draw_step(num,up_trigger,domn_trigger,ex_str)
        large_name_len(num,up_trigger,domn_trigger,self,@_step_clken_)
"
logic [#{signal}.DSIZE-1:0]  lite_rdata_#{signal};
generate
begin:LITE_CMD_#{signal}
Lite_Addr_Data_CMD #(
    .ASIZE      (#{signal}.ASIZE),
    .DSIZE      (#{signal}.DSIZE)
)addrdatac_#{signal} [#{num.to_s}-1:0] ();

// FilePath::: ../../axi/AXI_Lite/gen_axi_lite_ctrl_C1.sv
gen_axi_lite_ctrl_C1 #(
    .NUM        (#{num.to_s})
)gen_axi_lite_ctrl_inst_#{signal}(
/*    input                     */  .clk_en             (#{align_signal(@_step_clken_  ,q_mark=false)}),
/*    input                     */  .from_up_trigger    (#{align_signal(up_trigger  ,q_mark=false)}),
/*    output logic              */  .to_domn_trigger    (#{align_signal(domn_trigger,q_mark=false)}),
/*    axi_lite_inf.master       */  .lite               (#{align_signal(self)}),
/*    Lite_Addr_Data_CMD.slaver */  .addrdatac          (addrdatac_#{signal}),
/*    output logic []           */  .lite_rdata         (lite_rdata_#{signal})
);

#{ex_str}
end
endgenerate
"
    end
cmd_read_exec(addr) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 59
def cmd_read_exec(addr)
    cmd_exec(type: :read,addr:addr)
end
cmd_read_meet_exec(addr,data) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 63
def cmd_read_meet_exec(addr,data)
    cmd_exec(type: :read_meet,addr:addr,data:data)
end
cmd_read_meet_keep_exec(addr,data,keep) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 67
def cmd_read_meet_keep_exec(addr,data,keep)
    cmd_exec(type: :read_meet_keep,addr:addr,data:data,keep:keep)
end
cmd_wr_exec(addr,data) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 55
def cmd_wr_exec(addr,data)
    cmd_exec(type: :write,addr:addr,data:data)
end
copy(name:@name.to_s,clock:@clock,reset:@reset,dsize:@dsize,asize:@asize,freqM:nil) click to toggle source
# File lib/tdl/elements/axi_lite.rb, line 85
def copy(name:@name.to_s,clock:@clock,reset:@reset,dsize:@dsize,asize:@asize,freqM:nil)
    _freqM = use_which_freq_when_copy(clock,freqM)
    append_name = name_copy(name)
    new_obj = AxiLite.new(name:append_name,clock:clock,reset:reset,dsize:dsize,asize:asize,freqM:_freqM)
    return new_obj
end
draw() click to toggle source

def self.inst

GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.inst_stack.map { |e| e.call }.join("")

end

def self.draw

str = ""
GlobalParam.CurrTdlModule.BindEleClassVars.AxiLite.draw_stack.each do |e|
    str += e.call
end
return str

end

Calls superclass method InfElm#draw
# File lib/tdl/elements/axi_lite.rb, line 74
def draw
    super
    return ''   if @interconnect_up_streams.empty? && @correlation_proc.empty?
    head_str = "\n//-------->>>> #{signal} <<<<----------------\n"
    end_str  = "\n//========<<<< #{signal} >>>>================\n"
    unless @interconnect_up_streams.empty?
        @correlation_proc += interconnect_draw
    end
    return head_str+@correlation_proc+end_str
end
inst() click to toggle source

def signal

if @port
    @name.to_s
else
    "lite_#{@name}_#{@id}_inf"
end

end

# File lib/tdl/elements/axi_lite.rb, line 47
    def inst
        return "" if @ghost
        large_name_len(@mode,@clock,@reset)
"
#{@inf_name} #(
    .ASIZE      (#{align_signal(asize)}),
    .DSIZE      (#{align_signal(dsize)}),
    .FreqM      (#{freq_align_signal})
)#{signal}(
    .axi_aclk       (#{align_signal(@clock,false)}),
    .axi_aresetn    (#{align_signal(@reset.low_signal,false)})
);
"
    end

Private Instance Methods

_axi_lite_slaver_empty_draw( lite:"lite", up_stream:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_slaver_empty_auto.rb, line 32
    def _axi_lite_slaver_empty_draw(
        lite:"lite",
        up_stream:nil
    )

        large_name_len(
            lite
        )
        instance_name = "axi_lite_slaver_empty_#{signal}_inst"
"
// FilePath:::../../axi/AXI_Lite/axi_lite_slaver_empty.sv
axi_lite_slaver_empty #{instance_name}(
/*  axi_lite_inf.slaver*/ .lite (#{align_signal(lite,q_mark=false)})
);
"
    end
axi_lite_master_empty_draw( lite:"lite", down_stream:nil ) click to toggle source
# File lib/tdl/axi_lite/axi_lite_master_empty_auto.rb, line 38
    def axi_lite_master_empty_draw(
        lite:"lite",
        down_stream:nil
    )

        large_name_len(
            lite
        )
        instance_name = "axi_lite_master_empty_#{signal}_inst"
"
// FilePath:::../../axi/AXI_Lite/axi_lite_master_empty.sv
axi_lite_master_empty #{instance_name}(
/*  axi_lite_inf.master*/ .lite (#{align_signal(lite,q_mark=false)})
);
"
    end
render_cmd(index:0,type: :write,addr:0,data:0,keep:0) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 81
def render_cmd(index:0,type: :write,addr:0,data:0,keep:0)
    case type
    when :write then
        "Lite_Addr_Data_WR WR_CMD_#{index}_inst    (addrdatac_#{signal}[#{index}],#{tohex addr},#{tohex data});"
    when :read_meet then
        "Lite_Addr_Data_RD_MEET RD_MEET_#{index}_inst (addrdatac_#{signal}[#{index}],#{tohex addr},#{tohex data});"
    when :read_meet_keep then
        "Lite_Addr_Data_RD_MEET_KEEP RD_MEET_#{index}_inst (addrdatac_#{signal}[#{index}],#{tohex addr},#{tohex data},#{tohex keep});"
    when :read then
        "Lite_Addr_Data_RD RD_#{index}_inst (addrdatac_#{signal}[#{index}],#{tohex addr});"
    else
        "// No Render CMD #{type}!!!"
    end
end
render_cmds() click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 73
def render_cmds
    str_array = []
    @__cmds__.each_index do |index|
        str_array << render_cmd(index:index,type:@__cmds__[index][0],addr:@__cmds__[index][1],data:@__cmds__[index][2],keep:@__cmds__[index][3])
    end
    str_array.join("\n")
end
tohex(num) click to toggle source
# File lib/tdl/axi_lite/lite_cmd.rb, line 96
def tohex(num)
    if num.is_a? Integer
        "32'h#{num.to_s(16)}"
    else
        num
    end
end