class TdlSpace::TdlBaseInterface
Attributes
belong_to_module[RW]
Public Class Methods
inherited(subclass)
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# File lib/tdl/rebuild_ele/ele_base.rb, line 566 def self.inherited(subclass) unless @@child.include? subclass @@child << subclass end end
new(belong_to_module=nil)
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# File lib/tdl/rebuild_ele/ele_base.rb, line 551 def initialize(belong_to_module=nil) element_to_module(belong_to_module) end
parse_ports(port_array,rep,inf_name,up_stream_rep,type) { |h| ... }
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# File lib/tdl/rebuild_ele/ele_base.rb, line 576 def self.parse_ports(port_array,rep,inf_name,up_stream_rep,type) ports = [] del_ports = [] if port_array ports = port_array.map do |e| me = e.match(rep) if me del_ports << e h = Hash.new h[:type] = type h[:modport] = me["modport"].downcase if h[:modport]=="master" h[:way] = :to_down elsif h[:modport]=="slaver" h[:way] = :from_up else h[:way] = :mirror end h[:name] = me["name"].downcase h[:origin_name] = me["name"] h[:vector] = me["vector"] if me["vector"] if me["ud_name"] h[:up_down] = me["ud_name"] =~ up_stream_rep ? "up_stream" : "down_stream" else h[:up_down] = "nil" end ## port_left_len = 4+"#{inf_name}.#{h[:modport]}".length+6 port_right_len = 4+h[:origin_name].length h[:port_left_len] = port_left_len h[:port_right_len] = port_right_len h[:inst_ex_port] = lambda {|left,right| if left >= port_left_len ll = left - port_left_len else ll = 1 end if right >= port_right_len rl = right - port_right_len else rl = 1 end "/* #{inf_name}.#{h[:modport]}" + " "*ll+ "*/ " + ".#{h[:origin_name]}"+" "*rl + " (\#{align_signal(#{h[:name]},q_mark=false)})" } if block_given? yield h end ## h else nil end end end # puts port_array,"=====",del_ports return_ports = port_array - del_ports return return_ports end
subclass()
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# File lib/tdl/rebuild_ele/ele_base.rb, line 572 def self.subclass @@child end
Public Instance Methods
clock_reset_taps(def_clock_name,def_reset_name,self_clock,self_reset)
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# File lib/tdl/rebuild_ele/ele_base.rb, line 675 def clock_reset_taps(def_clock_name,def_reset_name,self_clock,self_reset) new_clk = belong_to_module.logic.clock(self.FreqM) - def_clock_name new_reset = belong_to_module.logic.reset('low') - def_reset_name belong_to_module.Assign do new_clk <= self_clock new_reset <= self_reset end [new_clk,new_reset] end
element_to_module(belong2m)
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# File lib/tdl/rebuild_ele/ele_base.rb, line 555 def element_to_module(belong2m) @belong_to_module = belong2m ec = @belong_to_module.instance_variable_get("@__element_collect__") || [] unless ec.include? self ec << self @belong_to_module.instance_variable_set("@__element_collect__",ec) end end
name_copy(nstr)
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Monkey 布丁, 引入一个 StringBandItegration
集成变量
# File lib/tdl/rebuild_ele/ele_base.rb, line 643 def name_copy(nstr) nstr = nstr || inst_name if nstr.is_a?(StringBandItegration) && true return nstr else if nstr.to_s.eql?(inst_name.to_s) @copy_id ||= 0 str = "#{nstr.to_s}_copy_#{@copy_id}" @copy_id += 1 str else nstr.to_s end end end
path_refs() { |new_name| ... }
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获取信号的绝对路径
# File lib/tdl/exlib/test_point.rb, line 177 def path_refs(&block) collects = [] if @belong_to_module != TopModule.current.techbench @belong_to_module.parents_inst_tree do |tree| ll = ["$root"] rt = tree.reverse rt.each_index do |index| if rt[index].respond_to? :module_name ll << rt[index].module_name else ll << rt[index].inst_name end end ll << inst_name new_name = ll.join('.').to_nq if block_given? if yield(new_name) collects << new_name end else collects << new_name end end else collects = ["$root.#{@belong_to_module.module_name}.#{inst_name}".to_nq] end collects end
use_which_freq_when_copy(argv_clock,argv_origin)
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# File lib/tdl/rebuild_ele/ele_base.rb, line 659 def use_which_freq_when_copy(argv_clock,argv_origin) if argv_clock == @clock && @clock if @clock.respond_to? :freqM @clock.freqM else "#{inst_name}.FreqM".to_nq end elsif argv_clock != @clock && argv_clock.is_a?(Clock) argv_clock.freqM elsif !(argv_clock.is_a?(Clock)) && argv_origin argv_origin else nil end end