1. define_module¶ ↑
define module like systemverilog, include port, parameter
2. hdl_class¶ ↑
syntax look like hdl
3. hdl_sdl_instance¶ ↑
instance of hdl and sdl
4. generate¶ ↑
examples for generate
5. logic_combin¶ ↑
combin logic by (>>, <<)
6. module_with_interface¶ ↑
define interface in module
7. module_with_package¶ ↑
define module with package
8. top_module¶ ↑
define hdl top module with xdc
9. itegration¶ ↑
powerful!!! Itegrative design