module TdlSpace::VarElemenCore

Attributes

dimension[RW]
inst_name[RW]
logic_type[RW]

Public Instance Methods

[](*a) click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 371
def [](*a)
    a.each do |e| 
        if e.is_a? ClassHDL::OpertorChain
            e.slaver = true
        end 
    end
    TdlSpace::ArrayChain.create(obj: self,lchain: a, belong_to_module: belong_to_module)
end
_inner_inst() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 409
def _inner_inst 
    "#{get_class_var('hdl_name')}#{_inner_param_inst}#{inst_name}#{_back_dimension_}#{_inner_io_inst};"
end
inst_port() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 388
def inst_port
    return [_port_inst_core_front,inst_name,_back_dimension_]
end
instance(exp_len: nil) click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 380
def instance(exp_len: nil)
    if modport_type 
        _port_inst(exp_len)
    else
        _inner_inst
    end
end
modport_type() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 392
def modport_type
    @modport_type 
end
modport_type=(a) click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 396
def modport_type=(a)
    ## 清除内部例化
    define_singleton_method('_inner_inst') do 
        nil
    end

    ports = @belong_to_module.instance_variable_get("@ports")
    ports ||= Hash.new
    ports[inst_name] = self
    @belong_to_module.instance_variable_set("@ports",ports)
    @modport_type = a 
end
name() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 362
def name 
    "#{inst_name}"
end
name=(n) click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 366
def name=(n)
    inst_name = n 
    "#{inst_name}"
end
to_s() click to toggle source

# File lib/tdl/rebuild_ele/ele_base.rb, line 358
def to_s 
    "#{inst_name}"
end

Private Instance Methods

_back_dimension_() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 483
def _back_dimension_ 
    ##普通逻辑类型
    if @logic_type.to_s == "logic"  || @logic_type.to_s == "wire"
        if dimension && dimension.size > 1
            str = dimension[0,dimension.size-2].map do |e|
                if e.is_a? Integer
                        "[#{e-1}:0]"
                elsif e.is_a? Array 
                    return "[#{e[0]}:#{e[1]}]"
                else 
                    return "[#{e.to_s}-1:0]"
                end 
            end.join('')
            return " #{str}"
        else
            return ""
        end
    else 
        if dimension && dimension.size > 0
            str = dimension.map do |e|
                if e.is_a? Integer
                        "[#{e-1}:0]"
                elsif e.is_a? Array 
                    return "[#{e[0]}:#{e[1]}]"
                else 
                    return "[#{e.to_s}-1:0]"
                end 
            end.join('')
            return " #{str}"
        else 
            return ''
        end
    end
end
_front_dimension_() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 518
def _front_dimension_
    ##普通逻辑类型
    if @logic_type.to_s == "logic"  || @logic_type.to_s == "wire"
        if dimension && dimension.any? 
            if dimension.last.is_a? Integer
                return " [#{dimension.last-1}-1:0] "
            elsif dimension.last.is_a? Array 
                return " [#{dimension.last[0]}:#{dimension.last[1]}] "
            else 
                return " [#{dimension.last.to_s}-1:0] "
            end 
        else
            return " "
        end
    else 
        return " "
    end
end
_inner_io_inst() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 455
def _inner_io_inst 
    origin_interface_io = get_class_var('origin_interface_io')
    unless origin_interface_io
        return '()'
    end 

    str = []
    origin_interface_io.each do |k,v|
        vv = self.send(k) || v[1]
        ## 去除 sdata pdata 这些内部信号
        if vv && v[2] != 'sdata' && v[2] != 'pdata'
            str << ".#{v[0]}(#{vv})"
        end
    end
    if str.any?
        " (#{str.join(',')}) "
    else 
        '()'
    end

end
_inner_param_inst() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 424
def _inner_param_inst
    origin_interface_params = get_class_var('origin_interface_params')
    unless origin_interface_params
        return ' '
    end
    str = []
    origin_interface_params.each do |k,v|
        rel = self.instance_variable_get("@_#{k}_")
        vv = rel || v[1]
        # vv = self.send(k) || v[1]
        ## 不例化 FreqM,FreqM只是为了SDL兼容
        # if vv && k.to_s != 'freqM'
        if vv 
            if vv.instance_of?(String)
                str << ".#{v[0]}(\"#{vv}\")"
            else
                if k.to_s == 'freqM'
                    str << ".#{v[0]}(#{(respond_to?(:clock) && self.clock.is_a?(Clock) && self.clock.freqM ) || vv})"
                else 
                    str << ".#{v[0]}(#{vv})"
                end
            end
        end
    end
    if str.any?
        " #(#{str.join(',')}) "
    else 
        ' '
    end
end
_port_inst(exp_len=nil) click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 415
def _port_inst(exp_len=nil)
    front_str = _port_inst_core_front
    len_front = front_str.size
    if exp_len && exp_len > front_str
        front_str   = front_str + " "*(exp_len - front_str)
    end
    "#{front_str}#{inst_name}#{_back_dimension_}"
end
_port_inst_core_front() click to toggle source
# File lib/tdl/rebuild_ele/ele_base.rb, line 477
def _port_inst_core_front
    # modport_type = :master
    "#{get_class_var('hdl_name')}#{@modport_type ? ".#{@modport_type}" : ""} #{@logic_type}#{_front_dimension_}"
    # modport_type
end
get_class_var(name) click to toggle source

获取 类变量

# File lib/tdl/rebuild_ele/ele_base.rb, line 538
def get_class_var(name)
    self.class.get_class_var(name,nil)
end