module Hypervisor

Constants

BAD_ARGUMENT
BUSY
CPU_BASED2_APIC_REG_VIRT
CPU_BASED2_DESC_TABLE
CPU_BASED2_EPT
CPU_BASED2_EPT_VE
CPU_BASED2_INVPCID
CPU_BASED2_PAUSE_LOOP
CPU_BASED2_RDRAND
CPU_BASED2_RDSEED
CPU_BASED2_RDTSCP
CPU_BASED2_UNRESTRICTED
CPU_BASED2_VIRTUAL_APIC
CPU_BASED2_VIRT_INTR_DELIVERY
CPU_BASED2_VMCS_SHADOW
CPU_BASED2_VMFUNC
CPU_BASED2_VPID
CPU_BASED2_WBINVD
CPU_BASED2_X2APIC
CPU_BASED2_XSAVES_XRSTORS
CPU_BASED_CR3_LOAD
CPU_BASED_CR3_STORE
CPU_BASED_CR8_LOAD
CPU_BASED_CR8_STORE
CPU_BASED_HLT
CPU_BASED_INVLPG
CPU_BASED_IO_BITMAPS
CPU_BASED_IRQ_WND
CPU_BASED_MONITOR
CPU_BASED_MOV_DR
CPU_BASED_MSR_BITMAPS
CPU_BASED_MTF
CPU_BASED_MWAIT
CPU_BASED_PAUSE
CPU_BASED_RDPMC
CPU_BASED_RDTSC
CPU_BASED_SECONDARY_CTLS
CPU_BASED_TPR_SHADOW
CPU_BASED_TSC_OFFSET
CPU_BASED_UNCOND_IO
CPU_BASED_VIRTUAL_NMI_WND
ERROR
IRQ_INFO_ERROR_VALID
IRQ_INFO_EXT_IRQ
IRQ_INFO_HARD_EXC
IRQ_INFO_NMI
IRQ_INFO_PRIV_SOFT_EXC
IRQ_INFO_SOFT_EXC
IRQ_INFO_SOFT_IRQ
IRQ_INFO_VALID
MEMORY_EXEC
MEMORY_READ
MEMORY_WRITE
NO_DEVICE
NO_RESOURCES
PIN_BASED_INTR
PIN_BASED_NMI
PIN_BASED_POSTED_INTR
PIN_BASED_PREEMPTION_TIMER
PIN_BASED_VIRTUAL_NMI
SUCCESS

hv_error.h

UNSUPPORTED
VCPU_DEFAULT
VERSION
VMCS_CTRL_APIC_ACCESS
VMCS_CTRL_CPU_BASED
VMCS_CTRL_CPU_BASED2
VMCS_CTRL_CR0_MASK
VMCS_CTRL_CR0_SHADOW
VMCS_CTRL_CR3_COUNT
VMCS_CTRL_CR3_VALUE0
VMCS_CTRL_CR3_VALUE1
VMCS_CTRL_CR3_VALUE2
VMCS_CTRL_CR3_VALUE3
VMCS_CTRL_CR4_MASK
VMCS_CTRL_CR4_SHADOW
VMCS_CTRL_EOI_EXIT_BITMAP_0
VMCS_CTRL_EOI_EXIT_BITMAP_1
VMCS_CTRL_EOI_EXIT_BITMAP_2
VMCS_CTRL_EOI_EXIT_BITMAP_3
VMCS_CTRL_EPTP
VMCS_CTRL_EPTP_INDEX
VMCS_CTRL_EPTP_LIST_ADDR
VMCS_CTRL_EXC_BITMAP
VMCS_CTRL_EXECUTIVE_VMCS_PTR
VMCS_CTRL_IO_BITMAP_A
VMCS_CTRL_IO_BITMAP_B
VMCS_CTRL_MSR_BITMAPS
VMCS_CTRL_PF_ERROR_MASK
VMCS_CTRL_PF_ERROR_MATCH
VMCS_CTRL_PIN_BASED
VMCS_CTRL_PLE_GAP
VMCS_CTRL_PLE_WINDOW
VMCS_CTRL_POSTED_INT_DESC_ADDR
VMCS_CTRL_POSTED_INT_N_VECTOR
VMCS_CTRL_TPR_THRESHOLD
VMCS_CTRL_TSC_OFFSET
VMCS_CTRL_VIRTUAL_APIC
VMCS_CTRL_VIRT_EXC_INFO_ADDR
VMCS_CTRL_VMENTRY_CONTROLS
VMCS_CTRL_VMENTRY_EXC_ERROR
VMCS_CTRL_VMENTRY_INSTR_LEN
VMCS_CTRL_VMENTRY_IRQ_INFO
VMCS_CTRL_VMENTRY_MSR_LOAD_ADDR
VMCS_CTRL_VMENTRY_MSR_LOAD_COUNT
VMCS_CTRL_VMEXIT_CONTROLS
VMCS_CTRL_VMEXIT_MSR_LOAD_ADDR
VMCS_CTRL_VMEXIT_MSR_LOAD_COUNT
VMCS_CTRL_VMEXIT_MSR_STORE_ADDR
VMCS_CTRL_VMEXIT_MSR_STORE_COUNT
VMCS_CTRL_VMFUNC_CTRL
VMCS_CTRL_VMREAD_BITMAP_ADDR
VMCS_CTRL_VMWRITE_BITMAP_ADDR
VMCS_CTRL_XSS_EXITING_BITMAP
VMCS_GUEST_ACTIVITY_STATE
VMCS_GUEST_CR0
VMCS_GUEST_CR3
VMCS_GUEST_CR4
VMCS_GUEST_CS
VMCS_GUEST_CS_AR
VMCS_GUEST_CS_BASE
VMCS_GUEST_CS_LIMIT
VMCS_GUEST_DEBUG_EXC
VMCS_GUEST_DR7
VMCS_GUEST_DS
VMCS_GUEST_DS_AR
VMCS_GUEST_DS_BASE
VMCS_GUEST_DS_LIMIT
VMCS_GUEST_ES
VMCS_GUEST_ES_AR
VMCS_GUEST_ES_BASE
VMCS_GUEST_ES_LIMIT
VMCS_GUEST_FS
VMCS_GUEST_FS_AR
VMCS_GUEST_FS_BASE
VMCS_GUEST_FS_LIMIT
VMCS_GUEST_GDTR_BASE
VMCS_GUEST_GDTR_LIMIT
VMCS_GUEST_GS
VMCS_GUEST_GS_AR
VMCS_GUEST_GS_BASE
VMCS_GUEST_GS_LIMIT
VMCS_GUEST_IA32_DEBUGCTL
VMCS_GUEST_IA32_EFER
VMCS_GUEST_IA32_PAT
VMCS_GUEST_IA32_PERF_GLOBAL_CTRL
VMCS_GUEST_IA32_SYSENTER_CS
VMCS_GUEST_IDTR_BASE
VMCS_GUEST_IDTR_LIMIT
VMCS_GUEST_IGNORE_IRQ
VMCS_GUEST_INT_STATUS
VMCS_GUEST_LDTR
VMCS_GUEST_LDTR_AR
VMCS_GUEST_LDTR_BASE
VMCS_GUEST_LDTR_LIMIT
VMCS_GUEST_PDPTE0
VMCS_GUEST_PDPTE1
VMCS_GUEST_PDPTE2
VMCS_GUEST_PDPTE3
VMCS_GUEST_PHYSICAL_ADDRESS
VMCS_GUEST_RFLAGS
VMCS_GUEST_RIP
VMCS_GUEST_RSP
VMCS_GUEST_SMBASE
VMCS_GUEST_SS
VMCS_GUEST_SS_AR
VMCS_GUEST_SS_BASE
VMCS_GUEST_SS_LIMIT
VMCS_GUEST_SYSENTER_EIP
VMCS_GUEST_SYSENTER_ESP
VMCS_GUEST_TR
VMCS_GUEST_TR_AR
VMCS_GUEST_TR_BASE
VMCS_GUEST_TR_LIMIT
VMCS_GUEST_VMX_TIMER_VALUE
VMCS_HOST_CR0
VMCS_HOST_CR3
VMCS_HOST_CR4
VMCS_HOST_CS
VMCS_HOST_DS
VMCS_HOST_ES
VMCS_HOST_FS
VMCS_HOST_FS_BASE
VMCS_HOST_GDTR_BASE
VMCS_HOST_GS
VMCS_HOST_GS_BASE
VMCS_HOST_IA32_EFER
VMCS_HOST_IA32_PAT
VMCS_HOST_IA32_PERF_GLOBAL_CTRL
VMCS_HOST_IA32_SYSENTER_CS
VMCS_HOST_IA32_SYSENTER_EIP
VMCS_HOST_IA32_SYSENTER_ESP
VMCS_HOST_IDTR_BASE
VMCS_HOST_RIP
VMCS_HOST_RSP
VMCS_HOST_SS
VMCS_HOST_TR
VMCS_HOST_TR_BASE
VMCS_MAX
VMCS_RO_EXIT_QUALIFIC
VMCS_RO_EXIT_REASON
VMCS_RO_GUEST_LIN_ADDR
VMCS_RO_IDT_VECTOR_ERROR
VMCS_RO_IDT_VECTOR_INFO
VMCS_RO_INSTR_ERROR
VMCS_RO_IO_RCX
VMCS_RO_IO_RDI
VMCS_RO_IO_RIP
VMCS_RO_IO_RSI
VMCS_RO_VMEXIT_INSTR_LEN
VMCS_RO_VMEXIT_IRQ_ERROR
VMCS_RO_VMEXIT_IRQ_INFO
VMCS_RO_VMX_INSTR_INFO
VMCS_VPID

hv_arch_vmx.h

VMENTRY_DEACTIVATE_DUAL_MONITOR
VMENTRY_GUEST_IA32E
VMENTRY_LOAD_DBG_CONTROLS
VMENTRY_LOAD_EFER
VMENTRY_LOAD_IA32_PAT
VMENTRY_LOAD_IA32_PERF_GLOBAL_CTRL
VMENTRY_SMM
VMEXIT_ACK_INTR
VMEXIT_HOST_IA32E
VMEXIT_LOAD_EFER
VMEXIT_LOAD_IA32_PAT
VMEXIT_LOAD_IA32_PERF_GLOBAL_CTRL
VMEXIT_SAVE_DBG_CONTROLS
VMEXIT_SAVE_EFER
VMEXIT_SAVE_IA32_PAT
VMEXIT_SAVE_VMX_TIMER
VMX_BASIC_TRUE_CTLS
VMX_CAP_ENTRY
VMX_CAP_EXIT
VMX_CAP_PINBASED

hv_vmx.h

VMX_CAP_PREEMPTION_TIMER
VMX_CAP_PROCBASED
VMX_CAP_PROCBASED2
VMX_EPT_VPID_SUPPORT_AD
VMX_EPT_VPID_SUPPORT_EXONLY
VMX_REASON_APIC_ACCESS
VMX_REASON_APIC_WRITE
VMX_REASON_CPUID
VMX_REASON_EPT_INVEPT
VMX_REASON_EPT_MISCONFIG
VMX_REASON_EPT_VIOLATION
VMX_REASON_EXC_NMI
VMX_REASON_GDTR_IDTR
VMX_REASON_GETSEC
VMX_REASON_HLT
VMX_REASON_INIT
VMX_REASON_INVD
VMX_REASON_INVLPG
VMX_REASON_INVPCID
VMX_REASON_INVVPID
VMX_REASON_IO
VMX_REASON_IO_SMI
VMX_REASON_IRQ
VMX_REASON_IRQ_WND
VMX_REASON_LDTR_TR
VMX_REASON_MONITOR
VMX_REASON_MOV_CR
VMX_REASON_MOV_DR
VMX_REASON_MTF
VMX_REASON_MWAIT
VMX_REASON_OTHER_SMI
VMX_REASON_PAUSE
VMX_REASON_RDMSR
VMX_REASON_RDPMC
VMX_REASON_RDRAND
VMX_REASON_RDSEED
VMX_REASON_RDTSC
VMX_REASON_RDTSCP
VMX_REASON_RSM
VMX_REASON_SIPI
VMX_REASON_TASK
VMX_REASON_TPR_THRESHOLD
VMX_REASON_TRIPLE_FAULT
VMX_REASON_VIRTUALIZED_EOI
VMX_REASON_VIRTUAL_NMI_WND
VMX_REASON_VMCALL
VMX_REASON_VMCLEAR
VMX_REASON_VMENTRY_GUEST
VMX_REASON_VMENTRY_MC
VMX_REASON_VMENTRY_MSR
VMX_REASON_VMFUNC
VMX_REASON_VMLAUNCH
VMX_REASON_VMOFF
VMX_REASON_VMON
VMX_REASON_VMPTRLD
VMX_REASON_VMPTRST
VMX_REASON_VMREAD
VMX_REASON_VMRESUME
VMX_REASON_VMWRITE
VMX_REASON_VMX_TIMER_EXPIRED
VMX_REASON_WBINVD
VMX_REASON_WRMSR
VMX_REASON_XRSTORS
VMX_REASON_XSAVES
VMX_REASON_XSETBV
VM_DEFAULT

hv_types.h

VM_MITIGATION_A_ENABLE
VM_MITIGATION_B_ENABLE
VM_MITIGATION_C_ENABLE
VM_MITIGATION_D_ENABLE
VM_SPECIFY_MITIGATIONS
X86_CR0
X86_CR1
X86_CR2
X86_CR3
X86_CR4
X86_CS
X86_DR0
X86_DR1
X86_DR2
X86_DR3
X86_DR4
X86_DR5
X86_DR6
X86_DR7
X86_DS
X86_ES
X86_FS
X86_GDT_BASE
X86_GDT_LIMIT
X86_GS
X86_IDT_BASE
X86_IDT_LIMIT
X86_LDTR
X86_LDT_AR
X86_LDT_BASE
X86_LDT_LIMIT
X86_R10
X86_R11
X86_R12
X86_R13
X86_R14
X86_R15
X86_R8
X86_R9
X86_RAX
X86_RBP
X86_RBX
X86_RCX
X86_RDI
X86_RDX
X86_RFLAGS
X86_RIP

hv_arch_x86.h

X86_RSI
X86_RSP
X86_SS
X86_TPR
X86_TR
X86_TSS_AR
X86_TSS_BASE
X86_TSS_LIMIT
X86_XCR0

Public Class Methods

allocate(n, &block) click to toggle source
# File lib/hypervisor.rb, line 9
def self.allocate(n, &block)
  FFI::AutoPointer.new(Hypervisor::Framework.valloc(n), Hypervisor::Framework.method(:free), &block)
end
create(options = VM_DEFAULT) click to toggle source
# File lib/hypervisor.rb, line 13
def self.create(options = VM_DEFAULT)
  Framework.return_t(Framework.hv_vm_create(options))
end
destroy() click to toggle source
# File lib/hypervisor.rb, line 17
def self.destroy
  Framework.return_t(Framework.hv_vm_destroy)
end
map(uva, gpa, size, flags) click to toggle source
# File lib/hypervisor.rb, line 21
def self.map(uva, gpa, size, flags)
  Framework.return_t(Framework.hv_vm_map(uva, gpa, size, flags))
end
protect(gpa, size, flags) click to toggle source
# File lib/hypervisor.rb, line 29
def self.protect(gpa, size, flags)
  Framework.return_t(Framework.hv_vm_protect(gpa, size, flags))
end
read_capability(field) click to toggle source
# File lib/hypervisor.rb, line 37
def self.read_capability(field)
  FFI::MemoryPointer.new(:uint64_t, 1) do |value|
    Framework.return_t(Framework.hv_vmx_read_capability(field, value))

    return value.get_uint64(0)
  end
end
sync_tsc(tsc) click to toggle source
# File lib/hypervisor.rb, line 33
def self.sync_tsc(tsc)
  Framework.return_t(Framework.hv_vm_sync_tsc(tsc))
end
unmap(gpa, size) click to toggle source
# File lib/hypervisor.rb, line 25
def self.unmap(gpa, size)
  Framework.return_t(Framework.hv_vm_unmap(gpa, size))
end