module RgGen::SystemVerilog::RTL::RegisterType

Private Instance Methods

address_width() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 23
def address_width
  register_block.local_address_width
end
bus_width() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 19
def bus_width
  configuration.bus_width
end
byte_offset(component) click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 42
def byte_offset(component)
  "#{component.byte_size(false)}*(#{component.local_index})"
end
collect_offsets(component) click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 34
def collect_offsets(component)
  if component.register_file? && component.array?
    [component.offset_address, byte_offset(component)]
  else
    component.offset_address
  end
end
format_offset(offset) click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 50
def format_offset(offset)
  offset.is_a?(Integer) ? hex(offset, address_width) : offset
end
format_offsets(offsets) click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 46
def format_offsets(offsets)
  offsets.map(&method(:format_offset)).join('+')
end
offset_address() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 27
def offset_address
  [*register_files, register]
    .flat_map(&method(:collect_offsets))
    .yield_self(&method(:partial_sums))
    .yield_self(&method(:format_offsets))
end
readable() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 11
def readable
  register.readable? && 1 || 0
end
register_index() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 63
def register_index
  register.local_index || 0
end
valid_bits() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 58
def valid_bits
  bits = register.bit_fields.map(&:bit_map).inject(:|)
  hex(bits, register.width)
end
width() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 54
def width
  register.width
end
writable() click to toggle source
# File lib/rggen/systemverilog/rtl/register_type.rb, line 15
def writable
  register.writable? && 1 || 0
end