class Object
Public Instance Methods
access()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 26 def access (helper.access || bit_field.type).to_s.upcase end
access_rights()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 63 def access_rights if read_only? 'RO' elsif write_only? 'WO' else 'RW' end end
address_width()
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 27 def address_width register_block.local_address_width end
arguments(index)
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 47 def arguments(index) [ ral_model[index], bit_field.lsb(index), bit_field.width, string(access), volatile, reset_value(index), valid_reset, index || -1, string(reference) ] end
array_port_format()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 8 def array_port_format configuration.array_port_format end
array_size()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 43 def array_size Array(bit_field.sequence_size) end
assign_axi4lite_signals(code)
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# File lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb, line 122 def assign_axi4lite_signals(code) [ [axi4lite_if.awvalid, awvalid], [awready, axi4lite_if.awready], [axi4lite_if.awid, awid], [axi4lite_if.awaddr, awaddr], [axi4lite_if.awprot, awprot], [axi4lite_if.wvalid, wvalid], [wready, axi4lite_if.wready], [axi4lite_if.wdata, wdata], [axi4lite_if.wstrb, wstrb], [bvalid, axi4lite_if.bvalid], [axi4lite_if.bready, bready], [bid, axi4lite_if.bid], [bresp, axi4lite_if.bresp], [axi4lite_if.arvalid, arvalid], [arready, axi4lite_if.arready], [axi4lite_if.arid, arid], [axi4lite_if.araddr, araddr], [axi4lite_if.arprot, arprot], [rvalid, axi4lite_if.rvalid], [axi4lite_if.rready, rready], [rid, axi4lite_if.rid], [rdata, axi4lite_if.rdata], [rresp, axi4lite_if.rresp] ].each { |lhs, rhs| code << assign(lhs, rhs) << nl } end
available_protocols()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 9 def available_protocols feature_registries .map(&method(:collect_available_protocols)).inject(:&) end
bit_field_if()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 48 def bit_field_if bit_field.bit_field_sub_if end
bit_field_if_connection()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 117 def bit_field_if_connection macro_call( 'rggen_connect_bit_field_if', [ register.bit_field_if, bit_field.bit_field_sub_if, bit_field.lsb(local_index), bit_field.width ] ) end
body_code(code)
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 113 def body_code(code) bit_field.generate_code(code, :bit_field, :top_down) end
bus_width()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 95 def bus_width configuration.bus_width end
byte_size()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 111 def byte_size register_block.byte_size end
byte_width()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb, line 28 def byte_width configuration.byte_width end
child_model_constructors()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb, line 32 def child_model_constructors register_block.children.flat_map(&:constructors) end
clear_signal()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rwc.rb, line 22 def clear_signal reference_bit_field || clear[loop_variables] end
clock()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 20 def clock register_block.clock end
collect_available_protocols(registry)
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 20 def collect_available_protocols(registry) registry .enabled_features(:protocol) .select { |protocol| registry.feature?(:protocol, protocol) } end
constructor(&body)
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# File lib/rggen/systemverilog/ral/register/type.rb, line 19 def constructor(&body) @constructor = body if block_given? @constructor end
constructor_code(array_index, index)
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# File lib/rggen/systemverilog/ral/register/type.rb, line 48 def constructor_code(array_index, index) if helper.constructor instance_exec(array_index, index, &helper.constructor) else macro_call(:rggen_ral_create_reg, arguments(array_index, index)) end end
constructors()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 35 def constructors (bit_field.sequence_size&.times || [nil]).map do |index| macro_call('rggen_ral_create_field', arguments(index)) end end
control_signal()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb, line 26 def control_signal reference_bit_field || control[loop_variables] end
default_protocol()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 59 def default_protocol available_protocols.first end
enable_or_lock()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb, line 22 def enable_or_lock { rwe: :enable, rwl: :lock }[bit_field.type] end
end_address()
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# File lib/rggen/systemverilog/rtl/register/type/external.rb, line 74 def end_address address = register.offset_address + register.byte_size - 1 hex(address, address_width) end
feature_registries()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 16 def feature_registries @feature_registries ||= [] end
feature_registry(registry)
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 5 def feature_registry(registry) feature_registries << registry end
field_full_name(field)
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# File lib/rggen/systemverilog/ral/register/type/indirect.rb, line 34 def field_full_name(field) [field.register.full_name('.'), field.name].join('.') end
field_model_constructors()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 85 def field_model_constructors register.bit_fields.flat_map(&:constructors) end
find_protocol(value)
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 55 def find_protocol(value) available_protocols.find(&value.to_sym.method(:casecmp?)) end
full_name()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 12 def full_name bit_field.full_name('_') end
id_port_width()
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# File lib/rggen/systemverilog/rtl/register_block/protocol/axi4lite.rb, line 118 def id_port_width "((#{id_width}>0)?#{id_width}:1)" end
include_files()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb, line 30 def include_files ['uvm_macros.svh', 'rggen_ral_macros.svh'] end
index_fields()
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# File lib/rggen/systemverilog/ral/register/type/indirect.rb, line 30 def index_fields register.collect_index_fields(register_block.bit_fields) end
index_properties()
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# File lib/rggen/systemverilog/ral/register/type/indirect.rb, line 17 def index_properties array_position = -1 register.index_entries.zip(index_fields).map do |entry, field| value = if entry.value_index? hex(entry.value, field.width) else "array_index[#{array_position += 1}]" end [field_full_name(field), value] end end
initial_value()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 32 def initial_value index = bit_field.initial_value_array? && bit_field.local_index || nil bit_field.initial_value[index] end
initial_value_array_rhs()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 80 def initial_value_array_rhs if fixed_initial_value? array(sized_initial_values) elsif initial_value_format == :unpacked array(default: sized_initial_value) else repeat(bit_field.sequence_size, sized_initial_value) end end
initial_value_format()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 71 def initial_value_format fixed_initial_value? && :unpacked || configuration.array_port_format end
initial_value_name()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 60 def initial_value_name identifiers = [] identifiers << bit_field.full_name('_') unless fixed_initial_value? identifiers << 'initial_value' identifiers.join('_').upcase end
initial_value_rhs()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 76 def initial_value_rhs initial_value_array? && initial_value_array_rhs || sized_initial_value end
initial_value_size()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 67 def initial_value_size initial_value_array? && [bit_field.sequence_size] || nil end
local_address_width()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 103 def local_address_width register_block.local_address_width end
loop_size()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 99 def loop_size loop_variable = local_index loop_variable && { loop_variable => bit_field.sequence_size } end
loop_variables()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 52 def loop_variables bit_field.loop_variables end
macro_definition(code)
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 44 def macro_definition(code) code << process_template(File.join(__dir__, 'sv_rtl_macros.erb')) end
mask()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 37 def mask reference_bit_field || all_bits_1 end
model_body()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 101 def model_body process_template(File.join(__dir__, 'type', 'default.erb')) end
model_name(name = nil, &block)
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 9 def model_name(name = nil, &block) @model_name = name || block || @model_name @model_name end
offset_address(&body)
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# File lib/rggen/systemverilog/ral/register/type.rb, line 14 def offset_address(&body) @offset_address = body if block_given? @offset_address end
package_name()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb, line 19 def package_name "#{register_block.name}_ral_pkg" end
packages()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_package.rb, line 23 def packages [ 'uvm_pkg', 'rggen_ral_pkg', *register_block.package_imports(:ral_package) ] end
parameters()
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# File lib/rggen/systemverilog/ral/register_block/sv_ral_model.rb, line 20 def parameters register_block.declarations[:parameter] end
polarity()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rwe_rwl.rb, line 30 def polarity { rwe: 'RGGEN_ACTIVE_HIGH', rwl: 'RGGEN_ACTIVE_LOW' }[bit_field.type] end
ports()
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 66 def ports register_block.declarations[:port] end
read_action()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 26 def read_action { rc: 'RGGEN_READ_CLEAR', w0c: 'RGGEN_READ_DEFAULT', w1c: 'RGGEN_READ_DEFAULT', wc: 'RGGEN_READ_DEFAULT', woc: 'RGGEN_READ_NONE' }[bit_field.type] end
read_only?()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 73 def read_only? !register.writable? end
read_set?()
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# File lib/rggen/systemverilog/rtl/bit_field/type/w0crs_w0src_w1crs_w1src_wcrs_wsrc.rb, line 22 def read_set? [:w0crs, :w1crs, :wcrs].include?(bit_field.type) end
reference()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 68 def reference if bit_field.reference? reference_field = bit_field.reference [reference_field.register.full_name('.'), reference_field.name].join('.') else '' end end
reference_bit_field()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 41 def reference_bit_field bit_field.reference? && bit_field .find_reference(register_block.bit_fields) .value(bit_field.local_indices, bit_field.reference_width) end
reference_or_value_in()
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# File lib/rggen/systemverilog/rtl/bit_field/type/ro.rb, line 18 def reference_or_value_in bit_field.reference? && reference_bit_field || value_in[loop_variables] end
register_if(offsets)
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 55 def register_if(offsets) index = register.index(offsets || register.local_indices) register_block.register_if[index] end
reset()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 24 def reset register_block.reset end
reset_value(index)
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 58 def reset_value(index) value = bit_field.initial_values&.at(index) || bit_field.initial_value || 0 hex(value, bit_field.width) end
set_signal()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rws.rb, line 26 def set_signal reference_bit_field || set[loop_variables] end
sized_initial_value()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 90 def sized_initial_value bit_field.initial_value && hex(bit_field.initial_value, bit_field.width) end
sized_initial_values()
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 95 def sized_initial_values bit_field.initial_values&.map { |v| hex(v, bit_field.width) } end
start_address()
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# File lib/rggen/systemverilog/rtl/register/type/external.rb, line 70 def start_address hex(register.offset_address, address_width) end
sv_module_body(code)
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 74 def sv_module_body(code) { register_block: nil, register_file: 1 }.each do |kind, depth| register_block.generate_code(code, kind, :top_down, depth) end end
sv_module_definition(code)
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 48 def sv_module_definition(code) code << module_definition(register_block.name) do |sv_module| sv_module.package_imports packages sv_module.parameters parameters sv_module.ports ports sv_module.variables variables sv_module.body(&method(:sv_module_body)) end end
target_feature_key(_configuration, bit_field)
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 82 def target_feature_key(_configuration, bit_field) bit_field.type end
top_scope?()
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# File lib/rggen/systemverilog/rtl/register/sv_rtl_top.rb, line 28 def top_scope? register_file.nil? end
total_registers()
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# File lib/rggen/systemverilog/rtl/register_block/protocol.rb, line 107 def total_registers register_block.total_registers end
trigger_value()
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# File lib/rggen/systemverilog/rtl/bit_field/type/w0trg_w1trg.rb, line 16 def trigger_value bin({ w0trg: 0, w1trg: 1 }[bit_field.type], 1) end
valid_reset()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 64 def valid_reset bit_field.initial_value? && 1 || 0 end
value(offsets = nil, width = nil)
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# File lib/rggen/systemverilog/rtl/bit_field/sv_rtl_top.rb, line 43 def value(offsets = nil, width = nil) value_lsb = bit_field.lsb(offsets&.last || local_index) value_width = width || bit_field.width register_if(offsets&.slice(0..-2)).value[value_lsb, value_width] end
value_out_unmasked()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 50 def value_out_unmasked (bit_field.reference? || nil) && value_unmasked[loop_variables] end
value_width()
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# File lib/rggen/systemverilog/rtl/register_block/sv_rtl_top.rb, line 35 def value_width register_block.registers.map(&:width).max end
variables()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 81 def variables register.declarations[:variable] end
volatile()
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# File lib/rggen/systemverilog/ral/bit_field/type.rb, line 54 def volatile bit_field.volatile? && 1 || 0 end
width()
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# File lib/rggen/systemverilog/rtl/bit_field/type.rb, line 16 def width bit_field.width end
write_action()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 36 def write_action { rc: 'RGGEN_WRITE_NONE', w0c: 'RGGEN_WRITE_0_CLEAR', w1c: 'RGGEN_WRITE_1_CLEAR', wc: 'RGGEN_WRITE_CLEAR', woc: 'RGGEN_WRITE_CLEAR' }[bit_field.type] end
write_enable()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rc_w0c_w1c_wc_woc.rb, line 46 def write_enable bit_field.writable? && all_bits_1 || all_bits_0 end
write_once()
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# File lib/rggen/systemverilog/rtl/bit_field/type/rw_w1_wo_wo1.rb, line 20 def write_once [:w1, :wo1].include?(bit_field.type) && 1 || 0 end
write_only?()
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# File lib/rggen/systemverilog/ral/register/type.rb, line 77 def write_only? register.writable? && !register.readable? end