module RgGen::SystemVerilog::RTL::RegisterType
Private Instance Methods
address_width()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 23 def address_width register_block.local_address_width end
bus_width()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 19 def bus_width configuration.bus_width end
byte_offset(component)
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 42 def byte_offset(component) "#{component.byte_size(false)}*(#{component.local_index})" end
collect_offsets(component)
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 34 def collect_offsets(component) if component.register_file? && component.array? [component.offset_address, byte_offset(component)] else component.offset_address end end
format_offset(offset)
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 50 def format_offset(offset) offset.is_a?(Integer) ? hex(offset, address_width) : offset end
format_offsets(offsets)
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 46 def format_offsets(offsets) offsets.map(&method(:format_offset)).join('+') end
offset_address()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 27 def offset_address [*register_files, register] .flat_map(&method(:collect_offsets)) .yield_self(&method(:partial_sums)) .yield_self(&method(:format_offsets)) end
readable()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 11 def readable register.readable? && 1 || 0 end
register_index()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 63 def register_index register.local_index || 0 end
valid_bits()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 58 def valid_bits bits = register.bit_fields.map(&:bit_map).inject(:|) hex(bits, register.width) end
width()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 54 def width register.width end
writable()
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# File lib/rggen/systemverilog/rtl/register_type.rb, line 15 def writable register.writable? && 1 || 0 end