/*******************************************************************************
* Copyright 2023-2024 Intel Corporation
*
* Licensed under the Apache License, Version 2.0 (the "License");
* you may not use this file except in compliance with the License.
* You may obtain a copy of the License at
*
*     http://www.apache.org/licenses/LICENSE-2.0
*
* Unless required by applicable law or agreed to in writing, software
* distributed under the License is distributed on an "AS IS" BASIS,
* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
* See the License for the specific language governing permissions and
* limitations under the License.
*******************************************************************************/

#include "cpu/reorder/cpu_reorder.hpp"

namespace dnnl {
namespace impl {
namespace cpu {

// clang-format off

const impl_list_map_t &regular_s4_impl_list_map() {
    static const impl_list_map_t the_map = REG_REORDER_P({
        {{f32, s4, 0}, {
            REG_SR(f32, any, s4, any, fmt_order::any, spec::reference)
            nullptr,
        }},
        {{s4, data_type::undef, 0}, {
            REG_SR(s4, any, s4, OI8i8o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI8i16o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI8i24o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI8i32o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI8i64o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI16i16o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI16i32o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI16i48o2i, fmt_order_keep)
            REG_SR(s4, any, s4, OI16i64o2i, fmt_order_keep)
            REG_SR(s4, any, s4, aBC8c8b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC8c16b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC8c24b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC8c32b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC8c64b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c16b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c32b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c48b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c64b2c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c16b4c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c32b4c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c48b4c, fmt_order_keep)
            REG_SR(s4, any, s4, aBC16c64b4c, fmt_order_keep)
            REG_SR(s4, any, u8, any, fmt_order_keep, spec::reference)
            REG_SR(s4, any, f32, any, fmt_order_keep, spec::reference)
            REG_SR(s4, any, f32, any, fmt_order::any, spec::reference)
            REG_SR(s4, any, bf16, any, fmt_order::any, spec::reference)
            REG_SR(s4, any, f16, any, fmt_order::any, spec::reference)
            nullptr,
        }},
        {{s4, f32, 0}, {
            REG_SR(s4, any, f32, any, fmt_order::any, spec::reference)
            DNNL_X64_ONLY(CPU_REORDER_INSTANCE(x64_brgemm_matmul_copy_reorder_t))
            nullptr,
        }},
    });
    return the_map;
}

// clang-format on

} // namespace cpu
} // namespace impl
} // namespace dnnl
