// Copyright (C) 2023-2025 Intel Corporation
// SPDX-License-Identifier: Apache-2.0
namespace MVCNN;

enum PhysicalProcessor : byte {
    // Enum for describing processor resources
    NULL = 0, // This is either an invalid processor, or a conceptual one that cannot be computed on.
    LEON_RT = 1,
    LEON_NN = 2,
    NN_SHV = 3,
    ARM = 4,
    NCE_Cluster = 5,
    NCE_PerClusterDPU = 6
}

enum DMAEngine : byte{
    NULL = 0,
    NN = 1
}

// Flatbuffers does not compile the full name, so shorted to Mem
enum PhysicalMem : byte {
    // Different to MemoryLocation in that this represents the actual hardware
    // and MemoryLoc ation represents conceptual addressing.
    NULL = 0, // This is either an invalid location, or a conceptual one that cannot be computed on.
    DDR = 1,
    NN_CMX = 2,
    CSRAM = 3
}

// Constructs to show relations and quantities
// Unfortunately Unions do not play well with enums
table MemoryMapping {
  item: PhysicalMem;
  number: double;
}

table ProcessorMapping{
  item: PhysicalProcessor;
  number: double;
  is_bitmask: bool; // Indicates that "number" is a bitmask, not a count
  activity_factor: float; // Value in [0.0..1.0] range indicating the expected usage of this resource during the inference.
}

table MemoryRelationshipMapping {
  from_item: PhysicalMem;
  to_item: PhysicalMem;
  number: double;
}

enum TargetDevice : byte {
    // Enum for defining target device type
    NONE = 0,
    VPUX30XX = 1,
    VPUX37XX = 2,
    VPUX311X = 3,
    VPUX40XX = 4,
}

enum TargetDeviceRevision : byte {
    // Enum for defining target device revision
    NONE = 0,
    A0 = 1,
    B0 = 2
}

// Row entry for Scalability table: value in [0.0..1.0] range indicating scalability of network for a given DDR bandwidth.
table ScalabilityByBandwidth {
  by_bw:[float]; // Must contain 5 entries.
}

// Table of scalability values for different VPU frequency values.
table Scalability {
  by_freq: [ScalabilityByBandwidth]; // Must contain 5 entries.
}

// Row entry for InferenceTiming table: expected ticks (based on FRC @37.5MHz) an inference should take for a given DDR bandwidth.
table InferenceTimingByBandwidth {
  by_bw: [ulong]; // Must contain 5 entries.
}

// Table of inference timings for different VPU frequency values.
table InferenceTiming {
  by_freq: [InferenceTimingByBandwidth]; // Must contain 5 entries.
}

table PerformanceMetrics {
  freq_base: uint;          // Base of frequency values used in tables (in MHz).
  freq_step: uint;          // Step of frequency for each entry in tables (in MHz).
  bw_base: uint;            // Base of bandwidth values used in tables (in MB/s).
  bw_step: uint;            // Step of bandwidth values used in tables (in MB/s).
  scalability:Scalability;  // Scalability by frequency & bandwidth.
  timing:InferenceTiming;   // InferenceTiming by frequency & bandwidth.
}
