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;  Copyright(c) 2011-2016 Intel Corporation All rights reserved.
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;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%include "md5_job.asm"
%include "md5_mb_mgr_datastruct.asm"
%include "reg_sizes.asm"

%ifdef HAVE_AS_KNOWS_AVX512
extern md5_mb_x16x2_avx512

[bits 64]
default rel
section .text

%if 1
%ifidn __OUTPUT_FORMAT__, elf64
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; UN*X register definitions
%define arg1    rdi ; rcx
%define arg2    rsi ; rdx

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;

%else

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
; WINDOWS register definitions
%define arg1    rcx
%define arg2    rdx

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
%endif

; Common register definitions

%define state   arg1
%define len2    arg2

; idx must be a register not clobberred by md5_mb_x16_avx512
%define idx	rbp

%define unused_lanes    ymm7
%define lane		r9

%define lane_data	r10

%define job_rax		rax
%define tmp		rax

%define num_lanes_inuse r8

%endif ;; if 1

; STACK_SPACE needs to be an odd multiple of 8
_XMM_SAVE_SIZE  equ 10*16
_GPR_SAVE_SIZE  equ 8*8
_ALIGN_SIZE     equ 8

_XMM_SAVE       equ 0
_GPR_SAVE       equ _XMM_SAVE + _XMM_SAVE_SIZE
STACK_SPACE     equ _GPR_SAVE + _GPR_SAVE_SIZE + _ALIGN_SIZE

%define APPEND(a,b) a %+ b

;; Byte shift in MEM addr, read a extra byte [addr+16]
%macro MEM_VPSRLDDQ 2
%define %%addr	  %1
%define %%TMP_YMM %2
	vmovdqu	%%TMP_YMM, [%%addr + 1]
	vmovdqu [%%addr], %%TMP_YMM
	mov	[%%addr + 31], byte 0
%endmacro

;; Byte shift in MEM addr, read a extra byte [addr-1]
%macro MEM_VPSLLDDQ 2
%define %%addr	  %1
%define %%TMP_YMM %2
	vmovdqu	%%TMP_YMM, [%%addr-1]
	vmovdqu [%%addr], %%TMP_YMM
	mov	[%%addr], byte 0
%endmacro

align 64

; JOB* md5_mb_mgr_flush_avx512(MB_MGR_HMAC_OOO *state)
; arg 1 : rcx : state
mk_global md5_mb_mgr_flush_avx512, function
md5_mb_mgr_flush_avx512:
	endbranch
	sub	rsp, STACK_SPACE
	mov	[rsp + _GPR_SAVE + 8*0], rbx
	mov	[rsp + _GPR_SAVE + 8*3], rbp
	mov	[rsp + _GPR_SAVE + 8*4], r12
	mov	[rsp + _GPR_SAVE + 8*5], r13
	mov	[rsp + _GPR_SAVE + 8*6], r14
	mov	[rsp + _GPR_SAVE + 8*7], r15
%ifidn __OUTPUT_FORMAT__, win64
	mov	[rsp + _GPR_SAVE + 8*1], rsi
	mov	[rsp + _GPR_SAVE + 8*2], rdi
	vmovdqa  [rsp + _XMM_SAVE + 16*0], xmm6
	vmovdqa  [rsp + _XMM_SAVE + 16*1], xmm7
	vmovdqa  [rsp + _XMM_SAVE + 16*2], xmm8
	vmovdqa  [rsp + _XMM_SAVE + 16*3], xmm9
	vmovdqa  [rsp + _XMM_SAVE + 16*4], xmm10
	vmovdqa  [rsp + _XMM_SAVE + 16*5], xmm11
	vmovdqa  [rsp + _XMM_SAVE + 16*6], xmm12
	vmovdqa  [rsp + _XMM_SAVE + 16*7], xmm13
	vmovdqa  [rsp + _XMM_SAVE + 16*8], xmm14
	vmovdqa  [rsp + _XMM_SAVE + 16*9], xmm15
%endif

	mov	DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
	cmp	num_lanes_inuse, 0
	jz	return_null

	; find a lane with a non-null job
	xor	idx, idx
%assign I 1
%rep 31
	cmp	qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
	cmovne	idx, [APPEND(lane_,I)]
%assign I (I+1)
%endrep

	; copy idx to empty lanes
copy_lane_data:
	mov	tmp, [state + _args + _data_ptr + 8*idx]

%assign I 0
%rep 32
	cmp	qword [state + _ldata + I * _LANE_DATA_size + _job_in_lane], 0
	jne	APPEND(skip_,I)
	mov	[state + _args + _data_ptr + 8*I], tmp
	mov	dword [state + _lens + 4*I], 0xFFFFFFFF
APPEND(skip_,I):
%assign I (I+1)
%endrep

	; Find min length
	vmovdqu ymm0, [state + _lens + 0*32]
	vmovdqu ymm1, [state + _lens + 1*32]

	vpminud ymm2, ymm0, ymm1	; ymm2 has {D,C,B,A}
	vpalignr ymm3, ymm3, ymm2, 8    ; ymm3 has {x,x,D,C}
	vpminud ymm2, ymm2, ymm3	; ymm2 has {x,x,E,F}
	vpalignr ymm3, ymm3, ymm2, 4    ; ymm3 has {x,x,x,E}
	vpminud ymm2, ymm2, ymm3	; ymm2 has min value in low dword
	vperm2i128 ymm3, ymm2, ymm2, 1	; ymm3 has halves of ymm2 reversed
	vpminud ymm2, ymm2, ymm3	; ymm2 has min value in low dword
	; Find min length
	vmovdqu ymm5, [state + _lens + 2*32]
	vmovdqu ymm6, [state + _lens + 3*32]

	vpminud ymm4, ymm5, ymm6	; ymm4 has {D,C,B,A}
	vpalignr ymm3, ymm3, ymm4, 8    ; ymm3 has {x,x,D,C}
	vpminud ymm4, ymm4, ymm3	; ymm4 has {x,x,E,F}
	vpalignr ymm3, ymm3, ymm4, 4    ; ymm3 has {x,x,x,E}
	vpminud ymm4, ymm4, ymm3	; ymm4 has min value in low dword
	vperm2i128 ymm3, ymm4, ymm4, 1	; ymm3 has halves of ymm4 reversed
	vpminud ymm4, ymm4, ymm3	; ymm4 has min value in low dword

	vpminud ymm2, ymm2, ymm4	; ymm2 has min value in low dword
	vmovd	DWORD(idx), xmm2
	mov	len2, idx
	and	idx, 0x3F
	shr	len2, 6
	jz	len_is_0

	vpand	ymm2, ymm2, [rel clear_low_6bits]
	vpshufd ymm2, ymm2, 0

	vpsubd  ymm0, ymm0, ymm2
	vpsubd  ymm1, ymm1, ymm2
	vpsubd  ymm5, ymm5, ymm2
	vpsubd  ymm6, ymm6, ymm2

	vmovdqu [state + _lens + 0*32], ymm0
	vmovdqu [state + _lens + 1*32], ymm1
	vmovdqu [state + _lens + 2*32], ymm5
	vmovdqu [state + _lens + 3*32], ymm6

	; "state" and "args" are the same address, arg1
	; len is arg2
	call	md5_mb_x16x2_avx512
	; state and idx are intact

len_is_0:
	; process completed job "idx"
	imul	lane_data, idx, _LANE_DATA_size
	lea	lane_data, [state + _ldata + lane_data]

	mov	job_rax, [lane_data + _job_in_lane]
	mov	lane, [state + _unused_lanes]
	mov	qword [lane_data + _job_in_lane], 0
	mov	dword [job_rax + _status], STS_COMPLETED

	shl	lane, 8
	or	lane, idx
	MEM_VPSLLDDQ    (state + _unused_lanes), unused_lanes
	mov	[state + _unused_lanes], lane

	mov	DWORD(num_lanes_inuse), [state + _num_lanes_inuse]
	sub	num_lanes_inuse, 1
	mov	[state + _num_lanes_inuse], DWORD(num_lanes_inuse)

	mov	dword [state + _lens + 4*idx], 0xFFFFFFFF

	vmovd	xmm0, [state + _args_digest + 4*idx + 0*4*16*2]
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 1*4*16*2], 1
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 2*4*16*2], 2
	vpinsrd	xmm0, [state + _args_digest + 4*idx + 3*4*16*2], 3

	vmovdqa	[job_rax + _result_digest + 0*16], xmm0

return:

%ifidn __OUTPUT_FORMAT__, win64
	vmovdqa  xmm6, [rsp + _XMM_SAVE + 16*0]
	vmovdqa  xmm7, [rsp + _XMM_SAVE + 16*1]
	vmovdqa  xmm8, [rsp + _XMM_SAVE + 16*2]
	vmovdqa  xmm9, [rsp + _XMM_SAVE + 16*3]
	vmovdqa  xmm10, [rsp + _XMM_SAVE + 16*4]
	vmovdqa  xmm11, [rsp + _XMM_SAVE + 16*5]
	vmovdqa  xmm12, [rsp + _XMM_SAVE + 16*6]
	vmovdqa  xmm13, [rsp + _XMM_SAVE + 16*7]
	vmovdqa  xmm14, [rsp + _XMM_SAVE + 16*8]
	vmovdqa  xmm15, [rsp + _XMM_SAVE + 16*9]
	mov	rsi, [rsp + _GPR_SAVE + 8*1]
	mov	rdi, [rsp + _GPR_SAVE + 8*2]
%endif
	mov	rbx, [rsp + _GPR_SAVE + 8*0]
	mov	rbp, [rsp + _GPR_SAVE + 8*3]
	mov	r12, [rsp + _GPR_SAVE + 8*4]
	mov	r13, [rsp + _GPR_SAVE + 8*5]
	mov	r14, [rsp + _GPR_SAVE + 8*6]
	mov	r15, [rsp + _GPR_SAVE + 8*7]
	add	rsp, STACK_SPACE

	ret

return_null:
	xor	job_rax, job_rax
	jmp	return


section .data align=16

align 16
clear_low_6bits:
	dq 0x00000000FFFFFFC0, 0x0000000000000000
	dq 0x00000000FFFFFFC0, 0x0000000000000000
lane_1:     dq  1
lane_2:     dq  2
lane_3:     dq  3
lane_4:     dq  4
lane_5:     dq  5
lane_6:     dq  6
lane_7:     dq  7
lane_8:     dq  8
lane_9:     dq  9
lane_10:    dq  10
lane_11:    dq  11
lane_12:    dq  12
lane_13:    dq  13
lane_14:    dq  14
lane_15:    dq  15
lane_16:    dq  16
lane_17:    dq  17
lane_18:    dq  18
lane_19:    dq  19
lane_20:    dq  20
lane_21:    dq  21
lane_22:    dq  22
lane_23:    dq  23
lane_24:    dq  24
lane_25:    dq  25
lane_26:    dq  26
lane_27:    dq  27
lane_28:    dq  28
lane_29:    dq  29
lane_30:    dq  30
lane_31:    dq  31

%else
%ifidn __OUTPUT_FORMAT__, win64
global no_md5_mb_mgr_flush_avx512
no_md5_mb_mgr_flush_avx512:
%endif
%endif ; HAVE_AS_KNOWS_AVX512
