29#include "SystemRAMBank.h"
80 static event_clock_t
const C64_CPU6510_DATA_PORT_FALL_OFF_CYCLES = 350000;
81 static event_clock_t
const C64_CPU8500_DATA_PORT_FALL_OFF_CYCLES = 1500000;
86 event_clock_t dataSetClk;
101 uint8_t readBit(event_clock_t phi2time)
103 if (isFallingOff && (dataSetClk < phi2time))
111 void writeBit(event_clock_t phi2time, uint8_t value)
113 dataSetClk = phi2time + C64_CPU6510_DATA_PORT_FALL_OFF_CYCLES;
114 dataSet = value & (1 << Bit);
135 static bool const tape_sense =
false;
159 uint8_t procPortPins;
165 procPortPins = (procPortPins & ~dir) | (data & dir);
167 dataRead = (data | ~dir) & (procPortPins | 0x17);
169 pla.setCpuPort((data | ~dir) & 0x07);
171 if ((dir & 0x20) == 0)
175 if (tape_sense && (dir & 0x10) == 0)
200 uint8_t
peek(uint_least16_t address)
override
208 uint8_t retval = dataRead;
216 retval |= dataBit6.readBit(pla.getPhi2Time());
223 retval |= dataBit7.readBit(pla.getPhi2Time());
229 return ramBank.
peek(address);
233 void poke(uint_least16_t address, uint8_t value)
override
245 if ((dir & 0x40) && !(value & 0x40))
246 dataBit6.writeBit(pla.getPhi2Time(), data);
249 if ((dir & 0x80) && !(value & 0x80))
250 dataBit7.writeBit(pla.getPhi2Time(), data);
256 value = pla.getLastReadByte();
263 dataBit6.writeBit(pla.getPhi2Time(), value);
266 dataBit7.writeBit(pla.getPhi2Time(), value);
274 value = pla.getLastReadByte();
280 ramBank.
poke(address, value);
Definition: SystemRAMBank.h:39
uint8_t peek(uint_least16_t address) override
Definition: SystemRAMBank.h:72
void poke(uint_least16_t address, uint8_t value) override
Definition: SystemRAMBank.h:77
Definition: ZeroRAMBank.h:132
void poke(uint_least16_t address, uint8_t value) override
Definition: ZeroRAMBank.h:233
uint8_t peek(uint_least16_t address) override
Definition: ZeroRAMBank.h:200
Definition: ZeroRAMBank.h:56