# Raspberry Pi 5 Boot Configuration
# Direct kernel boot (no UEFI/GRUB chain — RPi5 firmware does not include UEFI).
# build-all-node-disks.sh post_process_efi places kernel_2712.img + initramfs.img
# on this EFI partition and appends `initramfs initramfs.img followkernel` here.
# RPi5 firmware then loads kernel directly with cmdline.txt.
#
# BOOT_ORDER is baked into pieeprom.upd at container-build time
# (Containerfile.rpi5 Step 4.5 → rpi-eeprom-config) — NVMe first, SD/USB
# fallback. EEPROM auto-update runs once on first boot.

[all]
# 64-bit ARM mode (required for aarch64 OKD)
arm_64bit=1

# UART for serial console — full chain on J14 debug header (ttyAMA10).
# RPi5 has TWO PL011s relevant: ttyAMA0 on GPIO 14/15 (RP1 chip) and ttyAMA10
# on the dedicated debug J14 JST-HS connector (BCM2712 chip). Cluster control
# plane (cp1/cp2) physically uses J14 for the console-server cable, so we
# keep bootloader, firmware, kernel and userspace all writing to J14.
#
# RPi firmware default: serial0 → ttyAMA10 (J14). Bootloader (BootROM /
# EEPROM stage / start.elf) and BL31 ATF always write to the debug UART
# regardless of cmdline / DT — that path is hard-wired. The kernel console
# follows the cmdline.txt `console=ttyAMA10,115200` directive set by
# build-all-node-disks.sh post_process_efi.
#
# uart_2ndstage=1: enable start*.elf / firmware diagnostic logging on UART
#   (default became 1 on Pi5 from 2025-01-06, but assert explicitly).
#
# enable_uart=0: assert explicitly that we do NOT want the EEPROM 2025-02-12+
#   "kernel console on GPIO 14/15" semantic. From that EEPROM onward
#   `enable_uart=1` *moves the kernel console from ttyAMA10 (J14) to
#   ttyAMA0 (GPIO 14/15)* — bootloader stays on J14, but Linux silently
#   redirects to GPIO. We ship pieeprom 2026-04-30, so enable_uart MUST
#   be 0 (or absent) to keep the kernel console on J14.
#   Confirmed by Phil Elwell (RPi staff) in
#   github.com/raspberrypi/rpi-eeprom/issues/673:
#     "You must have enable_uart=1 in config.txt. Try removing it."
#   davidemyers reply: "Commenting it out caused the console to be
#   initialized on ttyAMA10 with pieeprom-2025-02-12.bin as expected. It
#   also works to leave it uncommented and add enable_uart=0 at the bottom
#   of the file."
#
# Notably ABSENT (vs every "easy guide" online):
# - enable_rp1_uart would redirect bootloader UART to RP1 (GPIO 14/15) —
#   wrong direction for a J14 cable.
# - dtparam=uart0_console=on would remap serial0 → ttyAMA0 (RP1 GPIO 14/15)
#   and break our J14 console — explicitly NOT set.
uart_2ndstage=1
enable_uart=0

# Minimal GPU memory (headless server — no GUI workload, but HDMI console
# tty1 still works because that's framebuffer, not GPU compute).
gpu_mem=16

# Disable overscan for clean HDMI output to a directly-connected monitor.
disable_overscan=1

# Active cooling fan control (PWM-driven).
dtoverlay=pwm-fan

# Disable WiFi + Bluetooth radios — cluster nodes are wired-only.
# Frees ~50-100ms of boot time and avoids loading brcmfmac/hci_uart drivers.
# IMPORTANT: use plain `disable-wifi` / `disable-bt`, NOT the `-pi5` variants.
# raspberrypi/linux#6930: disable-wifi-pi5 also kills Bluetooth (shared RP1
# resources), and disable-bt-pi5 has issues. Plain overlays auto-resolve to
# the right architecture-specific variant via overlay_map.dts.
dtoverlay=disable-wifi
dtoverlay=disable-bt

# Disable HDMI audio — RPi5 has no analog audio output, so this just stops
# the kernel from registering the HDMI audio codec. HDMI VIDEO is unaffected.
dtparam=audio=off

# Disable boot splash (the small Pi-logo bitmap during early firmware boot).
# HDMI console output (tty1) starts as soon as kernel takes over, so we
# don't lose anything diagnostically.
disable_splash=1

# Skip the 1-second boot delay that early firmware uses to wait for slow SD
# cards. NVMe enumerates fast.
boot_delay=0

# Enable RP1 turbo clock — bumps max ARM frequency to 2.4 GHz (D-stepping
# silicon) or 1.8 GHz (C-stepping). Default firmware on newer EEPROMs has
# this on, but assert it explicitly.
arm_boost=1

# PCIe Gen 3 for NVMe. RPi5 is officially certified at Gen 2 (~5 GT/s ≈
# 500 MB/s) but works at Gen 3 (~10 GT/s ≈ 900 MB/s) with most NVMe SSDs +
# decent FPC cables. Worst case: PCIe bus errors → kernel falls back to
# Gen 2 automatically. Worth it for image-pull-heavy nodes.
dtparam=pciex1_gen=3

# D0 silicon support is automatic via firmware detection.
