Processor Counter Monitor
types.h
Go to the documentation of this file.
1 /*
2 Copyright (c) 2009-2018, Intel Corporation
3 All rights reserved.
4 
5 Redistribution and use in source and binary forms, with or without modification, are permitted provided that the following conditions are met:
6 
7  * Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.
8  * Redistributions in binary form must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution.
9  * Neither the name of Intel Corporation nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission.
10 
11 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
12 */
13 // written by Roman Dementiev
14 //
15 
16 #ifndef CPUCounters_TYPES_H
17 #define CPUCounters_TYPES_H
18 
19 
24 #undef PCM_DEBUG
25 
26 #include <iostream>
27 #include <istream>
28 #include <sstream>
29 #include <iomanip>
30 
31 typedef unsigned long long uint64;
32 typedef signed long long int64;
33 typedef unsigned int uint32;
34 typedef signed int int32;
35 
36 
37 /*
38  MSR addreses from
39  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
40  System Programming Guide, Part 2", Appendix A "PERFORMANCE-MONITORING EVENTS"
41 */
42 
43 #define INST_RETIRED_ANY_ADDR (0x309)
44 #define CPU_CLK_UNHALTED_THREAD_ADDR (0x30A)
45 #define CPU_CLK_UNHALTED_REF_ADDR (0x30B)
46 #define IA32_CR_PERF_GLOBAL_CTRL (0x38F)
47 #define IA32_CR_FIXED_CTR_CTRL (0x38D)
48 #define IA32_PERFEVTSEL0_ADDR (0x186)
49 #define IA32_PERFEVTSEL1_ADDR (IA32_PERFEVTSEL0_ADDR + 1)
50 #define IA32_PERFEVTSEL2_ADDR (IA32_PERFEVTSEL0_ADDR + 2)
51 #define IA32_PERFEVTSEL3_ADDR (IA32_PERFEVTSEL0_ADDR + 3)
52 
53 #define PERF_MAX_FIXED_COUNTERS (3)
54 #define PERF_MAX_CUSTOM_COUNTERS (8)
55 #define PERF_MAX_COUNTERS (PERF_MAX_FIXED_COUNTERS + PERF_MAX_CUSTOM_COUNTERS)
56 
57 #define IA32_DEBUGCTL (0x1D9)
58 
59 #define IA32_PMC0 (0xC1)
60 #define IA32_PMC1 (0xC1 + 1)
61 #define IA32_PMC2 (0xC1 + 2)
62 #define IA32_PMC3 (0xC1 + 3)
63 
64 #define MSR_OFFCORE_RSP0 (0x1A6)
65 #define MSR_OFFCORE_RSP1 (0x1A7)
66 
67 /* From Table B-5. of the above mentioned document */
68 #define PLATFORM_INFO_ADDR (0xCE)
69 
70 #define IA32_TIME_STAMP_COUNTER (0x10)
71 
72 // Event IDs
73 
74 // Nehalem/Westmere on-core events
75 #define MEM_LOAD_RETIRED_L3_MISS_EVTNR (0xCB)
76 #define MEM_LOAD_RETIRED_L3_MISS_UMASK (0x10)
77 
78 #define MEM_LOAD_RETIRED_L3_UNSHAREDHIT_EVTNR (0xCB)
79 #define MEM_LOAD_RETIRED_L3_UNSHAREDHIT_UMASK (0x04)
80 
81 #define MEM_LOAD_RETIRED_L2_HITM_EVTNR (0xCB)
82 #define MEM_LOAD_RETIRED_L2_HITM_UMASK (0x08)
83 
84 #define MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
85 #define MEM_LOAD_RETIRED_L2_HIT_UMASK (0x02)
86 
87 // Sandy Bridge on-core events
88 
89 #define MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_EVTNR (0xD4)
90 #define MEM_LOAD_UOPS_MISC_RETIRED_LLC_MISS_UMASK (0x02)
91 
92 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_EVTNR (0xD2)
93 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_NONE_UMASK (0x08)
94 
95 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_EVTNR (0xD2)
96 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_HITM_UMASK (0x04)
97 
98 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_EVTNR (0xD2)
99 #define MEM_LOAD_UOPS_LLC_HIT_RETIRED_XSNP_UMASK (0x07)
100 
101 #define MEM_LOAD_UOPS_RETIRED_L2_HIT_EVTNR (0xD1)
102 #define MEM_LOAD_UOPS_RETIRED_L2_HIT_UMASK (0x02)
103 
104 // Skylake on-core events
105 
106 #define SKL_MEM_LOAD_RETIRED_L3_MISS_EVTNR (0xD1)
107 #define SKL_MEM_LOAD_RETIRED_L3_MISS_UMASK (0x20)
108 
109 #define SKL_MEM_LOAD_RETIRED_L3_HIT_EVTNR (0xD1)
110 #define SKL_MEM_LOAD_RETIRED_L3_HIT_UMASK (0x04)
111 
112 #define SKL_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xD1)
113 #define SKL_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x10)
114 
115 #define SKL_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xD1)
116 #define SKL_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x02)
117 
118 // architectural on-core events
119 
120 #define ARCH_LLC_REFERENCE_EVTNR (0x2E)
121 #define ARCH_LLC_REFERENCE_UMASK (0x4F)
122 
123 #define ARCH_LLC_MISS_EVTNR (0x2E)
124 #define ARCH_LLC_MISS_UMASK (0x41)
125 
126 // Atom on-core events
127 
128 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
129 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
130 
131 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
132 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
133 
134 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
135 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
136 
137 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
138 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
139 
140 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_EVTNR (0xCB)
141 #define ATOM_MEM_LOAD_RETIRED_L2_HIT_UMASK (0x01)
142 
143 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_EVTNR (0xCB)
144 #define ATOM_MEM_LOAD_RETIRED_L2_MISS_UMASK (0x02)
145 
146 // Offcore response events
147 #define OFFCORE_RESPONSE_0_EVTNR (0xB7)
148 #define OFFCORE_RESPONSE_1_EVTNR (0xBB)
149 #define OFFCORE_RESPONSE_0_UMASK (1)
150 #define OFFCORE_RESPONSE_1_UMASK (1)
151 /*
152  For Nehalem(-EP) processors from Intel(r) 64 and IA-32 Architectures Software Developer's Manual
153 */
154 
155 // Uncore msrs
156 
157 #define MSR_UNCORE_PERF_GLOBAL_CTRL_ADDR (0x391)
158 
159 #define MSR_UNCORE_PERFEVTSEL0_ADDR (0x3C0)
160 #define MSR_UNCORE_PERFEVTSEL1_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 1)
161 #define MSR_UNCORE_PERFEVTSEL2_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 2)
162 #define MSR_UNCORE_PERFEVTSEL3_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 3)
163 #define MSR_UNCORE_PERFEVTSEL4_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 4)
164 #define MSR_UNCORE_PERFEVTSEL5_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 5)
165 #define MSR_UNCORE_PERFEVTSEL6_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 6)
166 #define MSR_UNCORE_PERFEVTSEL7_ADDR (MSR_UNCORE_PERFEVTSEL0_ADDR + 7)
167 
168 
169 #define MSR_UNCORE_PMC0 (0x3B0)
170 #define MSR_UNCORE_PMC1 (MSR_UNCORE_PMC0 + 1)
171 #define MSR_UNCORE_PMC2 (MSR_UNCORE_PMC0 + 2)
172 #define MSR_UNCORE_PMC3 (MSR_UNCORE_PMC0 + 3)
173 #define MSR_UNCORE_PMC4 (MSR_UNCORE_PMC0 + 4)
174 #define MSR_UNCORE_PMC5 (MSR_UNCORE_PMC0 + 5)
175 #define MSR_UNCORE_PMC6 (MSR_UNCORE_PMC0 + 6)
176 #define MSR_UNCORE_PMC7 (MSR_UNCORE_PMC0 + 7)
177 
178 // Uncore event IDs
179 
180 #define UNC_QMC_WRITES_FULL_ANY_EVTNR (0x2F)
181 #define UNC_QMC_WRITES_FULL_ANY_UMASK (0x07)
182 
183 #define UNC_QMC_NORMAL_READS_ANY_EVTNR (0x2C)
184 #define UNC_QMC_NORMAL_READS_ANY_UMASK (0x07)
185 
186 #define UNC_QHL_REQUESTS_EVTNR (0x20)
187 
188 #define UNC_QHL_REQUESTS_IOH_READS_UMASK (0x01)
189 #define UNC_QHL_REQUESTS_IOH_WRITES_UMASK (0x02)
190 #define UNC_QHL_REQUESTS_REMOTE_READS_UMASK (0x04)
191 #define UNC_QHL_REQUESTS_REMOTE_WRITES_UMASK (0x08)
192 #define UNC_QHL_REQUESTS_LOCAL_READS_UMASK (0x10)
193 #define UNC_QHL_REQUESTS_LOCAL_WRITES_UMASK (0x20)
194 
195 /*
196  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
197 */
198 
199 // Beckton uncore event IDs
200 
201 #define U_MSR_PMON_GLOBAL_CTL (0x0C00)
202 
203 #define MB0_MSR_PERF_GLOBAL_CTL (0x0CA0)
204 #define MB0_MSR_PMU_CNT_0 (0x0CB1)
205 #define MB0_MSR_PMU_CNT_CTL_0 (0x0CB0)
206 #define MB0_MSR_PMU_CNT_1 (0x0CB3)
207 #define MB0_MSR_PMU_CNT_CTL_1 (0x0CB2)
208 #define MB0_MSR_PMU_ZDP_CTL_FVC (0x0CAB)
209 
210 
211 #define MB1_MSR_PERF_GLOBAL_CTL (0x0CE0)
212 #define MB1_MSR_PMU_CNT_0 (0x0CF1)
213 #define MB1_MSR_PMU_CNT_CTL_0 (0x0CF0)
214 #define MB1_MSR_PMU_CNT_1 (0x0CF3)
215 #define MB1_MSR_PMU_CNT_CTL_1 (0x0CF2)
216 #define MB1_MSR_PMU_ZDP_CTL_FVC (0x0CEB)
217 
218 #define BB0_MSR_PERF_GLOBAL_CTL (0x0C20)
219 #define BB0_MSR_PERF_CNT_1 (0x0C33)
220 #define BB0_MSR_PERF_CNT_CTL_1 (0x0C32)
221 
222 #define BB1_MSR_PERF_GLOBAL_CTL (0x0C60)
223 #define BB1_MSR_PERF_CNT_1 (0x0C73)
224 #define BB1_MSR_PERF_CNT_CTL_1 (0x0C72)
225 
226 #define R_MSR_PMON_CTL0 (0x0E10)
227 #define R_MSR_PMON_CTR0 (0x0E11)
228 #define R_MSR_PMON_CTL1 (0x0E12)
229 #define R_MSR_PMON_CTR1 (0x0E13)
230 #define R_MSR_PMON_CTL2 (0x0E14)
231 #define R_MSR_PMON_CTR2 (0x0E15)
232 #define R_MSR_PMON_CTL3 (0x0E16)
233 #define R_MSR_PMON_CTR3 (0x0E17)
234 #define R_MSR_PMON_CTL4 (0x0E18)
235 #define R_MSR_PMON_CTR4 (0x0E19)
236 #define R_MSR_PMON_CTL5 (0x0E1A)
237 #define R_MSR_PMON_CTR5 (0x0E1B)
238 #define R_MSR_PMON_CTL6 (0x0E1C)
239 #define R_MSR_PMON_CTR6 (0x0E1D)
240 #define R_MSR_PMON_CTL7 (0x0E1E)
241 #define R_MSR_PMON_CTR7 (0x0E1F)
242 #define R_MSR_PMON_CTL8 (0x0E30)
243 #define R_MSR_PMON_CTR8 (0x0E31)
244 #define R_MSR_PMON_CTL9 (0x0E32)
245 #define R_MSR_PMON_CTR9 (0x0E33)
246 #define R_MSR_PMON_CTL10 (0x0E34)
247 #define R_MSR_PMON_CTR10 (0x0E35)
248 #define R_MSR_PMON_CTL11 (0x0E36)
249 #define R_MSR_PMON_CTR11 (0x0E37)
250 #define R_MSR_PMON_CTL12 (0x0E38)
251 #define R_MSR_PMON_CTR12 (0x0E39)
252 #define R_MSR_PMON_CTL13 (0x0E3A)
253 #define R_MSR_PMON_CTR13 (0x0E3B)
254 #define R_MSR_PMON_CTL14 (0x0E3C)
255 #define R_MSR_PMON_CTR14 (0x0E3D)
256 #define R_MSR_PMON_CTL15 (0x0E3E)
257 #define R_MSR_PMON_CTR15 (0x0E3F)
258 
259 #define R_MSR_PORT0_IPERF_CFG0 (0x0E04)
260 #define R_MSR_PORT1_IPERF_CFG0 (0x0E05)
261 #define R_MSR_PORT2_IPERF_CFG0 (0x0E06)
262 #define R_MSR_PORT3_IPERF_CFG0 (0x0E07)
263 #define R_MSR_PORT4_IPERF_CFG0 (0x0E08)
264 #define R_MSR_PORT5_IPERF_CFG0 (0x0E09)
265 #define R_MSR_PORT6_IPERF_CFG0 (0x0E0A)
266 #define R_MSR_PORT7_IPERF_CFG0 (0x0E0B)
267 
268 #define R_MSR_PORT0_IPERF_CFG1 (0x0E24)
269 #define R_MSR_PORT1_IPERF_CFG1 (0x0E25)
270 #define R_MSR_PORT2_IPERF_CFG1 (0x0E26)
271 #define R_MSR_PORT3_IPERF_CFG1 (0x0E27)
272 #define R_MSR_PORT4_IPERF_CFG1 (0x0E28)
273 #define R_MSR_PORT5_IPERF_CFG1 (0x0E29)
274 #define R_MSR_PORT6_IPERF_CFG1 (0x0E2A)
275 #define R_MSR_PORT7_IPERF_CFG1 (0x0E2B)
276 
277 #define R_MSR_PMON_GLOBAL_CTL_7_0 (0x0E00)
278 #define R_MSR_PMON_GLOBAL_CTL_15_8 (0x0E20)
279 
280 #define W_MSR_PMON_GLOBAL_CTL (0xC80)
281 #define W_MSR_PMON_FIXED_CTR_CTL (0x395)
282 #define W_MSR_PMON_FIXED_CTR (0x394)
283 
284 /*
285  * Platform QoS MSRs
286  */
287 
288 #define IA32_PQR_ASSOC (0xc8f)
289 #define IA32_QM_EVTSEL (0xc8d)
290 #define IA32_QM_CTR (0xc8e)
291 
292 #define PCM_INVALID_QOS_MONITORING_DATA ((std::numeric_limits<uint64>::max)())
293 
294 /* \brief Event Select Register format
295 
296  According to
297  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
298  System Programming Guide, Part 2", Figure 30-6. Layout of IA32_PERFEVTSELx
299  MSRs Supporting Architectural Performance Monitoring Version 3
300 */
302 {
303  union
304  {
305  struct
306  {
307  uint64 event_select : 8;
308  uint64 umask : 8;
309  uint64 usr : 1;
310  uint64 os : 1;
311  uint64 edge : 1;
312  uint64 pin_control : 1;
313  uint64 apic_int : 1;
314  uint64 any_thread : 1;
315  uint64 enable : 1;
316  uint64 invert : 1;
317  uint64 cmask : 8;
318  uint64 in_tx : 1;
319  uint64 in_txcp : 1;
320  uint64 reservedX : 30;
321  } fields;
322  uint64 value;
323  };
324 
325  EventSelectRegister() : value(0) {}
326 };
327 
328 
329 /* \brief Fixed Event Control Register format
330 
331  According to
332  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
333  System Programming Guide, Part 2", Figure 30-7. Layout of
334  IA32_FIXED_CTR_CTRL MSR Supporting Architectural Performance Monitoring Version 3
335 */
337 {
338  union
339  {
340  struct
341  {
342  // CTR0
343  uint64 os0 : 1;
344  uint64 usr0 : 1;
345  uint64 any_thread0 : 1;
346  uint64 enable_pmi0 : 1;
347  // CTR1
348  uint64 os1 : 1;
349  uint64 usr1 : 1;
350  uint64 any_thread1 : 1;
351  uint64 enable_pmi1 : 1;
352  // CTR2
353  uint64 os2 : 1;
354  uint64 usr2 : 1;
355  uint64 any_thread2 : 1;
356  uint64 enable_pmi2 : 1;
357 
358  uint64 reserved1 : 52;
359  } fields;
360  uint64 value;
361  };
362 };
363 
364 inline std::ostream & operator << (std::ostream & o, const FixedEventControlRegister & reg)
365 {
366  o << "os0\t\t" << reg.fields.os0 << std::endl;
367  o << "usr0\t\t" << reg.fields.usr0 << std::endl;
368  o << "any_thread0\t" << reg.fields.any_thread0 << std::endl;
369  o << "enable_pmi0\t" << reg.fields.enable_pmi0 << std::endl;
370 
371  o << "os1\t\t" << reg.fields.os1 << std::endl;
372  o << "usr1\t\t" << reg.fields.usr1 << std::endl;
373  o << "any_thread1\t" << reg.fields.any_thread1 << std::endl;
374  o << "enable_pmi10\t" << reg.fields.enable_pmi1 << std::endl;
375 
376  o << "os2\t\t" << reg.fields.os2 << std::endl;
377  o << "usr2\t\t" << reg.fields.usr2 << std::endl;
378  o << "any_thread2\t" << reg.fields.any_thread2 << std::endl;
379  o << "enable_pmi2\t" << reg.fields.enable_pmi2 << std::endl;
380 
381  o << "reserved1\t" << reg.fields.reserved1 << std::endl;
382  return o;
383 }
384 
385 // UNCORE COUNTER CONTROL
386 
387 /* \brief Uncore Event Select Register Register format
388 
389  According to
390  "Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B:
391  System Programming Guide, Part 2", Figure 30-20. Layout of MSR_UNCORE_PERFEVTSELx MSRs
392 */
394 {
395  union
396  {
397  struct
398  {
399  uint64 event_select : 8;
400  uint64 umask : 8;
401  uint64 reserved1 : 1;
402  uint64 occ_ctr_rst : 1;
403  uint64 edge : 1;
404  uint64 reserved2 : 1;
405  uint64 enable_pmi : 1;
406  uint64 reserved3 : 1;
407  uint64 enable : 1;
408  uint64 invert : 1;
409  uint64 cmask : 8;
410  uint64 reservedx : 32;
411  } fields;
412  uint64 value;
413  };
414 };
415 
416 /* \brief Beckton Uncore PMU ZDP FVC Control Register format
417 
418  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
419  Table 2-80. M_MSR_PMU_ZDP_CTL_FVC Register - Field Definitions
420 */
422 {
423  union
424  {
425  struct
426  {
427  uint64 fvid : 5;
428  uint64 bcmd : 3;
429  uint64 resp : 3;
430  uint64 evnt0 : 3;
431  uint64 evnt1 : 3;
432  uint64 evnt2 : 3;
433  uint64 evnt3 : 3;
434  uint64 pbox_init_err : 1;
435  } fields; // nehalem-ex version
436  struct
437  {
438  uint64 fvid : 6;
439  uint64 bcmd : 3;
440  uint64 resp : 3;
441  uint64 evnt0 : 3;
442  uint64 evnt1 : 3;
443  uint64 evnt2 : 3;
444  uint64 evnt3 : 3;
445  uint64 pbox_init_err : 1;
446  } fields_wsm; // westmere-ex version
447  uint64 value;
448  };
449 };
450 
451 /* \brief Beckton Uncore PMU Counter Control Register format
452 
453  From "Intel(r) Xeon(r) Processor 7500 Series Uncore Programming Guide"
454  Table 2-67. M_MSR_PMU_CNT_CTL{5-0} Register - Field Definitions
455 */
457 {
458  union
459  {
460  struct
461  {
462  uint64 en : 1;
463  uint64 pmi_en : 1;
464  uint64 count_mode : 2;
465  uint64 storage_mode : 2;
466  uint64 wrap_mode : 1;
467  uint64 flag_mode : 1;
468  uint64 rsv1 : 1;
469  uint64 inc_sel : 5;
470  uint64 rsv2 : 5;
471  uint64 set_flag_sel : 3;
472  } fields;
473  uint64 value;
474  };
475 };
476 
477 #define MSR_SMI_COUNT (0x34)
478 
479 /* \brief Sandy Bridge energy counters
480 */
481 
482 #define MSR_PKG_ENERGY_STATUS (0x611)
483 #define MSR_RAPL_POWER_UNIT (0x606)
484 #define MSR_PKG_POWER_INFO (0x614)
485 
486 #define PCM_INTEL_PCI_VENDOR_ID (0x8086)
487 #define PCM_PCI_VENDOR_ID_OFFSET (0)
488 
489 // server PCICFG uncore counters
490 
491 #define JKTIVT_MC0_CH0_REGISTER_DEV_ADDR (16)
492 #define JKTIVT_MC0_CH1_REGISTER_DEV_ADDR (16)
493 #define JKTIVT_MC0_CH2_REGISTER_DEV_ADDR (16)
494 #define JKTIVT_MC0_CH3_REGISTER_DEV_ADDR (16)
495 #define JKTIVT_MC0_CH0_REGISTER_FUNC_ADDR (4)
496 #define JKTIVT_MC0_CH1_REGISTER_FUNC_ADDR (5)
497 #define JKTIVT_MC0_CH2_REGISTER_FUNC_ADDR (0)
498 #define JKTIVT_MC0_CH3_REGISTER_FUNC_ADDR (1)
499 
500 #define JKTIVT_MC1_CH0_REGISTER_DEV_ADDR (30)
501 #define JKTIVT_MC1_CH1_REGISTER_DEV_ADDR (30)
502 #define JKTIVT_MC1_CH2_REGISTER_DEV_ADDR (30)
503 #define JKTIVT_MC1_CH3_REGISTER_DEV_ADDR (30)
504 #define JKTIVT_MC1_CH0_REGISTER_FUNC_ADDR (4)
505 #define JKTIVT_MC1_CH1_REGISTER_FUNC_ADDR (5)
506 #define JKTIVT_MC1_CH2_REGISTER_FUNC_ADDR (0)
507 #define JKTIVT_MC1_CH3_REGISTER_FUNC_ADDR (1)
508 
509 #define HSX_MC0_CH0_REGISTER_DEV_ADDR (20)
510 #define HSX_MC0_CH1_REGISTER_DEV_ADDR (20)
511 #define HSX_MC0_CH2_REGISTER_DEV_ADDR (21)
512 #define HSX_MC0_CH3_REGISTER_DEV_ADDR (21)
513 #define HSX_MC0_CH0_REGISTER_FUNC_ADDR (0)
514 #define HSX_MC0_CH1_REGISTER_FUNC_ADDR (1)
515 #define HSX_MC0_CH2_REGISTER_FUNC_ADDR (0)
516 #define HSX_MC0_CH3_REGISTER_FUNC_ADDR (1)
517 
518 #define HSX_MC1_CH0_REGISTER_DEV_ADDR (23)
519 #define HSX_MC1_CH1_REGISTER_DEV_ADDR (23)
520 #define HSX_MC1_CH2_REGISTER_DEV_ADDR (24)
521 #define HSX_MC1_CH3_REGISTER_DEV_ADDR (24)
522 #define HSX_MC1_CH0_REGISTER_FUNC_ADDR (0)
523 #define HSX_MC1_CH1_REGISTER_FUNC_ADDR (1)
524 #define HSX_MC1_CH2_REGISTER_FUNC_ADDR (0)
525 #define HSX_MC1_CH3_REGISTER_FUNC_ADDR (1)
526 
527 #define KNL_MC0_CH0_REGISTER_DEV_ADDR (8)
528 #define KNL_MC0_CH1_REGISTER_DEV_ADDR (8)
529 #define KNL_MC0_CH2_REGISTER_DEV_ADDR (8)
530 #define KNL_MC0_CH0_REGISTER_FUNC_ADDR (2)
531 #define KNL_MC0_CH1_REGISTER_FUNC_ADDR (3)
532 #define KNL_MC0_CH2_REGISTER_FUNC_ADDR (4)
533 
534 #define SKX_MC0_CH0_REGISTER_DEV_ADDR (10)
535 #define SKX_MC0_CH1_REGISTER_DEV_ADDR (10)
536 #define SKX_MC0_CH2_REGISTER_DEV_ADDR (11)
537 #define SKX_MC0_CH3_REGISTER_DEV_ADDR (-1) //Does not exist
538 #define SKX_MC0_CH0_REGISTER_FUNC_ADDR (2)
539 #define SKX_MC0_CH1_REGISTER_FUNC_ADDR (6)
540 #define SKX_MC0_CH2_REGISTER_FUNC_ADDR (2)
541 #define SKX_MC0_CH3_REGISTER_FUNC_ADDR (-1) //Does not exist
542 
543 #define SKX_MC1_CH0_REGISTER_DEV_ADDR (12)
544 #define SKX_MC1_CH1_REGISTER_DEV_ADDR (12)
545 #define SKX_MC1_CH2_REGISTER_DEV_ADDR (13)
546 #define SKX_MC1_CH3_REGISTER_DEV_ADDR (-1) //Does not exist
547 #define SKX_MC1_CH0_REGISTER_FUNC_ADDR (2)
548 #define SKX_MC1_CH1_REGISTER_FUNC_ADDR (6)
549 #define SKX_MC1_CH2_REGISTER_FUNC_ADDR (2)
550 #define SKX_MC1_CH3_REGISTER_FUNC_ADDR (-1) //Does not exist
551 
552 
553 #define KNL_MC1_CH0_REGISTER_DEV_ADDR (9)
554 #define KNL_MC1_CH1_REGISTER_DEV_ADDR (9)
555 #define KNL_MC1_CH2_REGISTER_DEV_ADDR (9)
556 #define KNL_MC1_CH0_REGISTER_FUNC_ADDR (2)
557 #define KNL_MC1_CH1_REGISTER_FUNC_ADDR (3)
558 #define KNL_MC1_CH2_REGISTER_FUNC_ADDR (4)
559 
560 #define KNL_EDC0_ECLK_REGISTER_DEV_ADDR (24)
561 #define KNL_EDC0_ECLK_REGISTER_FUNC_ADDR (2)
562 #define KNL_EDC1_ECLK_REGISTER_DEV_ADDR (25)
563 #define KNL_EDC1_ECLK_REGISTER_FUNC_ADDR (2)
564 #define KNL_EDC2_ECLK_REGISTER_DEV_ADDR (26)
565 #define KNL_EDC2_ECLK_REGISTER_FUNC_ADDR (2)
566 #define KNL_EDC3_ECLK_REGISTER_DEV_ADDR (27)
567 #define KNL_EDC3_ECLK_REGISTER_FUNC_ADDR (2)
568 #define KNL_EDC4_ECLK_REGISTER_DEV_ADDR (28)
569 #define KNL_EDC4_ECLK_REGISTER_FUNC_ADDR (2)
570 #define KNL_EDC5_ECLK_REGISTER_DEV_ADDR (29)
571 #define KNL_EDC5_ECLK_REGISTER_FUNC_ADDR (2)
572 #define KNL_EDC6_ECLK_REGISTER_DEV_ADDR (30)
573 #define KNL_EDC6_ECLK_REGISTER_FUNC_ADDR (2)
574 #define KNL_EDC7_ECLK_REGISTER_DEV_ADDR (31)
575 #define KNL_EDC7_ECLK_REGISTER_FUNC_ADDR (2)
576 
581 #define XPF_MC_CH_PCI_PMON_BOX_CTL_ADDR (0x0F4)
582 #define KNX_MC_CH_PCI_PMON_BOX_CTL_ADDR (0xB30)
583 #define KNX_EDC_CH_PCI_PMON_BOX_CTL_ADDR (0xA30)
584 
586 #define XPF_MC_CH_PCI_PMON_FIXED_CTL_ADDR (0x0F0)
587 #define XPF_MC_CH_PCI_PMON_CTL3_ADDR (0x0E4)
588 #define XPF_MC_CH_PCI_PMON_CTL2_ADDR (0x0E0)
589 #define XPF_MC_CH_PCI_PMON_CTL1_ADDR (0x0DC)
590 #define XPF_MC_CH_PCI_PMON_CTL0_ADDR (0x0D8)
591 
593 #define KNX_MC_CH_PCI_PMON_FIXED_CTL_ADDR (0xB44)
594 #define KNX_MC_CH_PCI_PMON_CTL3_ADDR (0xB2C)
595 #define KNX_MC_CH_PCI_PMON_CTL2_ADDR (0xB28)
596 #define KNX_MC_CH_PCI_PMON_CTL1_ADDR (0xB24)
597 #define KNX_MC_CH_PCI_PMON_CTL0_ADDR (0xB20)
598 
600 #define KNX_EDC_CH_PCI_PMON_FIXED_CTL_ADDR (0xA44)
601 #define KNX_EDC_CH_PCI_PMON_CTL3_ADDR (0xA2C)
602 #define KNX_EDC_CH_PCI_PMON_CTL2_ADDR (0xA28)
603 #define KNX_EDC_CH_PCI_PMON_CTL1_ADDR (0xA24)
604 #define KNX_EDC_CH_PCI_PMON_CTL0_ADDR (0xA20)
605 #define KNX_EDC_ECLK_PMON_UNIT_CTL_REG (0xA30)
606 
608 #define XPF_MC_CH_PCI_PMON_FIXED_CTR_ADDR (0x0D0)
609 #define XPF_MC_CH_PCI_PMON_CTR3_ADDR (0x0B8)
610 #define XPF_MC_CH_PCI_PMON_CTR2_ADDR (0x0B0)
611 #define XPF_MC_CH_PCI_PMON_CTR1_ADDR (0x0A8)
612 #define XPF_MC_CH_PCI_PMON_CTR0_ADDR (0x0A0)
613 
615 #define KNX_MC_CH_PCI_PMON_FIXED_CTR_ADDR (0xB3C)
616 #define KNX_MC_CH_PCI_PMON_CTR3_ADDR (0xB18)
617 #define KNX_MC_CH_PCI_PMON_CTR2_ADDR (0xB10)
618 #define KNX_MC_CH_PCI_PMON_CTR1_ADDR (0xB08)
619 #define KNX_MC_CH_PCI_PMON_CTR0_ADDR (0xB00)
620 
622 #define KNX_EDC_CH_PCI_PMON_FIXED_CTR_ADDR (0xA3C)
623 #define KNX_EDC_CH_PCI_PMON_CTR3_ADDR (0xA18)
624 #define KNX_EDC_CH_PCI_PMON_CTR2_ADDR (0xA10)
625 #define KNX_EDC_CH_PCI_PMON_CTR1_ADDR (0xA08)
626 #define KNX_EDC_CH_PCI_PMON_CTR0_ADDR (0xA00)
627 
628 #define JKTIVT_QPI_PORT0_REGISTER_DEV_ADDR (8)
629 #define JKTIVT_QPI_PORT0_REGISTER_FUNC_ADDR (2)
630 #define JKTIVT_QPI_PORT1_REGISTER_DEV_ADDR (9)
631 #define JKTIVT_QPI_PORT1_REGISTER_FUNC_ADDR (2)
632 #define JKTIVT_QPI_PORT2_REGISTER_DEV_ADDR (24)
633 #define JKTIVT_QPI_PORT2_REGISTER_FUNC_ADDR (2)
634 
635 #define HSX_QPI_PORT0_REGISTER_DEV_ADDR (8)
636 #define HSX_QPI_PORT0_REGISTER_FUNC_ADDR (2)
637 #define HSX_QPI_PORT1_REGISTER_DEV_ADDR (9)
638 #define HSX_QPI_PORT1_REGISTER_FUNC_ADDR (2)
639 #define HSX_QPI_PORT2_REGISTER_DEV_ADDR (10)
640 #define HSX_QPI_PORT2_REGISTER_FUNC_ADDR (2)
641 
642 #define SKX_QPI_PORT0_REGISTER_DEV_ADDR (14)
643 #define SKX_QPI_PORT0_REGISTER_FUNC_ADDR (0)
644 #define SKX_QPI_PORT1_REGISTER_DEV_ADDR (15)
645 #define SKX_QPI_PORT1_REGISTER_FUNC_ADDR (0)
646 #define SKX_QPI_PORT2_REGISTER_DEV_ADDR (16)
647 #define SKX_QPI_PORT2_REGISTER_FUNC_ADDR (0)
648 
649 #define QPI_PORT0_MISC_REGISTER_FUNC_ADDR (0)
650 #define QPI_PORT1_MISC_REGISTER_FUNC_ADDR (0)
651 #define QPI_PORT2_MISC_REGISTER_FUNC_ADDR (0)
652 
653 #define SKX_M2M_0_REGISTER_DEV_ADDR (8)
654 #define SKX_M2M_0_REGISTER_FUNC_ADDR (0)
655 #define SKX_M2M_1_REGISTER_DEV_ADDR (9)
656 #define SKX_M2M_1_REGISTER_FUNC_ADDR (0)
657 
658 #define M2M_PCI_PMON_BOX_CTL_ADDR (0x258)
659 
660 #define M2M_PCI_PMON_CTL0_ADDR (0x228)
661 #define M2M_PCI_PMON_CTL1_ADDR (0x230)
662 #define M2M_PCI_PMON_CTL2_ADDR (0x238)
663 #define M2M_PCI_PMON_CTL3_ADDR (0x240)
664 
665 #define M2M_PCI_PMON_CTR0_ADDR (0x200)
666 #define M2M_PCI_PMON_CTR1_ADDR (0x208)
667 #define M2M_PCI_PMON_CTR2_ADDR (0x210)
668 #define M2M_PCI_PMON_CTR3_ADDR (0x218)
669 
670 #define PCM_INVALID_DEV_ADDR (~(uint32)0UL)
671 #define PCM_INVALID_FUNC_ADDR (~(uint32)0UL)
672 
673 #define Q_P_PCI_PMON_BOX_CTL_ADDR (0x0F4)
674 
675 #define Q_P_PCI_PMON_CTL3_ADDR (0x0E4)
676 #define Q_P_PCI_PMON_CTL2_ADDR (0x0E0)
677 #define Q_P_PCI_PMON_CTL1_ADDR (0x0DC)
678 #define Q_P_PCI_PMON_CTL0_ADDR (0x0D8)
679 
680 #define Q_P_PCI_PMON_CTR3_ADDR (0x0B8)
681 #define Q_P_PCI_PMON_CTR2_ADDR (0x0B0)
682 #define Q_P_PCI_PMON_CTR1_ADDR (0x0A8)
683 #define Q_P_PCI_PMON_CTR0_ADDR (0x0A0)
684 
685 #define QPI_RATE_STATUS_ADDR (0x0D4)
686 
687 #define U_L_PCI_PMON_BOX_CTL_ADDR (0x378)
688 
689 #define U_L_PCI_PMON_CTL3_ADDR (0x368)
690 #define U_L_PCI_PMON_CTL2_ADDR (0x360)
691 #define U_L_PCI_PMON_CTL1_ADDR (0x358)
692 #define U_L_PCI_PMON_CTL0_ADDR (0x350)
693 
694 #define U_L_PCI_PMON_CTR3_ADDR (0x330)
695 #define U_L_PCI_PMON_CTR2_ADDR (0x328)
696 #define U_L_PCI_PMON_CTR1_ADDR (0x320)
697 #define U_L_PCI_PMON_CTR0_ADDR (0x318)
698 
699 #define UCLK_FIXED_CTR_ADDR (0x704)
700 #define UCLK_FIXED_CTL_ADDR (0x703)
701 #define UBOX_MSR_PMON_CTL0_ADDR (0x705)
702 #define UBOX_MSR_PMON_CTL1_ADDR (0x706)
703 #define UBOX_MSR_PMON_CTR0_ADDR (0x709)
704 #define UBOX_MSR_PMON_CTR1_ADDR (0x70a)
705 
706 #define JKTIVT_PCU_MSR_PMON_CTR3_ADDR (0x0C39)
707 #define JKTIVT_PCU_MSR_PMON_CTR2_ADDR (0x0C38)
708 #define JKTIVT_PCU_MSR_PMON_CTR1_ADDR (0x0C37)
709 #define JKTIVT_PCU_MSR_PMON_CTR0_ADDR (0x0C36)
710 
711 #define JKTIVT_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0C34)
712 
713 #define JKTIVT_PCU_MSR_PMON_CTL3_ADDR (0x0C33)
714 #define JKTIVT_PCU_MSR_PMON_CTL2_ADDR (0x0C32)
715 #define JKTIVT_PCU_MSR_PMON_CTL1_ADDR (0x0C31)
716 #define JKTIVT_PCU_MSR_PMON_CTL0_ADDR (0x0C30)
717 
718 #define JKTIVT_PCU_MSR_PMON_BOX_CTL_ADDR (0x0C24)
719 
720 #define HSX_PCU_MSR_PMON_CTR3_ADDR (0x071A)
721 #define HSX_PCU_MSR_PMON_CTR2_ADDR (0x0719)
722 #define HSX_PCU_MSR_PMON_CTR1_ADDR (0x0718)
723 #define HSX_PCU_MSR_PMON_CTR0_ADDR (0x0717)
724 
725 #define HSX_PCU_MSR_PMON_BOX_FILTER_ADDR (0x0715)
726 
727 #define HSX_PCU_MSR_PMON_CTL3_ADDR (0x0714)
728 #define HSX_PCU_MSR_PMON_CTL2_ADDR (0x0713)
729 #define HSX_PCU_MSR_PMON_CTL1_ADDR (0x0712)
730 #define HSX_PCU_MSR_PMON_CTL0_ADDR (0x0711)
731 
732 #define HSX_PCU_MSR_PMON_BOX_CTL_ADDR (0x0710)
733 
734 #define UNC_PMON_UNIT_CTL_RST_CONTROL (1 << 0)
735 #define UNC_PMON_UNIT_CTL_RST_COUNTERS (1 << 1)
736 #define UNC_PMON_UNIT_CTL_FRZ (1 << 8)
737 #define UNC_PMON_UNIT_CTL_FRZ_EN (1 << 16)
738 #define UNC_PMON_UNIT_CTL_RSV ((1 << 16) + (1 << 17))
739 
740 #define UNC_PMON_UNIT_CTL_VALID_BITS_MASK ((1 << 17) - 1)
741 
742 #define MC_CH_PCI_PMON_FIXED_CTL_RST (1 << 19)
743 #define MC_CH_PCI_PMON_FIXED_CTL_EN (1 << 22)
744 #define EDC_CH_PCI_PMON_FIXED_CTL_EN (1 << 0)
745 
746 #define MC_CH_PCI_PMON_CTL_EVENT(x) (x << 0)
747 #define MC_CH_PCI_PMON_CTL_UMASK(x) (x << 8)
748 #define MC_CH_PCI_PMON_CTL_RST (1 << 17)
749 #define MC_CH_PCI_PMON_CTL_EDGE_DET (1 << 18)
750 #define MC_CH_PCI_PMON_CTL_EN (1 << 22)
751 #define MC_CH_PCI_PMON_CTL_INVERT (1 << 23)
752 #define MC_CH_PCI_PMON_CTL_THRESH(x) (x << 24UL)
753 
754 #define Q_P_PCI_PMON_CTL_EVENT(x) (x << 0)
755 #define Q_P_PCI_PMON_CTL_UMASK(x) (x << 8)
756 #define Q_P_PCI_PMON_CTL_RST (1 << 17)
757 #define Q_P_PCI_PMON_CTL_EDGE_DET (1 << 18)
758 #define Q_P_PCI_PMON_CTL_EVENT_EXT (1 << 21)
759 #define Q_P_PCI_PMON_CTL_EN (1 << 22)
760 #define Q_P_PCI_PMON_CTL_INVERT (1 << 23)
761 #define Q_P_PCI_PMON_CTL_THRESH(x) (x << 24UL)
762 
763 #define PCU_MSR_PMON_BOX_FILTER_BAND_0(x) (x << 0)
764 #define PCU_MSR_PMON_BOX_FILTER_BAND_1(x) (x << 8)
765 #define PCU_MSR_PMON_BOX_FILTER_BAND_2(x) (x << 16)
766 #define PCU_MSR_PMON_BOX_FILTER_BAND_3(x) (x << 24)
767 
768 #define PCU_MSR_PMON_CTL_EVENT(x) (x << 0)
769 #define PCU_MSR_PMON_CTL_OCC_SEL(x) (x << 14)
770 #define PCU_MSR_PMON_CTL_RST (1 << 17)
771 #define PCU_MSR_PMON_CTL_EDGE_DET (1 << 18)
772 #define PCU_MSR_PMON_CTL_EXTRA_SEL (1 << 21)
773 #define PCU_MSR_PMON_CTL_EN (1 << 22)
774 #define PCU_MSR_PMON_CTL_INVERT (1 << 23)
775 #define PCU_MSR_PMON_CTL_THRESH(x) (x << 24UL)
776 #define PCU_MSR_PMON_CTL_OCC_INVERT (1UL << 30UL)
777 #define PCU_MSR_PMON_CTL_OCC_EDGE_DET (1UL << 31UL)
778 
779 
780 #define JKT_C0_MSR_PMON_CTR3 0x0D19 // CBo 0 PMON Counter 3
781 #define JKT_C0_MSR_PMON_CTR2 0x0D18 // CBo 0 PMON Counter 2
782 #define JKT_C0_MSR_PMON_CTR1 0x0D17 // CBo 0 PMON Counter 1
783 #define JKT_C0_MSR_PMON_CTR0 0x0D16 // CBo 0 PMON Counter 0
784 #define JKT_C0_MSR_PMON_BOX_FILTER 0x0D14 // CBo 0 PMON Filter
785 #define JKT_C0_MSR_PMON_CTL3 0x0D13 // CBo 0 PMON Control for Counter 3
786 #define JKT_C0_MSR_PMON_CTL2 0x0D12 // CBo 0 PMON Control for Counter 2
787 #define JKT_C0_MSR_PMON_CTL1 0x0D11 // CBo 0 PMON Control for Counter 1
788 #define JKT_C0_MSR_PMON_CTL0 0x0D10 // CBo 0 PMON Control for Counter 0
789 #define JKT_C0_MSR_PMON_BOX_CTL 0x0D04 // CBo 0 PMON Box-Wide Control
790 
791 #define JKTIVT_CBO_MSR_STEP 0x0020 // CBo MSR Step
792 
793 #define IVT_C0_MSR_PMON_BOX_FILTER1 0x0D1A // CBo 0 PMON Filter 1
794 
795 #define HSX_C0_MSR_PMON_CTR3 0x0E0B // CBo 0 PMON Counter 3
796 #define HSX_C0_MSR_PMON_CTR2 0x0E0A // CBo 0 PMON Counter 2
797 #define HSX_C0_MSR_PMON_CTR1 0x0E09 // CBo 0 PMON Counter 1
798 #define HSX_C0_MSR_PMON_CTR0 0x0E08 // CBo 0 PMON Counter 0
799 
800 #define HSX_C0_MSR_PMON_BOX_FILTER1 0x0E06 // CBo 0 PMON Filter1
801 #define HSX_C0_MSR_PMON_BOX_FILTER 0x0E05 // CBo 0 PMON Filter0
802 
803 #define HSX_C0_MSR_PMON_CTL3 0x0E04 // CBo 0 PMON Control for Counter 3
804 #define HSX_C0_MSR_PMON_CTL2 0x0E03 // CBo 0 PMON Control for Counter 2
805 #define HSX_C0_MSR_PMON_CTL1 0x0E02 // CBo 0 PMON Control for Counter 1
806 #define HSX_C0_MSR_PMON_CTL0 0x0E01 // CBo 0 PMON Control for Counter 0
807 
808 #define HSX_C0_MSR_PMON_BOX_STATUS 0x0E07 // CBo 0 PMON Box-Wide Status
809 #define HSX_C0_MSR_PMON_BOX_CTL 0x0E00 // CBo 0 PMON Box-Wide Control
810 
811 #define HSX_CBO_MSR_STEP 0x0010 // CBo MSR Step
812 
813 #define KNL_CHA_MSR_STEP 0x000C // CHA MSR Step
814 #define KNL_CHA0_MSR_PMON_BOX_CTRL 0x0E00 // CHA 0 PMON Control
815 
816 #define KNL_CHA0_MSR_PMON_EVT_SEL0 0x0E01 // CHA 0 PMON Event Select for Counter 0
817 #define KNL_CHA0_MSR_PMON_EVT_SEL1 0x0E02 // CHA 0 PMON Event Select for Counter 1
818 #define KNL_CHA0_MSR_PMON_EVT_SEL2 0x0E03 // CHA 0 PMON Event Select for Counter 2
819 #define KNL_CHA0_MSR_PMON_EVT_SEL3 0x0E04 // CHA 0 PMON Event Select for Counter 3
820 
821 #define KNL_CHA0_MSR_PMON_BOX_CTL 0x0E05 // PERF_UNIT_CTL_CHA_0
822 #define KNL_CHA0_MSR_PMON_BOX_CTL1 0x0E06 // PERF_UNIT_CTL_1_CHA_0
823 #define KNL_CHA0_MSR_PMON_BOX_STATUS 0x0E07 // CHA 0 PMON Status
824 
825 #define KNL_CHA0_MSR_PMON_CTR0 0x0E08 // CHA 0 PMON Counter 0
826 #define KNL_CHA0_MSR_PMON_CTR1 0x0E09 // CHA 0 PMON Counter 1
827 #define KNL_CHA0_MSR_PMON_CTR2 0x0E0A // CHA 0 PMON Counter 2
828 #define KNL_CHA0_MSR_PMON_CTR3 0x0E0B // CHA 0 PMON Counter 3
829 
830 #define CBO_MSR_PMON_CTL_EVENT(x) (x << 0)
831 #define CBO_MSR_PMON_CTL_UMASK(x) (x << 8)
832 #define CBO_MSR_PMON_CTL_RST (1 << 17)
833 #define CBO_MSR_PMON_CTL_EDGE_DET (1 << 18)
834 #define CBO_MSR_PMON_CTL_TID_EN (1 << 19)
835 #define CBO_MSR_PMON_CTL_EN (1 << 22)
836 #define CBO_MSR_PMON_CTL_INVERT (1 << 23)
837 #define CBO_MSR_PMON_CTL_THRESH(x) (x << 24UL)
838 
839 #define JKT_CBO_MSR_PMON_BOX_FILTER_OPC(x) (x << 23UL)
840 #define IVTHSX_CBO_MSR_PMON_BOX_FILTER1_OPC(x) (x << 20UL)
841 
842 #define SKX_CHA_MSR_PMON_BOX_FILTER1_REM(x) (x << 0UL)
843 #define SKX_CHA_MSR_PMON_BOX_FILTER1_LOC(x) (x << 1UL)
844 #define SKX_CHA_MSR_PMON_BOX_FILTER1_NM(x) (x << 4UL)
845 #define SKX_CHA_MSR_PMON_BOX_FILTER1_NOT_NM(x) (x << 5UL)
846 #define SKX_CHA_MSR_PMON_BOX_FILTER1_OPC0(x) ((x) << 9UL)
847 #define SKX_CHA_MSR_PMON_BOX_FILTER1_OPC1(x) ((x) << 19UL)
848 #define SKX_CHA_MSR_PMON_BOX_FILTER1_NC(x) (x << 30UL)
849 
850 #define SKX_CHA_TOR_INSERTS_UMASK_IRQ(x) (x << 0)
851 #define SKX_CHA_TOR_INSERTS_UMASK_PRQ(x) (x << 2)
852 #define SKX_CHA_TOR_INSERTS_UMASK_HIT(x) (x << 4)
853 #define SKX_CHA_TOR_INSERTS_UMASK_MISS(x) (x << 5)
854 
855 #define SKX_IIO_CBDMA_UNIT_STATUS (0x0A47)
856 #define SKX_IIO_CBDMA_UNIT_CTL (0x0A40)
857 #define SKX_IIO_CBDMA_CTR0 (0x0A41)
858 #define SKX_IIO_CBDMA_CLK (0x0A45)
859 #define SKX_IIO_CBDMA_CTL0 (0x0A48)
860 #define SKX_IIO_PM_REG_STEP (0x0020)
861 
862 #define IIO_MSR_PMON_CTL_EVENT(x) ((x) << 0)
863 #define IIO_MSR_PMON_CTL_UMASK(x) ((x) << 8)
864 #define IIO_MSR_PMON_CTL_RST (1 << 17)
865 #define IIO_MSR_PMON_CTL_EDGE_DET (1 << 18)
866 #define IIO_MSR_PMON_CTL_OV_EN (1 << 20)
867 #define IIO_MSR_PMON_CTL_EN (1 << 22)
868 #define IIO_MSR_PMON_CTL_INVERT (1 << 23)
869 #define IIO_MSR_PMON_CTL_THRESH(x) ((x) << 24ULL)
870 #define IIO_MSR_PMON_CTL_CH_MASK(x) ((x) << 36ULL)
871 #define IIO_MSR_PMON_CTL_FC_MASK(x) ((x) << 44ULL)
872 
873 #define M2M_PCI_PMON_CTL_EVENT(x) ((x) << 0)
874 #define M2M_PCI_PMON_CTL_UMASK(x) ((x) << 8)
875 #define M2M_PCI_PMON_CTL_RST (1 << 17)
876 #define M2M_PCI_PMON_CTL_EDGE_DET (1 << 18)
877 #define M2M_PCI_PMON_CTL_OV_EN (1 << 20)
878 #define M2M_PCI_PMON_CTL_EN (1 << 22)
879 #define M2M_PCI_PMON_CTL_INVERT (1 << 23)
880 #define M2M_PCI_PMON_CTL_THRESH(x) ((x) << 24ULL)
881 
882 #define UCLK_FIXED_CTL_OV_EN (1 << 20)
883 #define UCLK_FIXED_CTL_EN (1 << 22)
884 
885 /* \brief IIO Performance Monitoring Control Register format
886 
887  IIOn_MSR_PMON_CTL{3-0} Register- Field Definitions
888 */
890 {
891  union
892  {
893  struct
894  {
895  uint64 event_select : 8;
896  uint64 umask : 8;
897  uint64 reserved1 : 1;
898  uint64 reset : 1;
899  uint64 edge_det : 1;
900  uint64 ignored : 1;
901  uint64 overflow_enable : 1;
902  uint64 reserved2 : 1;
903  uint64 enable : 1;
904  uint64 invert : 1;
905  uint64 thresh : 12;
906  uint64 ch_mask : 8;
907  uint64 fc_mask : 3;
908  uint64 reservedX : 17;
909  } fields;
910  uint64 value;
911  };
912  IIOPMUCNTCTLRegister() : value(0) { }
913 };
914 
915 #define MSR_PACKAGE_THERM_STATUS (0x01B1)
916 #define MSR_IA32_THERM_STATUS (0x019C)
917 #define PCM_INVALID_THERMAL_HEADROOM ((std::numeric_limits<int32>::min)())
918 
919 #define MSR_IA32_BIOS_SIGN_ID (0x8B)
920 
921 #define MSR_DRAM_ENERGY_STATUS (0x0619)
922 
923 #define MSR_PKG_C2_RESIDENCY (0x60D)
924 #define MSR_PKG_C3_RESIDENCY (0x3F8)
925 #define MSR_PKG_C6_RESIDENCY (0x3F9)
926 #define MSR_PKG_C7_RESIDENCY (0x3FA)
927 #define MSR_CORE_C3_RESIDENCY (0x3FC)
928 #define MSR_CORE_C6_RESIDENCY (0x3FD)
929 #define MSR_CORE_C7_RESIDENCY (0x3FE)
930 
931 #define MSR_PERF_GLOBAL_INUSE (0x392)
932 
933 #define MSR_IA32_SPEC_CTRL (0x48)
934 #define MSR_IA32_ARCH_CAPABILITIES (0x10A)
935 
936 #ifdef _MSC_VER
937 #include <windows.h>
938 // data structure for converting two uint32s <-> uin64
939 union cvt_ds
940 {
941  UINT64 ui64;
942  struct
943  {
944  DWORD low;
945  DWORD high;
946  } ui32;
947 };
948 
949 #endif
950 
952 {
953  unsigned long long baseAddress;
954  unsigned short PCISegmentGroupNumber;
955  unsigned char startBusNumber;
956  unsigned char endBusNumber;
957  char reserved[4];
958  void print()
959  {
960  std::cout << "BaseAddress=" << (std::hex) << "0x" << baseAddress << " PCISegmentGroupNumber=0x" << PCISegmentGroupNumber <<
961  " startBusNumber=0x" << (unsigned)startBusNumber << " endBusNumber=0x" << (unsigned)endBusNumber << std::endl;
962  }
963 };
964 
966 {
967  char signature[4];
968  unsigned length;
969  unsigned char revision;
970  unsigned char checksum;
971  char OEMID[6];
972  char OEMTableID[8];
973  unsigned OEMRevision;
974  unsigned creatorID;
975  unsigned creatorRevision;
976  char reserved[8];
977 
978  unsigned nrecords() const
979  {
980  return (length - sizeof(MCFGHeader)) / sizeof(MCFGRecord);
981  }
982 
983  void print()
984  {
985  std::cout << "Header: length=" << length << " nrecords=" << nrecords() << std::endl;
986  }
987 };
988 
989 #endif
Definition: types.h:301
Definition: types.h:336
Definition: types.h:965
Definition: types.h:889
Definition: types.h:393
Definition: types.h:456
Definition: types.h:421
Definition: types.h:951