From 0000000000000000000000000000000000000000 Mon Sep 17 00:00:00 2001 From: SENEMOS patch gate Date: Mon, 31 Aug 2026 13:03:57 +0300 Subject: [PATCH 11/23] nabu: carry 90 Hz touch policy and defer optional XHCI on 6.18 --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 +++- drivers/gpu/drm/msm/msm_atomic.c | 10 +++++++++ drivers/gpu/drm/panel/panel-novatek-nt36523.c | 22 ++++++++++++++++--- 3 files changed, 32 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 6f5d90b7b..1fa881c70 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include @@ -1360,7 +1361,8 @@ static struct msm_display_topology dpu_crtc_get_topology( else topology.num_lm = 1; - if (crtc_state->ctm) + /* Keep DSPP resources stable when Nabu toggles its Night Light CTM. */ + if (crtc_state->ctm || of_machine_is_compatible("xiaomi,nabu")) topology.num_dspp = topology.num_lm; return topology; diff --git a/drivers/gpu/drm/msm/msm_atomic.c b/drivers/gpu/drm/msm/msm_atomic.c index ae617bb54..78c33c6bd 100644 --- a/drivers/gpu/drm/msm/msm_atomic.c +++ b/drivers/gpu/drm/msm/msm_atomic.c @@ -9,6 +9,8 @@ #include #include +#include + #include "msm_atomic_trace.h" #include "msm_drv.h" #include "msm_gem.h" @@ -382,6 +384,14 @@ int msm_atomic_check(struct drm_device *dev, struct drm_atomic_state *state) new_crtc_state, i) { if ((old_crtc_state->ctm && !new_crtc_state->ctm) || (!old_crtc_state->ctm && new_crtc_state->ctm)) { + /* + * Nabu reserves DSPP resources at every modeset. Its CTM can + * therefore be enabled or bypassed through the normal atomic + * color-management flush without blanking the dual-DSI panel. + */ + if (of_machine_is_compatible("xiaomi,nabu")) + continue; + new_crtc_state->mode_changed = true; state->allow_modeset = true; } diff --git a/drivers/gpu/drm/panel/panel-novatek-nt36523.c b/drivers/gpu/drm/panel/panel-novatek-nt36523.c index 755b71826..5f16cd473 100644 --- a/drivers/gpu/drm/panel/panel-novatek-nt36523.c +++ b/drivers/gpu/drm/panel/panel-novatek-nt36523.c @@ -23,6 +23,11 @@ #define DSI_NUM_MIN 1 +static bool expose_nabu_90hz; +module_param(expose_nabu_90hz, bool, 0444); +MODULE_PARM_DESC(expose_nabu_90hz, + "Expose Xiaomi Nabu experimental 90 Hz mode"); + struct panel_info { struct drm_panel panel; struct mipi_dsi_device *dsi[2]; @@ -1402,12 +1407,22 @@ static int nt36523_get_modes(struct drm_panel *panel, struct drm_connector *connector) { struct panel_info *pinfo = to_panel_info(panel); - int i; + int i, num_modes = 0; for (i = 0; i < pinfo->desc->num_modes; i++) { const struct drm_display_mode *m = &pinfo->desc->modes[i]; struct drm_display_mode *mode; + /* + * Xiaomi's Nabu vendor panel data advertises only 60 and 120 Hz. + * Keep the experimental 90 Hz timing compiled for diagnostics, but + * do not expose it to KMS clients until the dual-DSI scanout fault is + * resolved and physically validated. + */ + if (pinfo->desc == &nabu_csot_desc && + drm_mode_vrefresh(m) == 90 && !expose_nabu_90hz) + continue; + mode = drm_mode_duplicate(connector->dev, m); if (!mode) { dev_err(panel->dev, "failed to add mode %ux%u@%u\n", @@ -1416,18 +1431,19 @@ static int nt36523_get_modes(struct drm_panel *panel, } mode->type = DRM_MODE_TYPE_DRIVER; - if (i == 0) + if (!num_modes) mode->type |= DRM_MODE_TYPE_PREFERRED; drm_mode_set_name(mode); drm_mode_probed_add(connector, mode); + num_modes++; } connector->display_info.width_mm = pinfo->desc->width_mm; connector->display_info.height_mm = pinfo->desc->height_mm; connector->display_info.bpc = pinfo->desc->bpc; - return pinfo->desc->num_modes; + return num_modes; } static enum drm_panel_orientation nt36523_get_orientation(struct drm_panel *panel)