From 0000000000000000000000000000000000000157 Mon Sep 17 00:00:00 2001
From: SENEMOS patch gate <mcc45tr@gmail.com>
Date: Mon, 21 Sep 2026 18:00:00 +0300
Subject: [PATCH] drm/msm/dsi: preserve the SM8150 bonded PLL bias lifetime

The revert 44784327815b restores standalone displays but brings back the
bonded PLL initialization regression addressed by 93c97bc8d85d. Nabu uses
two 7nm SM8150 PHYs sharing PLL0. Restore the reference-count and bias
refresh behavior only for bonded SM8150 links; keep the upstream behavior
for standalone links and other SoCs. Retain the existing register lock.

This is a device-scoped downstream fix. Boot and suspend/resume still
require physical validation; a source-level test cannot prove signal
integrity on the panel.

Signed-off-by: SENEMOS patch gate <mcc45tr@gmail.com>
---
diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
index 5d805a797..d63f7142e 100644
--- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
+++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
@@ -420,15 +420,28 @@ static void dsi_pll_disable_pll_bias(struct dsi_pll_7nm *pll)
 	ndelay(250);
 }
 
+/*
+ * The bonded SM8150 links share PLL0. Clock operations from the other link
+ * can precede PHY enable, and PHY reset can clear the bias while clock users
+ * still hold references. Keep the working bonded sequence from 93c97bc8d85d
+ * without changing the standalone sequence restored by 44784327815b.
+ */
+static bool dsi_7nm_bonded_8150(const struct msm_dsi_phy *phy)
+{
+	return phy->cfg == &dsi_phy_7nm_8150_cfgs &&
+		phy->usecase != MSM_DSI_PHY_STANDALONE;
+}
+
 static void dsi_pll_enable_pll_bias(struct dsi_pll_7nm *pll)
 {
 	unsigned long flags;
 	u32 data;
 
 	spin_lock_irqsave(&pll->pll_enable_lock, flags);
-	if (pll->pll_enable_cnt++) {
+	pll->pll_enable_cnt++;
+	WARN_ON(pll->pll_enable_cnt == INT_MAX);
+	if (pll->pll_enable_cnt > 1 && !dsi_7nm_bonded_8150(pll->phy)) {
 		spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
-		WARN_ON(pll->pll_enable_cnt == INT_MAX);
 		return;
 	}
 
@@ -1091,7 +1104,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
 	}
 
 	spin_lock_irqsave(&pll->pll_enable_lock, flags);
-	pll->pll_enable_cnt = 1;
+	if (!dsi_7nm_bonded_8150(phy))
+		pll->pll_enable_cnt = 1;
 	/* de-assert digital and pll power down */
 	data = DSI_7nm_PHY_CMN_CTRL_0_DIGTOP_PWRDN_B |
 	       DSI_7nm_PHY_CMN_CTRL_0_PLL_SHUTDOWNB;
@@ -1239,7 +1253,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
 	writel(0, base + REG_DSI_7nm_PHY_CMN_LANE_CTRL0);
 
 	spin_lock_irqsave(&pll->pll_enable_lock, flags);
-	pll->pll_enable_cnt = 0;
+	if (!dsi_7nm_bonded_8150(phy))
+		pll->pll_enable_cnt = 0;
 	/* Turn off all PHY blocks */
 	writel(0x00, base + REG_DSI_7nm_PHY_CMN_CTRL_0);
 	spin_unlock_irqrestore(&pll->pll_enable_lock, flags);
-- 
2.55.0