Warning: Permanently added '34.238.154.64' (ED25519) to the list of known hosts. You can reproduce this build on your computer by running: sudo dnf install copr-rpmbuild /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/11009165-epel-10-aarch64 --chroot epel-10-aarch64 Version: 1.9 PID: 71693 Logging PID: 71695 Task: {'allow_user_ssh': False, 'appstream': False, 'background': False, 'build_id': 11009165, 'buildroot_pkgs': [], 'chroot': 'epel-10-aarch64', 'enable_net': True, 'fedora_review': False, 'git_hash': 'de7cee888f9b010852e7403fe11d3a013bf625e2', 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6', 'isolation': 'default', 'memory_reqs': 2048, 'package_name': 'litex-pythondata-cpu-cva6', 'package_version': '2026.04-20260917.0.git2b51ea6a', 'project_dirname': 'HDL', 'project_name': 'HDL', 'project_owner': 'rezso', 'repo_priority': None, 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/HDL/epel-10-aarch64/', 'id': 'copr_base', 'name': 'Copr repository', 'priority': None, 'repo_gpgcheck': False}], 'sandbox': 'rezso/HDL--rezso', 'source_json': {}, 'source_type': None, 'ssh_public_keys': None, 'storage': 0, 'submitter': 'rezso', 'tags': [], 'task_id': '11009165-epel-10-aarch64', 'timeout': 180000, 'uses_devel_repo': False, 'with_opts': [], 'without_opts': []} Running: git clone https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6 /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6 --depth 500 --no-single-branch --recursive cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6', '/var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6', '--depth', '500', '--no-single-branch', '--recursive'] cwd: . rc: 0 stdout: stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6'... Running: git checkout de7cee888f9b010852e7403fe11d3a013bf625e2 -- cmd: ['git', 'checkout', 'de7cee888f9b010852e7403fe11d3a013bf625e2', '--'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6 rc: 0 stdout: stderr: Note: switching to 'de7cee888f9b010852e7403fe11d3a013bf625e2'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at de7cee8 automatic import of litex-pythondata-cpu-cva6 Running: dist-git-client sources cmd: ['dist-git-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6 rc: 0 stdout: stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources tail: /var/lib/copr-rpmbuild/main.log: file truncated Running (timeout=180000): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1789969169.608280 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 6.8 starting (python version = 3.14.5, NVR = mock-6.8-1.fc44), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1789969169.608280 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(centos-stream+epel-10-aarch64) Start: clean chroot Finish: clean chroot Mock Version: 6.8 INFO: Mock Version: 6.8 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/centos-stream+epel-10-aarch64-bootstrap-1789969169.608280/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using container image: quay.io/centos/centos:stream10 INFO: Pulling image: quay.io/centos/centos:stream10 INFO: Tagging container image as mock-bootstrap-f140fa3c-29cf-4d1e-b85d-a2171d22ec54 INFO: Checking that 73dc7ebecda05f1b2d9aea1c04dfa3314665cdaeb2e706020ce53b177607c0d1 image matches host's architecture INFO: Copy content of container 73dc7ebecda05f1b2d9aea1c04dfa3314665cdaeb2e706020ce53b177607c0d1 to /var/lib/mock/centos-stream+epel-10-aarch64-bootstrap-1789969169.608280/root INFO: mounting 73dc7ebecda05f1b2d9aea1c04dfa3314665cdaeb2e706020ce53b177607c0d1 with podman image mount INFO: image 73dc7ebecda05f1b2d9aea1c04dfa3314665cdaeb2e706020ce53b177607c0d1 as /var/lib/containers/storage/overlay/21d1cbd0b5ded111068514af846a0e3c3b594fa57313a20c6bf708ea550caf50/merged INFO: umounting image 73dc7ebecda05f1b2d9aea1c04dfa3314665cdaeb2e706020ce53b177607c0d1 (/var/lib/containers/storage/overlay/21d1cbd0b5ded111068514af846a0e3c3b594fa57313a20c6bf708ea550caf50/merged) with podman image umount INFO: Removing image mock-bootstrap-f140fa3c-29cf-4d1e-b85d-a2171d22ec54 INFO: Package manager dnf4 detected and used (fallback) INFO: Not updating bootstrap chroot, bootstrap_image_ready=True Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf4 detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.1.1-25.el10.aarch64 rpm-sequoia-1.10.2.3-1.el10.aarch64 python3-dnf-4.20.0-28.el10.noarch python3-dnf-plugins-core-4.7.0-12.el10.noarch yum-4.20.0-28.el10.noarch Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 5.2 kB/s | 940 B 00:00 Errors during downloading metadata for repository 'copr_base': - Status code: 503 for https://download.copr.fedorainfracloud.org/results/rezso/HDL/epel-10-aarch64/repodata/ccae04ed66ebb8b1b573dcf7a91b7feee864568346e8cd8e5e2759b388c3b229-primary.xml.gz (IP: 108.138.85.54) Error: Failed to download metadata for repo 'copr_base': Yum repo downloading error: Downloading error(s): repodata/ccae04ed66ebb8b1b573dcf7a91b7feee864568346e8cd8e5e2759b388c3b229-primary.xml.gz - Cannot download, all mirrors were already tried without success WARNING: DNF4 command failed, retrying, attempt #2, sleeping 10s No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 2.1 MB/s | 94 kB 00:00 CentOS Stream 10 - BaseOS 26 MB/s | 9.3 MB 00:00 CentOS Stream 10 - AppStream 9.0 MB/s | 3.2 MB 00:00 CentOS Stream 10 - CRB 2.8 MB/s | 753 kB 00:00 CentOS Stream 10 - Extras packages 39 kB/s | 11 kB 00:00 Extra Packages for Enterprise Linux 10 - aarch6 54 MB/s | 7.1 MB 00:00 Dependencies resolved. ====================================================================================== Package Arch Version Repo Size ====================================================================================== Installing: bash aarch64 5.2.26-6.el10 baseos 1.8 M bzip2 aarch64 1.0.8-25.el10 baseos 54 k centos-stream-release noarch 10.0-23.el10 baseos 29 k coreutils aarch64 9.5-13.el10 baseos 1.1 M cpio aarch64 2.15-3.el10 baseos 290 k diffutils aarch64 3.10-8.el10 baseos 405 k epel-rpm-macros noarch 10-7.el10_3 epel 8.4 k findutils aarch64 1:4.10.0-5.el10 baseos 555 k gawk aarch64 5.3.0-7.el10 baseos 1.1 M glibc-minimal-langpack aarch64 2.39-141.el10 baseos 24 k grep aarch64 3.11-10.el10 baseos 298 k gzip aarch64 1.13-4.el10 baseos 167 k info aarch64 7.1-6.el10 baseos 182 k patch aarch64 2.7.6-26.el10 appstream 130 k redhat-rpm-config noarch 296-1.el10 appstream 73 k rpm-build aarch64 4.19.1.1-25.el10 appstream 76 k sed aarch64 4.9-5.el10 baseos 315 k shadow-utils aarch64 2:4.15.0-13.el10 baseos 1.3 M tar aarch64 2:1.35-13.el10 baseos 860 k unzip aarch64 6.0-69.el10 baseos 186 k util-linux aarch64 2.40.2-20.el10 baseos 1.2 M which aarch64 2.21-44.el10 baseos 42 k xz aarch64 1:5.6.2-5.el10 baseos 480 k Installing dependencies: R-srpm-macros noarch 1.3.7-2.el10_3 epel 11 k alternatives aarch64 1.30-2.el10 baseos 41 k ansible-srpm-macros noarch 1-21.el10_3 epel 20 k audit-libs aarch64 4.2.1-3.el10 baseos 141 k authselect aarch64 1.5.3-1.el10 baseos 229 k authselect-libs aarch64 1.5.3-1.el10 baseos 266 k basesystem noarch 11-22.el10 baseos 4.3 k binutils aarch64 2.41-66.el10 baseos 6.7 M binutils-gold aarch64 2.41-66.el10 baseos 936 k bzip2-libs aarch64 1.0.8-25.el10 baseos 42 k ca-certificates noarch 2026.2.90_v9.0.316-100.0.el10 baseos 1.1 M centos-gpg-keys noarch 10.0-23.el10 baseos 26 k centos-stream-repos noarch 10.0-23.el10 baseos 11 k coreutils-common aarch64 9.5-13.el10 baseos 2.1 M cracklib aarch64 2.9.11-8.el10 baseos 96 k cracklib-dicts aarch64 2.9.11-8.el10 baseos 3.6 M crypto-policies noarch 20260811-1.git4dcd294.el10 baseos 95 k curl aarch64 8.12.1-6.el10 baseos 213 k cyrus-sasl-lib aarch64 2.1.28-27.el10 baseos 107 k debugedit aarch64 5.3-2.el10 appstream 87 k dwz aarch64 0.16-1.el10 appstream 137 k ed aarch64 1.20-5.el10 baseos 82 k efi-srpm-macros noarch 6-8.el10 appstream 23 k elfutils aarch64 0.195-1.el10 baseos 581 k elfutils-debuginfod-client aarch64 0.195-1.el10 baseos 43 k elfutils-default-yama-scope noarch 0.195-1.el10 baseos 8.6 k elfutils-libelf aarch64 0.195-1.el10 baseos 204 k elfutils-libs aarch64 0.195-1.el10 baseos 264 k file aarch64 5.45-12.el10 baseos 48 k file-libs aarch64 5.45-12.el10 baseos 761 k filesystem aarch64 3.18-17.el10 baseos 4.8 M fonts-srpm-macros noarch 1:2.0.5-18.el10 appstream 27 k forge-srpm-macros noarch 0.4.0-6.el10 appstream 21 k fpc-srpm-macros noarch 1.3-7.el10_1 epel 7.8 k gdb-minimal aarch64 17.2-3.1.el10 appstream 4.2 M gdbm aarch64 1:1.23-14.el10 baseos 150 k gdbm-libs aarch64 1:1.23-14.el10 baseos 56 k ghc-srpm-macros noarch 1.9.2-1.el10_0 epel 9.1 k glibc aarch64 2.39-141.el10 baseos 1.8 M glibc-common aarch64 2.39-141.el10 baseos 306 k glibc-gconv-extra aarch64 2.39-141.el10 baseos 1.7 M gmp aarch64 1:6.2.1-12.el10 baseos 268 k go-srpm-macros noarch 3.8.0-1.el10 appstream 27 k jansson aarch64 2.14-3.el10 baseos 47 k json-c aarch64 0.18-3.el10 baseos 46 k kernel-srpm-macros noarch 1.0-29.el10 appstream 8.7 k keyutils-libs aarch64 1.6.3-5.el10 baseos 33 k krb5-libs aarch64 1.21.3-11.el10 baseos 769 k libacl aarch64 2.4.0-2.el10 baseos 26 k libarchive aarch64 3.7.7-11.el10 baseos 406 k libattr aarch64 2.6.0-2.el10 baseos 17 k libblkid aarch64 2.40.2-20.el10 baseos 123 k libbrotli aarch64 1.1.0-8.el10 baseos 344 k libcap aarch64 2.69-7.el10 baseos 91 k libcap-ng aarch64 0.9.3-2.el10 baseos 33 k libcbor aarch64 0.11.0-3.el10 baseos 34 k libcom_err aarch64 1.47.1-5.el10 baseos 26 k libcurl aarch64 8.12.1-6.el10 baseos 360 k libeconf aarch64 0.6.2-4.el10 baseos 33 k libevent aarch64 2.1.12-16.el10 baseos 256 k libfdisk aarch64 2.40.2-20.el10 baseos 156 k libffi aarch64 3.4.4-10.el10 baseos 38 k libfido2 aarch64 1.14.0-7.el10 baseos 97 k libgcc aarch64 14.4.1-3.el10 baseos 114 k libgomp aarch64 14.4.1-3.el10 baseos 345 k libidn2 aarch64 2.3.7-3.el10 baseos 119 k libmount aarch64 2.40.2-20.el10 baseos 152 k libnghttp2 aarch64 1.68.0-6.el10 baseos 71 k libpkgconf aarch64 2.1.0-3.el10 baseos 39 k libpsl aarch64 0.21.5-6.el10 baseos 65 k libpwquality aarch64 1.4.5-13.el10 baseos 121 k libselinux aarch64 3.11-2.el10 baseos 98 k libsemanage aarch64 3.11-2.el10 baseos 119 k libsepol aarch64 3.11-2.el10 baseos 333 k libsmartcols aarch64 2.40.2-20.el10 baseos 81 k libssh aarch64 0.12.2-2.el10 baseos 277 k libssh-config noarch 0.12.2-2.el10 baseos 8.4 k libstdc++ aarch64 14.4.1-3.el10 baseos 858 k libtasn1 aarch64 4.20.0-5.el10 baseos 73 k libunistring aarch64 1.1-10.el10 baseos 540 k libutempter aarch64 1.2.1-15.el10 baseos 28 k libuuid aarch64 2.40.2-20.el10 baseos 28 k libverto aarch64 0.3.2-10.el10 baseos 22 k libxcrypt aarch64 4.4.36-10.el10 baseos 124 k libxml2 aarch64 2.12.5-15.el10 baseos 673 k libzstd aarch64 1.5.5-9.el10 baseos 285 k lua-libs aarch64 5.4.8-1.el10 baseos 128 k lua-srpm-macros noarch 1-15.el10 appstream 9.8 k lz4-libs aarch64 1.9.4-8.el10 baseos 68 k mpfr aarch64 4.2.1-8.el10 baseos 324 k ncurses-base noarch 6.4-15.20240127.el10 baseos 98 k ncurses-libs aarch64 6.4-15.20240127.el10 baseos 325 k ocaml-srpm-macros noarch 10-4.el10 appstream 10 k openblas-srpm-macros noarch 2-19.el10 appstream 8.7 k openldap aarch64 2.6.13-1.el10 baseos 236 k openssl-fips-provider aarch64 1:3.5.8-1.el10 baseos 716 k openssl-libs aarch64 1:3.5.8-1.el10 baseos 2.1 M p11-kit aarch64 0.26.4-1.el10 baseos 539 k p11-kit-trust aarch64 0.26.4-1.el10 baseos 141 k package-notes-srpm-macros noarch 0.5-13.el10 appstream 10 k pam aarch64 1.6.1-11.el10 baseos 589 k pam-libs aarch64 1.6.1-11.el10 baseos 55 k pcre2 aarch64 10.44-1.el10.3 baseos 227 k pcre2-syntax noarch 10.44-1.el10.3 baseos 151 k perl-srpm-macros noarch 1-57.el10 appstream 9.5 k pkgconf aarch64 2.1.0-3.el10 baseos 44 k pkgconf-m4 noarch 2.1.0-3.el10 baseos 15 k pkgconf-pkg-config aarch64 2.1.0-3.el10 baseos 11 k popt aarch64 1.19-9.el10 baseos 64 k publicsuffix-list-dafsa noarch 20240107-5.el10 baseos 59 k pyproject-srpm-macros noarch 1.23.2-1.el10 appstream 15 k python-srpm-macros noarch 3.12-11.el10 appstream 22 k qt6-srpm-macros noarch 6.10.1-1.el10 appstream 9.1 k readline aarch64 8.2-11.el10 baseos 212 k rpm aarch64 4.19.1.1-25.el10 baseos 562 k rpm-build-libs aarch64 4.19.1.1-25.el10 baseos 88 k rpm-libs aarch64 4.19.1.1-25.el10 baseos 300 k rpm-sequoia aarch64 1.10.2.3-1.el10 baseos 900 k rust-toolset-srpm-macros noarch 1.97.1-4.el10 appstream 10 k setup noarch 2.14.5-7.el10 baseos 153 k sqlite-libs aarch64 3.46.1-6.el10 baseos 729 k systemd-libs aarch64 257-33.el10 baseos 813 k util-linux-core aarch64 2.40.2-20.el10 baseos 543 k xz-libs aarch64 1:5.6.2-5.el10 baseos 108 k zip aarch64 3.0-45.el10 baseos 264 k zlib-ng-compat aarch64 2.2.3-3.el10 baseos 63 k zstd aarch64 1.5.5-9.el10 baseos 455 k Transaction Summary ====================================================================================== Install 150 Packages Total download size: 60 M Installed size: 217 M Downloading Packages: (1/150): alternatives-1.30-2.el10.aarch64.rpm 3.2 MB/s | 41 kB 00:00 (2/150): audit-libs-4.2.1-3.el10.aarch64.rpm 9.2 MB/s | 141 kB 00:00 (3/150): authselect-1.5.3-1.el10.aarch64.rpm 13 MB/s | 229 kB 00:00 (4/150): authselect-libs-1.5.3-1.el10.aarch64.r 43 MB/s | 266 kB 00:00 (5/150): basesystem-11-22.el10.noarch.rpm 1.2 MB/s | 4.3 kB 00:00 (6/150): bash-5.2.26-6.el10.aarch64.rpm 135 MB/s | 1.8 MB 00:00 (7/150): binutils-gold-2.41-66.el10.aarch64.rpm 62 MB/s | 936 kB 00:00 (8/150): bzip2-1.0.8-25.el10.aarch64.rpm 3.7 MB/s | 54 kB 00:00 (9/150): binutils-2.41-66.el10.aarch64.rpm 182 MB/s | 6.7 MB 00:00 (10/150): bzip2-libs-1.0.8-25.el10.aarch64.rpm 1.9 MB/s | 42 kB 00:00 (11/150): ca-certificates-2026.2.90_v9.0.316-10 71 MB/s | 1.1 MB 00:00 (12/150): centos-stream-release-10.0-23.el10.no 5.4 MB/s | 29 kB 00:00 (13/150): centos-gpg-keys-10.0-23.el10.noarch.r 3.2 MB/s | 26 kB 00:00 (14/150): centos-stream-repos-10.0-23.el10.noar 4.8 MB/s | 11 kB 00:00 (15/150): coreutils-9.5-13.el10.aarch64.rpm 149 MB/s | 1.1 MB 00:00 (16/150): cpio-2.15-3.el10.aarch64.rpm 40 MB/s | 290 kB 00:00 (17/150): coreutils-common-9.5-13.el10.aarch64. 150 MB/s | 2.1 MB 00:00 (18/150): cracklib-2.9.11-8.el10.aarch64.rpm 9.9 MB/s | 96 kB 00:00 (19/150): crypto-policies-20260811-1.git4dcd294 18 MB/s | 95 kB 00:00 (20/150): curl-8.12.1-6.el10.aarch64.rpm 38 MB/s | 213 kB 00:00 (21/150): cyrus-sasl-lib-2.1.28-27.el10.aarch64 20 MB/s | 107 kB 00:00 (22/150): diffutils-3.10-8.el10.aarch64.rpm 58 MB/s | 405 kB 00:00 (23/150): cracklib-dicts-2.9.11-8.el10.aarch64. 143 MB/s | 3.6 MB 00:00 (24/150): ed-1.20-5.el10.aarch64.rpm 9.8 MB/s | 82 kB 00:00 (25/150): elfutils-0.195-1.el10.aarch64.rpm 72 MB/s | 581 kB 00:00 (26/150): elfutils-default-yama-scope-0.195-1.e 3.6 MB/s | 8.6 kB 00:00 (27/150): elfutils-debuginfod-client-0.195-1.el 13 MB/s | 43 kB 00:00 (28/150): file-5.45-12.el10.aarch64.rpm 23 MB/s | 48 kB 00:00 (29/150): elfutils-libelf-0.195-1.el10.aarch64. 52 MB/s | 204 kB 00:00 (30/150): elfutils-libs-0.195-1.el10.aarch64.rp 57 MB/s | 264 kB 00:00 (31/150): file-libs-5.45-12.el10.aarch64.rpm 112 MB/s | 761 kB 00:00 (32/150): findutils-4.10.0-5.el10.aarch64.rpm 71 MB/s | 555 kB 00:00 (33/150): gawk-5.3.0-7.el10.aarch64.rpm 65 MB/s | 1.1 MB 00:00 (34/150): gdbm-1.23-14.el10.aarch64.rpm 10 MB/s | 150 kB 00:00 (35/150): filesystem-3.18-17.el10.aarch64.rpm 169 MB/s | 4.8 MB 00:00 (36/150): gdbm-libs-1.23-14.el10.aarch64.rpm 8.5 MB/s | 56 kB 00:00 (37/150): glibc-common-2.39-141.el10.aarch64.rp 66 MB/s | 306 kB 00:00 (38/150): glibc-2.39-141.el10.aarch64.rpm 107 MB/s | 1.8 MB 00:00 (39/150): glibc-minimal-langpack-2.39-141.el10. 2.7 MB/s | 24 kB 00:00 (40/150): glibc-gconv-extra-2.39-141.el10.aarch 113 MB/s | 1.7 MB 00:00 (41/150): gmp-6.2.1-12.el10.aarch64.rpm 44 MB/s | 268 kB 00:00 (42/150): grep-3.11-10.el10.aarch64.rpm 59 MB/s | 298 kB 00:00 (43/150): gzip-1.13-4.el10.aarch64.rpm 42 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10 kB 00:00 (146/150): epel-rpm-macros-10-7.el10_3.noarch.r 1.2 MB/s | 8.4 kB 00:00 (147/150): R-srpm-macros-1.3.7-2.el10_3.noarch. 1.2 MB/s | 11 kB 00:00 (148/150): ansible-srpm-macros-1-21.el10_3.noar 2.0 MB/s | 20 kB 00:00 (149/150): fpc-srpm-macros-1.3-7.el10_1.noarch. 2.0 MB/s | 7.8 kB 00:00 (150/150): ghc-srpm-macros-1.9.2-1.el10_0.noarc 3.1 MB/s | 9.1 kB 00:00 -------------------------------------------------------------------------------- Total 87 MB/s | 60 MB 00:00 CentOS Stream 10 - BaseOS 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x8483C65D: Userid : "CentOS (CentOS Official Signing Key) " Fingerprint: 99DB 70FA E1D7 CE22 7FB6 4882 05B5 55B3 8483 C65D From : /usr/share/distribution-gpg-keys/centos/RPM-GPG-KEY-CentOS-Official-SHA256 Key imported successfully Extra Packages for Enterprise Linux 10 - aarch6 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0xE37ED158: Userid : "Fedora (epel10) " Fingerprint: 7D8D 15CB FC4E 6268 8591 FB26 33D9 8517 E37E D158 From : /usr/share/distribution-gpg-keys/epel/RPM-GPG-KEY-EPEL-10 Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-17.el10.aarch64 1/1 Preparing : 1/1 Installing : libgcc-14.4.1-3.el10.aarch64 1/150 Running scriptlet: libgcc-14.4.1-3.el10.aarch64 1/150 Installing : ghc-srpm-macros-1.9.2-1.el10_0.noarch 2/150 Installing : fpc-srpm-macros-1.3-7.el10_1.noarch 3/150 Installing : ansible-srpm-macros-1-21.el10_3.noarch 4/150 Installing : rust-toolset-srpm-macros-1.97.1-4.el10.noarch 5/150 Installing : qt6-srpm-macros-6.10.1-1.el10.noarch 6/150 Installing : perl-srpm-macros-1-57.el10.noarch 7/150 Installing : package-notes-srpm-macros-0.5-13.el10.noarch 8/150 Installing : openblas-srpm-macros-2-19.el10.noarch 9/150 Installing : ocaml-srpm-macros-10-4.el10.noarch 10/150 Installing : kernel-srpm-macros-1.0-29.el10.noarch 11/150 Installing : publicsuffix-list-dafsa-20240107-5.el10.noarch 12/150 Installing : pkgconf-m4-2.1.0-3.el10.noarch 13/150 Installing : pcre2-syntax-10.44-1.el10.3.noarch 14/150 Installing : ncurses-base-6.4-15.20240127.el10.noarch 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82/150 Installing : p11-kit-trust-0.26.4-1.el10.aarch64 83/150 Running scriptlet: p11-kit-trust-0.26.4-1.el10.aarch64 83/150 Installing : openssl-fips-provider-1:3.5.8-1.el10.aarch64 84/150 Installing : openssl-libs-1:3.5.8-1.el10.aarch64 85/150 Installing : coreutils-9.5-13.el10.aarch64 86/150 Running scriptlet: ca-certificates-2026.2.90_v9.0.316-100.0.el10.no 87/150 Installing : ca-certificates-2026.2.90_v9.0.316-100.0.el10.no 87/150 Running scriptlet: ca-certificates-2026.2.90_v9.0.316-100.0.el10.no 87/150 Installing : authselect-libs-1.5.3-1.el10.aarch64 88/150 Installing : gzip-1.13-4.el10.aarch64 89/150 Installing : cracklib-2.9.11-8.el10.aarch64 90/150 Installing : cracklib-dicts-2.9.11-8.el10.aarch64 91/150 Installing : libpwquality-1.4.5-13.el10.aarch64 92/150 Installing : libevent-2.1.12-16.el10.aarch64 93/150 Installing : rpm-sequoia-1.10.2.3-1.el10.aarch64 94/150 Installing : zip-3.0-45.el10.aarch64 95/150 Installing : cyrus-sasl-lib-2.1.28-27.el10.aarch64 96/150 Installing : openldap-2.6.13-1.el10.aarch64 97/150 Installing : gdbm-1:1.23-14.el10.aarch64 98/150 Installing : pam-1.6.1-11.el10.aarch64 99/150 Installing : libfdisk-2.40.2-20.el10.aarch64 100/150 Installing : libxml2-2.12.5-15.el10.aarch64 101/150 Installing : libarchive-3.7.7-11.el10.aarch64 102/150 Installing : bzip2-1.0.8-25.el10.aarch64 103/150 Installing : sqlite-libs-3.46.1-6.el10.aarch64 104/150 Installing : rpm-libs-4.19.1.1-25.el10.aarch64 105/150 Installing : ed-1.20-5.el10.aarch64 106/150 Installing : patch-2.7.6-26.el10.aarch64 107/150 Installing : elfutils-default-yama-scope-0.195-1.el10.noarch 108/150 Running scriptlet: elfutils-default-yama-scope-0.195-1.el10.noarch 108/150 Installing : cpio-2.15-3.el10.aarch64 109/150 Installing : diffutils-3.10-8.el10.aarch64 110/150 Installing : json-c-0.18-3.el10.aarch64 111/150 Installing : keyutils-libs-1.6.3-5.el10.aarch64 112/150 Installing : libbrotli-1.1.0-8.el10.aarch64 113/150 Installing : libcbor-0.11.0-3.el10.aarch64 114/150 Installing : libfido2-1.14.0-7.el10.aarch64 115/150 Installing : libcom_err-1.47.1-5.el10.aarch64 116/150 Installing : libgomp-14.4.1-3.el10.aarch64 117/150 Installing : libnghttp2-1.68.0-6.el10.aarch64 118/150 Installing : libpkgconf-2.1.0-3.el10.aarch64 119/150 Installing : pkgconf-2.1.0-3.el10.aarch64 120/150 Installing : pkgconf-pkg-config-2.1.0-3.el10.aarch64 121/150 Installing : libverto-0.3.2-10.el10.aarch64 122/150 Installing : krb5-libs-1.21.3-11.el10.aarch64 123/150 Installing : libssh-0.12.2-2.el10.aarch64 124/150 Installing : libcurl-8.12.1-6.el10.aarch64 125/150 Installing : elfutils-libs-0.195-1.el10.aarch64 126/150 Installing : elfutils-debuginfod-client-0.195-1.el10.aarch64 127/150 Installing : binutils-gold-2.41-66.el10.aarch64 128/150 Running scriptlet: binutils-gold-2.41-66.el10.aarch64 128/150 Installing : binutils-2.41-66.el10.aarch64 129/150 Running scriptlet: binutils-2.41-66.el10.aarch64 129/150 Installing : elfutils-0.195-1.el10.aarch64 130/150 Installing : gdb-minimal-17.2-3.1.el10.aarch64 131/150 Installing : debugedit-5.3-2.el10.aarch64 132/150 Installing : rpm-build-libs-4.19.1.1-25.el10.aarch64 133/150 Installing : curl-8.12.1-6.el10.aarch64 134/150 Running scriptlet: rpm-4.19.1.1-25.el10.aarch64 135/150 Installing : rpm-4.19.1.1-25.el10.aarch64 135/150 Installing : efi-srpm-macros-6-8.el10.noarch 136/150 Installing : lua-srpm-macros-1-15.el10.noarch 137/150 Installing : fonts-srpm-macros-1:2.0.5-18.el10.noarch 138/150 Installing : forge-srpm-macros-0.4.0-6.el10.noarch 139/150 Installing : go-srpm-macros-3.8.0-1.el10.noarch 140/150 Installing : python-srpm-macros-3.12-11.el10.noarch 141/150 Installing : redhat-rpm-config-296-1.el10.noarch 142/150 Installing : rpm-build-4.19.1.1-25.el10.aarch64 143/150 Installing : pyproject-srpm-macros-1.23.2-1.el10.noarch 144/150 Installing : R-srpm-macros-1.3.7-2.el10_3.noarch 145/150 Installing : epel-rpm-macros-10-7.el10_3.noarch 146/150 Installing : util-linux-2.40.2-20.el10.aarch64 147/150 Running scriptlet: util-linux-2.40.2-20.el10.aarch64 147/150 Installing : authselect-1.5.3-1.el10.aarch64 148/150 Installing : which-2.21-44.el10.aarch64 149/150 Installing : info-7.1-6.el10.aarch64 150/150 Running scriptlet: filesystem-3.18-17.el10.aarch64 150/150 Running scriptlet: ca-certificates-2026.2.90_v9.0.316-100.0.el10.no 150/150 Running scriptlet: authselect-libs-1.5.3-1.el10.aarch64 150/150 Running scriptlet: rpm-4.19.1.1-25.el10.aarch64 150/150 Running scriptlet: info-7.1-6.el10.aarch64 150/150 Installed: R-srpm-macros-1.3.7-2.el10_3.noarch alternatives-1.30-2.el10.aarch64 ansible-srpm-macros-1-21.el10_3.noarch audit-libs-4.2.1-3.el10.aarch64 authselect-1.5.3-1.el10.aarch64 authselect-libs-1.5.3-1.el10.aarch64 basesystem-11-22.el10.noarch bash-5.2.26-6.el10.aarch64 binutils-2.41-66.el10.aarch64 binutils-gold-2.41-66.el10.aarch64 bzip2-1.0.8-25.el10.aarch64 bzip2-libs-1.0.8-25.el10.aarch64 ca-certificates-2026.2.90_v9.0.316-100.0.el10.noarch centos-gpg-keys-10.0-23.el10.noarch centos-stream-release-10.0-23.el10.noarch centos-stream-repos-10.0-23.el10.noarch coreutils-9.5-13.el10.aarch64 coreutils-common-9.5-13.el10.aarch64 cpio-2.15-3.el10.aarch64 cracklib-2.9.11-8.el10.aarch64 cracklib-dicts-2.9.11-8.el10.aarch64 crypto-policies-20260811-1.git4dcd294.el10.noarch curl-8.12.1-6.el10.aarch64 cyrus-sasl-lib-2.1.28-27.el10.aarch64 debugedit-5.3-2.el10.aarch64 diffutils-3.10-8.el10.aarch64 dwz-0.16-1.el10.aarch64 ed-1.20-5.el10.aarch64 efi-srpm-macros-6-8.el10.noarch elfutils-0.195-1.el10.aarch64 elfutils-debuginfod-client-0.195-1.el10.aarch64 elfutils-default-yama-scope-0.195-1.el10.noarch elfutils-libelf-0.195-1.el10.aarch64 elfutils-libs-0.195-1.el10.aarch64 epel-rpm-macros-10-7.el10_3.noarch file-5.45-12.el10.aarch64 file-libs-5.45-12.el10.aarch64 filesystem-3.18-17.el10.aarch64 findutils-1:4.10.0-5.el10.aarch64 fonts-srpm-macros-1:2.0.5-18.el10.noarch forge-srpm-macros-0.4.0-6.el10.noarch fpc-srpm-macros-1.3-7.el10_1.noarch gawk-5.3.0-7.el10.aarch64 gdb-minimal-17.2-3.1.el10.aarch64 gdbm-1:1.23-14.el10.aarch64 gdbm-libs-1:1.23-14.el10.aarch64 ghc-srpm-macros-1.9.2-1.el10_0.noarch glibc-2.39-141.el10.aarch64 glibc-common-2.39-141.el10.aarch64 glibc-gconv-extra-2.39-141.el10.aarch64 glibc-minimal-langpack-2.39-141.el10.aarch64 gmp-1:6.2.1-12.el10.aarch64 go-srpm-macros-3.8.0-1.el10.noarch grep-3.11-10.el10.aarch64 gzip-1.13-4.el10.aarch64 info-7.1-6.el10.aarch64 jansson-2.14-3.el10.aarch64 json-c-0.18-3.el10.aarch64 kernel-srpm-macros-1.0-29.el10.noarch keyutils-libs-1.6.3-5.el10.aarch64 krb5-libs-1.21.3-11.el10.aarch64 libacl-2.4.0-2.el10.aarch64 libarchive-3.7.7-11.el10.aarch64 libattr-2.6.0-2.el10.aarch64 libblkid-2.40.2-20.el10.aarch64 libbrotli-1.1.0-8.el10.aarch64 libcap-2.69-7.el10.aarch64 libcap-ng-0.9.3-2.el10.aarch64 libcbor-0.11.0-3.el10.aarch64 libcom_err-1.47.1-5.el10.aarch64 libcurl-8.12.1-6.el10.aarch64 libeconf-0.6.2-4.el10.aarch64 libevent-2.1.12-16.el10.aarch64 libfdisk-2.40.2-20.el10.aarch64 libffi-3.4.4-10.el10.aarch64 libfido2-1.14.0-7.el10.aarch64 libgcc-14.4.1-3.el10.aarch64 libgomp-14.4.1-3.el10.aarch64 libidn2-2.3.7-3.el10.aarch64 libmount-2.40.2-20.el10.aarch64 libnghttp2-1.68.0-6.el10.aarch64 libpkgconf-2.1.0-3.el10.aarch64 libpsl-0.21.5-6.el10.aarch64 libpwquality-1.4.5-13.el10.aarch64 libselinux-3.11-2.el10.aarch64 libsemanage-3.11-2.el10.aarch64 libsepol-3.11-2.el10.aarch64 libsmartcols-2.40.2-20.el10.aarch64 libssh-0.12.2-2.el10.aarch64 libssh-config-0.12.2-2.el10.noarch libstdc++-14.4.1-3.el10.aarch64 libtasn1-4.20.0-5.el10.aarch64 libunistring-1.1-10.el10.aarch64 libutempter-1.2.1-15.el10.aarch64 libuuid-2.40.2-20.el10.aarch64 libverto-0.3.2-10.el10.aarch64 libxcrypt-4.4.36-10.el10.aarch64 libxml2-2.12.5-15.el10.aarch64 libzstd-1.5.5-9.el10.aarch64 lua-libs-5.4.8-1.el10.aarch64 lua-srpm-macros-1-15.el10.noarch lz4-libs-1.9.4-8.el10.aarch64 mpfr-4.2.1-8.el10.aarch64 ncurses-base-6.4-15.20240127.el10.noarch ncurses-libs-6.4-15.20240127.el10.aarch64 ocaml-srpm-macros-10-4.el10.noarch openblas-srpm-macros-2-19.el10.noarch openldap-2.6.13-1.el10.aarch64 openssl-fips-provider-1:3.5.8-1.el10.aarch64 openssl-libs-1:3.5.8-1.el10.aarch64 p11-kit-0.26.4-1.el10.aarch64 p11-kit-trust-0.26.4-1.el10.aarch64 package-notes-srpm-macros-0.5-13.el10.noarch pam-1.6.1-11.el10.aarch64 pam-libs-1.6.1-11.el10.aarch64 patch-2.7.6-26.el10.aarch64 pcre2-10.44-1.el10.3.aarch64 pcre2-syntax-10.44-1.el10.3.noarch perl-srpm-macros-1-57.el10.noarch pkgconf-2.1.0-3.el10.aarch64 pkgconf-m4-2.1.0-3.el10.noarch pkgconf-pkg-config-2.1.0-3.el10.aarch64 popt-1.19-9.el10.aarch64 publicsuffix-list-dafsa-20240107-5.el10.noarch pyproject-srpm-macros-1.23.2-1.el10.noarch python-srpm-macros-3.12-11.el10.noarch qt6-srpm-macros-6.10.1-1.el10.noarch readline-8.2-11.el10.aarch64 redhat-rpm-config-296-1.el10.noarch rpm-4.19.1.1-25.el10.aarch64 rpm-build-4.19.1.1-25.el10.aarch64 rpm-build-libs-4.19.1.1-25.el10.aarch64 rpm-libs-4.19.1.1-25.el10.aarch64 rpm-sequoia-1.10.2.3-1.el10.aarch64 rust-toolset-srpm-macros-1.97.1-4.el10.noarch sed-4.9-5.el10.aarch64 setup-2.14.5-7.el10.noarch shadow-utils-2:4.15.0-13.el10.aarch64 sqlite-libs-3.46.1-6.el10.aarch64 systemd-libs-257-33.el10.aarch64 tar-2:1.35-13.el10.aarch64 unzip-6.0-69.el10.aarch64 util-linux-2.40.2-20.el10.aarch64 util-linux-core-2.40.2-20.el10.aarch64 which-2.21-44.el10.aarch64 xz-1:5.6.2-5.el10.aarch64 xz-libs-1:5.6.2-5.el10.aarch64 zip-3.0-45.el10.aarch64 zlib-ng-compat-2.2.3-3.el10.aarch64 zstd-1.5.5-9.el10.aarch64 Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: R-srpm-macros-1.3.7-2.el10_3.noarch alternatives-1.30-2.el10.aarch64 ansible-srpm-macros-1-21.el10_3.noarch audit-libs-4.2.1-3.el10.aarch64 authselect-1.5.3-1.el10.aarch64 authselect-libs-1.5.3-1.el10.aarch64 basesystem-11-22.el10.noarch bash-5.2.26-6.el10.aarch64 binutils-2.41-66.el10.aarch64 binutils-gold-2.41-66.el10.aarch64 bzip2-1.0.8-25.el10.aarch64 bzip2-libs-1.0.8-25.el10.aarch64 ca-certificates-2026.2.90_v9.0.316-100.0.el10.noarch centos-gpg-keys-10.0-23.el10.noarch centos-stream-release-10.0-23.el10.noarch centos-stream-repos-10.0-23.el10.noarch coreutils-9.5-13.el10.aarch64 coreutils-common-9.5-13.el10.aarch64 cpio-2.15-3.el10.aarch64 cracklib-2.9.11-8.el10.aarch64 cracklib-dicts-2.9.11-8.el10.aarch64 crypto-policies-20260811-1.git4dcd294.el10.noarch curl-8.12.1-6.el10.aarch64 cyrus-sasl-lib-2.1.28-27.el10.aarch64 debugedit-5.3-2.el10.aarch64 diffutils-3.10-8.el10.aarch64 dwz-0.16-1.el10.aarch64 ed-1.20-5.el10.aarch64 efi-srpm-macros-6-8.el10.noarch elfutils-0.195-1.el10.aarch64 elfutils-debuginfod-client-0.195-1.el10.aarch64 elfutils-default-yama-scope-0.195-1.el10.noarch elfutils-libelf-0.195-1.el10.aarch64 elfutils-libs-0.195-1.el10.aarch64 epel-rpm-macros-10-7.el10_3.noarch file-5.45-12.el10.aarch64 file-libs-5.45-12.el10.aarch64 filesystem-3.18-17.el10.aarch64 findutils-4.10.0-5.el10.aarch64 fonts-srpm-macros-2.0.5-18.el10.noarch forge-srpm-macros-0.4.0-6.el10.noarch fpc-srpm-macros-1.3-7.el10_1.noarch gawk-5.3.0-7.el10.aarch64 gdb-minimal-17.2-3.1.el10.aarch64 gdbm-1.23-14.el10.aarch64 gdbm-libs-1.23-14.el10.aarch64 ghc-srpm-macros-1.9.2-1.el10_0.noarch glibc-2.39-141.el10.aarch64 glibc-common-2.39-141.el10.aarch64 glibc-gconv-extra-2.39-141.el10.aarch64 glibc-minimal-langpack-2.39-141.el10.aarch64 gmp-6.2.1-12.el10.aarch64 go-srpm-macros-3.8.0-1.el10.noarch gpg-pubkey-8483c65d-5ccc5b19 gpg-pubkey-e37ed158-65785fa9 grep-3.11-10.el10.aarch64 gzip-1.13-4.el10.aarch64 info-7.1-6.el10.aarch64 jansson-2.14-3.el10.aarch64 json-c-0.18-3.el10.aarch64 kernel-srpm-macros-1.0-29.el10.noarch keyutils-libs-1.6.3-5.el10.aarch64 krb5-libs-1.21.3-11.el10.aarch64 libacl-2.4.0-2.el10.aarch64 libarchive-3.7.7-11.el10.aarch64 libattr-2.6.0-2.el10.aarch64 libblkid-2.40.2-20.el10.aarch64 libbrotli-1.1.0-8.el10.aarch64 libcap-2.69-7.el10.aarch64 libcap-ng-0.9.3-2.el10.aarch64 libcbor-0.11.0-3.el10.aarch64 libcom_err-1.47.1-5.el10.aarch64 libcurl-8.12.1-6.el10.aarch64 libeconf-0.6.2-4.el10.aarch64 libevent-2.1.12-16.el10.aarch64 libfdisk-2.40.2-20.el10.aarch64 libffi-3.4.4-10.el10.aarch64 libfido2-1.14.0-7.el10.aarch64 libgcc-14.4.1-3.el10.aarch64 libgomp-14.4.1-3.el10.aarch64 libidn2-2.3.7-3.el10.aarch64 libmount-2.40.2-20.el10.aarch64 libnghttp2-1.68.0-6.el10.aarch64 libpkgconf-2.1.0-3.el10.aarch64 libpsl-0.21.5-6.el10.aarch64 libpwquality-1.4.5-13.el10.aarch64 libselinux-3.11-2.el10.aarch64 libsemanage-3.11-2.el10.aarch64 libsepol-3.11-2.el10.aarch64 libsmartcols-2.40.2-20.el10.aarch64 libssh-0.12.2-2.el10.aarch64 libssh-config-0.12.2-2.el10.noarch libstdc++-14.4.1-3.el10.aarch64 libtasn1-4.20.0-5.el10.aarch64 libunistring-1.1-10.el10.aarch64 libutempter-1.2.1-15.el10.aarch64 libuuid-2.40.2-20.el10.aarch64 libverto-0.3.2-10.el10.aarch64 libxcrypt-4.4.36-10.el10.aarch64 libxml2-2.12.5-15.el10.aarch64 libzstd-1.5.5-9.el10.aarch64 lua-libs-5.4.8-1.el10.aarch64 lua-srpm-macros-1-15.el10.noarch lz4-libs-1.9.4-8.el10.aarch64 mpfr-4.2.1-8.el10.aarch64 ncurses-base-6.4-15.20240127.el10.noarch ncurses-libs-6.4-15.20240127.el10.aarch64 ocaml-srpm-macros-10-4.el10.noarch openblas-srpm-macros-2-19.el10.noarch openldap-2.6.13-1.el10.aarch64 openssl-fips-provider-3.5.8-1.el10.aarch64 openssl-libs-3.5.8-1.el10.aarch64 p11-kit-0.26.4-1.el10.aarch64 p11-kit-trust-0.26.4-1.el10.aarch64 package-notes-srpm-macros-0.5-13.el10.noarch pam-1.6.1-11.el10.aarch64 pam-libs-1.6.1-11.el10.aarch64 patch-2.7.6-26.el10.aarch64 pcre2-10.44-1.el10.3.aarch64 pcre2-syntax-10.44-1.el10.3.noarch perl-srpm-macros-1-57.el10.noarch pkgconf-2.1.0-3.el10.aarch64 pkgconf-m4-2.1.0-3.el10.noarch pkgconf-pkg-config-2.1.0-3.el10.aarch64 popt-1.19-9.el10.aarch64 publicsuffix-list-dafsa-20240107-5.el10.noarch pyproject-srpm-macros-1.23.2-1.el10.noarch python-srpm-macros-3.12-11.el10.noarch qt6-srpm-macros-6.10.1-1.el10.noarch readline-8.2-11.el10.aarch64 redhat-rpm-config-296-1.el10.noarch rpm-4.19.1.1-25.el10.aarch64 rpm-build-4.19.1.1-25.el10.aarch64 rpm-build-libs-4.19.1.1-25.el10.aarch64 rpm-libs-4.19.1.1-25.el10.aarch64 rpm-sequoia-1.10.2.3-1.el10.aarch64 rust-toolset-srpm-macros-1.97.1-4.el10.noarch sed-4.9-5.el10.aarch64 setup-2.14.5-7.el10.noarch shadow-utils-4.15.0-13.el10.aarch64 sqlite-libs-3.46.1-6.el10.aarch64 systemd-libs-257-33.el10.aarch64 tar-1.35-13.el10.aarch64 unzip-6.0-69.el10.aarch64 util-linux-2.40.2-20.el10.aarch64 util-linux-core-2.40.2-20.el10.aarch64 which-2.21-44.el10.aarch64 xz-5.6.2-5.el10.aarch64 xz-libs-5.6.2-5.el10.aarch64 zip-3.0-45.el10.aarch64 zlib-ng-compat-2.2.3-3.el10.aarch64 zstd-1.5.5-9.el10.aarch64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Finish: rpmbuild -bs INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.rpm.log /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.librepo.log /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-hgt3_o0d/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(child) 0 minutes 32 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm) Config(centos-stream+epel-10-aarch64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/centos-stream+epel-10-aarch64-bootstrap-1789969169.608280/root. INFO: reusing tmpfs at /var/lib/mock/centos-stream+epel-10-aarch64-bootstrap-1789969169.608280/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.1.1-25.el10.aarch64 rpm-sequoia-1.10.2.3-1.el10.aarch64 python3-dnf-4.20.0-28.el10.noarch python3-dnf-plugins-core-4.7.0-12.el10.noarch yum-4.20.0-28.el10.noarch Finish: chroot init Start: build phase for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Start: build setup for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 18 kB/s | 1.5 kB 00:00 CentOS Stream 10 - BaseOS 95 kB/s | 5.5 kB 00:00 CentOS Stream 10 - AppStream 61 kB/s | 5.5 kB 00:00 CentOS Stream 10 - CRB 59 kB/s | 5.4 kB 00:00 CentOS Stream 10 - Extras packages 109 kB/s | 5.9 kB 00:00 Extra Packages for Enterprise Linux 10 - aarch6 91 kB/s | 8.8 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repository Size ================================================================================ Installing: git aarch64 2.52.0-1.el10 appstream 40 k python3-devel aarch64 3.12.14-1.el10 appstream 328 k python3-setuptools noarch 69.0.3-12.el10 baseos 1.6 M Installing dependencies: expat aarch64 2.7.3-2.el10 baseos 114 k git-core aarch64 2.52.0-1.el10 appstream 5.2 M git-core-doc noarch 2.52.0-1.el10 appstream 3.2 M groff-base aarch64 1.23.0-10.el10 baseos 1.1 M less aarch64 661-3.el10 baseos 191 k libedit aarch64 3.1-52.20230828cvs.el10 baseos 106 k mpdecimal aarch64 2.5.1-12.el10 baseos 90 k ncurses aarch64 6.4-15.20240127.el10 baseos 418 k openssh aarch64 9.9p1-30.el10 baseos 348 k openssh-clients aarch64 9.9p1-30.el10 baseos 745 k perl-AutoLoader noarch 5.74-515.el10 appstream 19 k perl-B aarch64 1.89-515.el10 appstream 177 k perl-Carp noarch 1.54-511.el10 baseos 30 k perl-Class-Struct noarch 0.68-515.el10 appstream 20 k perl-Data-Dumper aarch64 2.189-512.el10 baseos 56 k perl-Digest noarch 1.20-511.el10 baseos 26 k perl-Digest-MD5 aarch64 2.59-6.el10 baseos 37 k perl-DynaLoader aarch64 1.56-515.el10 appstream 24 k perl-Encode aarch64 4:3.21-511.el10 baseos 1.1 M perl-Errno aarch64 1.38-515.el10 appstream 13 k perl-Error noarch 1:0.17029-18.el10 appstream 42 k perl-Exporter noarch 5.78-511.el10 baseos 32 k perl-Fcntl aarch64 1.18-515.el10 appstream 28 k perl-File-Basename noarch 2.86-515.el10 appstream 15 k perl-File-Path noarch 2.18-512.el10 appstream 35 k perl-File-Temp noarch 1:0.231.100-512.el10 baseos 60 k perl-File-stat noarch 1.14-515.el10 appstream 15 k perl-FileHandle noarch 2.05-515.el10 appstream 14 k perl-Getopt-Long noarch 1:2.58-3.el10 baseos 65 k perl-Getopt-Std noarch 1.14-515.el10 appstream 14 k perl-Git noarch 2.52.0-1.el10 appstream 37 k perl-HTTP-Tiny noarch 0.088-512.el10 baseos 57 k perl-IO aarch64 1.55-515.el10 appstream 79 k perl-IO-Socket-IP noarch 0.42-512.el10 baseos 43 k perl-IO-Socket-SSL noarch 2.085-3.el10 baseos 227 k perl-IPC-Open3 noarch 1.22-515.el10 appstream 20 k perl-MIME-Base64 aarch64 3.16-511.el10 baseos 31 k perl-Mozilla-CA noarch 20231213-5.el10 baseos 15 k perl-Net-SSLeay aarch64 1.94-9.el10 appstream 377 k perl-POSIX aarch64 2.20-515.el10 appstream 95 k perl-PathTools aarch64 3.91-512.el10 baseos 85 k perl-Pod-Escapes noarch 1:1.07-511.el10 baseos 21 k perl-Pod-Perldoc noarch 3.28.01-512.el10 baseos 84 k perl-Pod-Simple noarch 1:3.45-511.el10 baseos 218 k perl-Pod-Usage noarch 4:2.03-511.el10 baseos 41 k perl-Scalar-List-Utils aarch64 5:1.63-511.el10 baseos 73 k perl-SelectSaver noarch 1.02-515.el10 appstream 10 k perl-Socket aarch64 4:2.038-511.el10 baseos 56 k perl-Storable aarch64 1:3.32-511.el10 baseos 98 k perl-Symbol noarch 1.09-515.el10 appstream 12 k perl-Term-ANSIColor noarch 5.01-512.el10 baseos 49 k perl-Term-Cap noarch 1.18-511.el10 baseos 23 k perl-TermReadKey aarch64 2.38-24.el10 appstream 37 k perl-Text-ParseWords noarch 3.31-511.el10 baseos 17 k perl-Text-Tabs+Wrap noarch 2024.001-511.el10 baseos 23 k perl-Time-Local noarch 2:1.350-511.el10 baseos 35 k perl-URI noarch 5.27-3.el10 baseos 134 k perl-base noarch 2.27-515.el10 appstream 14 k perl-constant noarch 1.33-512.el10 baseos 24 k perl-if noarch 0.61.000-515.el10 appstream 12 k perl-interpreter aarch64 4:5.40.2-515.el10 appstream 70 k perl-lib aarch64 0.65-515.el10 appstream 13 k perl-libnet noarch 3.15-512.el10 baseos 127 k perl-libs aarch64 4:5.40.2-515.el10 appstream 2.3 M perl-locale noarch 1.12-515.el10 appstream 12 k perl-mro aarch64 1.29-515.el10 appstream 28 k perl-overload noarch 1.37-515.el10 appstream 44 k perl-overloading noarch 0.02-515.el10 appstream 11 k perl-parent noarch 1:0.241-512.el10 baseos 16 k perl-podlators noarch 1:5.01-511.el10 baseos 124 k perl-vars noarch 1.05-515.el10 appstream 11 k python-rpm-macros noarch 3.12-11.el10 appstream 16 k python3 aarch64 3.12.14-1.el10 baseos 27 k python3-libs aarch64 3.12.14-1.el10 baseos 9.3 M python3-packaging noarch 24.2-2.el10 baseos 153 k python3-pip-wheel noarch 23.3.2-11.el10 baseos 1.5 M python3-rpm-generators noarch 14-12.el10 appstream 30 k python3-rpm-macros noarch 3.12-11.el10 appstream 11 k tzdata noarch 2026c-1.el10 baseos 904 k Transaction Summary ================================================================================ Install 82 Packages Total download size: 32 M Installed size: 128 M Downloading Packages: (1/82): expat-2.7.3-2.el10.aarch64.rpm 8.1 MB/s | 114 kB 00:00 (2/82): less-661-3.el10.aarch64.rpm 11 MB/s | 191 kB 00:00 (3/82): libedit-3.1-52.20230828cvs.el10.aarch64 27 MB/s | 106 kB 00:00 (4/82): mpdecimal-2.5.1-12.el10.aarch64.rpm 20 MB/s | 90 kB 00:00 (5/82): ncurses-6.4-15.20240127.el10.aarch64.rp 55 MB/s | 418 kB 00:00 (6/82): groff-base-1.23.0-10.el10.aarch64.rpm 39 MB/s | 1.1 MB 00:00 (7/82): openssh-9.9p1-30.el10.aarch64.rpm 49 MB/s | 348 kB 00:00 (8/82): openssh-clients-9.9p1-30.el10.aarch64.r 109 MB/s | 745 kB 00:00 (9/82): perl-Carp-1.54-511.el10.noarch.rpm 6.3 MB/s | 30 kB 00:00 (10/82): perl-Data-Dumper-2.189-512.el10.aarch6 14 MB/s | 56 kB 00:00 (11/82): perl-Digest-1.20-511.el10.noarch.rpm 8.9 MB/s | 26 kB 00:00 (12/82): perl-Digest-MD5-2.59-6.el10.aarch64.rp 11 MB/s | 37 kB 00:00 (13/82): perl-Encode-3.21-511.el10.aarch64.rpm 134 MB/s | 1.1 MB 00:00 (14/82): perl-Exporter-5.78-511.el10.noarch.rpm 5.8 MB/s | 32 kB 00:00 (15/82): perl-File-Temp-0.231.100-512.el10.noar 7.6 MB/s | 60 kB 00:00 (16/82): perl-HTTP-Tiny-0.088-512.el10.noarch.r 18 MB/s | 57 kB 00:00 (17/82): perl-Getopt-Long-2.58-3.el10.noarch.rp 17 MB/s | 65 kB 00:00 (18/82): perl-IO-Socket-IP-0.42-512.el10.noarch 14 MB/s | 43 kB 00:00 (19/82): perl-MIME-Base64-3.16-511.el10.aarch64 10 MB/s | 31 kB 00:00 (20/82): perl-IO-Socket-SSL-2.085-3.el10.noarch 53 MB/s | 227 kB 00:00 (21/82): perl-Mozilla-CA-20231213-5.el10.noarch 5.9 MB/s | 15 kB 00:00 (22/82): perl-Pod-Escapes-1.07-511.el10.noarch. 7.8 MB/s | 21 kB 00:00 (23/82): perl-PathTools-3.91-512.el10.aarch64.r 18 MB/s | 85 kB 00:00 (24/82): perl-Pod-Perldoc-3.28.01-512.el10.noar 20 MB/s | 84 kB 00:00 (25/82): perl-Pod-Simple-3.45-511.el10.noarch.r 52 MB/s | 218 kB 00:00 (26/82): perl-Pod-Usage-2.03-511.el10.noarch.rp 11 MB/s | 41 kB 00:00 (27/82): perl-Scalar-List-Utils-1.63-511.el10.a 19 MB/s | 73 kB 00:00 (28/82): perl-Socket-2.038-511.el10.aarch64.rpm 21 MB/s | 56 kB 00:00 (29/82): perl-Term-ANSIColor-5.01-512.el10.noar 16 MB/s | 49 kB 00:00 (30/82): perl-Storable-3.32-511.el10.aarch64.rp 20 MB/s | 98 kB 00:00 (31/82): perl-Term-Cap-1.18-511.el10.noarch.rpm 8.5 MB/s | 23 kB 00:00 (32/82): perl-Text-ParseWords-3.31-511.el10.noa 5.9 MB/s | 17 kB 00:00 (33/82): perl-Text-Tabs+Wrap-2024.001-511.el10. 7.9 MB/s | 23 kB 00:00 (34/82): perl-Time-Local-1.350-511.el10.noarch. 11 MB/s | 35 kB 00:00 (35/82): perl-constant-1.33-512.el10.noarch.rpm 9.3 MB/s | 24 kB 00:00 (36/82): perl-URI-5.27-3.el10.noarch.rpm 31 MB/s | 134 kB 00:00 (37/82): perl-libnet-3.15-512.el10.noarch.rpm 30 MB/s | 127 kB 00:00 (38/82): perl-parent-0.241-512.el10.noarch.rpm 5.5 MB/s | 16 kB 00:00 (39/82): python3-3.12.14-1.el10.aarch64.rpm 9.3 MB/s | 27 kB 00:00 (40/82): perl-podlators-5.01-511.el10.noarch.rp 28 MB/s | 124 kB 00:00 (41/82): python3-packaging-24.2-2.el10.noarch.r 20 MB/s | 153 kB 00:00 (42/82): python3-setuptools-69.0.3-12.el10.noar 66 MB/s | 1.6 MB 00:00 (43/82): python3-libs-3.12.14-1.el10.aarch64.rp 176 MB/s | 9.3 MB 00:00 (44/82): python3-pip-wheel-23.3.2-11.el10.noarc 28 MB/s | 1.5 MB 00:00 (45/82): tzdata-2026c-1.el10.noarch.rpm 35 MB/s | 904 kB 00:00 (46/82): git-2.52.0-1.el10.aarch64.rpm 6.0 MB/s | 40 kB 00:00 (47/82): perl-AutoLoader-5.74-515.el10.noarch.r 4.6 MB/s | 19 kB 00:00 (48/82): perl-B-1.89-515.el10.aarch64.rpm 20 MB/s | 177 kB 00:00 (49/82): git-core-doc-2.52.0-1.el10.noarch.rpm 151 MB/s | 3.2 MB 00:00 (50/82): perl-Class-Struct-0.68-515.el10.noarch 2.3 MB/s | 20 kB 00:00 (51/82): perl-DynaLoader-1.56-515.el10.aarch64. 5.9 MB/s | 24 kB 00:00 (52/82): perl-Errno-1.38-515.el10.aarch64.rpm 4.2 MB/s | 13 kB 00:00 (53/82): perl-Error-0.17029-18.el10.noarch.rpm 11 MB/s | 42 kB 00:00 (54/82): perl-Fcntl-1.18-515.el10.aarch64.rpm 7.6 MB/s | 28 kB 00:00 (55/82): perl-File-Basename-2.86-515.el10.noarc 5.9 MB/s | 15 kB 00:00 (56/82): perl-File-Path-2.18-512.el10.noarch.rp 11 MB/s | 35 kB 00:00 (57/82): perl-File-stat-1.14-515.el10.noarch.rp 6.1 MB/s | 15 kB 00:00 (58/82): perl-FileHandle-2.05-515.el10.noarch.r 5.6 MB/s | 14 kB 00:00 (59/82): perl-Getopt-Std-1.14-515.el10.noarch.r 4.5 MB/s | 14 kB 00:00 (60/82): perl-Git-2.52.0-1.el10.noarch.rpm 11 MB/s | 37 kB 00:00 (61/82): perl-IPC-Open3-1.22-515.el10.noarch.rp 6.1 MB/s | 20 kB 00:00 (62/82): perl-IO-1.55-515.el10.aarch64.rpm 16 MB/s | 79 kB 00:00 (63/82): perl-Net-SSLeay-1.94-9.el10.aarch64.rp 58 MB/s | 377 kB 00:00 (64/82): perl-POSIX-2.20-515.el10.aarch64.rpm 16 MB/s | 95 kB 00:00 (65/82): perl-SelectSaver-1.02-515.el10.noarch. 3.1 MB/s | 10 kB 00:00 (66/82): perl-Symbol-1.09-515.el10.noarch.rpm 3.9 MB/s | 12 kB 00:00 (67/82): perl-TermReadKey-2.38-24.el10.aarch64. 13 MB/s | 37 kB 00:00 (68/82): perl-base-2.27-515.el10.noarch.rpm 4.9 MB/s | 14 kB 00:00 (69/82): git-core-2.52.0-1.el10.aarch64.rpm 79 MB/s | 5.2 MB 00:00 (70/82): perl-if-0.61.000-515.el10.noarch.rpm 1.8 MB/s | 12 kB 00:00 (71/82): perl-interpreter-5.40.2-515.el10.aarch 9.6 MB/s | 70 kB 00:00 (72/82): perl-lib-0.65-515.el10.aarch64.rpm 3.9 MB/s | 13 kB 00:00 (73/82): perl-locale-1.12-515.el10.noarch.rpm 4.5 MB/s | 12 kB 00:00 (74/82): perl-mro-1.29-515.el10.aarch64.rpm 6.0 MB/s | 28 kB 00:00 (75/82): perl-overload-1.37-515.el10.noarch.rpm 7.8 MB/s | 44 kB 00:00 (76/82): perl-libs-5.40.2-515.el10.aarch64.rpm 129 MB/s | 2.3 MB 00:00 (77/82): perl-overloading-0.02-515.el10.noarch. 1.0 MB/s | 11 kB 00:00 (78/82): perl-vars-1.05-515.el10.noarch.rpm 1.2 MB/s | 11 kB 00:00 (79/82): python-rpm-macros-3.12-11.el10.noarch. 4.8 MB/s | 16 kB 00:00 (80/82): python3-rpm-generators-14-12.el10.noar 9.1 MB/s | 30 kB 00:00 (81/82): python3-devel-3.12.14-1.el10.aarch64.r 66 MB/s | 328 kB 00:00 (82/82): python3-rpm-macros-3.12-11.el10.noarch 5.2 MB/s | 11 kB 00:00 -------------------------------------------------------------------------------- Total 86 MB/s | 32 MB 00:00 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.12-11.el10.noarch 1/82 Installing : expat-2.7.3-2.el10.aarch64 2/82 Installing : python3-rpm-macros-3.12-11.el10.noarch 3/82 Installing : tzdata-2026c-1.el10.noarch 4/82 Installing : python3-pip-wheel-23.3.2-11.el10.noarch 5/82 Installing : openssh-9.9p1-30.el10.aarch64 6/82 Installing : ncurses-6.4-15.20240127.el10.aarch64 7/82 Installing : mpdecimal-2.5.1-12.el10.aarch64 8/82 Installing : python3-3.12.14-1.el10.aarch64 9/82 Installing : python3-libs-3.12.14-1.el10.aarch64 10/82 Installing : python3-packaging-24.2-2.el10.noarch 11/82 Installing : python3-rpm-generators-14-12.el10.noarch 12/82 Installing : libedit-3.1-52.20230828cvs.el10.aarch64 13/82 Installing : openssh-clients-9.9p1-30.el10.aarch64 14/82 Running scriptlet: openssh-clients-9.9p1-30.el10.aarch64 14/82 Installing : less-661-3.el10.aarch64 15/82 Installing : git-core-2.52.0-1.el10.aarch64 16/82 Installing : git-core-doc-2.52.0-1.el10.noarch 17/82 Running scriptlet: groff-base-1.23.0-10.el10.aarch64 18/82 Installing : groff-base-1.23.0-10.el10.aarch64 18/82 Running scriptlet: groff-base-1.23.0-10.el10.aarch64 18/82 Installing : perl-Digest-1.20-511.el10.noarch 19/82 Installing : perl-Digest-MD5-2.59-6.el10.aarch64 20/82 Installing : perl-B-1.89-515.el10.aarch64 21/82 Installing : perl-FileHandle-2.05-515.el10.noarch 22/82 Installing : perl-Data-Dumper-2.189-512.el10.aarch64 23/82 Installing : perl-libnet-3.15-512.el10.noarch 24/82 Installing : perl-AutoLoader-5.74-515.el10.noarch 25/82 Installing : perl-URI-5.27-3.el10.noarch 26/82 Installing : perl-Text-Tabs+Wrap-2024.001-511.el10.noarch 27/82 Installing : perl-Time-Local-2:1.350-511.el10.noarch 28/82 Installing : perl-Mozilla-CA-20231213-5.el10.noarch 29/82 Installing : perl-if-0.61.000-515.el10.noarch 30/82 Installing : perl-locale-1.12-515.el10.noarch 31/82 Installing : perl-IO-Socket-IP-0.42-512.el10.noarch 32/82 Installing : perl-Pod-Escapes-1:1.07-511.el10.noarch 33/82 Installing : perl-File-Path-2.18-512.el10.noarch 34/82 Installing : perl-IO-Socket-SSL-2.085-3.el10.noarch 35/82 Installing : perl-Net-SSLeay-1.94-9.el10.aarch64 36/82 Installing : perl-Term-ANSIColor-5.01-512.el10.noarch 37/82 Installing : perl-Class-Struct-0.68-515.el10.noarch 38/82 Installing : perl-POSIX-2.20-515.el10.aarch64 39/82 Installing : perl-IPC-Open3-1.22-515.el10.noarch 40/82 Installing : perl-Term-Cap-1.18-511.el10.noarch 41/82 Installing : perl-File-Temp-1:0.231.100-512.el10.noarch 42/82 Installing : perl-HTTP-Tiny-0.088-512.el10.noarch 43/82 Installing : perl-Pod-Simple-1:3.45-511.el10.noarch 44/82 Installing : perl-Socket-4:2.038-511.el10.aarch64 45/82 Installing : perl-SelectSaver-1.02-515.el10.noarch 46/82 Installing : perl-Symbol-1.09-515.el10.noarch 47/82 Installing : perl-File-stat-1.14-515.el10.noarch 48/82 Installing : perl-podlators-1:5.01-511.el10.noarch 49/82 Installing : perl-Pod-Perldoc-3.28.01-512.el10.noarch 50/82 Installing : perl-Text-ParseWords-3.31-511.el10.noarch 51/82 Installing : perl-Fcntl-1.18-515.el10.aarch64 52/82 Installing : perl-base-2.27-515.el10.noarch 53/82 Installing : perl-mro-1.29-515.el10.aarch64 54/82 Installing : perl-IO-1.55-515.el10.aarch64 55/82 Installing : perl-overloading-0.02-515.el10.noarch 56/82 Installing : perl-Pod-Usage-4:2.03-511.el10.noarch 57/82 Installing : perl-MIME-Base64-3.16-511.el10.aarch64 58/82 Installing : perl-Scalar-List-Utils-5:1.63-511.el10.aarch64 59/82 Installing : perl-constant-1.33-512.el10.noarch 60/82 Installing : perl-parent-1:0.241-512.el10.noarch 61/82 Installing : perl-Errno-1.38-515.el10.aarch64 62/82 Installing : perl-File-Basename-2.86-515.el10.noarch 63/82 Installing : perl-Getopt-Std-1.14-515.el10.noarch 64/82 Installing : perl-Storable-1:3.32-511.el10.aarch64 65/82 Installing : perl-overload-1.37-515.el10.noarch 66/82 Installing : perl-vars-1.05-515.el10.noarch 67/82 Installing : perl-Getopt-Long-1:2.58-3.el10.noarch 68/82 Installing : perl-Carp-1.54-511.el10.noarch 69/82 Installing : perl-Exporter-5.78-511.el10.noarch 70/82 Installing : perl-PathTools-3.91-512.el10.aarch64 71/82 Installing : perl-DynaLoader-1.56-515.el10.aarch64 72/82 Installing : perl-Encode-4:3.21-511.el10.aarch64 73/82 Installing : perl-libs-4:5.40.2-515.el10.aarch64 74/82 Installing : perl-interpreter-4:5.40.2-515.el10.aarch64 75/82 Installing : perl-Error-1:0.17029-18.el10.noarch 76/82 Installing : perl-TermReadKey-2.38-24.el10.aarch64 77/82 Installing : perl-lib-0.65-515.el10.aarch64 78/82 Installing : perl-Git-2.52.0-1.el10.noarch 79/82 Installing : git-2.52.0-1.el10.aarch64 80/82 Installing : python3-devel-3.12.14-1.el10.aarch64 81/82 Installing : python3-setuptools-69.0.3-12.el10.noarch 82/82 Running scriptlet: python3-setuptools-69.0.3-12.el10.noarch 82/82 Installed: expat-2.7.3-2.el10.aarch64 git-2.52.0-1.el10.aarch64 git-core-2.52.0-1.el10.aarch64 git-core-doc-2.52.0-1.el10.noarch groff-base-1.23.0-10.el10.aarch64 less-661-3.el10.aarch64 libedit-3.1-52.20230828cvs.el10.aarch64 mpdecimal-2.5.1-12.el10.aarch64 ncurses-6.4-15.20240127.el10.aarch64 openssh-9.9p1-30.el10.aarch64 openssh-clients-9.9p1-30.el10.aarch64 perl-AutoLoader-5.74-515.el10.noarch perl-B-1.89-515.el10.aarch64 perl-Carp-1.54-511.el10.noarch perl-Class-Struct-0.68-515.el10.noarch perl-Data-Dumper-2.189-512.el10.aarch64 perl-Digest-1.20-511.el10.noarch perl-Digest-MD5-2.59-6.el10.aarch64 perl-DynaLoader-1.56-515.el10.aarch64 perl-Encode-4:3.21-511.el10.aarch64 perl-Errno-1.38-515.el10.aarch64 perl-Error-1:0.17029-18.el10.noarch perl-Exporter-5.78-511.el10.noarch perl-Fcntl-1.18-515.el10.aarch64 perl-File-Basename-2.86-515.el10.noarch perl-File-Path-2.18-512.el10.noarch perl-File-Temp-1:0.231.100-512.el10.noarch perl-File-stat-1.14-515.el10.noarch perl-FileHandle-2.05-515.el10.noarch perl-Getopt-Long-1:2.58-3.el10.noarch perl-Getopt-Std-1.14-515.el10.noarch perl-Git-2.52.0-1.el10.noarch perl-HTTP-Tiny-0.088-512.el10.noarch perl-IO-1.55-515.el10.aarch64 perl-IO-Socket-IP-0.42-512.el10.noarch perl-IO-Socket-SSL-2.085-3.el10.noarch perl-IPC-Open3-1.22-515.el10.noarch perl-MIME-Base64-3.16-511.el10.aarch64 perl-Mozilla-CA-20231213-5.el10.noarch perl-Net-SSLeay-1.94-9.el10.aarch64 perl-POSIX-2.20-515.el10.aarch64 perl-PathTools-3.91-512.el10.aarch64 perl-Pod-Escapes-1:1.07-511.el10.noarch perl-Pod-Perldoc-3.28.01-512.el10.noarch perl-Pod-Simple-1:3.45-511.el10.noarch perl-Pod-Usage-4:2.03-511.el10.noarch perl-Scalar-List-Utils-5:1.63-511.el10.aarch64 perl-SelectSaver-1.02-515.el10.noarch perl-Socket-4:2.038-511.el10.aarch64 perl-Storable-1:3.32-511.el10.aarch64 perl-Symbol-1.09-515.el10.noarch perl-Term-ANSIColor-5.01-512.el10.noarch perl-Term-Cap-1.18-511.el10.noarch perl-TermReadKey-2.38-24.el10.aarch64 perl-Text-ParseWords-3.31-511.el10.noarch perl-Text-Tabs+Wrap-2024.001-511.el10.noarch perl-Time-Local-2:1.350-511.el10.noarch perl-URI-5.27-3.el10.noarch perl-base-2.27-515.el10.noarch perl-constant-1.33-512.el10.noarch perl-if-0.61.000-515.el10.noarch perl-interpreter-4:5.40.2-515.el10.aarch64 perl-lib-0.65-515.el10.aarch64 perl-libnet-3.15-512.el10.noarch perl-libs-4:5.40.2-515.el10.aarch64 perl-locale-1.12-515.el10.noarch perl-mro-1.29-515.el10.aarch64 perl-overload-1.37-515.el10.noarch perl-overloading-0.02-515.el10.noarch perl-parent-1:0.241-512.el10.noarch perl-podlators-1:5.01-511.el10.noarch perl-vars-1.05-515.el10.noarch python-rpm-macros-3.12-11.el10.noarch python3-3.12.14-1.el10.aarch64 python3-devel-3.12.14-1.el10.aarch64 python3-libs-3.12.14-1.el10.aarch64 python3-packaging-24.2-2.el10.noarch python3-pip-wheel-23.3.2-11.el10.noarch python3-rpm-generators-14-12.el10.noarch python3-rpm-macros-3.12-11.el10.noarch python3-setuptools-69.0.3-12.el10.noarch tzdata-2026c-1.el10.noarch Complete! Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 93 kB/s | 1.5 kB 00:00 CentOS Stream 10 - BaseOS 115 kB/s | 5.5 kB 00:00 CentOS Stream 10 - AppStream 64 kB/s | 5.5 kB 00:00 CentOS Stream 10 - CRB 110 kB/s | 5.4 kB 00:00 CentOS Stream 10 - Extras packages 58 kB/s | 5.9 kB 00:00 Extra Packages for Enterprise Linux 10 - aarch6 32 kB/s | 8.8 kB 00:00 Package git-2.52.0-1.el10.aarch64 is already installed. Package python3-devel-3.12.14-1.el10.aarch64 is already installed. Package python3-setuptools-69.0.3-12.el10.noarch is already installed. Dependencies resolved. Nothing to do. Complete! Finish: build setup for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Start: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.CJDx1f + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p litex-pythondata-cpu-cva6 + cd litex-pythondata-cpu-cva6 + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-SPECPARTS + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git . Cloning into '.'... + git fetch --depth 1 origin 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 From https://github.com/litex-hub/pythondata-cpu-cva6 * branch 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 -> FETCH_HEAD + git reset --hard 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 HEAD is now at 2b51ea6 Merge pull request #2 from shenki/update-cva6-c4c412a9 + git log --format=fuller commit 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 Author: enjoy-digital AuthorDate: Thu Sep 17 09:27:25 2026 +0200 Commit: GitHub CommitDate: Thu Sep 17 09:27:25 2026 +0200 Merge pull request #2 from shenki/update-cva6-c4c412a9 Update cva6 c4c412a9 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.7J8AwE + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_cva6 copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6 running egg_info creating pythondata_cpu_cva6.egg-info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.spyglass' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.spyglass' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.spyglass' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.spyglass' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.spyglass' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.tutorials' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.tutorials' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.tutorials' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.tutorials' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.tutorials' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util.sanitize' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util.sanitize' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util.sanitize' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util.sanitize' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util.sanitize' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.patches' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.patches' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.patches' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.patches' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.patches' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.riscv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.riscv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.riscv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.riscv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.riscv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.bsp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.bsp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.bsp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.bsp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.bsp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.regress' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.regress' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.regress' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.regress' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.regress' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.sim' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.sim' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.sim' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.sim' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.sim' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:207: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.readthedocs.yaml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ACKNOWLEDGEMENTS.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CITATION.cff -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/RESOURCES.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/SECURITY.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/verilator_config.vlt -> build/lib/pythondata_cpu_cva6/system_verilog creating build/lib/pythondata_cpu_cva6/system_verilog/.github copying pythondata_cpu_cva6/system_verilog/.github/dependabot.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github copying pythondata_cpu_cva6/system_verilog/.github/pull_request_template.md -> build/lib/pythondata_cpu_cva6/system_verilog/.github creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/1-bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/2-task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/3-other.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cva6/system_verilog/.github/actions creating build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env copying pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env/action.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts copying pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates/index.html -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/bender-up-to-date.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/dashboard-done.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier1.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier2.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-tier-dashboard.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/stale.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/verible.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/expected_synth.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example creating build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-prereq.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci creating build/lib/pythondata_cpu_cva6/system_verilog/common creating build/lib/pythondata_cpu_cva6/system_verilog/common/local creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_1rw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_wbyteenable_1rw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram_cache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper_cache_techno.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util creating build/lib/pythondata_cpu_cva6/system_verilog/config creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.rst -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/isa_template.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/spike.mako -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config copying pythondata_cpu_cva6/system_verilog/config/riscv-config/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config copying pythondata_cpu_cva6/system_verilog/config/riscv-config/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/custom_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/isa_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/platform_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/custom_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/isa_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/platform_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/custom_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/debug_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/isa_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/platform_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec creating build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cva6 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cva6_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/acc_dispatcher.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/aes.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_fpga.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_accel_first_pass_decoder_stub.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_fifo_v3.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_rvfi.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_rvfi_probes.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_compressed_if_driver.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_issue_register_commit_if_driver.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/macro_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/raw_checker.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/trigger_module.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/zcmt_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_if_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem creating build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_shared_tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir creating build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work/work.rlx -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/compressed_instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/copro_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht2lvl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend creating build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/aes_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/build_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a65x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdcv_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/dummy_l15_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/rvfi_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/triggers_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_data_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/altera.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/io_standard_constraints.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip_files.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/loc_constraints.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/search_paths.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/settings.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/u-boot-spl-dtb.hex -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints/SDC1.sdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/emif_cal.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/hps_cva6_altera.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iddr_intel.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/interconnect.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/io_pll.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iobuf.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/oddr_intel.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/test_mm_ccb_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/vJTAG.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag_tap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/nexys_video.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/agilex7.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/nexys_video.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_errno.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_io.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_time.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/cache.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dma-mapping.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dw_mmc.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dwmmc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/memalign.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/mmc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_nexys_video.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/Digilent.licence -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/EEPROM.PNG -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Gen2_wired.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/decoded_trace.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys-2.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/receiver.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src copying pythondata_cpu_cva6/system_verilog/corev_apu/src/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_gate_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs creating build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/AXI_Interface.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Cache_Control.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Performance_Counters.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV64A6_Control_Status_Registers.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVA6_user_guide.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVX_Interface_Coprocessor.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Compiler_Command_Lines.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Core_Integration.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Custom_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Interfaces.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Introduction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMA.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMP.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Parameters_Configuration.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Programmer_View.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32A.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32C.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32I.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32M.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZba.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Trigger_Module.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/rtype_format.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/user_cfg_doc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user creating build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements copying pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/cva6_requirements_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/MMU.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/LZC.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/RR.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/apb_uart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi2mem.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi_adapter.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bht2lvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bootrom.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/clint.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_hit.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dm_top_slave.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/in_out_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_control_flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_major_blocks.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/nested_translation.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic_top.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plru_tree_indexing.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw_s.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_idle.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_iptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_mis_sup.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_nlvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_flowchart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_state_diagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/replacement_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_set.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/test_harness.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/timer.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/update_tree.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/design.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/README.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_environment.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_process.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/frontendsb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/funccovresults.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/hvp.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image2.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image3.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image4.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image5.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image6.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image7.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/interrupt_uvm_agent.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparam.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparamgates.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/toggleresults.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/verif-strategy.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/README.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-edited.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures creating build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_apu.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_testharness.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/apb_uart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/ariane.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi2mem.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi_adapter.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/bootrom.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/clint.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dm_top_slave.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic_top.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/sram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/test_harness.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/timer.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/theme_overrides.css -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/common copying pythondata_cpu_cva6/system_verilog/docs/common/config_define.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/common creating build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact creating build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax creating build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design copying pythondata_cpu_cva6/system_verilog/docs/design/build.mk -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI_Interface.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CSRs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVXIF.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/architecture.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_caches.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_commit_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_controller.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_csr_regfile.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_execute.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_frontend.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_id_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_issue_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/design.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/functionality.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/glossary.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/instructions.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/intro.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/mmu.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/subsystem.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/traps.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/LZC.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/RR.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ZoominFrontend.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/caches.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_hit.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ex_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/id_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/in_out_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/issue_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/load_store_unit_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_control_flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_major_blocks.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mult_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/plru_tree_indexing.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw_s.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_idle.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_iptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_mis_sup.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_nlvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_flowchart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_state_diagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/replacement_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/schema_fsm_load_control.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_set.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/update_tree.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/build.mk -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/a-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/bfloat16.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/calling-convention.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/cmo.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/colophon.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/counters.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/d-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/f-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/hypervisor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/indirect-csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/machine.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/mm-formal.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-cfi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-csrs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-preface.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/q-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-privileged.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-unprivileged.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rnmi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv-32-64g.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv128.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv32e.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv64.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/scalar-crypto.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcdeleg.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcntrpmf.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smctr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smdbltrp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smepmp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smstateen.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sscofpmf.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ssdbltrp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sstc.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/supervisor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/unpriv-cfi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/v-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-crypto.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-examples.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zabha.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zacas.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zawrs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfa.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfh.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfinx.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zicond.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zifencei.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintntl.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintpause.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zimop.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zpm.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ztso-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images/ohg_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes/riscv-spec.yml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes creating build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide creating build/lib/pythondata_cpu_cva6/system_verilog/pd creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/isa.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/model.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/profile.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model creating build/lib/pythondata_cpu_cva6/system_verilog/spyglass copying pythondata_cpu_cva6/system_verilog/spyglass/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass copying pythondata_cpu_cva6/system_verilog/spyglass/reference_summary.rpt -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass creating build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup creating build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6.sgdc -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_waiver.awl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 creating build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/asic.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/fpga.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/running_sim.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials creating build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/flist_flattener.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/init_gate.do -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/user_config.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/vendor.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util creating build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize copying pythondata_cpu_cva6/system_verilog/util/sanitize/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize copying pythondata_cpu_cva6/system_verilog/util/sanitize/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize creating build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog/xlen_misuse.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog creating build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/gcc-cva6-tune.patch -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/get-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-13.1.0-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-14.1.0-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-master-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-18-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-master-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0001-enable-implied-B-ext.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0002-add-mstatus-UBE-bit.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/VERSION -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/typedef.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_atop_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_burst_splitter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_dst.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_src.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cut.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_delayer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_converter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_err_slv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_prepend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_remap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_serialize.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_isolate.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_iw_converter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_regs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_modify_address.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_multicut.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_serializer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_sim_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/assertions.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/registers.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/addr_decode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/binary_to_gray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cc_onehot.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_2phase.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/clk_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/delta_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_decode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_encode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_detect.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/exp_backoff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fall_through_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fifo_v3.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/gray_to_binary.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/id_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lzc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/max_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/mv_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/plru_tree.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/popcount.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/serial_deglitch.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/shift_reg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_delay.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fifo.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_omega_net.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_to_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sub_per_hash.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync_wedge.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/unread.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_LFSR_8bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo_adv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/prioarbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync_wedge.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Testbench.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run_gui.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/waves.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/expresp.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/stim.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include/assertions.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules/ClkRstGen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiBramLogger.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiToAxiLitePc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramDwc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramLogger.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramPort.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/TdpBramArray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramDwc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramPort.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/synthesize.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src/Top.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/synthesize.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_pwr_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_memory.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_rom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pad_functional.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/pad_functional_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_sram_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CONTRIBUTING.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/MANIFEST.in -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/README.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/CONTRIBUTING.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/code-doc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/new-extensions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/overview.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/quickstart.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/revisions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/riscv_config-flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/schema_custom.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/yaml-specs.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/Tall_2.png -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/custom.css -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/theme_overrides.css -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/breadcrumbs.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/layout.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/versions.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas creating build/lib/pythondata_cpu_cva6/system_verilog/verif copying pythondata_cpu_cva6/system_verilog/verif/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif copying pythondata_cpu_cva6/system_verilog/verif/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif creating build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/crt0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/useful_sites.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/vectors.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs copying pythondata_cpu_cva6/system_verilog/verif/docs/UVM_verif_env.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs copying pythondata_cpu_cva6/system_verilog/verif/docs/verif-approvals.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/interrupt-verification.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures/interrupt-ack-uvm.svg -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom/interrupt-ack-uvm.wave -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/cvxif_VP.xlsx -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/install-prerequisites.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/custom_instruction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP016.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP017.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP018.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP019.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP020.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP021.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP022.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP012.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP013.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP014.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP015.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP016.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP017.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP018.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP019.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP021.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP022.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP023.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP024.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP025.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP031.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/cva6_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_AXI.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_CVXIF.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FENCEI.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FRONTEND.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_PMP.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_traps.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status copying pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status/isacov_status.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images copying pythondata_cpu_cva6/system_verilog/verif/docs/images/CVA6_env.drawio.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6-files.f -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_asm_program_gen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_defines.svh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_ecall_instr_stream.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_illegal_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_base_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_config.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_tb_top.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_hazard_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_sequence.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_test_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_load_store_instr_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_reg_hazard_stream.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_signature_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_unsupported_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/simulator.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/cvxif_custom_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcmp_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zicond_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32x_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcmp_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zicond_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv64zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/user_define.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/x_extn_user_define.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_core_cntrl_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_env.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_prd.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_sb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_vsqr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvml_mem_vp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_ext_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_config_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_cov_model.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cvxif_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_exception_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_illegal_instr_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_interrupt_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_isa_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instruction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_block.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_file.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_predictor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_agent.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_drv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_sqr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_base_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq_item.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/benchmark.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/coremark.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cv32a6_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cv64a6_imafdc_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cvxif_verif_regression.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/debug_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone_smoke.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-csr-embedded-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-xif-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-interrupt-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-arch-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-csr-access-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-mmu-sv32-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/hwconfig_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-arch-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/iss-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/issue-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/iti_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/linux.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/pmp_cv32a65x_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-compliance.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-dv.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests-env.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-gen_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a65x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a6_imac_sv32.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a60x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a65x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/veri-testharness-pk-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/verilator-v5.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress creating build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cov-exclude-mod.lst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6-simulator.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.hvp -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6_base_testlist.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_fsdb.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_vpd.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_uvm.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/setup-env.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/Flist.cva6_tb -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/custom_uvm_macros.svh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/cva6_tb_verilator.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_core_cntrl_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_reference_model_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/cva6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components copying pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components/axi_master_connect.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/cva6_tb_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_assert.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_switch_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_axi_assert.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_default_inputs_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_csr_embedded.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_cvxif.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_hwconfig.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_interrupt.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_isacov.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_issues.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_pmp-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-rv32ima.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a6_imac_sv32.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a65x-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_marchid_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mstatus_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mvendorid_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr0_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr1_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr2_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr3_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr4_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr5_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr6_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr7_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg0_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg1_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_sstatus_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/readme.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_ro_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cva6_mscratch_csr_access.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/iti_asm.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mva01s_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mvsa01_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popret_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popretz_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_push_pop_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/readme.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/riscv_test.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/util.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/crt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_32.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_64.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/util.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/LICENSE.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_list_join.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_matrix.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_util.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark_main.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_counters_overflow.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcs_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcsi_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrst_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fields_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fullrandom_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_ro_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_unmapped_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrwi_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_add_nop.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_exc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_full.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_illegal.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_issexc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_macros.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_multi.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_nopexc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_rs3.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_s_mode.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_u_mode.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debug_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger_exception.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/single_step.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/trigger_code.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/bsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/corev_uvmt.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/crt0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link_corev-dv.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/vectors.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone_main.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/custom_test_template.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/hello_world.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt/jump_to_zero.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/branch_to_zero.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/illegal_isa.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/isa_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/jump_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_reg_hazard.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_store_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/seq_hazard.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/decreasing_entries_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/defined_matches_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/double_entries_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/exact_csrr_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/granularity_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_napot_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_tor_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_napot_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_tor_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0/return0.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params/misa_csr_we.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/macros.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_misaligned_superpage.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_nonleaf_pte.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_01.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_02.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_03.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_04.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_01.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_02.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_03.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_04.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_access.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_asid.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_mode_set.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39/noncanonical.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/etrigger_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_break_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_debug_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/itrigger_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/mcontrol6_tests.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_csrs_access.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_main.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long_ret.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_ret.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt_long.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/jvt_csr.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.dYvROH + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 --prefix /usr running install /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/jvt_csr.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt_long.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_ret.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long_ret.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_main.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_csrs_access.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/mcontrol6_tests.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/itrigger_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_debug_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_break_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/etrigger_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39/noncanonical.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_mode_set.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_asid.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_access.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_04.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_03.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_02.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_04.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_03.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_02.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_01.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_nonleaf_pte.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_misaligned_superpage.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_1.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/macros.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params/misa_csr_we.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0/return0.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_tor_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_napot_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_tor_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_napot_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/granularity_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/exact_csrr_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/double_entries_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/defined_matches_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/decreasing_entries_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/seq_hazard.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_store_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_reg_hazard.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/jump_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/isa_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/illegal_isa.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/branch_to_zero.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt/jump_to_zero.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/hello_world.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/custom_test_template.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone_main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link_corev-dv.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/handlers.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/crt0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/corev_uvmt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/bsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/trigger_code.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/test.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/single_step.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/handlers.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger_exception.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debug_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_u_mode.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_s_mode.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_rs3.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_nopexc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_multi.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_macros.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_issexc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_illegal.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_full.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_exc.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_add_nop.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrwi_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_unmapped_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_ro_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fullrandom_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fields_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrst_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcsi_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcs_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_counters_overflow.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark_main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_util.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_state.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_matrix.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_list_join.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/LICENSE.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/util.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_64.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_32.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/crt.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/util.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/riscv_test.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/readme.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_push_pop_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popretz_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popret_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mvsa01_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mva01s_test.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/iti_asm.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cva6_mscratch_csr_access.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_ro_csr_test.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/readme.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_sstatus_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg1_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg0_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr7_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr6_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr5_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr4_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr3_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr2_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr1_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr0_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mvendorid_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mstatus_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_marchid_csr_test_0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-v.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-p.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a65x-p.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a6_imac_sv32.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a65x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-rv32ima.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a65x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a60x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_pmp-cv32a65x.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_issues.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_isacov.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_interrupt.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_hwconfig.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_cvxif.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_custom.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_csr_embedded.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_default_inputs_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tdefs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_macros.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_constants.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_axi_assert.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_switch_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_assert.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/cva6_tb_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components/axi_master_connect.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/cva6.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_reference_model_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_rvfi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_core_cntrl_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/cva6_tb_verilator.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/custom_uvm_macros.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/Flist.cva6_tb -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/setup-env.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_uvm.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_vpd.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_fsdb.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_base_testlist.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.hvp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6-simulator.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cov-exclude-mod.lst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/verilator-v5.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/veri-testharness-pk-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a65x.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a60x.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a6_imac_sv32.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a65x.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-gen_tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests-env.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-dv.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-compliance.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/pmp_cv32a65x_tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/linux.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/iti_test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/issue-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/iss-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-arch-test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/hwconfig_tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-mmu-sv32-test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-csr-access-test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-arch-test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-interrupt-test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-xif-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-csr-embedded-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone_smoke.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/debug_test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cvxif_verif_regression.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cv64a6_imafdc_tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cv32a6_tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/coremark.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/benchmark.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq_item.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_base_seq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_tdefs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_sqr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_macros.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_if.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_drv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_constants.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cntxt.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_agent.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_predictor.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_file.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_block.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instruction.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_isa_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_interrupt_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_illegal_instr_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_exception_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cvxif_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_cov_model.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_config_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_ext_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_covg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvml_mem_vp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_vsqr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_tdefs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_sb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_prd.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_macros.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_env.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_core_cntrl_if.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_constants.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cntxt.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cfg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/x_extn_user_define.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/user_define.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv64zcb_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zicond_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcmp_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcb_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32x_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zicond_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcmp_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcb_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/cvxif_custom_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/simulator.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_unsupported_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_signature_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_reg_hazard_stream.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_load_store_instr_lib.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_test_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_sequence.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_hazard_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_tb_top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_config.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_base_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_illegal_instr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_ecall_instr_stream.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_defines.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_asm_program_gen.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6-files.f -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/images copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images/CVA6_env.drawio.drawio.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/images creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status/isacov_status.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP011.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP010.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP009.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP008.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP007.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_traps.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-access.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_PMP.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FRONTEND.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FENCEI.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_CVXIF.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_AXI.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/cva6_csr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP004.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP031.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP025.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP024.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP023.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP022.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP021.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP019.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP018.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP017.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP016.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP015.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP014.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP013.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP012.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP011.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP010.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP004.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP022.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP021.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP020.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP019.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP018.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP017.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP016.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP004.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/custom_instruction.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP003.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP002.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP001.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP000.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/runme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP009.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP008.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP007.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP006.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP005.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/install-prerequisites.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/cvxif_VP.xlsx -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom/interrupt-ack-uvm.wave -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures/interrupt-ack-uvm.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/interrupt-verification.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/verif-approvals.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/UVM_verif_env.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/useful_sites.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/handlers.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/crt0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_platform.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_debug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_custom.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform_checked.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa_checked.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_debug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_custom.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform_checked.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa_checked.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_debug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_custom.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/versions.html -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/layout.html -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/breadcrumbs.html -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/theme_overrides.css -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/custom.css -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/Tall_2.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/yaml-specs.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/schema_custom.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/riscv_config-flow.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/revisions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/quickstart.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/overview.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/new-extensions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/code-doc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/CONTRIBUTING.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/README.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/MANIFEST.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CONTRIBUTING.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_sram_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/pad_functional_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pad_functional.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_rom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_memory.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_pwr_cells.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/synthesize.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src/Top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/synthesize.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramPort.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramDwc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/TdpBramArray.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncTpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramPort.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramLogger.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramDwc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiToAxiLitePc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiBramLogger.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules/ClkRstGen.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include/assertions.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/stim.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/expresp.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/waves.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run_gui.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Testbench.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/sram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync_wedge.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/prioarbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo_adv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_LFSR_8bit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/find_first_one.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider_counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/unread.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync_wedge.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sub_per_hash.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_xbar.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_to_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_register.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_omega_net.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_mux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_join.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_filter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_demux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_delay.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/shift_reg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/serial_deglitch.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/popcount.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/plru_tree.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/mv_filter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/max_counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lzc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/id_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/gray_to_binary.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fifo_v3.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fall_through_register.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/exp_backoff.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_detect.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_encode.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_decode.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/delta_counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/clk_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_2phase.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cc_onehot.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/binary_to_gray.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/addr_decode.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/registers.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/assertions.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_xbar.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_test.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_sim_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_serializer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_mux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_multicut.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_modify_address.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_xbar.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_regs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_join.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_demux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_join.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_iw_converter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_isolate.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_serialize.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_remap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_prepend.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_err_slv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_converter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_demux.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_delayer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cut.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_src.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_dst.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_burst_splitter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_atop_filter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/typedef.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/assign.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/VERSION -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0002-add-mstatus-UBE-bit.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0001-enable-implied-B-ext.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.vendor.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.lock.hjson -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-master-baremetal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-18-baremetal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-master-baremetal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-14.1.0-baremetal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-13.1.0-baremetal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/get-toolchain.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/gcc-cva6-tune.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog/xlen_misuse.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize copying build/lib/pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/vendor.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/user_config.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/init_testharness.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/init_gate.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/CODEOWNERS -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/running_sim.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/fpga.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/asic.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/tutorials creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_waiver.awl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6.sgdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/reference_summary.rpt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/profile.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/model.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/isa.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes/riscv-spec.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images/ohg_logo.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ztso-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zpm.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zimop.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintpause.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintntl.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zifencei.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zicond.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfinx.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfh.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfa.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zawrs.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zacas.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zabha.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-examples.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-crypto.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/v-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/unpriv-cfi.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/supervisor.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sstc.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ssdbltrp.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sscofpmf.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smstateen.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smepmp.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smdbltrp.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smctr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcntrpmf.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcdeleg.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/scalar-crypto.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv64.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv32e.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv128.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv-32-64g.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rnmi.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-unprivileged.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-privileged.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/q-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-preface.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-csrs.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-cfi.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/mm-formal.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/machine.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/indirect-csr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/hypervisor.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/f-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/d-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/counters.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/colophon.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/cmo.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/calling-convention.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/bfloat16.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/a-st-ext.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/build.mk -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/update_tree.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_set.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_x0.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_asid.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_x0.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_asid.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/schema_fsm_load_control.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/replacement_entry.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_state_diagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_flowchart.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_1.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_nlvl.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_mis_sup.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_iptw.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_idle.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw_s.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/plru_tree_indexing.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mult_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_major_blocks.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_control_flow.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/load_store_unit_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/issue_stage_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/in_out_tlb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/id_stage_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/frontend_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ex_stage_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_hit.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_entry.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/caches.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/bht.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.drawio.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ZoominFrontend.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/RR.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/LZC.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/CVA6_subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/traps.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/subsystem.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/mmu.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/intro.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/instructions.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/glossary.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/functionality.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/design.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_issue_stage.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_id_stage.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_frontend.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_execute.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_csr_regfile.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_controller.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_commit_stage.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_caches.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/architecture.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVXIF.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CSRs.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI_Interface.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/build.mk -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr_list.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/common copying build/lib/pythondata_cpu_cva6/system_verilog/docs/common/config_define.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/theme_overrides.css -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/unpriv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/priv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/unpriv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/priv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/timer.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/test_harness.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/sram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic_top.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dm_top_slave.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/clint.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/bootrom.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi_adapter.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi2mem.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/ariane.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/apb_uart.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_testharness.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_apu.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-edited.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/README.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/verif-strategy.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/toggleresults.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparamgates.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparam.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/interrupt_uvm_agent.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image7.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image6.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image5.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image4.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image3.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image2.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image1.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/hvp.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/funccovresults.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/frontendsb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_process.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_environment.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/README.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/unpriv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/priv.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/design.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.ai -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/update_tree.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/timer.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/test_harness.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_set.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_x0.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_asid.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_x0.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_asid.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/replacement_entry.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_state_diagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_flowchart.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_1.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_nlvl.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_mis_sup.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_iptw.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_idle.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw_s.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plru_tree_indexing.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic_top.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/nested_translation.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_major_blocks.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_in_out.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_control_flow.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/logonav.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll-dark.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/in_out_tlb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dm_top_slave.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_hit.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_entry.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/clint.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bootrom.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bht2lvl.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bg.jpg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi_adapter.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi2mem.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.drawio.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/apb_uart.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/RR.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/LZC.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/pcgen_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/issue_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/if_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/id_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/ex_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/commit_stage.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/MMU.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images/cva6_scope.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/cva6_requirements_specification.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images/jade_design_automation_logo.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/user_cfg_doc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/rtype_format.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Trigger_Module.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZba.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32M.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32I.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32C.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32A.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Programmer_View.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Parameters_Configuration.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMP.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMA.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Introduction.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Interfaces.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Custom_Instructions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Core_Integration.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Compiler_Command_Lines.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVX_Interface_Coprocessor.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVA6_user_guide.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV64A6_Control_Status_Registers.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Performance_Counters.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Cache_Control.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU_list.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X_list.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX_list.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/AXI_Interface.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/axi_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_gate_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src/ariane.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/receiver.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys-2.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/decoded_trace.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Gen2_wired.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/EEPROM.PNG -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_light.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_types.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/Digilent.licence -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_nexys_video.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/mmc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/memalign.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dwmmc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dw_mmc.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dma-mapping.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/cache.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_types.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_time.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_io.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_errno.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/nexys_video.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/agilex7.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/nexys_video.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag_tap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/vJTAG.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/test_mm_ccb_0.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/oddr_intel.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iobuf.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/io_pll.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/interconnect.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iddr_intel.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/hps_cva6_altera.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/emif_cal.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints/SDC1.sdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/u-boot-spl-dtb.hex -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/settings.csv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/search_paths.csv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/loc_constraints.csv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip_files.csv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/io_standard_constraints.csv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/altera.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_data_if.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/triggers_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/rvfi_types.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/dummy_l15_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_types.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdcv_sv39_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a65x_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/build_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/aes_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht2lvl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/copro_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/compressed_instr_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work/work.rlx -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_tlb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_shared_tlb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_ptw.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_mmu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_if_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/zcmt_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/trigger_module.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/raw_checker.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/macro_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_issue_register_commit_if_driver.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_compressed_if_driver.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_rvfi_probes.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_rvfi.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_fifo_v3.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_accel_first_pass_decoder_stub.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_fpga.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/aes.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/acc_dispatcher.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cva6_gate -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cva6 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/platform_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/isa_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/debug_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/custom_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/platform_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/isa_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/custom_spec.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/platform_gen.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/isa_gen.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/custom_gen.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/spike.mako -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/isa_template.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper_cache_techno.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram_cache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_wbyteenable_1rw.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_1rw.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-toolchain.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-prereq.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/expected_synth.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/verible.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/stale.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-tier-dashboard.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier2.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier1.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/dashboard-done.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/bender-up-to-date.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates/index.html -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env copying build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env/action.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/3-other.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/2-task.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/1-bug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/pull_request_template.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github copying build/lib/pythondata_cpu_cva6/system_verilog/.github/dependabot.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github copying build/lib/pythondata_cpu_cva6/system_verilog/verilator_config.vlt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/SECURITY.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/RESOURCES.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CITATION.cff -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ACKNOWLEDGEMENTS.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.readthedocs.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py to verilator_log_to_trace_csv.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py to cva6_spike_log_to_trace_csv.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py to cva6.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py to vp_config.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py to warl.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py to utils.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py to schemaValidator.cpython-312.pyc /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: invalid escape sequence '\s' byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py to main.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py to isa_validator.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py to errors.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py to constants.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py to checker.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py to __init__.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py to setup.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/vendor.py to vendor.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/user_config.py to user_config.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py to parse_ila_trace.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py to flist_flattener.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/profile.py to profile.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/model.py to model.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/isa.py to isa.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py to cycle_diff.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py to spec_builder.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py to parameters_extractor.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py to define_blacklist.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py to classes.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py to script.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py to diff_color.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py to affiche_csv.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py to utils.cpython-312.pyc /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: invalid escape sequence '\|' byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py to spike_updater.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py to isa_updater.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py to csr_updater.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py to csr_factorizer.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py to riscv_config_gen.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py to report_tandem.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py to report_synth.cpython-312.pyc /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: invalid escape sequence '\ ' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: invalid escape sequence '\w' byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py to report_spyglass_lint.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py to report_simu.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py to report_pass.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py to report_fpga_boot.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py to report_fpga.cpython-312.pyc /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: invalid escape sequence '\|' byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py to report_fail.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py to report_envfail.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py to report_coverage.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py to report_builder.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py to report_benchmark.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py to merge_job_reports.cpython-312.pyc /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: invalid escape sequence '\w' byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py to github_integration.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py to parser.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py to generate_dashboard.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py to collect_data.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpta3zvt52.py' /usr/bin/python3 /tmp/tmpta3zvt52.py /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: invalid escape sequence '\ ' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: invalid escape sequence '\w' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: invalid escape sequence '\w' removing /tmp/tmpta3zvt52.py running install_egg_info running egg_info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6-4.2.0.post5856-py3.12.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/bin/__pycache__ + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/brp-strip-static-archive /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh from /usr/bin/env bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py from /bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 + /usr/lib/rpm/brp-remove-la-files + /usr/lib/rpm/redhat/brp-python-rpm-in-distinfo + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/lib/python3.12 using python3.12 /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: invalid escape sequence '\w' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: invalid escape sequence '\w' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: invalid escape sequence '\ ' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: invalid escape sequence '\w' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: invalid escape sequence '\ ' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: invalid escape sequence '\w' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: invalid escape sequence '\|' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: invalid escape sequence '\[' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: invalid escape sequence '\s' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: invalid escape sequence '\d' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: invalid escape sequence '\(' + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.el10.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.NC1Iv7 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + export LC_ALL= + LC_ALL= + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.LSl0j9 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + export LC_ALL= + LC_ALL= + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cva6-python3 = 2026.04-20260917.0.git2b51ea6a.el10 pythondata-cpu-cva6 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 warning: Arch dependent binaries in noarch package Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.el10.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.v0Ljy2 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.aarch64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.2X1qsT + umask 022 + cd /builddir/build/BUILD + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-SPECPARTS + rm -rf litex-pythondata-cpu-cva6 litex-pythondata-cpu-cva6.gemspec + RPM_EC=0 ++ jobs -p + exit 0 RPM build warnings: Arch dependent binaries in noarch package Finish: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm Finish: build phase for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.rpm.log /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.librepo.log /var/lib/mock/centos-stream+epel-10-aarch64-1789969169.608280/root/var/log/dnf.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.el10.src.rpm) Config(child) 0 minutes 42 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-cva6-python3", "epoch": null, "version": "2026.04", "release": "20260917.0.git2b51ea6a.el10", "arch": "noarch" }, { "name": "litex-pythondata-cpu-cva6", "epoch": null, "version": "2026.04", "release": "20260917.0.git2b51ea6a.el10", "arch": "src" } ] } RPMResults finished