%global pkgvers 1
%global scdate0 20221223
%global schash0 81838bc463d17148ef6872af34eb27585ee349ba
%global branch0 develop
%global source0 https://github.com/PyHDI/Pyverilog.git

%global sshort0 %{expand:%%{lua:print(('%{schash0}'):sub(1,8))}}

Name:           pyverilog
Version:        1.3.0
Release:        %{scdate0}.%{pkgvers}.git%{sshort0}%{?dist}
Summary:        Python-based Hardware Design Processing Toolkit for Verilog HDL
License:        Apache
BuildArch:      noarch

URL:            https://github.com/PyHDI/Pyverilog

BuildRequires:  git make python3 python3-rpm-macros python3-setuptools
BuildRequires:  python3-devel python3-pytest python3-jinja2 python3-ply iverilog

%description
Python-based Hardware Design Processing Toolkit for Verilog HDL.


%prep
%setup -T -c -n %{name}
find %{_builddir} -name SPECPARTS -exec rm -rf {} +
git clone --depth 1 -n -b %{branch0} %{source0} .
git fetch --depth 1 origin %{schash0}
git reset --hard %{schash0}
git log --format=fuller


%build
%py3_build


%install
%py3_install
rm -rf %{buildroot}/%{python3_sitelib}/tests


%check
make test


%files
%doc README.md
%license LICENSE
%doc examples
%{python3_sitelib}/*


%changelog
* Fri Feb 21 2020 Cristian Balint <cristian.balint@gmail.com>
- update github releases