Warning: Permanently added '3.216.29.240' (ED25519) to the list of known hosts. Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342025.169143 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 5.5 starting (python version = 3.12.1, NVR = mock-5.5-1.fc39), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342025.169143 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(rhel+epel-9-x86_64) Start: clean chroot Finish: clean chroot Mock Version: 5.5 INFO: Mock Version: 5.5 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/rhel+epel-9-x86_64-bootstrap-1709342025.169143/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using bootstrap image: registry.access.redhat.com/ubi9/ubi INFO: Pulling image: registry.access.redhat.com/ubi9/ubi INFO: Copy content of container registry.access.redhat.com/ubi9/ubi to /var/lib/mock/rhel+epel-9-x86_64-bootstrap-1709342025.169143/root INFO: Checking that registry.access.redhat.com/ubi9/ubi image matches host's architecture INFO: mounting registry.access.redhat.com/ubi9/ubi with podman image mount INFO: image registry.access.redhat.com/ubi9/ubi as /var/lib/containers/storage/overlay/f421bec48ce599d98007300b84ff30cbfc3349c3bd787e571f7d9bda45b8c20f/merged INFO: umounting image registry.access.redhat.com/ubi9/ubi (/var/lib/containers/storage/overlay/f421bec48ce599d98007300b84ff30cbfc3349c3bd787e571f7d9bda45b8c20f/merged) with podman image umount INFO: Package manager dnf detected and used (fallback) INFO: Not updating bootstrap chroot, bootstrap_image_ready=True Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.16.1.3-27.el9_3.x86_64 python3-dnf-4.14.0-8.el9.noarch python3-dnf-plugins-core-4.3.0-11.el9_3.noarch yum-4.14.0-8.el9.noarch Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Updating Subscription Management repositories. Unable to read consumer identity This system is not registered with an entitlement server. You can use subscription-manager to register. Copr repository 14 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 14 MB/s | 973 kB 00:00 Additional repo copr_rezso_CUDA 734 kB/s | 48 kB 00:00 Additional repo http_developer_download_nvidia_ 30 MB/s | 3.1 MB 00:00 Additional repo http_developer_download_nvidia_ 86 MB/s | 1.9 MB 00:00 Additional repo http_developer_download_nvidia_ 103 MB/s | 1.7 MB 00:00 Red Hat Enterprise Linux - BaseOS 22 MB/s | 17 MB 00:00 Red Hat Enterprise Linux - AppStream 35 MB/s | 29 MB 00:00 Red Hat Enterprise Linux - CodeReady Linux Buil 8.5 MB/s | 6.6 MB 00:00 Extra Packages for Enterprise Linux 9 - x86_64 103 MB/s | 20 MB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: bash x86_64 5.1.8-6.el9_1 baseos 1.7 M bzip2 x86_64 1.0.8-8.el9 baseos 60 k coreutils x86_64 8.32-34.el9 baseos 1.2 M cpio x86_64 2.13-16.el9 baseos 279 k diffutils x86_64 3.7-12.el9 baseos 402 k epel-rpm-macros noarch 9-13.el9 epel 15 k findutils x86_64 1:4.8.0-6.el9 baseos 550 k gawk x86_64 5.1.0-6.el9 baseos 1.0 M glibc-minimal-langpack x86_64 2.34-83.el9_3.7 baseos 37 k grep x86_64 3.6-5.el9 baseos 273 k gzip x86_64 1.12-1.el9 baseos 167 k info x86_64 6.7-15.el9 baseos 228 k patch x86_64 2.7.6-16.el9 appstream 130 k redhat-release x86_64 9.3-0.5.el9 baseos 44 k redhat-rpm-config noarch 201-1.el9 appstream 76 k rpm-build x86_64 4.16.1.3-27.el9_3 appstream 70 k sed x86_64 4.8-9.el9 baseos 309 k tar x86_64 2:1.34-6.el9_1 baseos 889 k unzip x86_64 6.0-56.el9 baseos 186 k util-linux x86_64 2.37.4-15.el9 baseos 2.3 M which x86_64 2.21-29.el9 baseos 45 k xz x86_64 5.2.5-8.el9_0 baseos 230 k Installing dependencies: alternatives x86_64 1.24-1.el9 baseos 42 k ansible-srpm-macros noarch 1-12.el9 epel 21 k audit-libs x86_64 3.0.7-104.el9 baseos 120 k basesystem noarch 11-13.el9 baseos 8.0 k binutils x86_64 2.35.2-42.el9 baseos 4.6 M binutils-gold x86_64 2.35.2-42.el9 baseos 736 k bzip2-libs x86_64 1.0.8-8.el9 baseos 42 k ca-certificates noarch 2023.2.60_v7.0.306-90.1.el9_2 baseos 846 k coreutils-common x86_64 8.32-34.el9 baseos 2.0 M cracklib x86_64 2.9.6-27.el9 baseos 99 k cracklib-dicts x86_64 2.9.6-27.el9 baseos 3.6 M crypto-policies noarch 20230731-1.git94f0e2c.el9_3.1 baseos 87 k curl x86_64 7.76.1-26.el9_3.2 baseos 298 k cyrus-sasl-lib x86_64 2.1.27-21.el9 baseos 774 k debugedit x86_64 5.0-4.el9 appstream 81 k dwz x86_64 0.14-3.el9 appstream 130 k ed x86_64 1.14.2-12.el9 baseos 78 k efi-srpm-macros noarch 6-2.el9_0 appstream 24 k elfutils x86_64 0.189-3.el9 baseos 540 k elfutils-debuginfod-client x86_64 0.189-3.el9 baseos 39 k elfutils-default-yama-scope noarch 0.189-3.el9 baseos 13 k elfutils-libelf x86_64 0.189-3.el9 baseos 196 k elfutils-libs x86_64 0.189-3.el9 baseos 258 k file x86_64 5.39-14.el9 baseos 52 k file-libs x86_64 5.39-14.el9 baseos 593 k filesystem x86_64 3.16-2.el9 baseos 4.7 M fonts-srpm-macros noarch 1:2.0.5-7.el9.1 appstream 29 k fpc-srpm-macros noarch 1.3-7.el9 epel 7.5 k gdb-minimal x86_64 10.2-11.el9 appstream 3.5 M gdbm-libs x86_64 1:1.19-4.el9 baseos 56 k ghc-srpm-macros noarch 1.5.0-6.el9 appstream 9.0 k glibc x86_64 2.34-83.el9_3.7 baseos 1.9 M glibc-common x86_64 2.34-83.el9_3.7 baseos 321 k glibc-gconv-extra x86_64 2.34-83.el9_3.7 baseos 1.7 M gmp x86_64 1:6.2.0-13.el9 baseos 319 k go-srpm-macros noarch 3.2.0-2.el9 appstream 28 k go-srpm-macros-epel noarch 3.3.0.4-1.el9 epel 26 k groff-base x86_64 1.22.4-10.el9 baseos 1.1 M kernel-srpm-macros noarch 1.0-13.el9 appstream 17 k keyutils-libs x86_64 1.6.3-1.el9 baseos 34 k krb5-libs x86_64 1.21.1-1.el9 baseos 770 k libacl x86_64 2.3.1-3.el9 baseos 26 k libarchive x86_64 3.5.3-4.el9 baseos 392 k libattr x86_64 2.5.1-3.el9 baseos 20 k libblkid x86_64 2.37.4-15.el9 baseos 110 k libbrotli x86_64 1.0.9-6.el9 baseos 317 k libcap x86_64 2.48-9.el9_2 baseos 74 k libcap-ng x86_64 0.8.2-7.el9 baseos 36 k libcom_err x86_64 1.46.5-3.el9 baseos 29 k libcurl x86_64 7.76.1-26.el9_3.2 baseos 286 k libdb x86_64 5.3.28-53.el9 baseos 740 k libeconf x86_64 0.4.1-3.el9_2 baseos 30 k libevent x86_64 2.1.12-6.el9 baseos 268 k libfdisk x86_64 2.37.4-15.el9 baseos 157 k libffi x86_64 3.4.2-8.el9 baseos 40 k libgcc x86_64 11.4.1-2.1.el9 baseos 98 k libgcrypt x86_64 1.10.0-10.el9_2 baseos 508 k libgomp x86_64 11.4.1-2.1.el9 baseos 273 k libgpg-error x86_64 1.42-5.el9 baseos 220 k libidn2 x86_64 2.3.0-7.el9 baseos 105 k libmount x86_64 2.37.4-15.el9 baseos 136 k libnghttp2 x86_64 1.43.0-5.el9_3.1 baseos 75 k libpkgconf x86_64 1.7.3-10.el9 baseos 37 k libpsl x86_64 0.21.1-5.el9 baseos 66 k libpwquality x86_64 1.4.4-8.el9 baseos 123 k libselinux x86_64 3.5-1.el9 baseos 88 k libsemanage x86_64 3.5-2.el9 baseos 121 k libsepol x86_64 3.5-1.el9 baseos 317 k libsigsegv x86_64 2.13-4.el9 baseos 30 k libsmartcols x86_64 2.37.4-15.el9 baseos 66 k libssh x86_64 0.10.4-11.el9 baseos 218 k libssh-config noarch 0.10.4-11.el9 baseos 11 k libstdc++ x86_64 11.4.1-2.1.el9 baseos 744 k libtasn1 x86_64 4.16.0-8.el9_1 baseos 77 k libunistring x86_64 0.9.10-15.el9 baseos 499 k libutempter x86_64 1.2.1-6.el9 baseos 30 k libuuid x86_64 2.37.4-15.el9 baseos 31 k libverto x86_64 0.3.2-3.el9 baseos 24 k libxcrypt x86_64 4.4.18-3.el9 baseos 120 k libxml2 x86_64 2.9.13-5.el9_3 baseos 751 k libzstd x86_64 1.5.1-2.el9 baseos 332 k lua-libs x86_64 5.4.4-4.el9 baseos 132 k lua-srpm-macros noarch 1-6.el9 appstream 10 k lz4-libs x86_64 1.9.3-5.el9 baseos 69 k mpfr x86_64 4.1.0-7.el9 baseos 329 k ncurses x86_64 6.2-10.20210508.el9 baseos 410 k ncurses-base noarch 6.2-10.20210508.el9 baseos 99 k ncurses-libs x86_64 6.2-10.20210508.el9 baseos 332 k ocaml-srpm-macros noarch 6-6.el9 appstream 9.1 k openblas-srpm-macros noarch 2-11.el9 appstream 8.6 k openldap x86_64 2.6.3-1.el9 baseos 287 k openssl x86_64 1:3.0.7-25.el9_3 baseos 1.2 M openssl-libs x86_64 1:3.0.7-25.el9_3 baseos 2.2 M p11-kit x86_64 0.24.1-2.el9 baseos 387 k p11-kit-trust x86_64 0.24.1-2.el9 baseos 148 k pam x86_64 1.5.1-15.el9 baseos 623 k pcre x86_64 8.44-3.el9.3 baseos 202 k pcre2 x86_64 10.40-2.el9 baseos 239 k pcre2-syntax noarch 10.40-2.el9 baseos 147 k perl-AutoLoader noarch 5.74-480.el9 appstream 23 k perl-B x86_64 1.80-480.el9 appstream 185 k perl-Carp noarch 1.50-460.el9 appstream 31 k perl-Class-Struct noarch 0.66-480.el9 appstream 24 k perl-Data-Dumper x86_64 2.174-462.el9 appstream 59 k perl-Digest noarch 1.19-4.el9 appstream 29 k perl-Digest-MD5 x86_64 2.58-4.el9 appstream 39 k perl-Encode x86_64 4:3.08-462.el9 appstream 1.7 M perl-Errno x86_64 1.30-480.el9 appstream 17 k perl-Exporter noarch 5.74-461.el9 appstream 34 k perl-Fcntl x86_64 1.13-480.el9 appstream 23 k perl-File-Basename noarch 2.85-480.el9 appstream 19 k perl-File-Path noarch 2.18-4.el9 appstream 38 k perl-File-Temp noarch 1:0.231.100-4.el9 appstream 63 k perl-File-stat noarch 1.09-480.el9 appstream 19 k perl-FileHandle noarch 2.03-480.el9 appstream 17 k perl-Getopt-Long noarch 1:2.52-4.el9 appstream 64 k perl-Getopt-Std noarch 1.12-480.el9 appstream 17 k perl-HTTP-Tiny noarch 0.076-461.el9 appstream 57 k perl-IO x86_64 1.43-480.el9 appstream 94 k perl-IO-Socket-IP noarch 0.41-5.el9 appstream 45 k perl-IO-Socket-SSL noarch 2.073-1.el9 appstream 223 k perl-IPC-Open3 noarch 1.21-480.el9 appstream 25 k perl-MIME-Base64 x86_64 3.16-4.el9 appstream 34 k perl-Mozilla-CA noarch 20200520-6.el9 appstream 14 k perl-Net-SSLeay x86_64 1.92-2.el9 appstream 392 k perl-POSIX x86_64 1.94-480.el9 appstream 99 k perl-PathTools x86_64 3.78-461.el9 appstream 92 k perl-Pod-Escapes noarch 1:1.07-460.el9 appstream 22 k perl-Pod-Perldoc noarch 3.28.01-461.el9 appstream 92 k perl-Pod-Simple noarch 1:3.42-4.el9 appstream 229 k perl-Pod-Usage noarch 4:2.01-4.el9 appstream 43 k perl-Scalar-List-Utils x86_64 4:1.56-461.el9 appstream 77 k perl-SelectSaver noarch 1.02-480.el9 appstream 13 k perl-Socket x86_64 4:2.031-4.el9 appstream 58 k perl-Storable x86_64 1:3.21-460.el9 appstream 98 k perl-Symbol noarch 1.08-480.el9 appstream 16 k perl-Term-ANSIColor noarch 5.01-461.el9 appstream 51 k perl-Term-Cap noarch 1.17-460.el9 appstream 24 k perl-Text-ParseWords noarch 3.30-460.el9 appstream 18 k perl-Text-Tabs+Wrap noarch 2013.0523-460.el9 appstream 25 k perl-Time-Local noarch 2:1.300-7.el9 appstream 37 k perl-URI noarch 5.09-3.el9 appstream 125 k perl-base noarch 2.27-480.el9 appstream 18 k perl-constant noarch 1.33-461.el9 appstream 25 k perl-if noarch 0.60.800-480.el9 appstream 16 k perl-interpreter x86_64 4:5.32.1-480.el9 appstream 75 k perl-libnet noarch 3.13-4.el9 appstream 134 k perl-libs x86_64 4:5.32.1-480.el9 appstream 2.2 M perl-mro x86_64 1.23-480.el9 appstream 31 k perl-overload noarch 1.31-480.el9 appstream 47 k perl-overloading noarch 0.02-480.el9 appstream 15 k perl-parent noarch 1:0.238-460.el9 appstream 16 k perl-podlators noarch 1:4.14-460.el9 appstream 118 k perl-srpm-macros noarch 1-41.el9 appstream 9.4 k perl-subs noarch 1.03-480.el9 appstream 13 k perl-vars noarch 1.05-480.el9 appstream 15 k pkgconf x86_64 1.7.3-10.el9 baseos 45 k pkgconf-m4 noarch 1.7.3-10.el9 baseos 16 k pkgconf-pkg-config x86_64 1.7.3-10.el9 baseos 12 k popt x86_64 1.18-8.el9 baseos 69 k publicsuffix-list-dafsa noarch 20210518-3.el9 baseos 59 k pyproject-srpm-macros noarch 1.9.0-1.el9 appstream 16 k python-srpm-macros noarch 3.9-52.el9 appstream 24 k qt5-srpm-macros noarch 5.15.9-1.el9 appstream 9.1 k qt6-srpm-macros noarch 6.5.2-3.el9 epel 8.9 k readline x86_64 8.1-4.el9 baseos 215 k rpm x86_64 4.16.1.3-27.el9_3 baseos 541 k rpm-build-libs x86_64 4.16.1.3-27.el9_3 baseos 90 k rpm-libs x86_64 4.16.1.3-27.el9_3 baseos 310 k rpmautospec-rpm-macros noarch 0.6.1-3.el9 epel 9.7 k rust-srpm-macros noarch 17-4.el9 appstream 11 k rust-srpm-macros-epel noarch 25.2-2.el9 epel 10 k setup noarch 2.13.7-9.el9 baseos 150 k shadow-utils x86_64 2:4.9-8.el9 baseos 1.2 M sqlite-libs x86_64 3.34.1-7.el9_3 baseos 622 k systemd-libs x86_64 252-18.el9 baseos 659 k tzdata noarch 2024a-1.el9 baseos 842 k util-linux-core x86_64 2.37.4-15.el9 baseos 466 k xz-libs x86_64 5.2.5-8.el9_0 baseos 94 k zip x86_64 3.0-35.el9 baseos 270 k zlib x86_64 1.2.11-40.el9 baseos 93 k zstd x86_64 1.5.1-2.el9 baseos 552 k Transaction Summary ================================================================================ Install 204 Packages Total download size: 67 M Installed size: 213 M Downloading Packages: (1/204): bzip2-libs-1.0.8-8.el9.x86_64.rpm 253 kB/s | 42 kB 00:00 (2/204): bzip2-1.0.8-8.el9.x86_64.rpm 333 kB/s | 60 kB 00:00 (3/204): basesystem-11-13.el9.noarch.rpm 35 kB/s | 8.0 kB 00:00 (4/204): cracklib-2.9.6-27.el9.x86_64.rpm 878 kB/s | 99 kB 00:00 (5/204): cpio-2.13-16.el9.x86_64.rpm 1.4 MB/s | 279 kB 00:00 (6/204): ed-1.14.2-12.el9.x86_64.rpm 585 kB/s | 78 kB 00:00 (7/204): grep-3.6-5.el9.x86_64.rpm 1.8 MB/s | 273 kB 00:00 (8/204): filesystem-3.16-2.el9.x86_64.rpm 18 MB/s | 4.7 MB 00:00 (9/204): groff-base-1.22.4-10.el9.x86_64.rpm 5.0 MB/s | 1.1 MB 00:00 (10/204): info-6.7-15.el9.x86_64.rpm 1.6 MB/s | 228 kB 00:00 (11/204): libacl-2.3.1-3.el9.x86_64.rpm 235 kB/s | 26 kB 00:00 (12/204): libcap-ng-0.8.2-7.el9.x86_64.rpm 406 kB/s | 36 kB 00:00 (13/204): libbrotli-1.0.9-6.el9.x86_64.rpm 2.6 MB/s | 317 kB 00:00 (14/204): libevent-2.1.12-6.el9.x86_64.rpm 2.5 MB/s | 268 kB 00:00 (15/204): libdb-5.3.28-53.el9.x86_64.rpm 6.4 MB/s | 740 kB 00:00 (16/204): libattr-2.5.1-3.el9.x86_64.rpm 63 kB/s | 20 kB 00:00 (17/204): libidn2-2.3.0-7.el9.x86_64.rpm 1.1 MB/s | 105 kB 00:00 (18/204): libgpg-error-1.42-5.el9.x86_64.rpm 1.7 MB/s | 220 kB 00:00 (19/204): libpwquality-1.4.4-8.el9.x86_64.rpm 814 kB/s | 123 kB 00:00 (20/204): libpsl-0.21.1-5.el9.x86_64.rpm 278 kB/s | 66 kB 00:00 (21/204): libsigsegv-2.13-4.el9.x86_64.rpm 171 kB/s | 30 kB 00:00 (22/204): libutempter-1.2.1-6.el9.x86_64.rpm 235 kB/s | 30 kB 00:00 (23/204): libunistring-0.9.10-15.el9.x86_64.rpm 2.9 MB/s | 499 kB 00:00 (24/204): libverto-0.3.2-3.el9.x86_64.rpm 166 kB/s | 24 kB 00:00 (25/204): libzstd-1.5.1-2.el9.x86_64.rpm 923 kB/s | 332 kB 00:00 (26/204): lz4-libs-1.9.3-5.el9.x86_64.rpm 196 kB/s | 69 kB 00:00 (27/204): libxcrypt-4.4.18-3.el9.x86_64.rpm 255 kB/s | 120 kB 00:00 (28/204): p11-kit-0.24.1-2.el9.x86_64.rpm 3.2 MB/s | 387 kB 00:00 (29/204): mpfr-4.1.0-7.el9.x86_64.rpm 2.0 MB/s | 329 kB 00:00 (30/204): pcre-8.44-3.el9.3.x86_64.rpm 1.7 MB/s | 202 kB 00:00 (31/204): publicsuffix-list-dafsa-20210518-3.el 364 kB/s | 59 kB 00:00 (32/204): popt-1.18-8.el9.x86_64.rpm 307 kB/s | 69 kB 00:00 (33/204): readline-8.1-4.el9.x86_64.rpm 1.0 MB/s | 215 kB 00:00 (34/204): unzip-6.0-56.el9.x86_64.rpm 1.3 MB/s | 186 kB 00:00 (35/204): cracklib-dicts-2.9.6-27.el9.x86_64.rp 25 MB/s | 3.6 MB 00:00 (36/204): gawk-5.1.0-6.el9.x86_64.rpm 10 MB/s | 1.0 MB 00:00 (37/204): diffutils-3.7-12.el9.x86_64.rpm 2.7 MB/s | 402 kB 00:00 (38/204): sed-4.8-9.el9.x86_64.rpm 859 kB/s | 309 kB 00:00 (39/204): libcom_err-1.46.5-3.el9.x86_64.rpm 236 kB/s | 29 kB 00:00 (40/204): gdbm-libs-1.19-4.el9.x86_64.rpm 293 kB/s | 56 kB 00:00 (41/204): p11-kit-trust-0.24.1-2.el9.x86_64.rpm 925 kB/s | 148 kB 00:00 (42/204): pcre2-syntax-10.40-2.el9.noarch.rpm 1.2 MB/s | 147 kB 00:00 (43/204): xz-5.2.5-8.el9_0.x86_64.rpm 2.0 MB/s | 230 kB 00:00 (44/204): xz-libs-5.2.5-8.el9_0.x86_64.rpm 676 kB/s | 94 kB 00:00 (45/204): zstd-1.5.1-2.el9.x86_64.rpm 2.9 MB/s | 552 kB 00:00 (46/204): bash-5.1.8-6.el9_1.x86_64.rpm 11 MB/s | 1.7 MB 00:00 (47/204): cyrus-sasl-lib-2.1.27-21.el9.x86_64.r 4.4 MB/s | 774 kB 00:00 (48/204): libselinux-3.5-1.el9.x86_64.rpm 917 kB/s | 88 kB 00:00 (49/204): gzip-1.12-1.el9.x86_64.rpm 1.3 MB/s | 167 kB 00:00 (50/204): libtasn1-4.16.0-8.el9_1.x86_64.rpm 658 kB/s | 77 kB 00:00 (51/204): pcre2-10.40-2.el9.x86_64.rpm 2.2 MB/s | 239 kB 00:00 (52/204): tar-1.34-6.el9_1.x86_64.rpm 5.9 MB/s | 889 kB 00:00 (53/204): ca-certificates-2023.2.60_v7.0.306-90 6.1 MB/s | 846 kB 00:00 (54/204): coreutils-8.32-34.el9.x86_64.rpm 8.8 MB/s | 1.2 MB 00:00 (55/204): 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epel-rpm-macros-9-13.el9.noarch.rpm 4.5 MB/s | 15 kB 00:00 (198/204): fpc-srpm-macros-1.3-7.el9.noarch.rpm 3.0 MB/s | 7.5 kB 00:00 (199/204): go-srpm-macros-epel-3.3.0.4-1.el9.no 6.7 MB/s | 26 kB 00:00 (200/204): qt6-srpm-macros-6.5.2-3.el9.noarch.r 3.0 MB/s | 8.9 kB 00:00 (201/204): rpmautospec-rpm-macros-0.6.1-3.el9.n 2.3 MB/s | 9.7 kB 00:00 (202/204): qt5-srpm-macros-5.15.9-1.el9.noarch. 87 kB/s | 9.1 kB 00:00 (203/204): rust-srpm-macros-epel-25.2-2.el9.noa 1.0 MB/s | 10 kB 00:00 (204/204): rpm-build-4.16.1.3-27.el9_3.x86_64.r 523 kB/s | 70 kB 00:00 -------------------------------------------------------------------------------- Total 6.2 MB/s | 67 MB 00:10 Red Hat Enterprise Linux - BaseOS 3.5 MB/s | 3.6 kB 00:00 Importing GPG key 0xFD431D51: Userid : "Red Hat, Inc. (release key 2) " Fingerprint: 567E 347A D004 4ADE 55BA 8A5F 199E 2F91 FD43 1D51 From : /usr/share/distribution-gpg-keys/redhat/RPM-GPG-KEY-redhat9-release Key imported successfully Importing GPG key 0x5A6340B3: Userid : "Red Hat, Inc. (auxiliary key 3) " Fingerprint: 7E46 2425 8C40 6535 D56D 6F13 5054 E4A4 5A63 40B3 From : /usr/share/distribution-gpg-keys/redhat/RPM-GPG-KEY-redhat9-release Key imported successfully Extra Packages for Enterprise Linux 9 - x86_64 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x3228467C: Userid : "Fedora (epel9) " Fingerprint: FF8A D134 4597 106E CE81 3B91 8A38 72BF 3228 467C From : /usr/share/distribution-gpg-keys/epel/RPM-GPG-KEY-EPEL-9 Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.16-2.el9.x86_64 1/1 Preparing : 1/1 Installing : libgcc-11.4.1-2.1.el9.x86_64 1/204 Running scriptlet: libgcc-11.4.1-2.1.el9.x86_64 1/204 Installing : crypto-policies-20230731-1.git94f0e2c.el9_3.1.no 2/204 Running scriptlet: crypto-policies-20230731-1.git94f0e2c.el9_3.1.no 2/204 Installing : rust-srpm-macros-17-4.el9.noarch 3/204 Installing : redhat-release-9.3-0.5.el9.x86_64 4/204 Installing : setup-2.13.7-9.el9.noarch 5/204 warning: /etc/hosts created as /etc/hosts.rpmnew Running scriptlet: setup-2.13.7-9.el9.noarch 5/204 Installing : filesystem-3.16-2.el9.x86_64 6/204 Installing : basesystem-11-13.el9.noarch 7/204 Installing : rust-srpm-macros-epel-25.2-2.el9.noarch 8/204 Installing : qt6-srpm-macros-6.5.2-3.el9.noarch 9/204 Installing : fpc-srpm-macros-1.3-7.el9.noarch 10/204 Installing : ansible-srpm-macros-1-12.el9.noarch 11/204 Installing : qt5-srpm-macros-5.15.9-1.el9.noarch 12/204 Installing : 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cracklib-dicts-2.9.6-27.el9.x86_64 36/204 Verifying : diffutils-3.7-12.el9.x86_64 37/204 Verifying : gawk-5.1.0-6.el9.x86_64 38/204 Verifying : gdbm-libs-1:1.19-4.el9.x86_64 39/204 Verifying : libcom_err-1.46.5-3.el9.x86_64 40/204 Verifying : p11-kit-trust-0.24.1-2.el9.x86_64 41/204 Verifying : pcre2-syntax-10.40-2.el9.noarch 42/204 Verifying : xz-5.2.5-8.el9_0.x86_64 43/204 Verifying : xz-libs-5.2.5-8.el9_0.x86_64 44/204 Verifying : zstd-1.5.1-2.el9.x86_64 45/204 Verifying : bash-5.1.8-6.el9_1.x86_64 46/204 Verifying : cyrus-sasl-lib-2.1.27-21.el9.x86_64 47/204 Verifying : gzip-1.12-1.el9.x86_64 48/204 Verifying : libselinux-3.5-1.el9.x86_64 49/204 Verifying : libtasn1-4.16.0-8.el9_1.x86_64 50/204 Verifying : pcre2-10.40-2.el9.x86_64 51/204 Verifying : tar-2:1.34-6.el9_1.x86_64 52/204 Verifying : ca-certificates-2023.2.60_v7.0.306-90.1.el9_2.no 53/204 Verifying : coreutils-8.32-34.el9.x86_64 54/204 Verifying : coreutils-common-8.32-34.el9.x86_64 55/204 Verifying : keyutils-libs-1.6.3-1.el9.x86_64 56/204 Verifying : libarchive-3.5.3-4.el9.x86_64 57/204 Verifying : libcap-2.48-9.el9_2.x86_64 58/204 Verifying : libeconf-0.4.1-3.el9_2.x86_64 59/204 Verifying : libgcrypt-1.10.0-10.el9_2.x86_64 60/204 Verifying : libpkgconf-1.7.3-10.el9.x86_64 61/204 Verifying : libsepol-3.5-1.el9.x86_64 62/204 Verifying : pkgconf-1.7.3-10.el9.x86_64 63/204 Verifying : pkgconf-m4-1.7.3-10.el9.noarch 64/204 Verifying : pkgconf-pkg-config-1.7.3-10.el9.x86_64 65/204 Verifying : setup-2.13.7-9.el9.noarch 66/204 Verifying : zip-3.0-35.el9.x86_64 67/204 Verifying : alternatives-1.24-1.el9.x86_64 68/204 Verifying : audit-libs-3.0.7-104.el9.x86_64 69/204 Verifying : binutils-2.35.2-42.el9.x86_64 70/204 Verifying : binutils-gold-2.35.2-42.el9.x86_64 71/204 Verifying : crypto-policies-20230731-1.git94f0e2c.el9_3.1.no 72/204 Verifying : curl-7.76.1-26.el9_3.2.x86_64 73/204 Verifying : elfutils-0.189-3.el9.x86_64 74/204 Verifying : elfutils-debuginfod-client-0.189-3.el9.x86_64 75/204 Verifying : elfutils-default-yama-scope-0.189-3.el9.noarch 76/204 Verifying : elfutils-libelf-0.189-3.el9.x86_64 77/204 Verifying : elfutils-libs-0.189-3.el9.x86_64 78/204 Verifying : file-5.39-14.el9.x86_64 79/204 Verifying : file-libs-5.39-14.el9.x86_64 80/204 Verifying : findutils-1:4.8.0-6.el9.x86_64 81/204 Verifying : glibc-2.34-83.el9_3.7.x86_64 82/204 Verifying : glibc-common-2.34-83.el9_3.7.x86_64 83/204 Verifying : glibc-gconv-extra-2.34-83.el9_3.7.x86_64 84/204 Verifying : glibc-minimal-langpack-2.34-83.el9_3.7.x86_64 85/204 Verifying : gmp-1:6.2.0-13.el9.x86_64 86/204 Verifying : krb5-libs-1.21.1-1.el9.x86_64 87/204 Verifying : libblkid-2.37.4-15.el9.x86_64 88/204 Verifying : libcurl-7.76.1-26.el9_3.2.x86_64 89/204 Verifying : libfdisk-2.37.4-15.el9.x86_64 90/204 Verifying : libffi-3.4.2-8.el9.x86_64 91/204 Verifying : libgcc-11.4.1-2.1.el9.x86_64 92/204 Verifying : libgomp-11.4.1-2.1.el9.x86_64 93/204 Verifying : libmount-2.37.4-15.el9.x86_64 94/204 Verifying : libnghttp2-1.43.0-5.el9_3.1.x86_64 95/204 Verifying : libsemanage-3.5-2.el9.x86_64 96/204 Verifying : libsmartcols-2.37.4-15.el9.x86_64 97/204 Verifying : libssh-0.10.4-11.el9.x86_64 98/204 Verifying : libssh-config-0.10.4-11.el9.noarch 99/204 Verifying : libstdc++-11.4.1-2.1.el9.x86_64 100/204 Verifying : libuuid-2.37.4-15.el9.x86_64 101/204 Verifying : lua-libs-5.4.4-4.el9.x86_64 102/204 Verifying : ncurses-6.2-10.20210508.el9.x86_64 103/204 Verifying : ncurses-base-6.2-10.20210508.el9.noarch 104/204 Verifying : ncurses-libs-6.2-10.20210508.el9.x86_64 105/204 Verifying : openldap-2.6.3-1.el9.x86_64 106/204 Verifying : pam-1.5.1-15.el9.x86_64 107/204 Verifying : redhat-release-9.3-0.5.el9.x86_64 108/204 Verifying : shadow-utils-2:4.9-8.el9.x86_64 109/204 Verifying : systemd-libs-252-18.el9.x86_64 110/204 Verifying : util-linux-2.37.4-15.el9.x86_64 111/204 Verifying : util-linux-core-2.37.4-15.el9.x86_64 112/204 Verifying : which-2.21-29.el9.x86_64 113/204 Verifying : zlib-1.2.11-40.el9.x86_64 114/204 Verifying : libxml2-2.9.13-5.el9_3.x86_64 115/204 Verifying : openssl-1:3.0.7-25.el9_3.x86_64 116/204 Verifying : openssl-libs-1:3.0.7-25.el9_3.x86_64 117/204 Verifying : rpm-4.16.1.3-27.el9_3.x86_64 118/204 Verifying : rpm-build-libs-4.16.1.3-27.el9_3.x86_64 119/204 Verifying : rpm-libs-4.16.1.3-27.el9_3.x86_64 120/204 Verifying : sqlite-libs-3.34.1-7.el9_3.x86_64 121/204 Verifying : tzdata-2024a-1.el9.noarch 122/204 Verifying : ghc-srpm-macros-1.5.0-6.el9.noarch 123/204 Verifying : lua-srpm-macros-1-6.el9.noarch 124/204 Verifying : perl-Data-Dumper-2.174-462.el9.x86_64 125/204 Verifying : perl-Digest-MD5-2.58-4.el9.x86_64 126/204 Verifying : perl-Encode-4:3.08-462.el9.x86_64 127/204 Verifying : perl-IO-Socket-SSL-2.073-1.el9.noarch 128/204 Verifying : perl-Mozilla-CA-20200520-6.el9.noarch 129/204 Verifying : perl-Pod-Simple-1:3.42-4.el9.noarch 130/204 Verifying : perl-Term-Cap-1.17-460.el9.noarch 131/204 Verifying : perl-Time-Local-2:1.300-7.el9.noarch 132/204 Verifying : rust-srpm-macros-17-4.el9.noarch 133/204 Verifying : perl-Pod-Escapes-1:1.07-460.el9.noarch 134/204 Verifying : perl-Storable-1:3.21-460.el9.x86_64 135/204 Verifying : perl-podlators-1:4.14-460.el9.noarch 136/204 Verifying : python-srpm-macros-3.9-52.el9.noarch 137/204 Verifying : dwz-0.14-3.el9.x86_64 138/204 Verifying : perl-Exporter-5.74-461.el9.noarch 139/204 Verifying : perl-File-Temp-1:0.231.100-4.el9.noarch 140/204 Verifying : perl-Getopt-Long-1:2.52-4.el9.noarch 141/204 Verifying : perl-MIME-Base64-3.16-4.el9.x86_64 142/204 Verifying : perl-Text-Tabs+Wrap-2013.0523-460.el9.noarch 143/204 Verifying : perl-parent-1:0.238-460.el9.noarch 144/204 Verifying : perl-srpm-macros-1-41.el9.noarch 145/204 Verifying : efi-srpm-macros-6-2.el9_0.noarch 146/204 Verifying : openblas-srpm-macros-2-11.el9.noarch 147/204 Verifying : perl-Digest-1.19-4.el9.noarch 148/204 Verifying : perl-File-Path-2.18-4.el9.noarch 149/204 Verifying : perl-IO-Socket-IP-0.41-5.el9.noarch 150/204 Verifying : perl-Pod-Usage-4:2.01-4.el9.noarch 151/204 Verifying : perl-Scalar-List-Utils-4:1.56-461.el9.x86_64 152/204 Verifying : perl-Socket-4:2.031-4.el9.x86_64 153/204 Verifying : perl-Term-ANSIColor-5.01-461.el9.noarch 154/204 Verifying : perl-Text-ParseWords-3.30-460.el9.noarch 155/204 Verifying : perl-URI-5.09-3.el9.noarch 156/204 Verifying : perl-constant-1.33-461.el9.noarch 157/204 Verifying : fonts-srpm-macros-1:2.0.5-7.el9.1.noarch 158/204 Verifying : ocaml-srpm-macros-6-6.el9.noarch 159/204 Verifying : patch-2.7.6-16.el9.x86_64 160/204 Verifying : perl-Pod-Perldoc-3.28.01-461.el9.noarch 161/204 Verifying : perl-libnet-3.13-4.el9.noarch 162/204 Verifying : perl-Carp-1.50-460.el9.noarch 163/204 Verifying : perl-PathTools-3.78-461.el9.x86_64 164/204 Verifying : perl-Net-SSLeay-1.92-2.el9.x86_64 165/204 Verifying : perl-AutoLoader-5.74-480.el9.noarch 166/204 Verifying : perl-B-1.80-480.el9.x86_64 167/204 Verifying : perl-Class-Struct-0.66-480.el9.noarch 168/204 Verifying : perl-Errno-1.30-480.el9.x86_64 169/204 Verifying : perl-Fcntl-1.13-480.el9.x86_64 170/204 Verifying : perl-File-Basename-2.85-480.el9.noarch 171/204 Verifying : perl-File-stat-1.09-480.el9.noarch 172/204 Verifying : perl-FileHandle-2.03-480.el9.noarch 173/204 Verifying : perl-IPC-Open3-1.21-480.el9.noarch 174/204 Verifying : perl-POSIX-1.94-480.el9.x86_64 175/204 Verifying : perl-Symbol-1.08-480.el9.noarch 176/204 Verifying : perl-interpreter-4:5.32.1-480.el9.x86_64 177/204 Verifying : perl-libs-4:5.32.1-480.el9.x86_64 178/204 Verifying : perl-mro-1.23-480.el9.x86_64 179/204 Verifying : perl-overload-1.31-480.el9.noarch 180/204 Verifying : perl-overloading-0.02-480.el9.noarch 181/204 Verifying : perl-Getopt-Std-1.12-480.el9.noarch 182/204 Verifying : perl-IO-1.43-480.el9.x86_64 183/204 Verifying : perl-SelectSaver-1.02-480.el9.noarch 184/204 Verifying : perl-base-2.27-480.el9.noarch 185/204 Verifying : perl-if-0.60.800-480.el9.noarch 186/204 Verifying : perl-subs-1.03-480.el9.noarch 187/204 Verifying : perl-vars-1.05-480.el9.noarch 188/204 Verifying : debugedit-5.0-4.el9.x86_64 189/204 Verifying : pyproject-srpm-macros-1.9.0-1.el9.noarch 190/204 Verifying : redhat-rpm-config-201-1.el9.noarch 191/204 Verifying : gdb-minimal-10.2-11.el9.x86_64 192/204 Verifying : go-srpm-macros-3.2.0-2.el9.noarch 193/204 Verifying : kernel-srpm-macros-1.0-13.el9.noarch 194/204 Verifying : perl-HTTP-Tiny-0.076-461.el9.noarch 195/204 Verifying : qt5-srpm-macros-5.15.9-1.el9.noarch 196/204 Verifying : rpm-build-4.16.1.3-27.el9_3.x86_64 197/204 Verifying : ansible-srpm-macros-1-12.el9.noarch 198/204 Verifying : epel-rpm-macros-9-13.el9.noarch 199/204 Verifying : fpc-srpm-macros-1.3-7.el9.noarch 200/204 Verifying : go-srpm-macros-epel-3.3.0.4-1.el9.noarch 201/204 Verifying : qt6-srpm-macros-6.5.2-3.el9.noarch 202/204 Verifying : rpmautospec-rpm-macros-0.6.1-3.el9.noarch 203/204 Verifying : rust-srpm-macros-epel-25.2-2.el9.noarch 204/204 Installed products updated. Installed: alternatives-1.24-1.el9.x86_64 ansible-srpm-macros-1-12.el9.noarch audit-libs-3.0.7-104.el9.x86_64 basesystem-11-13.el9.noarch bash-5.1.8-6.el9_1.x86_64 binutils-2.35.2-42.el9.x86_64 binutils-gold-2.35.2-42.el9.x86_64 bzip2-1.0.8-8.el9.x86_64 bzip2-libs-1.0.8-8.el9.x86_64 ca-certificates-2023.2.60_v7.0.306-90.1.el9_2.noarch coreutils-8.32-34.el9.x86_64 coreutils-common-8.32-34.el9.x86_64 cpio-2.13-16.el9.x86_64 cracklib-2.9.6-27.el9.x86_64 cracklib-dicts-2.9.6-27.el9.x86_64 crypto-policies-20230731-1.git94f0e2c.el9_3.1.noarch curl-7.76.1-26.el9_3.2.x86_64 cyrus-sasl-lib-2.1.27-21.el9.x86_64 debugedit-5.0-4.el9.x86_64 diffutils-3.7-12.el9.x86_64 dwz-0.14-3.el9.x86_64 ed-1.14.2-12.el9.x86_64 efi-srpm-macros-6-2.el9_0.noarch elfutils-0.189-3.el9.x86_64 elfutils-debuginfod-client-0.189-3.el9.x86_64 elfutils-default-yama-scope-0.189-3.el9.noarch elfutils-libelf-0.189-3.el9.x86_64 elfutils-libs-0.189-3.el9.x86_64 epel-rpm-macros-9-13.el9.noarch file-5.39-14.el9.x86_64 file-libs-5.39-14.el9.x86_64 filesystem-3.16-2.el9.x86_64 findutils-1:4.8.0-6.el9.x86_64 fonts-srpm-macros-1:2.0.5-7.el9.1.noarch fpc-srpm-macros-1.3-7.el9.noarch gawk-5.1.0-6.el9.x86_64 gdb-minimal-10.2-11.el9.x86_64 gdbm-libs-1:1.19-4.el9.x86_64 ghc-srpm-macros-1.5.0-6.el9.noarch glibc-2.34-83.el9_3.7.x86_64 glibc-common-2.34-83.el9_3.7.x86_64 glibc-gconv-extra-2.34-83.el9_3.7.x86_64 glibc-minimal-langpack-2.34-83.el9_3.7.x86_64 gmp-1:6.2.0-13.el9.x86_64 go-srpm-macros-3.2.0-2.el9.noarch go-srpm-macros-epel-3.3.0.4-1.el9.noarch grep-3.6-5.el9.x86_64 groff-base-1.22.4-10.el9.x86_64 gzip-1.12-1.el9.x86_64 info-6.7-15.el9.x86_64 kernel-srpm-macros-1.0-13.el9.noarch keyutils-libs-1.6.3-1.el9.x86_64 krb5-libs-1.21.1-1.el9.x86_64 libacl-2.3.1-3.el9.x86_64 libarchive-3.5.3-4.el9.x86_64 libattr-2.5.1-3.el9.x86_64 libblkid-2.37.4-15.el9.x86_64 libbrotli-1.0.9-6.el9.x86_64 libcap-2.48-9.el9_2.x86_64 libcap-ng-0.8.2-7.el9.x86_64 libcom_err-1.46.5-3.el9.x86_64 libcurl-7.76.1-26.el9_3.2.x86_64 libdb-5.3.28-53.el9.x86_64 libeconf-0.4.1-3.el9_2.x86_64 libevent-2.1.12-6.el9.x86_64 libfdisk-2.37.4-15.el9.x86_64 libffi-3.4.2-8.el9.x86_64 libgcc-11.4.1-2.1.el9.x86_64 libgcrypt-1.10.0-10.el9_2.x86_64 libgomp-11.4.1-2.1.el9.x86_64 libgpg-error-1.42-5.el9.x86_64 libidn2-2.3.0-7.el9.x86_64 libmount-2.37.4-15.el9.x86_64 libnghttp2-1.43.0-5.el9_3.1.x86_64 libpkgconf-1.7.3-10.el9.x86_64 libpsl-0.21.1-5.el9.x86_64 libpwquality-1.4.4-8.el9.x86_64 libselinux-3.5-1.el9.x86_64 libsemanage-3.5-2.el9.x86_64 libsepol-3.5-1.el9.x86_64 libsigsegv-2.13-4.el9.x86_64 libsmartcols-2.37.4-15.el9.x86_64 libssh-0.10.4-11.el9.x86_64 libssh-config-0.10.4-11.el9.noarch libstdc++-11.4.1-2.1.el9.x86_64 libtasn1-4.16.0-8.el9_1.x86_64 libunistring-0.9.10-15.el9.x86_64 libutempter-1.2.1-6.el9.x86_64 libuuid-2.37.4-15.el9.x86_64 libverto-0.3.2-3.el9.x86_64 libxcrypt-4.4.18-3.el9.x86_64 libxml2-2.9.13-5.el9_3.x86_64 libzstd-1.5.1-2.el9.x86_64 lua-libs-5.4.4-4.el9.x86_64 lua-srpm-macros-1-6.el9.noarch lz4-libs-1.9.3-5.el9.x86_64 mpfr-4.1.0-7.el9.x86_64 ncurses-6.2-10.20210508.el9.x86_64 ncurses-base-6.2-10.20210508.el9.noarch ncurses-libs-6.2-10.20210508.el9.x86_64 ocaml-srpm-macros-6-6.el9.noarch openblas-srpm-macros-2-11.el9.noarch openldap-2.6.3-1.el9.x86_64 openssl-1:3.0.7-25.el9_3.x86_64 openssl-libs-1:3.0.7-25.el9_3.x86_64 p11-kit-0.24.1-2.el9.x86_64 p11-kit-trust-0.24.1-2.el9.x86_64 pam-1.5.1-15.el9.x86_64 patch-2.7.6-16.el9.x86_64 pcre-8.44-3.el9.3.x86_64 pcre2-10.40-2.el9.x86_64 pcre2-syntax-10.40-2.el9.noarch perl-AutoLoader-5.74-480.el9.noarch perl-B-1.80-480.el9.x86_64 perl-Carp-1.50-460.el9.noarch perl-Class-Struct-0.66-480.el9.noarch perl-Data-Dumper-2.174-462.el9.x86_64 perl-Digest-1.19-4.el9.noarch perl-Digest-MD5-2.58-4.el9.x86_64 perl-Encode-4:3.08-462.el9.x86_64 perl-Errno-1.30-480.el9.x86_64 perl-Exporter-5.74-461.el9.noarch perl-Fcntl-1.13-480.el9.x86_64 perl-File-Basename-2.85-480.el9.noarch perl-File-Path-2.18-4.el9.noarch perl-File-Temp-1:0.231.100-4.el9.noarch perl-File-stat-1.09-480.el9.noarch perl-FileHandle-2.03-480.el9.noarch perl-Getopt-Long-1:2.52-4.el9.noarch perl-Getopt-Std-1.12-480.el9.noarch perl-HTTP-Tiny-0.076-461.el9.noarch perl-IO-1.43-480.el9.x86_64 perl-IO-Socket-IP-0.41-5.el9.noarch perl-IO-Socket-SSL-2.073-1.el9.noarch perl-IPC-Open3-1.21-480.el9.noarch perl-MIME-Base64-3.16-4.el9.x86_64 perl-Mozilla-CA-20200520-6.el9.noarch perl-Net-SSLeay-1.92-2.el9.x86_64 perl-POSIX-1.94-480.el9.x86_64 perl-PathTools-3.78-461.el9.x86_64 perl-Pod-Escapes-1:1.07-460.el9.noarch perl-Pod-Perldoc-3.28.01-461.el9.noarch perl-Pod-Simple-1:3.42-4.el9.noarch perl-Pod-Usage-4:2.01-4.el9.noarch perl-Scalar-List-Utils-4:1.56-461.el9.x86_64 perl-SelectSaver-1.02-480.el9.noarch perl-Socket-4:2.031-4.el9.x86_64 perl-Storable-1:3.21-460.el9.x86_64 perl-Symbol-1.08-480.el9.noarch perl-Term-ANSIColor-5.01-461.el9.noarch perl-Term-Cap-1.17-460.el9.noarch perl-Text-ParseWords-3.30-460.el9.noarch perl-Text-Tabs+Wrap-2013.0523-460.el9.noarch perl-Time-Local-2:1.300-7.el9.noarch perl-URI-5.09-3.el9.noarch perl-base-2.27-480.el9.noarch perl-constant-1.33-461.el9.noarch perl-if-0.60.800-480.el9.noarch perl-interpreter-4:5.32.1-480.el9.x86_64 perl-libnet-3.13-4.el9.noarch perl-libs-4:5.32.1-480.el9.x86_64 perl-mro-1.23-480.el9.x86_64 perl-overload-1.31-480.el9.noarch perl-overloading-0.02-480.el9.noarch perl-parent-1:0.238-460.el9.noarch perl-podlators-1:4.14-460.el9.noarch perl-srpm-macros-1-41.el9.noarch perl-subs-1.03-480.el9.noarch perl-vars-1.05-480.el9.noarch pkgconf-1.7.3-10.el9.x86_64 pkgconf-m4-1.7.3-10.el9.noarch pkgconf-pkg-config-1.7.3-10.el9.x86_64 popt-1.18-8.el9.x86_64 publicsuffix-list-dafsa-20210518-3.el9.noarch pyproject-srpm-macros-1.9.0-1.el9.noarch python-srpm-macros-3.9-52.el9.noarch qt5-srpm-macros-5.15.9-1.el9.noarch qt6-srpm-macros-6.5.2-3.el9.noarch readline-8.1-4.el9.x86_64 redhat-release-9.3-0.5.el9.x86_64 redhat-rpm-config-201-1.el9.noarch rpm-4.16.1.3-27.el9_3.x86_64 rpm-build-4.16.1.3-27.el9_3.x86_64 rpm-build-libs-4.16.1.3-27.el9_3.x86_64 rpm-libs-4.16.1.3-27.el9_3.x86_64 rpmautospec-rpm-macros-0.6.1-3.el9.noarch rust-srpm-macros-17-4.el9.noarch rust-srpm-macros-epel-25.2-2.el9.noarch sed-4.8-9.el9.x86_64 setup-2.13.7-9.el9.noarch shadow-utils-2:4.9-8.el9.x86_64 sqlite-libs-3.34.1-7.el9_3.x86_64 systemd-libs-252-18.el9.x86_64 tar-2:1.34-6.el9_1.x86_64 tzdata-2024a-1.el9.noarch unzip-6.0-56.el9.x86_64 util-linux-2.37.4-15.el9.x86_64 util-linux-core-2.37.4-15.el9.x86_64 which-2.21-29.el9.x86_64 xz-5.2.5-8.el9_0.x86_64 xz-libs-5.2.5-8.el9_0.x86_64 zip-3.0-35.el9.x86_64 zlib-1.2.11-40.el9.x86_64 zstd-1.5.1-2.el9.x86_64 Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: alternatives-1.24-1.el9.x86_64 ansible-srpm-macros-1-12.el9.noarch audit-libs-3.0.7-104.el9.x86_64 basesystem-11-13.el9.noarch bash-5.1.8-6.el9_1.x86_64 binutils-2.35.2-42.el9.x86_64 binutils-gold-2.35.2-42.el9.x86_64 bzip2-1.0.8-8.el9.x86_64 bzip2-libs-1.0.8-8.el9.x86_64 ca-certificates-2023.2.60_v7.0.306-90.1.el9_2.noarch coreutils-8.32-34.el9.x86_64 coreutils-common-8.32-34.el9.x86_64 cpio-2.13-16.el9.x86_64 cracklib-2.9.6-27.el9.x86_64 cracklib-dicts-2.9.6-27.el9.x86_64 crypto-policies-20230731-1.git94f0e2c.el9_3.1.noarch curl-7.76.1-26.el9_3.2.x86_64 cyrus-sasl-lib-2.1.27-21.el9.x86_64 debugedit-5.0-4.el9.x86_64 diffutils-3.7-12.el9.x86_64 dwz-0.14-3.el9.x86_64 ed-1.14.2-12.el9.x86_64 efi-srpm-macros-6-2.el9_0.noarch elfutils-0.189-3.el9.x86_64 elfutils-debuginfod-client-0.189-3.el9.x86_64 elfutils-default-yama-scope-0.189-3.el9.noarch elfutils-libelf-0.189-3.el9.x86_64 elfutils-libs-0.189-3.el9.x86_64 epel-rpm-macros-9-13.el9.noarch file-5.39-14.el9.x86_64 file-libs-5.39-14.el9.x86_64 filesystem-3.16-2.el9.x86_64 findutils-4.8.0-6.el9.x86_64 fonts-srpm-macros-2.0.5-7.el9.1.noarch fpc-srpm-macros-1.3-7.el9.noarch gawk-5.1.0-6.el9.x86_64 gdb-minimal-10.2-11.el9.x86_64 gdbm-libs-1.19-4.el9.x86_64 ghc-srpm-macros-1.5.0-6.el9.noarch glibc-2.34-83.el9_3.7.x86_64 glibc-common-2.34-83.el9_3.7.x86_64 glibc-gconv-extra-2.34-83.el9_3.7.x86_64 glibc-minimal-langpack-2.34-83.el9_3.7.x86_64 gmp-6.2.0-13.el9.x86_64 go-srpm-macros-3.2.0-2.el9.noarch go-srpm-macros-epel-3.3.0.4-1.el9.noarch gpg-pubkey-3228467c-613798eb gpg-pubkey-5a6340b3-6229229e gpg-pubkey-fd431d51-4ae0493b grep-3.6-5.el9.x86_64 groff-base-1.22.4-10.el9.x86_64 gzip-1.12-1.el9.x86_64 info-6.7-15.el9.x86_64 kernel-srpm-macros-1.0-13.el9.noarch keyutils-libs-1.6.3-1.el9.x86_64 krb5-libs-1.21.1-1.el9.x86_64 libacl-2.3.1-3.el9.x86_64 libarchive-3.5.3-4.el9.x86_64 libattr-2.5.1-3.el9.x86_64 libblkid-2.37.4-15.el9.x86_64 libbrotli-1.0.9-6.el9.x86_64 libcap-2.48-9.el9_2.x86_64 libcap-ng-0.8.2-7.el9.x86_64 libcom_err-1.46.5-3.el9.x86_64 libcurl-7.76.1-26.el9_3.2.x86_64 libdb-5.3.28-53.el9.x86_64 libeconf-0.4.1-3.el9_2.x86_64 libevent-2.1.12-6.el9.x86_64 libfdisk-2.37.4-15.el9.x86_64 libffi-3.4.2-8.el9.x86_64 libgcc-11.4.1-2.1.el9.x86_64 libgcrypt-1.10.0-10.el9_2.x86_64 libgomp-11.4.1-2.1.el9.x86_64 libgpg-error-1.42-5.el9.x86_64 libidn2-2.3.0-7.el9.x86_64 libmount-2.37.4-15.el9.x86_64 libnghttp2-1.43.0-5.el9_3.1.x86_64 libpkgconf-1.7.3-10.el9.x86_64 libpsl-0.21.1-5.el9.x86_64 libpwquality-1.4.4-8.el9.x86_64 libselinux-3.5-1.el9.x86_64 libsemanage-3.5-2.el9.x86_64 libsepol-3.5-1.el9.x86_64 libsigsegv-2.13-4.el9.x86_64 libsmartcols-2.37.4-15.el9.x86_64 libssh-0.10.4-11.el9.x86_64 libssh-config-0.10.4-11.el9.noarch libstdc++-11.4.1-2.1.el9.x86_64 libtasn1-4.16.0-8.el9_1.x86_64 libunistring-0.9.10-15.el9.x86_64 libutempter-1.2.1-6.el9.x86_64 libuuid-2.37.4-15.el9.x86_64 libverto-0.3.2-3.el9.x86_64 libxcrypt-4.4.18-3.el9.x86_64 libxml2-2.9.13-5.el9_3.x86_64 libzstd-1.5.1-2.el9.x86_64 lua-libs-5.4.4-4.el9.x86_64 lua-srpm-macros-1-6.el9.noarch lz4-libs-1.9.3-5.el9.x86_64 mpfr-4.1.0-7.el9.x86_64 ncurses-6.2-10.20210508.el9.x86_64 ncurses-base-6.2-10.20210508.el9.noarch ncurses-libs-6.2-10.20210508.el9.x86_64 ocaml-srpm-macros-6-6.el9.noarch openblas-srpm-macros-2-11.el9.noarch openldap-2.6.3-1.el9.x86_64 openssl-3.0.7-25.el9_3.x86_64 openssl-libs-3.0.7-25.el9_3.x86_64 p11-kit-0.24.1-2.el9.x86_64 p11-kit-trust-0.24.1-2.el9.x86_64 pam-1.5.1-15.el9.x86_64 patch-2.7.6-16.el9.x86_64 pcre-8.44-3.el9.3.x86_64 pcre2-10.40-2.el9.x86_64 pcre2-syntax-10.40-2.el9.noarch perl-AutoLoader-5.74-480.el9.noarch perl-B-1.80-480.el9.x86_64 perl-Carp-1.50-460.el9.noarch perl-Class-Struct-0.66-480.el9.noarch perl-Data-Dumper-2.174-462.el9.x86_64 perl-Digest-1.19-4.el9.noarch perl-Digest-MD5-2.58-4.el9.x86_64 perl-Encode-3.08-462.el9.x86_64 perl-Errno-1.30-480.el9.x86_64 perl-Exporter-5.74-461.el9.noarch perl-Fcntl-1.13-480.el9.x86_64 perl-File-Basename-2.85-480.el9.noarch perl-File-Path-2.18-4.el9.noarch perl-File-Temp-0.231.100-4.el9.noarch perl-File-stat-1.09-480.el9.noarch perl-FileHandle-2.03-480.el9.noarch perl-Getopt-Long-2.52-4.el9.noarch perl-Getopt-Std-1.12-480.el9.noarch perl-HTTP-Tiny-0.076-461.el9.noarch perl-IO-1.43-480.el9.x86_64 perl-IO-Socket-IP-0.41-5.el9.noarch perl-IO-Socket-SSL-2.073-1.el9.noarch perl-IPC-Open3-1.21-480.el9.noarch perl-MIME-Base64-3.16-4.el9.x86_64 perl-Mozilla-CA-20200520-6.el9.noarch perl-Net-SSLeay-1.92-2.el9.x86_64 perl-POSIX-1.94-480.el9.x86_64 perl-PathTools-3.78-461.el9.x86_64 perl-Pod-Escapes-1.07-460.el9.noarch perl-Pod-Perldoc-3.28.01-461.el9.noarch perl-Pod-Simple-3.42-4.el9.noarch perl-Pod-Usage-2.01-4.el9.noarch perl-Scalar-List-Utils-1.56-461.el9.x86_64 perl-SelectSaver-1.02-480.el9.noarch perl-Socket-2.031-4.el9.x86_64 perl-Storable-3.21-460.el9.x86_64 perl-Symbol-1.08-480.el9.noarch perl-Term-ANSIColor-5.01-461.el9.noarch perl-Term-Cap-1.17-460.el9.noarch perl-Text-ParseWords-3.30-460.el9.noarch perl-Text-Tabs+Wrap-2013.0523-460.el9.noarch perl-Time-Local-1.300-7.el9.noarch perl-URI-5.09-3.el9.noarch perl-base-2.27-480.el9.noarch perl-constant-1.33-461.el9.noarch perl-if-0.60.800-480.el9.noarch perl-interpreter-5.32.1-480.el9.x86_64 perl-libnet-3.13-4.el9.noarch perl-libs-5.32.1-480.el9.x86_64 perl-mro-1.23-480.el9.x86_64 perl-overload-1.31-480.el9.noarch perl-overloading-0.02-480.el9.noarch perl-parent-0.238-460.el9.noarch perl-podlators-4.14-460.el9.noarch perl-srpm-macros-1-41.el9.noarch perl-subs-1.03-480.el9.noarch perl-vars-1.05-480.el9.noarch pkgconf-1.7.3-10.el9.x86_64 pkgconf-m4-1.7.3-10.el9.noarch pkgconf-pkg-config-1.7.3-10.el9.x86_64 popt-1.18-8.el9.x86_64 publicsuffix-list-dafsa-20210518-3.el9.noarch pyproject-srpm-macros-1.9.0-1.el9.noarch python-srpm-macros-3.9-52.el9.noarch qt5-srpm-macros-5.15.9-1.el9.noarch qt6-srpm-macros-6.5.2-3.el9.noarch readline-8.1-4.el9.x86_64 redhat-release-9.3-0.5.el9.x86_64 redhat-rpm-config-201-1.el9.noarch rpm-4.16.1.3-27.el9_3.x86_64 rpm-build-4.16.1.3-27.el9_3.x86_64 rpm-build-libs-4.16.1.3-27.el9_3.x86_64 rpm-libs-4.16.1.3-27.el9_3.x86_64 rpmautospec-rpm-macros-0.6.1-3.el9.noarch rust-srpm-macros-17-4.el9.noarch rust-srpm-macros-epel-25.2-2.el9.noarch sed-4.8-9.el9.x86_64 setup-2.13.7-9.el9.noarch shadow-utils-4.9-8.el9.x86_64 sqlite-libs-3.34.1-7.el9_3.x86_64 systemd-libs-252-18.el9.x86_64 tar-1.34-6.el9_1.x86_64 tzdata-2024a-1.el9.noarch unzip-6.0-56.el9.x86_64 util-linux-2.37.4-15.el9.x86_64 util-linux-core-2.37.4-15.el9.x86_64 which-2.21-29.el9.x86_64 xz-5.2.5-8.el9_0.x86_64 xz-libs-5.2.5-8.el9_0.x86_64 zip-3.0-35.el9.x86_64 zlib-1.2.11-40.el9.x86_64 zstd-1.5.1-2.el9.x86_64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Finish: rpmbuild -bs cp: preserving permissions for ‘/var/lib/copr-rpmbuild/results/chroot_scan/var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log’: No such file or directory INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.rpm.log /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.librepo.log /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.log Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-exus2al0/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(child) 0 minutes 44 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm) Config(rhel+epel-9-x86_64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/rhel+epel-9-x86_64-bootstrap-1709342025.169143/root. INFO: reusing tmpfs at /var/lib/mock/rhel+epel-9-x86_64-bootstrap-1709342025.169143/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.16.1.3-27.el9_3.x86_64 python3-dnf-4.14.0-8.el9.noarch python3-dnf-plugins-core-4.3.0-11.el9_3.noarch yum-4.14.0-8.el9.noarch Finish: chroot init Start: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Start: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Updating Subscription Management repositories. Unable to read consumer identity This system is not registered with an entitlement server. You can use subscription-manager to register. Copr repository 87 kB/s | 2.1 kB 00:00 Additional repo copr_rezso_ML 77 kB/s | 1.8 kB 00:00 Additional repo copr_rezso_CUDA 77 kB/s | 1.8 kB 00:00 Additional repo http_developer_download_nvidia_ 793 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 818 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 925 kB/s | 3.5 kB 00:00 Red Hat Enterprise Linux - BaseOS 24 kB/s | 4.1 kB 00:00 Red Hat Enterprise Linux - AppStream 25 kB/s | 4.5 kB 00:00 Red Hat Enterprise Linux - CodeReady Linux Buil 25 kB/s | 4.5 kB 00:00 Extra Packages for Enterprise Linux 9 - x86_64 226 kB/s | 29 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repository Size ================================================================================ Installing: git x86_64 2.39.3-1.el9_2 appstream 66 k python3-devel x86_64 3.9.18-1.el9_3.1 appstream 249 k python3-setuptools noarch 53.0.0-12.el9 baseos 948 k Installing dependencies: emacs-filesystem noarch 1:27.2-9.el9 appstream 9.6 k expat x86_64 2.5.0-1.el9 baseos 120 k git-core x86_64 2.39.3-1.el9_2 appstream 4.3 M git-core-doc noarch 2.39.3-1.el9_2 appstream 2.9 M less x86_64 590-2.el9_2 baseos 166 k libcbor x86_64 0.7.0-5.el9 baseos 59 k libedit x86_64 3.1-38.20210216cvs.el9 baseos 107 k libfido2 x86_64 1.13.0-1.el9 baseos 101 k openssh x86_64 8.7p1-34.el9 baseos 465 k openssh-clients x86_64 8.7p1-34.el9 baseos 719 k perl-DynaLoader x86_64 1.47-480.el9 appstream 27 k perl-Error noarch 1:0.17029-7.el9 appstream 46 k perl-File-Find noarch 1.37-480.el9 appstream 27 k perl-Git noarch 2.39.3-1.el9_2 appstream 39 k perl-TermReadKey x86_64 2.38-11.el9 appstream 40 k perl-lib x86_64 0.65-480.el9 appstream 17 k pyproject-rpm-macros noarch 1.9.0-1.el9 codeready-builder 44 k python-rpm-macros noarch 3.9-52.el9 appstream 20 k python3 x86_64 3.9.18-1.el9_3.1 baseos 29 k python3-libs x86_64 3.9.18-1.el9_3.1 baseos 7.8 M python3-packaging noarch 20.9-5.el9 appstream 81 k python3-pip-wheel noarch 21.2.3-7.el9 baseos 1.1 M python3-pyparsing noarch 2.4.7-9.el9 baseos 154 k python3-rpm-generators noarch 12-8.el9 appstream 33 k python3-rpm-macros noarch 3.9-52.el9 appstream 16 k python3-setuptools-wheel noarch 53.0.0-12.el9 baseos 470 k Transaction Summary ================================================================================ Install 29 Packages Total download size: 20 M Installed size: 80 M Downloading Packages: (1/29): libcbor-0.7.0-5.el9.x86_64.rpm 259 kB/s | 59 kB 00:00 (2/29): python3-pyparsing-2.4.7-9.el9.noarch.rp 534 kB/s | 154 kB 00:00 (3/29): expat-2.5.0-1.el9.x86_64.rpm 411 kB/s | 120 kB 00:00 (4/29): less-590-2.el9_2.x86_64.rpm 782 kB/s | 166 kB 00:00 (5/29): python3-setuptools-53.0.0-12.el9.noarch 4.7 MB/s | 948 kB 00:00 (6/29): python3-setuptools-wheel-53.0.0-12.el9. 2.2 MB/s | 470 kB 00:00 (7/29): libedit-3.1-38.20210216cvs.el9.x86_64.r 869 kB/s | 107 kB 00:00 (8/29): libfido2-1.13.0-1.el9.x86_64.rpm 667 kB/s | 101 kB 00:00 (9/29): openssh-8.7p1-34.el9.x86_64.rpm 3.4 MB/s | 465 kB 00:00 (10/29): openssh-clients-8.7p1-34.el9.x86_64.rp 4.0 MB/s | 719 kB 00:00 (11/29): python3-pip-wheel-21.2.3-7.el9.noarch. 8.9 MB/s | 1.1 MB 00:00 (12/29): python3-3.9.18-1.el9_3.1.x86_64.rpm 236 kB/s | 29 kB 00:00 (13/29): perl-Error-0.17029-7.el9.noarch.rpm 304 kB/s | 46 kB 00:00 (14/29): perl-TermReadKey-2.38-11.el9.x86_64.rp 246 kB/s | 40 kB 00:00 (15/29): python3-libs-3.9.18-1.el9_3.1.x86_64.r 39 MB/s | 7.8 MB 00:00 (16/29): python3-rpm-macros-3.9-52.el9.noarch.r 131 kB/s | 16 kB 00:00 (17/29): python3-rpm-generators-12-8.el9.noarch 247 kB/s | 33 kB 00:00 (18/29): python-rpm-macros-3.9-52.el9.noarch.rp 135 kB/s | 20 kB 00:00 (19/29): perl-DynaLoader-1.47-480.el9.x86_64.rp 211 kB/s | 27 kB 00:00 (20/29): python3-packaging-20.9-5.el9.noarch.rp 415 kB/s | 81 kB 00:00 (21/29): perl-lib-0.65-480.el9.x86_64.rpm 134 kB/s | 17 kB 00:00 (22/29): perl-File-Find-1.37-480.el9.noarch.rpm 103 kB/s | 27 kB 00:00 (23/29): git-2.39.3-1.el9_2.x86_64.rpm 578 kB/s | 66 kB 00:00 (24/29): git-core-doc-2.39.3-1.el9_2.noarch.rpm 19 MB/s | 2.9 MB 00:00 (25/29): git-core-2.39.3-1.el9_2.x86_64.rpm 24 MB/s | 4.3 MB 00:00 (26/29): perl-Git-2.39.3-1.el9_2.noarch.rpm 274 kB/s | 39 kB 00:00 (27/29): emacs-filesystem-27.2-9.el9.noarch.rpm 93 kB/s | 9.6 kB 00:00 (28/29): python3-devel-3.9.18-1.el9_3.1.x86_64. 2.0 MB/s | 249 kB 00:00 (29/29): pyproject-rpm-macros-1.9.0-1.el9.noarc 311 kB/s | 44 kB 00:00 -------------------------------------------------------------------------------- Total 12 MB/s | 20 MB 00:01 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.9-52.el9.noarch 1/29 Installing : python3-rpm-macros-3.9-52.el9.noarch 2/29 Installing : expat-2.5.0-1.el9.x86_64 3/29 Installing : emacs-filesystem-1:27.2-9.el9.noarch 4/29 Installing : perl-lib-0.65-480.el9.x86_64 5/29 Installing : perl-File-Find-1.37-480.el9.noarch 6/29 Installing : perl-DynaLoader-1.47-480.el9.x86_64 7/29 Installing : perl-TermReadKey-2.38-11.el9.x86_64 8/29 Installing : perl-Error-1:0.17029-7.el9.noarch 9/29 Installing : python3-pip-wheel-21.2.3-7.el9.noarch 10/29 Running scriptlet: openssh-8.7p1-34.el9.x86_64 11/29 Installing : openssh-8.7p1-34.el9.x86_64 11/29 Installing : libedit-3.1-38.20210216cvs.el9.x86_64 12/29 Installing : python3-setuptools-wheel-53.0.0-12.el9.noarch 13/29 Installing : python3-3.9.18-1.el9_3.1.x86_64 14/29 Installing : python3-libs-3.9.18-1.el9_3.1.x86_64 15/29 Installing : python3-pyparsing-2.4.7-9.el9.noarch 16/29 Installing : python3-packaging-20.9-5.el9.noarch 17/29 Installing : python3-rpm-generators-12-8.el9.noarch 18/29 Installing : python3-setuptools-53.0.0-12.el9.noarch 19/29 Installing : less-590-2.el9_2.x86_64 20/29 Installing : libcbor-0.7.0-5.el9.x86_64 21/29 Installing : libfido2-1.13.0-1.el9.x86_64 22/29 Installing : openssh-clients-8.7p1-34.el9.x86_64 23/29 Running scriptlet: openssh-clients-8.7p1-34.el9.x86_64 23/29 Installing : git-core-2.39.3-1.el9_2.x86_64 24/29 Installing : git-core-doc-2.39.3-1.el9_2.noarch 25/29 Installing : perl-Git-2.39.3-1.el9_2.noarch 26/29 Installing : git-2.39.3-1.el9_2.x86_64 27/29 Installing : python3-devel-3.9.18-1.el9_3.1.x86_64 28/29 Installing : pyproject-rpm-macros-1.9.0-1.el9.noarch 29/29 Running scriptlet: pyproject-rpm-macros-1.9.0-1.el9.noarch 29/29 Verifying : python3-pyparsing-2.4.7-9.el9.noarch 1/29 Verifying : libcbor-0.7.0-5.el9.x86_64 2/29 Verifying : expat-2.5.0-1.el9.x86_64 3/29 Verifying : less-590-2.el9_2.x86_64 4/29 Verifying : python3-setuptools-53.0.0-12.el9.noarch 5/29 Verifying : python3-setuptools-wheel-53.0.0-12.el9.noarch 6/29 Verifying : libedit-3.1-38.20210216cvs.el9.x86_64 7/29 Verifying : libfido2-1.13.0-1.el9.x86_64 8/29 Verifying : openssh-8.7p1-34.el9.x86_64 9/29 Verifying : openssh-clients-8.7p1-34.el9.x86_64 10/29 Verifying : python3-pip-wheel-21.2.3-7.el9.noarch 11/29 Verifying : python3-3.9.18-1.el9_3.1.x86_64 12/29 Verifying : python3-libs-3.9.18-1.el9_3.1.x86_64 13/29 Verifying : perl-Error-1:0.17029-7.el9.noarch 14/29 Verifying : perl-TermReadKey-2.38-11.el9.x86_64 15/29 Verifying : python-rpm-macros-3.9-52.el9.noarch 16/29 Verifying : python3-rpm-generators-12-8.el9.noarch 17/29 Verifying : python3-rpm-macros-3.9-52.el9.noarch 18/29 Verifying : python3-packaging-20.9-5.el9.noarch 19/29 Verifying : perl-DynaLoader-1.47-480.el9.x86_64 20/29 Verifying : perl-File-Find-1.37-480.el9.noarch 21/29 Verifying : perl-lib-0.65-480.el9.x86_64 22/29 Verifying : git-2.39.3-1.el9_2.x86_64 23/29 Verifying : git-core-2.39.3-1.el9_2.x86_64 24/29 Verifying : git-core-doc-2.39.3-1.el9_2.noarch 25/29 Verifying : perl-Git-2.39.3-1.el9_2.noarch 26/29 Verifying : emacs-filesystem-1:27.2-9.el9.noarch 27/29 Verifying : python3-devel-3.9.18-1.el9_3.1.x86_64 28/29 Verifying : pyproject-rpm-macros-1.9.0-1.el9.noarch 29/29 Installed products updated. Installed: emacs-filesystem-1:27.2-9.el9.noarch expat-2.5.0-1.el9.x86_64 git-2.39.3-1.el9_2.x86_64 git-core-2.39.3-1.el9_2.x86_64 git-core-doc-2.39.3-1.el9_2.noarch less-590-2.el9_2.x86_64 libcbor-0.7.0-5.el9.x86_64 libedit-3.1-38.20210216cvs.el9.x86_64 libfido2-1.13.0-1.el9.x86_64 openssh-8.7p1-34.el9.x86_64 openssh-clients-8.7p1-34.el9.x86_64 perl-DynaLoader-1.47-480.el9.x86_64 perl-Error-1:0.17029-7.el9.noarch perl-File-Find-1.37-480.el9.noarch perl-Git-2.39.3-1.el9_2.noarch perl-TermReadKey-2.38-11.el9.x86_64 perl-lib-0.65-480.el9.x86_64 pyproject-rpm-macros-1.9.0-1.el9.noarch python-rpm-macros-3.9-52.el9.noarch python3-3.9.18-1.el9_3.1.x86_64 python3-devel-3.9.18-1.el9_3.1.x86_64 python3-libs-3.9.18-1.el9_3.1.x86_64 python3-packaging-20.9-5.el9.noarch python3-pip-wheel-21.2.3-7.el9.noarch python3-pyparsing-2.4.7-9.el9.noarch python3-rpm-generators-12-8.el9.noarch python3-rpm-macros-3.9-52.el9.noarch python3-setuptools-53.0.0-12.el9.noarch python3-setuptools-wheel-53.0.0-12.el9.noarch Complete! Finish: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Start: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1637193600 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.ex4GbN + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-rocket + /usr/bin/mkdir -p litex-pythondata-cpu-rocket + cd litex-pythondata-cpu-rocket + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-rocket.git . Cloning into '.'... + git fetch --depth 1 origin 55d7e42913e46ba33e2ade792eef13191c895852 From https://github.com/litex-hub/pythondata-cpu-rocket * branch 55d7e42913e46ba33e2ade792eef13191c895852 -> FETCH_HEAD + git reset --hard 55d7e42913e46ba33e2ade792eef13191c895852 HEAD is now at 55d7e42 update.sh: factor out variant generation and build + git log --format=fuller commit 55d7e42913e46ba33e2ade792eef13191c895852 Author: Gabriel Somlo AuthorDate: Mon Feb 19 18:29:01 2024 -0500 Commit: Gabriel Somlo CommitDate: Mon Feb 19 19:48:33 2024 -0500 update.sh: factor out variant generation and build Signed-off-by: Gabriel Somlo + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.uLt1EY + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -march=x86-64-v2 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -s' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_rocket copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket running egg_info creating pythondata_cpu_rocket.egg-info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' adding license file 'LICENSE' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' creating build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog creating build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src creating build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.3XUM5k + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -march=x86-64-v2 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 running install running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/vsrc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket/__init__.py to __init__.cpython-39.pyc writing byte-compilation script '/tmp/tmpjbka78yc.py' /usr/bin/python3 /tmp/tmpjbka78yc.py removing /tmp/tmpjbka78yc.py running install_egg_info running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' Copying pythondata_cpu_rocket.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9/site-packages/pythondata_cpu_rocket-0.0.post7146-py3.9.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/bin/__pycache__ + /usr/bin/find-debuginfo -j4 --strict-build-id -m -i --build-id-seed 2023.12-20240219.0.git55d7e429.el9 --unique-debug-suffix -2023.12-20240219.0.git55d7e429.el9.x86_64 --unique-debug-src-base litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 110000000 --remove-section .gnu.build.attributes -S debugsourcefiles.list /builddir/build/BUILD/litex-pythondata-cpu-rocket find: 'debug': No such file or directory + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip + /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip + /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/lib/python3.9 using python3.9 + /usr/lib/rpm/brp-python-hardlink + /usr/lib/rpm/redhat/brp-mangle-shebangs Processing files: litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.el9.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.QKtP8W + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + cp -pr README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.Ge4QTc + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + cp -pr LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-rocket-python3 = 2023.12-20240219.0.git55d7e429.el9 python3.9dist(pythondata-cpu-rocket) = 0^post7146 python3dist(pythondata-cpu-rocket) = 0^post7146 pythondata-cpu-rocket Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/sh python(abi) = 3.9 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.el9.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.HngXZW + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.x86_64 + RPM_EC=0 ++ jobs -p + exit 0 Finish: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm Finish: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.rpm.log /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.librepo.log /var/lib/mock/rhel+epel-9-x86_64-1709342025.169143/root/var/log/dnf.log INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.el9.src.rpm) Config(child) 2 minutes 53 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-rocket-python3", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.el9", "arch": "noarch" }, { "name": "litex-pythondata-cpu-rocket", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.el9", "arch": "src" } ] } RPMResults finished