Warning: Permanently added '54.82.124.34' (ED25519) to the list of known hosts. You can reproduce this build on your computer by running: sudo dnf install copr-rpmbuild /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/6427977-fedora-37-aarch64 --chroot fedora-37-aarch64 Version: 0.69 PID: 5711 Logging PID: 5712 Task: {'appstream': False, 'background': False, 'build_id': 6427977, 'buildroot_pkgs': [], 'chroot': 'fedora-37-aarch64', 'enable_net': True, 'fedora_review': False, 'git_hash': '1a188bcff68793301e25a29b7dfcdfba5df81e13', 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', 'isolation': 'default', 'memory_reqs': 2048, 'package_name': 'litex-pythondata-cpu-rocket', 'package_version': '2023.08-20230919.0.gitd97c0f6b', 'project_dirname': 'HDL', 'project_name': 'HDL', 'project_owner': 'rezso', 'repo_priority': None, 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/HDL/fedora-37-aarch64/', 'id': 'copr_base', 'name': 'Copr repository', 'priority': None}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/ML/fedora-37-aarch64/', 'id': 'copr_rezso_ML', 'name': 'Additional repo copr_rezso_ML'}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/CUDA/fedora-37-aarch64/', 'id': 'copr_rezso_CUDA', 'name': 'Additional repo copr_rezso_CUDA'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/x86_64', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/sbsa', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/ppc64le', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le'}], 'sandbox': 'rezso/HDL--rezso', 'source_json': {}, 'source_type': None, 'submitter': 'rezso', 'tags': [], 'task_id': '6427977-fedora-37-aarch64', 'timeout': 172800, 'uses_devel_repo': False, 'with_opts': [], 'without_opts': []} Running: git clone https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket /var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket --depth 500 --no-single-branch --recursive cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', '/var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket', '--depth', '500', '--no-single-branch', '--recursive'] cwd: . rc: 0 stdout: stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket'... Running: git checkout 1a188bcff68793301e25a29b7dfcdfba5df81e13 -- cmd: ['git', 'checkout', '1a188bcff68793301e25a29b7dfcdfba5df81e13', '--'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket rc: 0 stdout: stderr: Note: switching to '1a188bcff68793301e25a29b7dfcdfba5df81e13'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at 1a188bc automatic import of litex-pythondata-cpu-rocket Running: copr-distgit-client sources cmd: ['copr-distgit-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket rc: 0 stdout: stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources /usr/bin/tail: /var/lib/copr-rpmbuild/main.log: file truncated Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1695260627.623462 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 5.1.1 starting (python version = 3.11.3, NVR = mock-5.1.1-1.fc38)... Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(fedora-37-aarch64) Start: clean chroot Finish: clean chroot Mock Version: 5.1.1 INFO: Mock Version: 5.1.1 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-37-aarch64-bootstrap-1695260627.623462/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using bootstrap image: registry.fedoraproject.org/fedora:37 INFO: Pulling image: registry.fedoraproject.org/fedora:37 INFO: Copy content of container registry.fedoraproject.org/fedora:37 to /var/lib/mock/fedora-37-aarch64-bootstrap-1695260627.623462/root INFO: Checking that registry.fedoraproject.org/fedora:37 image matches host's architecture INFO: mounting registry.fedoraproject.org/fedora:37 with podman image mount INFO: image registry.fedoraproject.org/fedora:37 as /var/lib/containers/storage/overlay/10d320c32b08e4e5d4e8a3e2b934705a3e5d6278dc72792d3af34ced56447b46/merged INFO: umounting image registry.fedoraproject.org/fedora:37 (/var/lib/containers/storage/overlay/10d320c32b08e4e5d4e8a3e2b934705a3e5d6278dc72792d3af34ced56447b46/merged) with podman image umount INFO: Package manager dnf detected and used (fallback) INFO: Bootstrap image not marked ready Start(bootstrap): installing dnf tooling No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 9.5 MB/s | 1.1 MB 00:00 Additional repo copr_rezso_ML 5.0 MB/s | 838 kB 00:00 Additional repo copr_rezso_CUDA 130 kB/s | 51 kB 00:00 Additional repo http_developer_download_nvidia_ 149 MB/s | 2.6 MB 00:00 Additional repo http_developer_download_nvidia_ 115 MB/s | 1.5 MB 00:00 Additional repo http_developer_download_nvidia_ 124 MB/s | 1.6 MB 00:00 fedora 49 MB/s | 78 MB 00:01 updates 23 MB/s | 38 MB 00:01 Package python3-dnf-4.15.1-1.fc37.noarch is already installed. Dependencies resolved. ================================================================================ Package Arch Version Repository Size ================================================================================ Installing: python3-dnf-plugins-core noarch 4.4.2-1.fc37 updates 299 k Upgrading: dnf noarch 4.16.2-1.fc37 updates 475 k dnf-data noarch 4.16.2-1.fc37 updates 38 k python3-dnf noarch 4.16.2-1.fc37 updates 604 k yum noarch 4.16.2-1.fc37 updates 36 k Installing dependencies: dbus-libs aarch64 1:1.14.10-1.fc37 updates 154 k python3-dateutil noarch 1:2.8.2-4.fc37 fedora 361 k python3-dbus aarch64 1.3.2-1.fc37 updates 158 k python3-distro noarch 1.7.0-3.fc37 fedora 48 k python3-six noarch 1.16.0-8.fc37 fedora 42 k python3-systemd aarch64 235-1.fc37 fedora 108 k Transaction Summary ================================================================================ Install 7 Packages Upgrade 4 Packages Total download size: 2.3 M Downloading Packages: (1/11): python3-six-1.16.0-8.fc37.noarch.rpm 519 kB/s | 42 kB 00:00 (2/11): python3-systemd-235-1.fc37.aarch64.rpm 28 MB/s | 108 kB 00:00 (3/11): python3-distro-1.7.0-3.fc37.noarch.rpm 563 kB/s | 48 kB 00:00 (4/11): dbus-libs-1.14.10-1.fc37.aarch64.rpm 35 MB/s | 154 kB 00:00 (5/11): python3-dbus-1.3.2-1.fc37.aarch64.rpm 32 MB/s | 158 kB 00:00 (6/11): python3-dateutil-2.8.2-4.fc37.noarch.rp 2.8 MB/s | 361 kB 00:00 (7/11): dnf-4.16.2-1.fc37.noarch.rpm 13 MB/s | 475 kB 00:00 (8/11): dnf-data-4.16.2-1.fc37.noarch.rpm 9.0 MB/s | 38 kB 00:00 (9/11): yum-4.16.2-1.fc37.noarch.rpm 7.9 MB/s | 36 kB 00:00 (10/11): python3-dnf-4.16.2-1.fc37.noarch.rpm 41 MB/s | 604 kB 00:00 (11/11): python3-dnf-plugins-core-4.4.2-1.fc37. 3.2 MB/s | 299 kB 00:00 -------------------------------------------------------------------------------- Total 4.1 MB/s | 2.3 MB 00:00 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Upgrading : dnf-data-4.16.2-1.fc37.noarch 1/15 Upgrading : python3-dnf-4.16.2-1.fc37.noarch 2/15 Installing : dbus-libs-1:1.14.10-1.fc37.aarch64 3/15 Installing : python3-dbus-1.3.2-1.fc37.aarch64 4/15 Upgrading : dnf-4.16.2-1.fc37.noarch 5/15 Running scriptlet: dnf-4.16.2-1.fc37.noarch 5/15 Installing : python3-systemd-235-1.fc37.aarch64 6/15 Installing : python3-six-1.16.0-8.fc37.noarch 7/15 Installing : python3-dateutil-1:2.8.2-4.fc37.noarch 8/15 Installing : python3-distro-1.7.0-3.fc37.noarch 9/15 Installing : python3-dnf-plugins-core-4.4.2-1.fc37.noarch 10/15 Upgrading : yum-4.16.2-1.fc37.noarch 11/15 Cleanup : yum-4.15.1-1.fc37.noarch 12/15 Running scriptlet: dnf-4.15.1-1.fc37.noarch 13/15 Cleanup : dnf-4.15.1-1.fc37.noarch 13/15 Running scriptlet: dnf-4.15.1-1.fc37.noarch 13/15 Cleanup : python3-dnf-4.15.1-1.fc37.noarch 14/15 Cleanup : dnf-data-4.15.1-1.fc37.noarch 15/15 Running scriptlet: dnf-data-4.15.1-1.fc37.noarch 15/15 Verifying : python3-dateutil-1:2.8.2-4.fc37.noarch 1/15 Verifying : python3-distro-1.7.0-3.fc37.noarch 2/15 Verifying : python3-six-1.16.0-8.fc37.noarch 3/15 Verifying : python3-systemd-235-1.fc37.aarch64 4/15 Verifying : dbus-libs-1:1.14.10-1.fc37.aarch64 5/15 Verifying : python3-dbus-1.3.2-1.fc37.aarch64 6/15 Verifying : python3-dnf-plugins-core-4.4.2-1.fc37.noarch 7/15 Verifying : dnf-4.16.2-1.fc37.noarch 8/15 Verifying : dnf-4.15.1-1.fc37.noarch 9/15 Verifying : dnf-data-4.16.2-1.fc37.noarch 10/15 Verifying : dnf-data-4.15.1-1.fc37.noarch 11/15 Verifying : python3-dnf-4.16.2-1.fc37.noarch 12/15 Verifying : python3-dnf-4.15.1-1.fc37.noarch 13/15 Verifying : yum-4.16.2-1.fc37.noarch 14/15 Verifying : yum-4.15.1-1.fc37.noarch 15/15 Upgraded: dnf-4.16.2-1.fc37.noarch dnf-data-4.16.2-1.fc37.noarch python3-dnf-4.16.2-1.fc37.noarch yum-4.16.2-1.fc37.noarch Installed: dbus-libs-1:1.14.10-1.fc37.aarch64 python3-dateutil-1:2.8.2-4.fc37.noarch python3-dbus-1.3.2-1.fc37.aarch64 python3-distro-1.7.0-3.fc37.noarch python3-dnf-plugins-core-4.4.2-1.fc37.noarch python3-six-1.16.0-8.fc37.noarch python3-systemd-235-1.fc37.aarch64 Complete! Finish(bootstrap): installing dnf tooling Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-37-aarch64-1695260627.623462/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf detected and used (direct choice) Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 12 MB/s | 1.1 MB 00:00 Additional repo copr_rezso_ML 3.1 MB/s | 838 kB 00:00 Additional repo copr_rezso_CUDA 570 kB/s | 51 kB 00:00 Additional repo http_developer_download_nvidia_ 169 MB/s | 2.6 MB 00:00 Additional repo http_developer_download_nvidia_ 111 MB/s | 1.5 MB 00:00 Additional repo http_developer_download_nvidia_ 70 MB/s | 1.6 MB 00:00 fedora 45 MB/s | 78 MB 00:01 updates 14 MB/s | 38 MB 00:02 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing group/module packages: bash aarch64 5.2.15-1.fc37 updates 1.8 M bzip2 aarch64 1.0.8-12.fc37 fedora 52 k coreutils aarch64 9.1-8.fc37 updates 1.0 M cpio aarch64 2.13-13.fc37 fedora 274 k diffutils aarch64 3.8-3.fc37 fedora 376 k fedora-release-common noarch 37-16 updates 21 k findutils aarch64 1:4.9.0-2.fc37 fedora 493 k gawk aarch64 5.1.1-4.fc37 fedora 1.0 M glibc-minimal-langpack aarch64 2.36-11.fc37 updates 85 k grep aarch64 3.7-4.fc37 fedora 270 k gzip aarch64 1.12-2.fc37 fedora 164 k info aarch64 6.8-4.fc37 fedora 220 k patch aarch64 2.7.6-17.fc37 fedora 121 k redhat-rpm-config noarch 229-1.fc37 updates 80 k rpm-build aarch64 4.18.1-2.fc37 updates 76 k sed aarch64 4.8-11.fc37 fedora 304 k shadow-utils aarch64 2:4.12.3-6.fc37 updates 1.3 M tar aarch64 2:1.34-6.fc37 updates 875 k unzip aarch64 6.0-58.fc37 fedora 182 k util-linux aarch64 2.38.1-1.fc37 fedora 2.3 M which aarch64 2.21-39.fc37 updates 42 k xz aarch64 5.4.1-1.fc37 updates 420 k Installing dependencies: alternatives aarch64 1.24-1.fc37 updates 38 k ansible-srpm-macros noarch 1-10.fc37 updates 20 k audit-libs aarch64 3.1.2-1.fc37 updates 117 k authselect aarch64 1.4.2-1.fc37 updates 144 k authselect-libs aarch64 1.4.2-1.fc37 updates 248 k basesystem noarch 11-14.fc37 fedora 7.0 k binutils aarch64 2.38-27.fc37 updates 5.8 M binutils-gold aarch64 2.38-27.fc37 updates 919 k bzip2-libs aarch64 1.0.8-12.fc37 fedora 43 k ca-certificates noarch 2023.2.60-1.0.fc37 updates 844 k coreutils-common aarch64 9.1-8.fc37 updates 2.0 M cracklib aarch64 2.9.7-30.fc37 fedora 93 k crypto-policies noarch 20220815-1.gite4ed860.fc37 fedora 86 k curl aarch64 7.85.0-10.fc37 updates 313 k cyrus-sasl-lib aarch64 2.1.28-8.fc37 fedora 778 k debugedit aarch64 5.0-7.fc37 updates 77 k dwz aarch64 0.14-7.fc37 fedora 126 k ed aarch64 1.18-2.fc37 fedora 78 k efi-srpm-macros noarch 5-6.fc37 fedora 22 k elfutils aarch64 0.189-3.fc37 updates 531 k elfutils-debuginfod-client aarch64 0.189-3.fc37 updates 37 k elfutils-default-yama-scope noarch 0.189-3.fc37 updates 13 k elfutils-libelf aarch64 0.189-3.fc37 updates 193 k elfutils-libs aarch64 0.189-3.fc37 updates 256 k fedora-gpg-keys noarch 37-2 updates 126 k fedora-release noarch 37-16 updates 10 k fedora-release-identity-basic noarch 37-16 updates 11 k fedora-repos noarch 37-2 updates 9.4 k file aarch64 5.42-4.fc37 fedora 49 k file-libs aarch64 5.42-4.fc37 fedora 674 k filesystem aarch64 3.18-2.fc37 fedora 1.1 M fonts-srpm-macros noarch 1:2.0.5-9.fc37 fedora 26 k fpc-srpm-macros noarch 1.3-6.fc37 fedora 7.7 k gdb-minimal aarch64 13.2-2.fc37 updates 3.7 M gdbm-libs aarch64 1:1.23-2.fc37 fedora 57 k ghc-srpm-macros noarch 1.6.1-1.fc37 updates 8.0 k glibc aarch64 2.36-11.fc37 updates 1.8 M glibc-common aarch64 2.36-11.fc37 updates 360 k glibc-gconv-extra aarch64 2.36-11.fc37 updates 1.7 M gmp aarch64 1:6.2.1-3.fc37 fedora 265 k gnat-srpm-macros noarch 5-1.fc37 updates 8.3 k go-srpm-macros noarch 3.2.0-1.fc37 fedora 27 k kernel-srpm-macros noarch 1.0-15.fc37 fedora 9.4 k keyutils-libs aarch64 1.6.1-5.fc37 fedora 31 k krb5-libs aarch64 1.19.2-13.fc37 updates 731 k libacl aarch64 2.3.1-4.fc37 fedora 23 k libarchive aarch64 3.6.1-3.fc37 updates 392 k libattr aarch64 2.5.1-5.fc37 fedora 18 k libblkid aarch64 2.38.1-1.fc37 fedora 106 k libbrotli aarch64 1.0.9-9.fc37 fedora 318 k libcap aarch64 2.48-5.fc37 fedora 67 k libcap-ng aarch64 0.8.3-3.fc37 fedora 33 k libcom_err aarch64 1.46.5-3.fc37 fedora 25 k libcurl aarch64 7.85.0-10.fc37 updates 298 k libdb aarch64 5.3.28-53.fc37 fedora 737 k libeconf aarch64 0.5.2-1.fc37 updates 30 k libevent aarch64 2.1.12-7.fc37 fedora 254 k libfdisk aarch64 2.38.1-1.fc37 fedora 155 k libffi aarch64 3.4.4-1.fc37 updates 35 k libgcc aarch64 12.3.1-1.fc37 updates 99 k libgomp aarch64 12.3.1-1.fc37 updates 298 k libidn2 aarch64 2.3.4-1.fc37 updates 159 k libmount aarch64 2.38.1-1.fc37 fedora 133 k libnghttp2 aarch64 1.51.0-1.fc37 updates 74 k libnsl2 aarch64 2.0.0-4.fc37 fedora 30 k libpkgconf aarch64 1.8.0-3.fc37 fedora 36 k libpsl aarch64 0.21.1-6.fc37 fedora 63 k libpwquality aarch64 1.4.5-3.fc37 updates 119 k libselinux aarch64 3.5-1.fc37 updates 86 k libsemanage aarch64 3.5-2.fc37 updates 116 k libsepol aarch64 3.5-1.fc37 updates 311 k libsigsegv aarch64 2.14-3.fc37 fedora 27 k libsmartcols aarch64 2.38.1-1.fc37 fedora 63 k libssh aarch64 0.10.5-1.fc37 updates 211 k libssh-config noarch 0.10.5-1.fc37 updates 8.6 k libstdc++ aarch64 12.3.1-1.fc37 updates 767 k libtasn1 aarch64 4.19.0-1.fc37 updates 73 k libtirpc aarch64 1.3.3-1.rc1.fc37 updates 93 k libunistring aarch64 1.0-2.fc37 fedora 543 k libutempter aarch64 1.2.1-7.fc37 fedora 26 k libuuid aarch64 2.38.1-1.fc37 fedora 28 k libverto aarch64 0.3.2-4.fc37 fedora 21 k libxcrypt aarch64 4.4.36-1.fc37 updates 123 k libxml2 aarch64 2.10.4-1.fc37 updates 686 k libzstd aarch64 1.5.5-1.fc37 updates 279 k lua-libs aarch64 5.4.4-9.fc37 updates 129 k lua-srpm-macros noarch 1-7.fc37 fedora 8.8 k lz4-libs aarch64 1.9.4-1.fc37 updates 67 k mpfr aarch64 4.1.0-10.fc37 fedora 240 k ncurses-base noarch 6.4-3.20230114.fc37 updates 86 k ncurses-libs aarch64 6.4-3.20230114.fc37 updates 319 k nim-srpm-macros noarch 3-7.fc37 fedora 8.4 k ocaml-srpm-macros noarch 7-2.fc37 fedora 13 k openblas-srpm-macros noarch 2-12.fc37 fedora 7.5 k openldap aarch64 2.6.4-1.fc37 updates 250 k openssl-libs aarch64 1:3.0.9-1.fc37 updates 2.0 M p11-kit aarch64 0.25.0-1.fc37 updates 483 k p11-kit-trust aarch64 0.25.0-1.fc37 updates 143 k package-notes-srpm-macros noarch 0.5-7.fc37 updates 11 k pam aarch64 1.5.2-14.fc37 fedora 567 k pam-libs aarch64 1.5.2-14.fc37 fedora 58 k pcre aarch64 8.45-1.fc37.2 fedora 184 k pcre2 aarch64 10.40-1.fc37.1 fedora 219 k pcre2-syntax noarch 10.40-1.fc37.1 fedora 142 k perl-srpm-macros noarch 1-46.fc37 fedora 8.3 k pkgconf aarch64 1.8.0-3.fc37 fedora 41 k pkgconf-m4 noarch 1.8.0-3.fc37 fedora 14 k pkgconf-pkg-config aarch64 1.8.0-3.fc37 fedora 10 k popt aarch64 1.19-1.fc37 fedora 66 k publicsuffix-list-dafsa noarch 20230812-1.fc37 updates 57 k pyproject-srpm-macros noarch 1.9.0-1.fc37 updates 15 k python-srpm-macros noarch 3.11-6.fc37 updates 24 k qt5-srpm-macros noarch 5.15.9-1.fc37 updates 8.1 k readline aarch64 8.2-2.fc37 updates 210 k rpm aarch64 4.18.1-2.fc37 updates 566 k rpm-build-libs aarch64 4.18.1-2.fc37 updates 89 k rpm-libs aarch64 4.18.1-2.fc37 updates 311 k rpmautospec-rpm-macros noarch 0.3.5-1.fc37 updates 9.3 k rust-srpm-macros noarch 24-4.fc37 updates 12 k setup noarch 2.14.1-2.fc37 fedora 149 k sqlite-libs aarch64 3.40.0-1.fc37 updates 661 k systemd-libs aarch64 251.14-2.fc37 updates 588 k tzdata noarch 2023c-1.fc37 updates 718 k util-linux-core aarch64 2.38.1-1.fc37 fedora 471 k xxhash-libs aarch64 0.8.2-1.fc37 updates 34 k xz-libs aarch64 5.4.1-1.fc37 updates 106 k zip aarch64 3.0-33.fc37 fedora 256 k zlib aarch64 1.2.12-5.fc37 fedora 93 k zstd aarch64 1.5.5-1.fc37 updates 444 k Installing Groups: Buildsystem building group Transaction Summary ================================================================================ Install 151 Packages Total download size: 51 M Installed size: 206 M Downloading Packages: (1/151): basesystem-11-14.fc37.noarch.rpm 82 kB/s | 7.0 kB 00:00 (2/151): bzip2-1.0.8-12.fc37.aarch64.rpm 601 kB/s | 52 kB 00:00 (3/151): bzip2-libs-1.0.8-12.fc37.aarch64.rpm 489 kB/s | 43 kB 00:00 (4/151): cracklib-2.9.7-30.fc37.aarch64.rpm 16 MB/s | 93 kB 00:00 (5/151): crypto-policies-20220815-1.gite4ed860. 14 MB/s | 86 kB 00:00 (6/151): cpio-2.13-13.fc37.aarch64.rpm 27 MB/s | 274 kB 00:00 (7/151): dwz-0.14-7.fc37.aarch64.rpm 23 MB/s | 126 kB 00:00 (8/151): ed-1.18-2.fc37.aarch64.rpm 12 MB/s | 78 kB 00:00 (9/151): diffutils-3.8-3.fc37.aarch64.rpm 24 MB/s | 376 kB 00:00 (10/151): efi-srpm-macros-5-6.fc37.noarch.rpm 6.7 MB/s | 22 kB 00:00 (11/151): file-5.42-4.fc37.aarch64.rpm 13 MB/s | 49 kB 00:00 (12/151): cyrus-sasl-lib-2.1.28-8.fc37.aarch64. 31 MB/s | 778 kB 00:00 (13/151): file-libs-5.42-4.fc37.aarch64.rpm 48 MB/s | 674 kB 00:00 (14/151): fonts-srpm-macros-2.0.5-9.fc37.noarch 9.7 MB/s | 26 kB 00:00 (15/151): fpc-srpm-macros-1.3-6.fc37.noarch.rpm 1.4 MB/s | 7.7 kB 00:00 (16/151): findutils-4.9.0-2.fc37.aarch64.rpm 27 MB/s | 493 kB 00:00 (17/151): filesystem-3.18-2.fc37.aarch64.rpm 42 MB/s | 1.1 MB 00:00 (18/151): gdbm-libs-1.23-2.fc37.aarch64.rpm 9.5 MB/s | 57 kB 00:00 (19/151): go-srpm-macros-3.2.0-1.fc37.noarch.rp 8.6 MB/s | 27 kB 00:00 (20/151): gmp-6.2.1-3.fc37.aarch64.rpm 27 MB/s | 265 kB 00:00 (21/151): gawk-5.1.1-4.fc37.aarch64.rpm 54 MB/s | 1.0 MB 00:00 (22/151): grep-3.7-4.fc37.aarch64.rpm 34 MB/s | 270 kB 00:00 (23/151): kernel-srpm-macros-1.0-15.fc37.noarch 3.9 MB/s | 9.4 kB 00:00 (24/151): gzip-1.12-2.fc37.aarch64.rpm 24 MB/s | 164 kB 00:00 (25/151): info-6.8-4.fc37.aarch64.rpm 33 MB/s | 220 kB 00:00 (26/151): keyutils-libs-1.6.1-5.fc37.aarch64.rp 7.8 MB/s | 31 kB 00:00 (27/151): libacl-2.3.1-4.fc37.aarch64.rpm 6.3 MB/s | 23 kB 00:00 (28/151): libattr-2.5.1-5.fc37.aarch64.rpm 6.9 MB/s | 18 kB 00:00 (29/151): libblkid-2.38.1-1.fc37.aarch64.rpm 25 MB/s | 106 kB 00:00 (30/151): libcap-2.48-5.fc37.aarch64.rpm 13 MB/s | 67 kB 00:00 (31/151): libbrotli-1.0.9-9.fc37.aarch64.rpm 39 MB/s | 318 kB 00:00 (32/151): libcap-ng-0.8.3-3.fc37.aarch64.rpm 6.8 MB/s | 33 kB 00:00 (33/151): libcom_err-1.46.5-3.fc37.aarch64.rpm 6.9 MB/s | 25 kB 00:00 (34/151): libfdisk-2.38.1-1.fc37.aarch64.rpm 5.6 MB/s | 155 kB 00:00 (35/151): libevent-2.1.12-7.fc37.aarch64.rpm 8.3 MB/s | 254 kB 00:00 (36/151): libmount-2.38.1-1.fc37.aarch64.rpm 20 MB/s | 133 kB 00:00 (37/151): libnsl2-2.0.0-4.fc37.aarch64.rpm 4.6 MB/s | 30 kB 00:00 (38/151): libpsl-0.21.1-6.fc37.aarch64.rpm 15 MB/s | 63 kB 00:00 (39/151): libdb-5.3.28-53.fc37.aarch64.rpm 16 MB/s | 737 kB 00:00 (40/151): libsigsegv-2.14-3.fc37.aarch64.rpm 7.3 MB/s | 27 kB 00:00 (41/151): libsmartcols-2.38.1-1.fc37.aarch64.rp 16 MB/s | 63 kB 00:00 (42/151): libutempter-1.2.1-7.fc37.aarch64.rpm 6.3 MB/s | 26 kB 00:00 (43/151): libpkgconf-1.8.0-3.fc37.aarch64.rpm 1.8 MB/s | 36 kB 00:00 (44/151): libuuid-2.38.1-1.fc37.aarch64.rpm 5.0 MB/s | 28 kB 00:00 (45/151): libverto-0.3.2-4.fc37.aarch64.rpm 5.7 MB/s | 21 kB 00:00 (46/151): lua-srpm-macros-1-7.fc37.noarch.rpm 3.4 MB/s | 8.8 kB 00:00 (47/151): nim-srpm-macros-3-7.fc37.noarch.rpm 2.7 MB/s | 8.4 kB 00:00 (48/151): libunistring-1.0-2.fc37.aarch64.rpm 26 MB/s | 543 kB 00:00 (49/151): ocaml-srpm-macros-7-2.fc37.noarch.rpm 4.5 MB/s | 13 kB 00:00 (50/151): mpfr-4.1.0-10.fc37.aarch64.rpm 24 MB/s | 240 kB 00:00 (51/151): openblas-srpm-macros-2-12.fc37.noarch 1.8 MB/s | 7.5 kB 00:00 (52/151): pam-libs-1.5.2-14.fc37.aarch64.rpm 15 MB/s | 58 kB 00:00 (53/151): patch-2.7.6-17.fc37.aarch64.rpm 28 MB/s | 121 kB 00:00 (54/151): pcre-8.45-1.fc37.2.aarch64.rpm 33 MB/s | 184 kB 00:00 (55/151): pcre2-10.40-1.fc37.1.aarch64.rpm 29 MB/s | 219 kB 00:00 (56/151): perl-srpm-macros-1-46.fc37.noarch.rpm 3.2 MB/s | 8.3 kB 00:00 (57/151): pcre2-syntax-10.40-1.fc37.1.noarch.rp 21 MB/s | 142 kB 00:00 (58/151): pam-1.5.2-14.fc37.aarch64.rpm 27 MB/s | 567 kB 00:00 (59/151): pkgconf-m4-1.8.0-3.fc37.noarch.rpm 5.1 MB/s | 14 kB 00:00 (60/151): pkgconf-1.8.0-3.fc37.aarch64.rpm 9.4 MB/s | 41 kB 00:00 (61/151): pkgconf-pkg-config-1.8.0-3.fc37.aarch 2.1 MB/s | 10 kB 00:00 (62/151): popt-1.19-1.fc37.aarch64.rpm 11 MB/s | 66 kB 00:00 (63/151): sed-4.8-11.fc37.aarch64.rpm 46 MB/s | 304 kB 00:00 (64/151): setup-2.14.1-2.fc37.noarch.rpm 18 MB/s | 149 kB 00:00 (65/151): unzip-6.0-58.fc37.aarch64.rpm 27 MB/s | 182 kB 00:00 (66/151): zip-3.0-33.fc37.aarch64.rpm 28 MB/s | 256 kB 00:00 (67/151): util-linux-core-2.38.1-1.fc37.aarch64 40 MB/s | 471 kB 00:00 (68/151): alternatives-1.24-1.fc37.aarch64.rpm 12 MB/s | 38 kB 00:00 (69/151): zlib-1.2.12-5.fc37.aarch64.rpm 19 MB/s | 93 kB 00:00 (70/151): ansible-srpm-macros-1-10.fc37.noarch. 4.3 MB/s | 20 kB 00:00 (71/151): audit-libs-3.1.2-1.fc37.aarch64.rpm 16 MB/s | 117 kB 00:00 (72/151): authselect-1.4.2-1.fc37.aarch64.rpm 21 MB/s | 144 kB 00:00 (73/151): authselect-libs-1.4.2-1.fc37.aarch64. 28 MB/s | 248 kB 00:00 (74/151): util-linux-2.38.1-1.fc37.aarch64.rpm 32 MB/s | 2.3 MB 00:00 (75/151): bash-5.2.15-1.fc37.aarch64.rpm 39 MB/s | 1.8 MB 00:00 (76/151): binutils-gold-2.38-27.fc37.aarch64.rp 47 MB/s | 919 kB 00:00 (77/151): ca-certificates-2023.2.60-1.0.fc37.no 49 MB/s | 844 kB 00:00 (78/151): coreutils-common-9.1-8.fc37.aarch64.r 103 MB/s | 2.0 MB 00:00 (79/151): coreutils-9.1-8.fc37.aarch64.rpm 45 MB/s | 1.0 MB 00:00 (80/151): curl-7.85.0-10.fc37.aarch64.rpm 20 MB/s | 313 kB 00:00 (81/151): debugedit-5.0-7.fc37.aarch64.rpm 3.2 MB/s | 77 kB 00:00 (82/151): elfutils-debuginfod-client-0.189-3.fc 8.5 MB/s | 37 kB 00:00 (83/151): elfutils-0.189-3.fc37.aarch64.rpm 33 MB/s | 531 kB 00:00 (84/151): elfutils-default-yama-scope-0.189-3.f 2.3 MB/s | 13 kB 00:00 (85/151): elfutils-libelf-0.189-3.fc37.aarch64. 24 MB/s | 193 kB 00:00 (86/151): elfutils-libs-0.189-3.fc37.aarch64.rp 35 MB/s | 256 kB 00:00 (87/151): fedora-release-37-16.noarch.rpm 3.5 MB/s | 10 kB 00:00 (88/151): fedora-gpg-keys-37-2.noarch.rpm 19 MB/s | 126 kB 00:00 (89/151): fedora-release-identity-basic-37-16.n 2.0 MB/s | 11 kB 00:00 (90/151): fedora-release-common-37-16.noarch.rp 3.1 MB/s | 21 kB 00:00 (91/151): fedora-repos-37-2.noarch.rpm 3.4 MB/s | 9.4 kB 00:00 (92/151): binutils-2.38-27.fc37.aarch64.rpm 41 MB/s | 5.8 MB 00:00 (93/151): ghc-srpm-macros-1.6.1-1.fc37.noarch.r 976 kB/s | 8.0 kB 00:00 (94/151): glibc-common-2.36-11.fc37.aarch64.rpm 29 MB/s | 360 kB 00:00 (95/151): glibc-2.36-11.fc37.aarch64.rpm 41 MB/s | 1.8 MB 00:00 (96/151): glibc-minimal-langpack-2.36-11.fc37.a 13 MB/s | 85 kB 00:00 (97/151): gnat-srpm-macros-5-1.fc37.noarch.rpm 2.6 MB/s | 8.3 kB 00:00 (98/151): glibc-gconv-extra-2.36-11.fc37.aarch6 35 MB/s | 1.7 MB 00:00 (99/151): gdb-minimal-13.2-2.fc37.aarch64.rpm 46 MB/s | 3.7 MB 00:00 (100/151): krb5-libs-1.19.2-13.fc37.aarch64.rpm 42 MB/s | 731 kB 00:00 (101/151): libarchive-3.6.1-3.fc37.aarch64.rpm 46 MB/s | 392 kB 00:00 (102/151): libffi-3.4.4-1.fc37.aarch64.rpm 9.4 MB/s | 35 kB 00:00 (103/151): libeconf-0.5.2-1.fc37.aarch64.rpm 5.0 MB/s | 30 kB 00:00 (104/151): libcurl-7.85.0-10.fc37.aarch64.rpm 29 MB/s | 298 kB 00:00 (105/151): libgcc-12.3.1-1.fc37.aarch64.rpm 14 MB/s | 99 kB 00:00 (106/151): libgomp-12.3.1-1.fc37.aarch64.rpm 29 MB/s | 298 kB 00:00 (107/151): libnghttp2-1.51.0-1.fc37.aarch64.rpm 9.3 MB/s | 74 kB 00:00 (108/151): libpwquality-1.4.5-3.fc37.aarch64.rp 22 MB/s | 119 kB 00:00 (109/151): libidn2-2.3.4-1.fc37.aarch64.rpm 10 MB/s | 159 kB 00:00 (110/151): libselinux-3.5-1.fc37.aarch64.rpm 11 MB/s | 86 kB 00:00 (111/151): libsemanage-3.5-2.fc37.aarch64.rpm 14 MB/s | 116 kB 00:00 (112/151): libssh-config-0.10.5-1.fc37.noarch.r 2.2 MB/s | 8.6 kB 00:00 (113/151): libssh-0.10.5-1.fc37.aarch64.rpm 22 MB/s | 211 kB 00:00 (114/151): libsepol-3.5-1.fc37.aarch64.rpm 19 MB/s | 311 kB 00:00 (115/151): libtasn1-4.19.0-1.fc37.aarch64.rpm 20 MB/s | 73 kB 00:00 (116/151): libtirpc-1.3.3-1.rc1.fc37.aarch64.rp 16 MB/s | 93 kB 00:00 (117/151): libxcrypt-4.4.36-1.fc37.aarch64.rpm 27 MB/s | 123 kB 00:00 (118/151): libzstd-1.5.5-1.fc37.aarch64.rpm 22 MB/s | 279 kB 00:00 (119/151): libstdc++-12.3.1-1.fc37.aarch64.rpm 25 MB/s | 767 kB 00:00 (120/151): lua-libs-5.4.4-9.fc37.aarch64.rpm 20 MB/s | 129 kB 00:00 (121/151): lz4-libs-1.9.4-1.fc37.aarch64.rpm 17 MB/s | 67 kB 00:00 (122/151): ncurses-libs-6.4-3.20230114.fc37.aar 20 MB/s | 319 kB 00:00 (123/151): ncurses-base-6.4-3.20230114.fc37.noa 4.3 MB/s | 86 kB 00:00 (124/151): libxml2-2.10.4-1.fc37.aarch64.rpm 14 MB/s | 686 kB 00:00 (125/151): openldap-2.6.4-1.fc37.aarch64.rpm 26 MB/s | 250 kB 00:00 (126/151): p11-kit-trust-0.25.0-1.fc37.aarch64. 9.1 MB/s | 143 kB 00:00 (127/151): p11-kit-0.25.0-1.fc37.aarch64.rpm 22 MB/s | 483 kB 00:00 (128/151): package-notes-srpm-macros-0.5-7.fc37 1.6 MB/s | 11 kB 00:00 (129/151): publicsuffix-list-dafsa-20230812-1.f 8.3 MB/s | 57 kB 00:00 (130/151): pyproject-srpm-macros-1.9.0-1.fc37.n 2.1 MB/s | 15 kB 00:00 (131/151): python-srpm-macros-3.11-6.fc37.noarc 8.3 MB/s | 24 kB 00:00 (132/151): qt5-srpm-macros-5.15.9-1.fc37.noarch 2.1 MB/s | 8.1 kB 00:00 (133/151): openssl-libs-3.0.9-1.fc37.aarch64.rp 43 MB/s | 2.0 MB 00:00 (134/151): readline-8.2-2.fc37.aarch64.rpm 28 MB/s | 210 kB 00:00 (135/151): redhat-rpm-config-229-1.fc37.noarch. 16 MB/s | 80 kB 00:00 (136/151): rpm-build-4.18.1-2.fc37.aarch64.rpm 18 MB/s | 76 kB 00:00 (137/151): rpm-build-libs-4.18.1-2.fc37.aarch64 17 MB/s | 89 kB 00:00 (138/151): rpmautospec-rpm-macros-0.3.5-1.fc37. 4.7 MB/s | 9.3 kB 00:00 (139/151): rust-srpm-macros-24-4.fc37.noarch.rp 4.8 MB/s | 12 kB 00:00 (140/151): rpm-4.18.1-2.fc37.aarch64.rpm 40 MB/s | 566 kB 00:00 (141/151): rpm-libs-4.18.1-2.fc37.aarch64.rpm 23 MB/s | 311 kB 00:00 (142/151): shadow-utils-4.12.3-6.fc37.aarch64.r 90 MB/s | 1.3 MB 00:00 (143/151): sqlite-libs-3.40.0-1.fc37.aarch64.rp 47 MB/s | 661 kB 00:00 (144/151): systemd-libs-251.14-2.fc37.aarch64.r 51 MB/s | 588 kB 00:00 (145/151): which-2.21-39.fc37.aarch64.rpm 13 MB/s | 42 kB 00:00 (146/151): xxhash-libs-0.8.2-1.fc37.aarch64.rpm 8.4 MB/s | 34 kB 00:00 (147/151): tar-1.34-6.fc37.aarch64.rpm 47 MB/s | 875 kB 00:00 (148/151): xz-libs-5.4.1-1.fc37.aarch64.rpm 17 MB/s | 106 kB 00:00 (149/151): xz-5.4.1-1.fc37.aarch64.rpm 33 MB/s | 420 kB 00:00 (150/151): tzdata-2023c-1.fc37.noarch.rpm 25 MB/s | 718 kB 00:00 (151/151): zstd-1.5.5-1.fc37.aarch64.rpm 48 MB/s | 444 kB 00:00 -------------------------------------------------------------------------------- Total 54 MB/s | 51 MB 00:00 fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x5323552A: Userid : "Fedora (37) " Fingerprint: ACB5 EE4E 831C 74BB 7C16 8D27 F55A D3FB 5323 552A From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-37-primary Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-2.fc37.aarch64 1/1 Preparing : 1/1 Installing : libgcc-12.3.1-1.fc37.aarch64 1/151 Running scriptlet: libgcc-12.3.1-1.fc37.aarch64 1/151 Installing : crypto-policies-20220815-1.gite4ed860.fc37.noarc 2/151 Running scriptlet: crypto-policies-20220815-1.gite4ed860.fc37.noarc 2/151 Installing : fedora-release-identity-basic-37-16.noarch 3/151 Installing : tzdata-2023c-1.fc37.noarch 4/151 Installing : rust-srpm-macros-24-4.fc37.noarch 5/151 Installing : qt5-srpm-macros-5.15.9-1.fc37.noarch 6/151 Installing : pyproject-srpm-macros-1.9.0-1.fc37.noarch 7/151 Installing : publicsuffix-list-dafsa-20230812-1.fc37.noarch 8/151 Installing : package-notes-srpm-macros-0.5-7.fc37.noarch 9/151 Installing : ncurses-base-6.4-3.20230114.fc37.noarch 10/151 Installing : libssh-config-0.10.5-1.fc37.noarch 11/151 Installing : gnat-srpm-macros-5-1.fc37.noarch 12/151 Installing : ghc-srpm-macros-1.6.1-1.fc37.noarch 13/151 Installing : fedora-gpg-keys-37-2.noarch 14/151 Installing : fedora-release-37-16.noarch 15/151 Installing : fedora-repos-37-2.noarch 16/151 Installing : fedora-release-common-37-16.noarch 17/151 Installing : setup-2.14.1-2.fc37.noarch 18/151 Running scriptlet: setup-2.14.1-2.fc37.noarch 18/151 Installing : filesystem-3.18-2.fc37.aarch64 19/151 Installing : basesystem-11-14.fc37.noarch 20/151 Installing : glibc-gconv-extra-2.36-11.fc37.aarch64 21/151 Running scriptlet: glibc-gconv-extra-2.36-11.fc37.aarch64 21/151 Installing : glibc-minimal-langpack-2.36-11.fc37.aarch64 22/151 Installing : glibc-common-2.36-11.fc37.aarch64 23/151 Running scriptlet: glibc-2.36-11.fc37.aarch64 24/151 Installing : glibc-2.36-11.fc37.aarch64 24/151 Running scriptlet: glibc-2.36-11.fc37.aarch64 24/151 Installing : ncurses-libs-6.4-3.20230114.fc37.aarch64 25/151 Installing : bash-5.2.15-1.fc37.aarch64 26/151 Running scriptlet: bash-5.2.15-1.fc37.aarch64 26/151 Installing : zlib-1.2.12-5.fc37.aarch64 27/151 Installing : xz-libs-5.4.1-1.fc37.aarch64 28/151 Installing : bzip2-libs-1.0.8-12.fc37.aarch64 29/151 Installing : libzstd-1.5.5-1.fc37.aarch64 30/151 Installing : elfutils-libelf-0.189-3.fc37.aarch64 31/151 Installing : libuuid-2.38.1-1.fc37.aarch64 32/151 Installing : popt-1.19-1.fc37.aarch64 33/151 Installing : libstdc++-12.3.1-1.fc37.aarch64 34/151 Installing : libblkid-2.38.1-1.fc37.aarch64 35/151 Installing : readline-8.2-2.fc37.aarch64 36/151 Installing : gmp-1:6.2.1-3.fc37.aarch64 37/151 Installing : libattr-2.5.1-5.fc37.aarch64 38/151 Installing : libacl-2.3.1-4.fc37.aarch64 39/151 Installing : libcap-2.48-5.fc37.aarch64 40/151 Installing : libxcrypt-4.4.36-1.fc37.aarch64 41/151 Installing : libeconf-0.5.2-1.fc37.aarch64 42/151 Installing : lz4-libs-1.9.4-1.fc37.aarch64 43/151 Installing : systemd-libs-251.14-2.fc37.aarch64 44/151 Installing : mpfr-4.1.0-10.fc37.aarch64 45/151 Installing : dwz-0.14-7.fc37.aarch64 46/151 Installing : unzip-6.0-58.fc37.aarch64 47/151 Installing : file-libs-5.42-4.fc37.aarch64 48/151 Installing : file-5.42-4.fc37.aarch64 49/151 Installing : sqlite-libs-3.40.0-1.fc37.aarch64 50/151 Installing : libcap-ng-0.8.3-3.fc37.aarch64 51/151 Installing : audit-libs-3.1.2-1.fc37.aarch64 52/151 Installing : pam-libs-1.5.2-14.fc37.aarch64 53/151 Installing : libcom_err-1.46.5-3.fc37.aarch64 54/151 Installing : libsmartcols-2.38.1-1.fc37.aarch64 55/151 Installing : libunistring-1.0-2.fc37.aarch64 56/151 Installing : libidn2-2.3.4-1.fc37.aarch64 57/151 Installing : alternatives-1.24-1.fc37.aarch64 58/151 Installing : libsepol-3.5-1.fc37.aarch64 59/151 Installing : lua-libs-5.4.4-9.fc37.aarch64 60/151 Installing : libpsl-0.21.1-6.fc37.aarch64 61/151 Installing : zip-3.0-33.fc37.aarch64 62/151 Installing : zstd-1.5.5-1.fc37.aarch64 63/151 Installing : libfdisk-2.38.1-1.fc37.aarch64 64/151 Installing : bzip2-1.0.8-12.fc37.aarch64 65/151 Installing : libxml2-2.10.4-1.fc37.aarch64 66/151 Installing : ed-1.18-2.fc37.aarch64 67/151 Installing : elfutils-default-yama-scope-0.189-3.fc37.noarch 68/151 Running scriptlet: elfutils-default-yama-scope-0.189-3.fc37.noarch 68/151 Installing : cpio-2.13-13.fc37.aarch64 69/151 Installing : diffutils-3.8-3.fc37.aarch64 70/151 Installing : gdbm-libs-1:1.23-2.fc37.aarch64 71/151 Installing : cyrus-sasl-lib-2.1.28-8.fc37.aarch64 72/151 Installing : keyutils-libs-1.6.1-5.fc37.aarch64 73/151 Installing : libbrotli-1.0.9-9.fc37.aarch64 74/151 Installing : libdb-5.3.28-53.fc37.aarch64 75/151 Installing : libpkgconf-1.8.0-3.fc37.aarch64 76/151 Installing : pkgconf-1.8.0-3.fc37.aarch64 77/151 Installing : libsigsegv-2.14-3.fc37.aarch64 78/151 Installing : gawk-5.1.1-4.fc37.aarch64 79/151 Installing : libverto-0.3.2-4.fc37.aarch64 80/151 Installing : pcre-8.45-1.fc37.2.aarch64 81/151 Installing : grep-3.7-4.fc37.aarch64 82/151 Installing : xz-5.4.1-1.fc37.aarch64 83/151 Installing : libffi-3.4.4-1.fc37.aarch64 84/151 Installing : p11-kit-0.25.0-1.fc37.aarch64 85/151 Installing : libgomp-12.3.1-1.fc37.aarch64 86/151 Installing : libnghttp2-1.51.0-1.fc37.aarch64 87/151 Installing : libtasn1-4.19.0-1.fc37.aarch64 88/151 Installing : p11-kit-trust-0.25.0-1.fc37.aarch64 89/151 Running scriptlet: p11-kit-trust-0.25.0-1.fc37.aarch64 89/151 Installing : xxhash-libs-0.8.2-1.fc37.aarch64 90/151 Installing : coreutils-common-9.1-8.fc37.aarch64 91/151 Installing : ansible-srpm-macros-1-10.fc37.noarch 92/151 Installing : pkgconf-m4-1.8.0-3.fc37.noarch 93/151 Installing : pkgconf-pkg-config-1.8.0-3.fc37.aarch64 94/151 Installing : perl-srpm-macros-1-46.fc37.noarch 95/151 Installing : pcre2-syntax-10.40-1.fc37.1.noarch 96/151 Installing : pcre2-10.40-1.fc37.1.aarch64 97/151 Installing : libselinux-3.5-1.fc37.aarch64 98/151 Installing : sed-4.8-11.fc37.aarch64 99/151 Installing : findutils-1:4.9.0-2.fc37.aarch64 100/151 Installing : libmount-2.38.1-1.fc37.aarch64 101/151 Installing : util-linux-core-2.38.1-1.fc37.aarch64 102/151 Installing : openssl-libs-1:3.0.9-1.fc37.aarch64 103/151 Installing : coreutils-9.1-8.fc37.aarch64 104/151 Running scriptlet: ca-certificates-2023.2.60-1.0.fc37.noarch 105/151 Installing : ca-certificates-2023.2.60-1.0.fc37.noarch 105/151 Running scriptlet: ca-certificates-2023.2.60-1.0.fc37.noarch 105/151 Installing : krb5-libs-1.19.2-13.fc37.aarch64 106/151 Installing : libtirpc-1.3.3-1.rc1.fc37.aarch64 107/151 Installing : gzip-1.12-2.fc37.aarch64 108/151 Running scriptlet: authselect-libs-1.4.2-1.fc37.aarch64 109/151 Installing : authselect-libs-1.4.2-1.fc37.aarch64 109/151 Installing : authselect-1.4.2-1.fc37.aarch64 110/151 Installing : cracklib-2.9.7-30.fc37.aarch64 111/151 Installing : libpwquality-1.4.5-3.fc37.aarch64 112/151 Installing : libnsl2-2.0.0-4.fc37.aarch64 113/151 Installing : pam-1.5.2-14.fc37.aarch64 114/151 Installing : libssh-0.10.5-1.fc37.aarch64 115/151 Installing : libevent-2.1.12-7.fc37.aarch64 116/151 Installing : openldap-2.6.4-1.fc37.aarch64 117/151 Installing : libcurl-7.85.0-10.fc37.aarch64 118/151 Installing : elfutils-debuginfod-client-0.189-3.fc37.aarch64 119/151 Installing : elfutils-libs-0.189-3.fc37.aarch64 120/151 Installing : binutils-gold-2.38-27.fc37.aarch64 121/151 Installing : binutils-2.38-27.fc37.aarch64 122/151 Running scriptlet: binutils-2.38-27.fc37.aarch64 122/151 Installing : elfutils-0.189-3.fc37.aarch64 123/151 Installing : gdb-minimal-13.2-2.fc37.aarch64 124/151 Installing : debugedit-5.0-7.fc37.aarch64 125/151 Installing : curl-7.85.0-10.fc37.aarch64 126/151 Installing : libarchive-3.6.1-3.fc37.aarch64 127/151 Running scriptlet: rpm-4.18.1-2.fc37.aarch64 128/151 Installing : rpm-4.18.1-2.fc37.aarch64 128/151 Installing : rpm-libs-4.18.1-2.fc37.aarch64 129/151 Installing : rpm-build-libs-4.18.1-2.fc37.aarch64 130/151 Installing : efi-srpm-macros-5-6.fc37.noarch 131/151 Installing : lua-srpm-macros-1-7.fc37.noarch 132/151 Installing : rpmautospec-rpm-macros-0.3.5-1.fc37.noarch 133/151 Installing : patch-2.7.6-17.fc37.aarch64 134/151 Installing : libsemanage-3.5-2.fc37.aarch64 135/151 Installing : shadow-utils-2:4.12.3-6.fc37.aarch64 136/151 Running scriptlet: libutempter-1.2.1-7.fc37.aarch64 137/151 Installing : libutempter-1.2.1-7.fc37.aarch64 137/151 Installing : tar-2:1.34-6.fc37.aarch64 138/151 Installing : openblas-srpm-macros-2-12.fc37.noarch 139/151 Installing : ocaml-srpm-macros-7-2.fc37.noarch 140/151 Installing : nim-srpm-macros-3-7.fc37.noarch 141/151 Installing : kernel-srpm-macros-1.0-15.fc37.noarch 142/151 Installing : fpc-srpm-macros-1.3-6.fc37.noarch 143/151 Installing : fonts-srpm-macros-1:2.0.5-9.fc37.noarch 144/151 Installing : go-srpm-macros-3.2.0-1.fc37.noarch 145/151 Installing : python-srpm-macros-3.11-6.fc37.noarch 146/151 Installing : redhat-rpm-config-229-1.fc37.noarch 147/151 Installing : rpm-build-4.18.1-2.fc37.aarch64 148/151 Installing : util-linux-2.38.1-1.fc37.aarch64 149/151 Installing : which-2.21-39.fc37.aarch64 150/151 Installing : info-6.8-4.fc37.aarch64 151/151 Running scriptlet: filesystem-3.18-2.fc37.aarch64 151/151 Running scriptlet: ca-certificates-2023.2.60-1.0.fc37.noarch 151/151 Running scriptlet: authselect-libs-1.4.2-1.fc37.aarch64 151/151 Running scriptlet: rpm-4.18.1-2.fc37.aarch64 151/151 Running scriptlet: info-6.8-4.fc37.aarch64 151/151 Verifying : basesystem-11-14.fc37.noarch 1/151 Verifying : bzip2-1.0.8-12.fc37.aarch64 2/151 Verifying : bzip2-libs-1.0.8-12.fc37.aarch64 3/151 Verifying : cpio-2.13-13.fc37.aarch64 4/151 Verifying : cracklib-2.9.7-30.fc37.aarch64 5/151 Verifying : crypto-policies-20220815-1.gite4ed860.fc37.noarc 6/151 Verifying : cyrus-sasl-lib-2.1.28-8.fc37.aarch64 7/151 Verifying : diffutils-3.8-3.fc37.aarch64 8/151 Verifying : dwz-0.14-7.fc37.aarch64 9/151 Verifying : ed-1.18-2.fc37.aarch64 10/151 Verifying : efi-srpm-macros-5-6.fc37.noarch 11/151 Verifying : file-5.42-4.fc37.aarch64 12/151 Verifying : file-libs-5.42-4.fc37.aarch64 13/151 Verifying : filesystem-3.18-2.fc37.aarch64 14/151 Verifying : findutils-1:4.9.0-2.fc37.aarch64 15/151 Verifying : fonts-srpm-macros-1:2.0.5-9.fc37.noarch 16/151 Verifying : fpc-srpm-macros-1.3-6.fc37.noarch 17/151 Verifying : gawk-5.1.1-4.fc37.aarch64 18/151 Verifying : gdbm-libs-1:1.23-2.fc37.aarch64 19/151 Verifying : gmp-1:6.2.1-3.fc37.aarch64 20/151 Verifying : go-srpm-macros-3.2.0-1.fc37.noarch 21/151 Verifying : grep-3.7-4.fc37.aarch64 22/151 Verifying : gzip-1.12-2.fc37.aarch64 23/151 Verifying : info-6.8-4.fc37.aarch64 24/151 Verifying : kernel-srpm-macros-1.0-15.fc37.noarch 25/151 Verifying : keyutils-libs-1.6.1-5.fc37.aarch64 26/151 Verifying : libacl-2.3.1-4.fc37.aarch64 27/151 Verifying : libattr-2.5.1-5.fc37.aarch64 28/151 Verifying : libblkid-2.38.1-1.fc37.aarch64 29/151 Verifying : libbrotli-1.0.9-9.fc37.aarch64 30/151 Verifying : libcap-2.48-5.fc37.aarch64 31/151 Verifying : libcap-ng-0.8.3-3.fc37.aarch64 32/151 Verifying : libcom_err-1.46.5-3.fc37.aarch64 33/151 Verifying : libdb-5.3.28-53.fc37.aarch64 34/151 Verifying : libevent-2.1.12-7.fc37.aarch64 35/151 Verifying : libfdisk-2.38.1-1.fc37.aarch64 36/151 Verifying : libmount-2.38.1-1.fc37.aarch64 37/151 Verifying : libnsl2-2.0.0-4.fc37.aarch64 38/151 Verifying : libpkgconf-1.8.0-3.fc37.aarch64 39/151 Verifying : libpsl-0.21.1-6.fc37.aarch64 40/151 Verifying : libsigsegv-2.14-3.fc37.aarch64 41/151 Verifying : libsmartcols-2.38.1-1.fc37.aarch64 42/151 Verifying : libunistring-1.0-2.fc37.aarch64 43/151 Verifying : libutempter-1.2.1-7.fc37.aarch64 44/151 Verifying : libuuid-2.38.1-1.fc37.aarch64 45/151 Verifying : libverto-0.3.2-4.fc37.aarch64 46/151 Verifying : lua-srpm-macros-1-7.fc37.noarch 47/151 Verifying : mpfr-4.1.0-10.fc37.aarch64 48/151 Verifying : nim-srpm-macros-3-7.fc37.noarch 49/151 Verifying : ocaml-srpm-macros-7-2.fc37.noarch 50/151 Verifying : openblas-srpm-macros-2-12.fc37.noarch 51/151 Verifying : pam-1.5.2-14.fc37.aarch64 52/151 Verifying : pam-libs-1.5.2-14.fc37.aarch64 53/151 Verifying : patch-2.7.6-17.fc37.aarch64 54/151 Verifying : pcre-8.45-1.fc37.2.aarch64 55/151 Verifying : pcre2-10.40-1.fc37.1.aarch64 56/151 Verifying : pcre2-syntax-10.40-1.fc37.1.noarch 57/151 Verifying : perl-srpm-macros-1-46.fc37.noarch 58/151 Verifying : pkgconf-1.8.0-3.fc37.aarch64 59/151 Verifying : pkgconf-m4-1.8.0-3.fc37.noarch 60/151 Verifying : pkgconf-pkg-config-1.8.0-3.fc37.aarch64 61/151 Verifying : popt-1.19-1.fc37.aarch64 62/151 Verifying : sed-4.8-11.fc37.aarch64 63/151 Verifying : setup-2.14.1-2.fc37.noarch 64/151 Verifying : unzip-6.0-58.fc37.aarch64 65/151 Verifying : util-linux-2.38.1-1.fc37.aarch64 66/151 Verifying : util-linux-core-2.38.1-1.fc37.aarch64 67/151 Verifying : zip-3.0-33.fc37.aarch64 68/151 Verifying : zlib-1.2.12-5.fc37.aarch64 69/151 Verifying : alternatives-1.24-1.fc37.aarch64 70/151 Verifying : ansible-srpm-macros-1-10.fc37.noarch 71/151 Verifying : audit-libs-3.1.2-1.fc37.aarch64 72/151 Verifying : authselect-1.4.2-1.fc37.aarch64 73/151 Verifying : authselect-libs-1.4.2-1.fc37.aarch64 74/151 Verifying : bash-5.2.15-1.fc37.aarch64 75/151 Verifying : binutils-2.38-27.fc37.aarch64 76/151 Verifying : binutils-gold-2.38-27.fc37.aarch64 77/151 Verifying : ca-certificates-2023.2.60-1.0.fc37.noarch 78/151 Verifying : coreutils-9.1-8.fc37.aarch64 79/151 Verifying : coreutils-common-9.1-8.fc37.aarch64 80/151 Verifying : curl-7.85.0-10.fc37.aarch64 81/151 Verifying : debugedit-5.0-7.fc37.aarch64 82/151 Verifying : elfutils-0.189-3.fc37.aarch64 83/151 Verifying : elfutils-debuginfod-client-0.189-3.fc37.aarch64 84/151 Verifying : elfutils-default-yama-scope-0.189-3.fc37.noarch 85/151 Verifying : elfutils-libelf-0.189-3.fc37.aarch64 86/151 Verifying : elfutils-libs-0.189-3.fc37.aarch64 87/151 Verifying : fedora-gpg-keys-37-2.noarch 88/151 Verifying : fedora-release-37-16.noarch 89/151 Verifying : fedora-release-common-37-16.noarch 90/151 Verifying : fedora-release-identity-basic-37-16.noarch 91/151 Verifying : fedora-repos-37-2.noarch 92/151 Verifying : gdb-minimal-13.2-2.fc37.aarch64 93/151 Verifying : ghc-srpm-macros-1.6.1-1.fc37.noarch 94/151 Verifying : glibc-2.36-11.fc37.aarch64 95/151 Verifying : glibc-common-2.36-11.fc37.aarch64 96/151 Verifying : glibc-gconv-extra-2.36-11.fc37.aarch64 97/151 Verifying : glibc-minimal-langpack-2.36-11.fc37.aarch64 98/151 Verifying : gnat-srpm-macros-5-1.fc37.noarch 99/151 Verifying : krb5-libs-1.19.2-13.fc37.aarch64 100/151 Verifying : libarchive-3.6.1-3.fc37.aarch64 101/151 Verifying : libcurl-7.85.0-10.fc37.aarch64 102/151 Verifying : libeconf-0.5.2-1.fc37.aarch64 103/151 Verifying : libffi-3.4.4-1.fc37.aarch64 104/151 Verifying : libgcc-12.3.1-1.fc37.aarch64 105/151 Verifying : libgomp-12.3.1-1.fc37.aarch64 106/151 Verifying : libidn2-2.3.4-1.fc37.aarch64 107/151 Verifying : libnghttp2-1.51.0-1.fc37.aarch64 108/151 Verifying : libpwquality-1.4.5-3.fc37.aarch64 109/151 Verifying : libselinux-3.5-1.fc37.aarch64 110/151 Verifying : libsemanage-3.5-2.fc37.aarch64 111/151 Verifying : libsepol-3.5-1.fc37.aarch64 112/151 Verifying : libssh-0.10.5-1.fc37.aarch64 113/151 Verifying : libssh-config-0.10.5-1.fc37.noarch 114/151 Verifying : libstdc++-12.3.1-1.fc37.aarch64 115/151 Verifying : libtasn1-4.19.0-1.fc37.aarch64 116/151 Verifying : libtirpc-1.3.3-1.rc1.fc37.aarch64 117/151 Verifying : libxcrypt-4.4.36-1.fc37.aarch64 118/151 Verifying : libxml2-2.10.4-1.fc37.aarch64 119/151 Verifying : libzstd-1.5.5-1.fc37.aarch64 120/151 Verifying : lua-libs-5.4.4-9.fc37.aarch64 121/151 Verifying : lz4-libs-1.9.4-1.fc37.aarch64 122/151 Verifying : ncurses-base-6.4-3.20230114.fc37.noarch 123/151 Verifying : ncurses-libs-6.4-3.20230114.fc37.aarch64 124/151 Verifying : openldap-2.6.4-1.fc37.aarch64 125/151 Verifying : openssl-libs-1:3.0.9-1.fc37.aarch64 126/151 Verifying : p11-kit-0.25.0-1.fc37.aarch64 127/151 Verifying : p11-kit-trust-0.25.0-1.fc37.aarch64 128/151 Verifying : package-notes-srpm-macros-0.5-7.fc37.noarch 129/151 Verifying : publicsuffix-list-dafsa-20230812-1.fc37.noarch 130/151 Verifying : pyproject-srpm-macros-1.9.0-1.fc37.noarch 131/151 Verifying : python-srpm-macros-3.11-6.fc37.noarch 132/151 Verifying : qt5-srpm-macros-5.15.9-1.fc37.noarch 133/151 Verifying : readline-8.2-2.fc37.aarch64 134/151 Verifying : redhat-rpm-config-229-1.fc37.noarch 135/151 Verifying : rpm-4.18.1-2.fc37.aarch64 136/151 Verifying : rpm-build-4.18.1-2.fc37.aarch64 137/151 Verifying : rpm-build-libs-4.18.1-2.fc37.aarch64 138/151 Verifying : rpm-libs-4.18.1-2.fc37.aarch64 139/151 Verifying : rpmautospec-rpm-macros-0.3.5-1.fc37.noarch 140/151 Verifying : rust-srpm-macros-24-4.fc37.noarch 141/151 Verifying : shadow-utils-2:4.12.3-6.fc37.aarch64 142/151 Verifying : sqlite-libs-3.40.0-1.fc37.aarch64 143/151 Verifying : systemd-libs-251.14-2.fc37.aarch64 144/151 Verifying : tar-2:1.34-6.fc37.aarch64 145/151 Verifying : tzdata-2023c-1.fc37.noarch 146/151 Verifying : which-2.21-39.fc37.aarch64 147/151 Verifying : xxhash-libs-0.8.2-1.fc37.aarch64 148/151 Verifying : xz-5.4.1-1.fc37.aarch64 149/151 Verifying : xz-libs-5.4.1-1.fc37.aarch64 150/151 Verifying : zstd-1.5.5-1.fc37.aarch64 151/151 Installed: alternatives-1.24-1.fc37.aarch64 ansible-srpm-macros-1-10.fc37.noarch audit-libs-3.1.2-1.fc37.aarch64 authselect-1.4.2-1.fc37.aarch64 authselect-libs-1.4.2-1.fc37.aarch64 basesystem-11-14.fc37.noarch bash-5.2.15-1.fc37.aarch64 binutils-2.38-27.fc37.aarch64 binutils-gold-2.38-27.fc37.aarch64 bzip2-1.0.8-12.fc37.aarch64 bzip2-libs-1.0.8-12.fc37.aarch64 ca-certificates-2023.2.60-1.0.fc37.noarch coreutils-9.1-8.fc37.aarch64 coreutils-common-9.1-8.fc37.aarch64 cpio-2.13-13.fc37.aarch64 cracklib-2.9.7-30.fc37.aarch64 crypto-policies-20220815-1.gite4ed860.fc37.noarch curl-7.85.0-10.fc37.aarch64 cyrus-sasl-lib-2.1.28-8.fc37.aarch64 debugedit-5.0-7.fc37.aarch64 diffutils-3.8-3.fc37.aarch64 dwz-0.14-7.fc37.aarch64 ed-1.18-2.fc37.aarch64 efi-srpm-macros-5-6.fc37.noarch elfutils-0.189-3.fc37.aarch64 elfutils-debuginfod-client-0.189-3.fc37.aarch64 elfutils-default-yama-scope-0.189-3.fc37.noarch elfutils-libelf-0.189-3.fc37.aarch64 elfutils-libs-0.189-3.fc37.aarch64 fedora-gpg-keys-37-2.noarch fedora-release-37-16.noarch fedora-release-common-37-16.noarch fedora-release-identity-basic-37-16.noarch fedora-repos-37-2.noarch file-5.42-4.fc37.aarch64 file-libs-5.42-4.fc37.aarch64 filesystem-3.18-2.fc37.aarch64 findutils-1:4.9.0-2.fc37.aarch64 fonts-srpm-macros-1:2.0.5-9.fc37.noarch fpc-srpm-macros-1.3-6.fc37.noarch gawk-5.1.1-4.fc37.aarch64 gdb-minimal-13.2-2.fc37.aarch64 gdbm-libs-1:1.23-2.fc37.aarch64 ghc-srpm-macros-1.6.1-1.fc37.noarch glibc-2.36-11.fc37.aarch64 glibc-common-2.36-11.fc37.aarch64 glibc-gconv-extra-2.36-11.fc37.aarch64 glibc-minimal-langpack-2.36-11.fc37.aarch64 gmp-1:6.2.1-3.fc37.aarch64 gnat-srpm-macros-5-1.fc37.noarch go-srpm-macros-3.2.0-1.fc37.noarch grep-3.7-4.fc37.aarch64 gzip-1.12-2.fc37.aarch64 info-6.8-4.fc37.aarch64 kernel-srpm-macros-1.0-15.fc37.noarch keyutils-libs-1.6.1-5.fc37.aarch64 krb5-libs-1.19.2-13.fc37.aarch64 libacl-2.3.1-4.fc37.aarch64 libarchive-3.6.1-3.fc37.aarch64 libattr-2.5.1-5.fc37.aarch64 libblkid-2.38.1-1.fc37.aarch64 libbrotli-1.0.9-9.fc37.aarch64 libcap-2.48-5.fc37.aarch64 libcap-ng-0.8.3-3.fc37.aarch64 libcom_err-1.46.5-3.fc37.aarch64 libcurl-7.85.0-10.fc37.aarch64 libdb-5.3.28-53.fc37.aarch64 libeconf-0.5.2-1.fc37.aarch64 libevent-2.1.12-7.fc37.aarch64 libfdisk-2.38.1-1.fc37.aarch64 libffi-3.4.4-1.fc37.aarch64 libgcc-12.3.1-1.fc37.aarch64 libgomp-12.3.1-1.fc37.aarch64 libidn2-2.3.4-1.fc37.aarch64 libmount-2.38.1-1.fc37.aarch64 libnghttp2-1.51.0-1.fc37.aarch64 libnsl2-2.0.0-4.fc37.aarch64 libpkgconf-1.8.0-3.fc37.aarch64 libpsl-0.21.1-6.fc37.aarch64 libpwquality-1.4.5-3.fc37.aarch64 libselinux-3.5-1.fc37.aarch64 libsemanage-3.5-2.fc37.aarch64 libsepol-3.5-1.fc37.aarch64 libsigsegv-2.14-3.fc37.aarch64 libsmartcols-2.38.1-1.fc37.aarch64 libssh-0.10.5-1.fc37.aarch64 libssh-config-0.10.5-1.fc37.noarch libstdc++-12.3.1-1.fc37.aarch64 libtasn1-4.19.0-1.fc37.aarch64 libtirpc-1.3.3-1.rc1.fc37.aarch64 libunistring-1.0-2.fc37.aarch64 libutempter-1.2.1-7.fc37.aarch64 libuuid-2.38.1-1.fc37.aarch64 libverto-0.3.2-4.fc37.aarch64 libxcrypt-4.4.36-1.fc37.aarch64 libxml2-2.10.4-1.fc37.aarch64 libzstd-1.5.5-1.fc37.aarch64 lua-libs-5.4.4-9.fc37.aarch64 lua-srpm-macros-1-7.fc37.noarch lz4-libs-1.9.4-1.fc37.aarch64 mpfr-4.1.0-10.fc37.aarch64 ncurses-base-6.4-3.20230114.fc37.noarch ncurses-libs-6.4-3.20230114.fc37.aarch64 nim-srpm-macros-3-7.fc37.noarch ocaml-srpm-macros-7-2.fc37.noarch openblas-srpm-macros-2-12.fc37.noarch openldap-2.6.4-1.fc37.aarch64 openssl-libs-1:3.0.9-1.fc37.aarch64 p11-kit-0.25.0-1.fc37.aarch64 p11-kit-trust-0.25.0-1.fc37.aarch64 package-notes-srpm-macros-0.5-7.fc37.noarch pam-1.5.2-14.fc37.aarch64 pam-libs-1.5.2-14.fc37.aarch64 patch-2.7.6-17.fc37.aarch64 pcre-8.45-1.fc37.2.aarch64 pcre2-10.40-1.fc37.1.aarch64 pcre2-syntax-10.40-1.fc37.1.noarch perl-srpm-macros-1-46.fc37.noarch pkgconf-1.8.0-3.fc37.aarch64 pkgconf-m4-1.8.0-3.fc37.noarch pkgconf-pkg-config-1.8.0-3.fc37.aarch64 popt-1.19-1.fc37.aarch64 publicsuffix-list-dafsa-20230812-1.fc37.noarch pyproject-srpm-macros-1.9.0-1.fc37.noarch python-srpm-macros-3.11-6.fc37.noarch qt5-srpm-macros-5.15.9-1.fc37.noarch readline-8.2-2.fc37.aarch64 redhat-rpm-config-229-1.fc37.noarch rpm-4.18.1-2.fc37.aarch64 rpm-build-4.18.1-2.fc37.aarch64 rpm-build-libs-4.18.1-2.fc37.aarch64 rpm-libs-4.18.1-2.fc37.aarch64 rpmautospec-rpm-macros-0.3.5-1.fc37.noarch rust-srpm-macros-24-4.fc37.noarch sed-4.8-11.fc37.aarch64 setup-2.14.1-2.fc37.noarch shadow-utils-2:4.12.3-6.fc37.aarch64 sqlite-libs-3.40.0-1.fc37.aarch64 systemd-libs-251.14-2.fc37.aarch64 tar-2:1.34-6.fc37.aarch64 tzdata-2023c-1.fc37.noarch unzip-6.0-58.fc37.aarch64 util-linux-2.38.1-1.fc37.aarch64 util-linux-core-2.38.1-1.fc37.aarch64 which-2.21-39.fc37.aarch64 xxhash-libs-0.8.2-1.fc37.aarch64 xz-5.4.1-1.fc37.aarch64 xz-libs-5.4.1-1.fc37.aarch64 zip-3.0-33.fc37.aarch64 zlib-1.2.12-5.fc37.aarch64 zstd-1.5.5-1.fc37.aarch64 Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: alternatives-1.24-1.fc37.aarch64 ansible-srpm-macros-1-10.fc37.noarch audit-libs-3.1.2-1.fc37.aarch64 authselect-1.4.2-1.fc37.aarch64 authselect-libs-1.4.2-1.fc37.aarch64 basesystem-11-14.fc37.noarch bash-5.2.15-1.fc37.aarch64 binutils-2.38-27.fc37.aarch64 binutils-gold-2.38-27.fc37.aarch64 bzip2-1.0.8-12.fc37.aarch64 bzip2-libs-1.0.8-12.fc37.aarch64 ca-certificates-2023.2.60-1.0.fc37.noarch coreutils-9.1-8.fc37.aarch64 coreutils-common-9.1-8.fc37.aarch64 cpio-2.13-13.fc37.aarch64 cracklib-2.9.7-30.fc37.aarch64 crypto-policies-20220815-1.gite4ed860.fc37.noarch curl-7.85.0-10.fc37.aarch64 cyrus-sasl-lib-2.1.28-8.fc37.aarch64 debugedit-5.0-7.fc37.aarch64 diffutils-3.8-3.fc37.aarch64 dwz-0.14-7.fc37.aarch64 ed-1.18-2.fc37.aarch64 efi-srpm-macros-5-6.fc37.noarch elfutils-0.189-3.fc37.aarch64 elfutils-debuginfod-client-0.189-3.fc37.aarch64 elfutils-default-yama-scope-0.189-3.fc37.noarch elfutils-libelf-0.189-3.fc37.aarch64 elfutils-libs-0.189-3.fc37.aarch64 fedora-gpg-keys-37-2.noarch fedora-release-37-16.noarch fedora-release-common-37-16.noarch fedora-release-identity-basic-37-16.noarch fedora-repos-37-2.noarch file-5.42-4.fc37.aarch64 file-libs-5.42-4.fc37.aarch64 filesystem-3.18-2.fc37.aarch64 findutils-4.9.0-2.fc37.aarch64 fonts-srpm-macros-2.0.5-9.fc37.noarch fpc-srpm-macros-1.3-6.fc37.noarch gawk-5.1.1-4.fc37.aarch64 gdb-minimal-13.2-2.fc37.aarch64 gdbm-libs-1.23-2.fc37.aarch64 ghc-srpm-macros-1.6.1-1.fc37.noarch glibc-2.36-11.fc37.aarch64 glibc-common-2.36-11.fc37.aarch64 glibc-gconv-extra-2.36-11.fc37.aarch64 glibc-minimal-langpack-2.36-11.fc37.aarch64 gmp-6.2.1-3.fc37.aarch64 gnat-srpm-macros-5-1.fc37.noarch go-srpm-macros-3.2.0-1.fc37.noarch gpg-pubkey-5323552a-6112bcdc grep-3.7-4.fc37.aarch64 gzip-1.12-2.fc37.aarch64 info-6.8-4.fc37.aarch64 kernel-srpm-macros-1.0-15.fc37.noarch keyutils-libs-1.6.1-5.fc37.aarch64 krb5-libs-1.19.2-13.fc37.aarch64 libacl-2.3.1-4.fc37.aarch64 libarchive-3.6.1-3.fc37.aarch64 libattr-2.5.1-5.fc37.aarch64 libblkid-2.38.1-1.fc37.aarch64 libbrotli-1.0.9-9.fc37.aarch64 libcap-2.48-5.fc37.aarch64 libcap-ng-0.8.3-3.fc37.aarch64 libcom_err-1.46.5-3.fc37.aarch64 libcurl-7.85.0-10.fc37.aarch64 libdb-5.3.28-53.fc37.aarch64 libeconf-0.5.2-1.fc37.aarch64 libevent-2.1.12-7.fc37.aarch64 libfdisk-2.38.1-1.fc37.aarch64 libffi-3.4.4-1.fc37.aarch64 libgcc-12.3.1-1.fc37.aarch64 libgomp-12.3.1-1.fc37.aarch64 libidn2-2.3.4-1.fc37.aarch64 libmount-2.38.1-1.fc37.aarch64 libnghttp2-1.51.0-1.fc37.aarch64 libnsl2-2.0.0-4.fc37.aarch64 libpkgconf-1.8.0-3.fc37.aarch64 libpsl-0.21.1-6.fc37.aarch64 libpwquality-1.4.5-3.fc37.aarch64 libselinux-3.5-1.fc37.aarch64 libsemanage-3.5-2.fc37.aarch64 libsepol-3.5-1.fc37.aarch64 libsigsegv-2.14-3.fc37.aarch64 libsmartcols-2.38.1-1.fc37.aarch64 libssh-0.10.5-1.fc37.aarch64 libssh-config-0.10.5-1.fc37.noarch libstdc++-12.3.1-1.fc37.aarch64 libtasn1-4.19.0-1.fc37.aarch64 libtirpc-1.3.3-1.rc1.fc37.aarch64 libunistring-1.0-2.fc37.aarch64 libutempter-1.2.1-7.fc37.aarch64 libuuid-2.38.1-1.fc37.aarch64 libverto-0.3.2-4.fc37.aarch64 libxcrypt-4.4.36-1.fc37.aarch64 libxml2-2.10.4-1.fc37.aarch64 libzstd-1.5.5-1.fc37.aarch64 lua-libs-5.4.4-9.fc37.aarch64 lua-srpm-macros-1-7.fc37.noarch lz4-libs-1.9.4-1.fc37.aarch64 mpfr-4.1.0-10.fc37.aarch64 ncurses-base-6.4-3.20230114.fc37.noarch ncurses-libs-6.4-3.20230114.fc37.aarch64 nim-srpm-macros-3-7.fc37.noarch ocaml-srpm-macros-7-2.fc37.noarch openblas-srpm-macros-2-12.fc37.noarch openldap-2.6.4-1.fc37.aarch64 openssl-libs-3.0.9-1.fc37.aarch64 p11-kit-0.25.0-1.fc37.aarch64 p11-kit-trust-0.25.0-1.fc37.aarch64 package-notes-srpm-macros-0.5-7.fc37.noarch pam-1.5.2-14.fc37.aarch64 pam-libs-1.5.2-14.fc37.aarch64 patch-2.7.6-17.fc37.aarch64 pcre-8.45-1.fc37.2.aarch64 pcre2-10.40-1.fc37.1.aarch64 pcre2-syntax-10.40-1.fc37.1.noarch perl-srpm-macros-1-46.fc37.noarch pkgconf-1.8.0-3.fc37.aarch64 pkgconf-m4-1.8.0-3.fc37.noarch pkgconf-pkg-config-1.8.0-3.fc37.aarch64 popt-1.19-1.fc37.aarch64 publicsuffix-list-dafsa-20230812-1.fc37.noarch pyproject-srpm-macros-1.9.0-1.fc37.noarch python-srpm-macros-3.11-6.fc37.noarch qt5-srpm-macros-5.15.9-1.fc37.noarch readline-8.2-2.fc37.aarch64 redhat-rpm-config-229-1.fc37.noarch rpm-4.18.1-2.fc37.aarch64 rpm-build-4.18.1-2.fc37.aarch64 rpm-build-libs-4.18.1-2.fc37.aarch64 rpm-libs-4.18.1-2.fc37.aarch64 rpmautospec-rpm-macros-0.3.5-1.fc37.noarch rust-srpm-macros-24-4.fc37.noarch sed-4.8-11.fc37.aarch64 setup-2.14.1-2.fc37.noarch shadow-utils-4.12.3-6.fc37.aarch64 sqlite-libs-3.40.0-1.fc37.aarch64 systemd-libs-251.14-2.fc37.aarch64 tar-1.34-6.fc37.aarch64 tzdata-2023c-1.fc37.noarch unzip-6.0-58.fc37.aarch64 util-linux-2.38.1-1.fc37.aarch64 util-linux-core-2.38.1-1.fc37.aarch64 which-2.21-39.fc37.aarch64 xxhash-libs-0.8.2-1.fc37.aarch64 xz-5.4.1-1.fc37.aarch64 xz-libs-5.4.1-1.fc37.aarch64 zip-3.0-33.fc37.aarch64 zlib-1.2.12-5.fc37.aarch64 zstd-1.5.5-1.fc37.aarch64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Finish: rpmbuild -bs INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.rpm.log /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.librepo.log /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.log Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-cl1nk4q3/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(child) 1 minutes 27 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm) Config(fedora-37-aarch64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-37-aarch64-bootstrap-1695260627.623462/root. INFO: reusing tmpfs at /var/lib/mock/fedora-37-aarch64-bootstrap-1695260627.623462/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-37-aarch64-1695260627.623462/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin Finish: chroot init INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.18.1-2.fc37.aarch64 python3-dnf-4.16.2-1.fc37.noarch python3-dnf-plugins-core-4.4.2-1.fc37.noarch yum-4.16.2-1.fc37.noarch Start: build phase for litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Start: build setup for litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 36 kB/s | 2.1 kB 00:00 Additional repo copr_rezso_ML 53 kB/s | 1.8 kB 00:00 Additional repo copr_rezso_CUDA 55 kB/s | 1.8 kB 00:00 Additional repo http_developer_download_nvidia_ 1.1 MB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 1.1 MB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 1.1 MB/s | 3.5 kB 00:00 fedora 124 kB/s | 14 kB 00:00 updates 39 kB/s | 12 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: git aarch64 2.41.0-1.fc37 updates 54 k python3-devel aarch64 3.11.5-1.fc37 updates 269 k python3-setuptools noarch 62.6.0-3.fc37 updates 1.6 M Installing dependencies: expat aarch64 2.5.0-1.fc37 updates 106 k git-core aarch64 2.41.0-1.fc37 updates 4.4 M git-core-doc noarch 2.41.0-1.fc37 updates 2.8 M groff-base aarch64 1.22.4-10.fc37 fedora 1.0 M less aarch64 633-1.fc37 updates 175 k libb2 aarch64 0.98.1-7.fc37 fedora 24 k libcbor aarch64 0.7.0-7.fc37 fedora 55 k libedit aarch64 3.1-43.20221009cvs.fc37 updates 105 k libfido2 aarch64 1.11.0-3.fc37 fedora 96 k mpdecimal aarch64 2.5.1-4.fc37 fedora 102 k ncurses aarch64 6.4-3.20230114.fc37 updates 410 k openssh aarch64 8.8p1-11.fc37 updates 439 k openssh-clients aarch64 8.8p1-11.fc37 updates 669 k perl-Carp noarch 1.52-489.fc37 fedora 29 k perl-Class-Struct noarch 0.66-494.fc37 updates 23 k perl-DynaLoader aarch64 1.52-494.fc37 updates 27 k perl-Encode aarch64 4:3.19-492.fc37 fedora 1.7 M perl-Errno aarch64 1.36-494.fc37 updates 16 k perl-Error noarch 1:0.17029-10.fc37 fedora 41 k perl-Exporter noarch 5.77-489.fc37 fedora 31 k perl-Fcntl aarch64 1.15-494.fc37 updates 22 k perl-File-Basename noarch 2.85-494.fc37 updates 18 k perl-File-Find noarch 1.40-494.fc37 updates 26 k perl-File-Path noarch 2.18-489.fc37 fedora 35 k perl-File-Temp noarch 1:0.231.100-489.fc37 fedora 59 k perl-File-stat noarch 1.12-494.fc37 updates 18 k perl-Getopt-Long noarch 1:2.54-1.fc37 updates 60 k perl-Getopt-Std noarch 1.13-494.fc37 updates 17 k perl-Git noarch 2.41.0-1.fc37 updates 42 k perl-HTTP-Tiny noarch 0.086-1.fc37 updates 55 k perl-IO aarch64 1.50-494.fc37 updates 93 k perl-IPC-Open3 noarch 1.22-494.fc37 updates 24 k perl-MIME-Base64 aarch64 3.16-489.fc37 fedora 30 k perl-POSIX aarch64 2.03-494.fc37 updates 99 k perl-PathTools aarch64 3.84-489.fc37 fedora 90 k perl-Pod-Escapes noarch 1:1.07-489.fc37 fedora 20 k perl-Pod-Perldoc noarch 3.28.01-490.fc37 fedora 90 k perl-Pod-Simple noarch 1:3.43-490.fc37 fedora 225 k perl-Pod-Usage noarch 4:2.03-3.fc37 fedora 40 k perl-Scalar-List-Utils aarch64 5:1.63-489.fc37 fedora 71 k perl-SelectSaver noarch 1.02-494.fc37 updates 13 k perl-Socket aarch64 4:2.036-1.fc37 fedora 55 k perl-Storable aarch64 1:3.26-489.fc37 fedora 95 k perl-Symbol noarch 1.09-494.fc37 updates 15 k perl-Term-ANSIColor noarch 5.01-490.fc37 fedora 48 k perl-Term-Cap noarch 1.17-489.fc37 fedora 22 k perl-TermReadKey aarch64 2.38-14.fc37 fedora 36 k perl-Text-ParseWords noarch 3.31-489.fc37 fedora 16 k perl-Text-Tabs+Wrap noarch 2023.0511-1.fc37 updates 23 k perl-Time-Local noarch 2:1.300-489.fc37 fedora 33 k perl-constant noarch 1.33-490.fc37 fedora 23 k perl-if noarch 0.61.000-494.fc37 updates 15 k perl-interpreter aarch64 4:5.36.1-494.fc37 updates 73 k perl-lib aarch64 0.65-494.fc37 updates 16 k perl-libs aarch64 4:5.36.1-494.fc37 updates 2.2 M perl-locale noarch 1.10-494.fc37 updates 15 k perl-mro aarch64 1.26-494.fc37 updates 29 k perl-overload noarch 1.35-494.fc37 updates 47 k perl-overloading noarch 0.02-494.fc37 updates 14 k perl-parent noarch 1:0.238-489.fc37 fedora 14 k perl-podlators noarch 1:4.14-489.fc37 fedora 116 k perl-subs noarch 1.04-494.fc37 updates 13 k perl-vars noarch 1.05-494.fc37 updates 14 k pyproject-rpm-macros noarch 1.9.0-1.fc37 updates 42 k python-pip-wheel noarch 22.2.2-3.fc37 updates 1.4 M python-rpm-macros noarch 3.11-6.fc37 updates 19 k python-setuptools-wheel noarch 62.6.0-3.fc37 updates 711 k python3 aarch64 3.11.5-1.fc37 updates 28 k python3-libs aarch64 3.11.5-1.fc37 updates 9.5 M python3-packaging noarch 21.3-6.fc37 fedora 98 k python3-pyparsing noarch 3.0.9-2.fc37 fedora 262 k python3-rpm-generators noarch 13-3.fc37 updates 29 k python3-rpm-macros noarch 3.11-6.fc37 updates 14 k Transaction Summary ================================================================================ Install 76 Packages Total download size: 30 M Installed size: 130 M Downloading Packages: (1/76): libb2-0.98.1-7.fc37.aarch64.rpm 315 kB/s | 24 kB 00:00 (2/76): libfido2-1.11.0-3.fc37.aarch64.rpm 24 MB/s | 96 kB 00:00 (3/76): libcbor-0.7.0-7.fc37.aarch64.rpm 669 kB/s | 55 kB 00:00 (4/76): perl-Carp-1.52-489.fc37.noarch.rpm 9.1 MB/s | 29 kB 00:00 (5/76): mpdecimal-2.5.1-4.fc37.aarch64.rpm 17 MB/s | 102 kB 00:00 (6/76): perl-Error-0.17029-10.fc37.noarch.rpm 15 MB/s | 41 kB 00:00 (7/76): groff-base-1.22.4-10.fc37.aarch64.rpm 11 MB/s | 1.0 MB 00:00 (8/76): perl-Exporter-5.77-489.fc37.noarch.rpm 10 MB/s | 31 kB 00:00 (9/76): perl-File-Path-2.18-489.fc37.noarch.rpm 10 MB/s | 35 kB 00:00 (10/76): perl-File-Temp-0.231.100-489.fc37.noar 12 MB/s | 59 kB 00:00 (11/76): perl-MIME-Base64-3.16-489.fc37.aarch64 8.1 MB/s | 30 kB 00:00 (12/76): perl-Pod-Escapes-1.07-489.fc37.noarch. 7.6 MB/s | 20 kB 00:00 (13/76): perl-Pod-Perldoc-3.28.01-490.fc37.noar 26 MB/s | 90 kB 00:00 (14/76): perl-PathTools-3.84-489.fc37.aarch64.r 11 MB/s | 90 kB 00:00 (15/76): perl-Pod-Usage-2.03-3.fc37.noarch.rpm 13 MB/s | 40 kB 00:00 (16/76): perl-Pod-Simple-3.43-490.fc37.noarch.r 37 MB/s | 225 kB 00:00 (17/76): perl-Scalar-List-Utils-1.63-489.fc37.a 15 MB/s | 71 kB 00:00 (18/76): perl-Socket-2.036-1.fc37.aarch64.rpm 9.8 MB/s | 55 kB 00:00 (19/76): perl-Storable-3.26-489.fc37.aarch64.rp 19 MB/s | 95 kB 00:00 (20/76): perl-Term-ANSIColor-5.01-490.fc37.noar 16 MB/s | 48 kB 00:00 (21/76): perl-Term-Cap-1.17-489.fc37.noarch.rpm 4.5 MB/s | 22 kB 00:00 (22/76): perl-TermReadKey-2.38-14.fc37.aarch64. 6.8 MB/s | 36 kB 00:00 (23/76): perl-Encode-3.19-492.fc37.aarch64.rpm 38 MB/s | 1.7 MB 00:00 (24/76): perl-Time-Local-1.300-489.fc37.noarch. 7.6 MB/s | 33 kB 00:00 (25/76): perl-parent-0.238-489.fc37.noarch.rpm 7.3 MB/s | 14 kB 00:00 (26/76): perl-Text-ParseWords-3.31-489.fc37.noa 1.8 MB/s | 16 kB 00:00 (27/76): perl-constant-1.33-490.fc37.noarch.rpm 6.6 MB/s | 23 kB 00:00 (28/76): perl-podlators-4.14-489.fc37.noarch.rp 32 MB/s | 116 kB 00:00 (29/76): python3-packaging-21.3-6.fc37.noarch.r 24 MB/s | 98 kB 00:00 (30/76): python3-pyparsing-3.0.9-2.fc37.noarch. 45 MB/s | 262 kB 00:00 (31/76): git-2.41.0-1.fc37.aarch64.rpm 8.4 MB/s | 54 kB 00:00 (32/76): expat-2.5.0-1.fc37.aarch64.rpm 11 MB/s | 106 kB 00:00 (33/76): less-633-1.fc37.aarch64.rpm 43 MB/s | 175 kB 00:00 (34/76): libedit-3.1-43.20221009cvs.fc37.aarch6 21 MB/s | 105 kB 00:00 (35/76): ncurses-6.4-3.20230114.fc37.aarch64.rp 45 MB/s | 410 kB 00:00 (36/76): openssh-8.8p1-11.fc37.aarch64.rpm 40 MB/s | 439 kB 00:00 (37/76): openssh-clients-8.8p1-11.fc37.aarch64. 49 MB/s | 669 kB 00:00 (38/76): git-core-doc-2.41.0-1.fc37.noarch.rpm 53 MB/s | 2.8 MB 00:00 (39/76): perl-Class-Struct-0.66-494.fc37.noarch 3.5 MB/s | 23 kB 00:00 (40/76): perl-DynaLoader-1.52-494.fc37.aarch64. 7.4 MB/s | 27 kB 00:00 (41/76): perl-Errno-1.36-494.fc37.aarch64.rpm 4.0 MB/s | 16 kB 00:00 (42/76): perl-Fcntl-1.15-494.fc37.aarch64.rpm 8.4 MB/s | 22 kB 00:00 (43/76): perl-File-Basename-2.85-494.fc37.noarc 8.3 MB/s | 18 kB 00:00 (44/76): git-core-2.41.0-1.fc37.aarch64.rpm 60 MB/s | 4.4 MB 00:00 (45/76): perl-File-Find-1.40-494.fc37.noarch.rp 3.0 MB/s | 26 kB 00:00 (46/76): perl-File-stat-1.12-494.fc37.noarch.rp 2.2 MB/s | 18 kB 00:00 (47/76): perl-Getopt-Std-1.13-494.fc37.noarch.r 6.7 MB/s | 17 kB 00:00 (48/76): perl-Git-2.41.0-1.fc37.noarch.rpm 13 MB/s | 42 kB 00:00 (49/76): perl-Getopt-Long-2.54-1.fc37.noarch.rp 13 MB/s | 60 kB 00:00 (50/76): perl-HTTP-Tiny-0.086-1.fc37.noarch.rpm 16 MB/s | 55 kB 00:00 (51/76): perl-IO-1.50-494.fc37.aarch64.rpm 26 MB/s | 93 kB 00:00 (52/76): perl-IPC-Open3-1.22-494.fc37.noarch.rp 6.3 MB/s | 24 kB 00:00 (53/76): perl-POSIX-2.03-494.fc37.aarch64.rpm 29 MB/s | 99 kB 00:00 (54/76): perl-SelectSaver-1.02-494.fc37.noarch. 4.4 MB/s | 13 kB 00:00 (55/76): perl-Symbol-1.09-494.fc37.noarch.rpm 4.9 MB/s | 15 kB 00:00 (56/76): perl-Text-Tabs+Wrap-2023.0511-1.fc37.n 9.5 MB/s | 23 kB 00:00 (57/76): perl-if-0.61.000-494.fc37.noarch.rpm 5.4 MB/s | 15 kB 00:00 (58/76): perl-interpreter-5.36.1-494.fc37.aarch 18 MB/s | 73 kB 00:00 (59/76): perl-lib-0.65-494.fc37.aarch64.rpm 7.3 MB/s | 16 kB 00:00 (60/76): perl-locale-1.10-494.fc37.noarch.rpm 4.7 MB/s | 15 kB 00:00 (61/76): perl-mro-1.26-494.fc37.aarch64.rpm 7.3 MB/s | 29 kB 00:00 (62/76): perl-overloading-0.02-494.fc37.noarch. 6.2 MB/s | 14 kB 00:00 (63/76): perl-overload-1.35-494.fc37.noarch.rpm 9.2 MB/s | 47 kB 00:00 (64/76): perl-subs-1.04-494.fc37.noarch.rpm 5.7 MB/s | 13 kB 00:00 (65/76): perl-vars-1.05-494.fc37.noarch.rpm 4.8 MB/s | 14 kB 00:00 (66/76): pyproject-rpm-macros-1.9.0-1.fc37.noar 12 MB/s | 42 kB 00:00 (67/76): python-rpm-macros-3.11-6.fc37.noarch.r 8.7 MB/s | 19 kB 00:00 (68/76): python-setuptools-wheel-62.6.0-3.fc37. 105 MB/s | 711 kB 00:00 (69/76): python3-3.11.5-1.fc37.aarch64.rpm 10 MB/s | 28 kB 00:00 (70/76): python3-devel-3.11.5-1.fc37.aarch64.rp 49 MB/s | 269 kB 00:00 (71/76): python-pip-wheel-22.2.2-3.fc37.noarch. 42 MB/s | 1.4 MB 00:00 (72/76): python3-rpm-generators-13-3.fc37.noarc 12 MB/s | 29 kB 00:00 (73/76): python3-rpm-macros-3.11-6.fc37.noarch. 7.5 MB/s | 14 kB 00:00 (74/76): perl-libs-5.36.1-494.fc37.aarch64.rpm 39 MB/s | 2.2 MB 00:00 (75/76): python3-setuptools-62.6.0-3.fc37.noarc 153 MB/s | 1.6 MB 00:00 (76/76): python3-libs-3.11.5-1.fc37.aarch64.rpm 62 MB/s | 9.5 MB 00:00 -------------------------------------------------------------------------------- Total 52 MB/s | 30 MB 00:00 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.11-6.fc37.noarch 1/76 Installing : python3-rpm-macros-3.11-6.fc37.noarch 2/76 Installing : expat-2.5.0-1.fc37.aarch64 3/76 Installing : pyproject-rpm-macros-1.9.0-1.fc37.noarch 4/76 Installing : python-setuptools-wheel-62.6.0-3.fc37.noarch 5/76 Installing : python-pip-wheel-22.2.2-3.fc37.noarch 6/76 Running scriptlet: openssh-8.8p1-11.fc37.aarch64 7/76 Installing : openssh-8.8p1-11.fc37.aarch64 7/76 Installing : ncurses-6.4-3.20230114.fc37.aarch64 8/76 Installing : libedit-3.1-43.20221009cvs.fc37.aarch64 9/76 Installing : less-633-1.fc37.aarch64 10/76 Installing : mpdecimal-2.5.1-4.fc37.aarch64 11/76 Installing : libcbor-0.7.0-7.fc37.aarch64 12/76 Installing : libfido2-1.11.0-3.fc37.aarch64 13/76 Installing : openssh-clients-8.8p1-11.fc37.aarch64 14/76 Running scriptlet: openssh-clients-8.8p1-11.fc37.aarch64 14/76 Installing : git-core-2.41.0-1.fc37.aarch64 15/76 Installing : git-core-doc-2.41.0-1.fc37.noarch 16/76 Installing : libb2-0.98.1-7.fc37.aarch64 17/76 Installing : python3-3.11.5-1.fc37.aarch64 18/76 Installing : python3-libs-3.11.5-1.fc37.aarch64 19/76 Installing : python3-pyparsing-3.0.9-2.fc37.noarch 20/76 Installing : python3-packaging-21.3-6.fc37.noarch 21/76 Installing : python3-rpm-generators-13-3.fc37.noarch 22/76 Running scriptlet: groff-base-1.22.4-10.fc37.aarch64 23/76 Installing : groff-base-1.22.4-10.fc37.aarch64 23/76 Running scriptlet: groff-base-1.22.4-10.fc37.aarch64 23/76 Installing : perl-Time-Local-2:1.300-489.fc37.noarch 24/76 Installing : perl-Text-Tabs+Wrap-2023.0511-1.fc37.noarch 25/76 Installing : perl-if-0.61.000-494.fc37.noarch 26/76 Installing : perl-locale-1.10-494.fc37.noarch 27/76 Installing : perl-File-Path-2.18-489.fc37.noarch 28/76 Installing : perl-Pod-Escapes-1:1.07-489.fc37.noarch 29/76 Installing : perl-Term-ANSIColor-5.01-490.fc37.noarch 30/76 Installing : perl-Class-Struct-0.66-494.fc37.noarch 31/76 Installing : perl-POSIX-2.03-494.fc37.aarch64 32/76 Installing : perl-HTTP-Tiny-0.086-1.fc37.noarch 33/76 Installing : perl-IPC-Open3-1.22-494.fc37.noarch 34/76 Installing : perl-subs-1.04-494.fc37.noarch 35/76 Installing : perl-File-Temp-1:0.231.100-489.fc37.noarch 36/76 Installing : perl-Term-Cap-1.17-489.fc37.noarch 37/76 Installing : perl-Pod-Simple-1:3.43-490.fc37.noarch 38/76 Installing : perl-Socket-4:2.036-1.fc37.aarch64 39/76 Installing : perl-SelectSaver-1.02-494.fc37.noarch 40/76 Installing : perl-Symbol-1.09-494.fc37.noarch 41/76 Installing : perl-File-stat-1.12-494.fc37.noarch 42/76 Installing : perl-podlators-1:4.14-489.fc37.noarch 43/76 Installing : perl-Pod-Perldoc-3.28.01-490.fc37.noarch 44/76 Installing : perl-Text-ParseWords-3.31-489.fc37.noarch 45/76 Installing : perl-Fcntl-1.15-494.fc37.aarch64 46/76 Installing : perl-mro-1.26-494.fc37.aarch64 47/76 Installing : perl-IO-1.50-494.fc37.aarch64 48/76 Installing : perl-overloading-0.02-494.fc37.noarch 49/76 Installing : perl-Pod-Usage-4:2.03-3.fc37.noarch 50/76 Installing : perl-MIME-Base64-3.16-489.fc37.aarch64 51/76 Installing : perl-Scalar-List-Utils-5:1.63-489.fc37.aarch64 52/76 Installing : perl-constant-1.33-490.fc37.noarch 53/76 Installing : perl-parent-1:0.238-489.fc37.noarch 54/76 Installing : perl-Errno-1.36-494.fc37.aarch64 55/76 Installing : perl-File-Basename-2.85-494.fc37.noarch 56/76 Installing : perl-Getopt-Std-1.13-494.fc37.noarch 57/76 Installing : perl-Storable-1:3.26-489.fc37.aarch64 58/76 Installing : perl-overload-1.35-494.fc37.noarch 59/76 Installing : perl-vars-1.05-494.fc37.noarch 60/76 Installing : perl-Getopt-Long-1:2.54-1.fc37.noarch 61/76 Installing : perl-Carp-1.52-489.fc37.noarch 62/76 Installing : perl-Exporter-5.77-489.fc37.noarch 63/76 Installing : perl-PathTools-3.84-489.fc37.aarch64 64/76 Installing : perl-DynaLoader-1.52-494.fc37.aarch64 65/76 Installing : perl-Encode-4:3.19-492.fc37.aarch64 66/76 Installing : perl-libs-4:5.36.1-494.fc37.aarch64 67/76 Installing : perl-interpreter-4:5.36.1-494.fc37.aarch64 68/76 Installing : perl-Error-1:0.17029-10.fc37.noarch 69/76 Installing : perl-TermReadKey-2.38-14.fc37.aarch64 70/76 Installing : perl-File-Find-1.40-494.fc37.noarch 71/76 Installing : perl-lib-0.65-494.fc37.aarch64 72/76 Installing : perl-Git-2.41.0-1.fc37.noarch 73/76 Installing : git-2.41.0-1.fc37.aarch64 74/76 Installing : python3-devel-3.11.5-1.fc37.aarch64 75/76 Installing : python3-setuptools-62.6.0-3.fc37.noarch 76/76 Running scriptlet: python3-setuptools-62.6.0-3.fc37.noarch 76/76 Verifying : groff-base-1.22.4-10.fc37.aarch64 1/76 Verifying : libb2-0.98.1-7.fc37.aarch64 2/76 Verifying : libcbor-0.7.0-7.fc37.aarch64 3/76 Verifying : libfido2-1.11.0-3.fc37.aarch64 4/76 Verifying : mpdecimal-2.5.1-4.fc37.aarch64 5/76 Verifying : perl-Carp-1.52-489.fc37.noarch 6/76 Verifying : perl-Encode-4:3.19-492.fc37.aarch64 7/76 Verifying : perl-Error-1:0.17029-10.fc37.noarch 8/76 Verifying : perl-Exporter-5.77-489.fc37.noarch 9/76 Verifying : perl-File-Path-2.18-489.fc37.noarch 10/76 Verifying : perl-File-Temp-1:0.231.100-489.fc37.noarch 11/76 Verifying : perl-MIME-Base64-3.16-489.fc37.aarch64 12/76 Verifying : perl-PathTools-3.84-489.fc37.aarch64 13/76 Verifying : perl-Pod-Escapes-1:1.07-489.fc37.noarch 14/76 Verifying : perl-Pod-Perldoc-3.28.01-490.fc37.noarch 15/76 Verifying : perl-Pod-Simple-1:3.43-490.fc37.noarch 16/76 Verifying : perl-Pod-Usage-4:2.03-3.fc37.noarch 17/76 Verifying : perl-Scalar-List-Utils-5:1.63-489.fc37.aarch64 18/76 Verifying : perl-Socket-4:2.036-1.fc37.aarch64 19/76 Verifying : perl-Storable-1:3.26-489.fc37.aarch64 20/76 Verifying : perl-Term-ANSIColor-5.01-490.fc37.noarch 21/76 Verifying : perl-Term-Cap-1.17-489.fc37.noarch 22/76 Verifying : perl-TermReadKey-2.38-14.fc37.aarch64 23/76 Verifying : perl-Text-ParseWords-3.31-489.fc37.noarch 24/76 Verifying : perl-Time-Local-2:1.300-489.fc37.noarch 25/76 Verifying : perl-constant-1.33-490.fc37.noarch 26/76 Verifying : perl-parent-1:0.238-489.fc37.noarch 27/76 Verifying : perl-podlators-1:4.14-489.fc37.noarch 28/76 Verifying : python3-packaging-21.3-6.fc37.noarch 29/76 Verifying : python3-pyparsing-3.0.9-2.fc37.noarch 30/76 Verifying : expat-2.5.0-1.fc37.aarch64 31/76 Verifying : git-2.41.0-1.fc37.aarch64 32/76 Verifying : git-core-2.41.0-1.fc37.aarch64 33/76 Verifying : git-core-doc-2.41.0-1.fc37.noarch 34/76 Verifying : less-633-1.fc37.aarch64 35/76 Verifying : libedit-3.1-43.20221009cvs.fc37.aarch64 36/76 Verifying : ncurses-6.4-3.20230114.fc37.aarch64 37/76 Verifying : openssh-8.8p1-11.fc37.aarch64 38/76 Verifying : openssh-clients-8.8p1-11.fc37.aarch64 39/76 Verifying : perl-Class-Struct-0.66-494.fc37.noarch 40/76 Verifying : perl-DynaLoader-1.52-494.fc37.aarch64 41/76 Verifying : perl-Errno-1.36-494.fc37.aarch64 42/76 Verifying : perl-Fcntl-1.15-494.fc37.aarch64 43/76 Verifying : perl-File-Basename-2.85-494.fc37.noarch 44/76 Verifying : perl-File-Find-1.40-494.fc37.noarch 45/76 Verifying : perl-File-stat-1.12-494.fc37.noarch 46/76 Verifying : perl-Getopt-Long-1:2.54-1.fc37.noarch 47/76 Verifying : perl-Getopt-Std-1.13-494.fc37.noarch 48/76 Verifying : perl-Git-2.41.0-1.fc37.noarch 49/76 Verifying : perl-HTTP-Tiny-0.086-1.fc37.noarch 50/76 Verifying : perl-IO-1.50-494.fc37.aarch64 51/76 Verifying : perl-IPC-Open3-1.22-494.fc37.noarch 52/76 Verifying : perl-POSIX-2.03-494.fc37.aarch64 53/76 Verifying : perl-SelectSaver-1.02-494.fc37.noarch 54/76 Verifying : perl-Symbol-1.09-494.fc37.noarch 55/76 Verifying : perl-Text-Tabs+Wrap-2023.0511-1.fc37.noarch 56/76 Verifying : perl-if-0.61.000-494.fc37.noarch 57/76 Verifying : perl-interpreter-4:5.36.1-494.fc37.aarch64 58/76 Verifying : perl-lib-0.65-494.fc37.aarch64 59/76 Verifying : perl-libs-4:5.36.1-494.fc37.aarch64 60/76 Verifying : perl-locale-1.10-494.fc37.noarch 61/76 Verifying : perl-mro-1.26-494.fc37.aarch64 62/76 Verifying : perl-overload-1.35-494.fc37.noarch 63/76 Verifying : perl-overloading-0.02-494.fc37.noarch 64/76 Verifying : perl-subs-1.04-494.fc37.noarch 65/76 Verifying : perl-vars-1.05-494.fc37.noarch 66/76 Verifying : pyproject-rpm-macros-1.9.0-1.fc37.noarch 67/76 Verifying : python-pip-wheel-22.2.2-3.fc37.noarch 68/76 Verifying : python-rpm-macros-3.11-6.fc37.noarch 69/76 Verifying : python-setuptools-wheel-62.6.0-3.fc37.noarch 70/76 Verifying : python3-3.11.5-1.fc37.aarch64 71/76 Verifying : python3-devel-3.11.5-1.fc37.aarch64 72/76 Verifying : python3-libs-3.11.5-1.fc37.aarch64 73/76 Verifying : python3-rpm-generators-13-3.fc37.noarch 74/76 Verifying : python3-rpm-macros-3.11-6.fc37.noarch 75/76 Verifying : python3-setuptools-62.6.0-3.fc37.noarch 76/76 Installed: expat-2.5.0-1.fc37.aarch64 git-2.41.0-1.fc37.aarch64 git-core-2.41.0-1.fc37.aarch64 git-core-doc-2.41.0-1.fc37.noarch groff-base-1.22.4-10.fc37.aarch64 less-633-1.fc37.aarch64 libb2-0.98.1-7.fc37.aarch64 libcbor-0.7.0-7.fc37.aarch64 libedit-3.1-43.20221009cvs.fc37.aarch64 libfido2-1.11.0-3.fc37.aarch64 mpdecimal-2.5.1-4.fc37.aarch64 ncurses-6.4-3.20230114.fc37.aarch64 openssh-8.8p1-11.fc37.aarch64 openssh-clients-8.8p1-11.fc37.aarch64 perl-Carp-1.52-489.fc37.noarch perl-Class-Struct-0.66-494.fc37.noarch perl-DynaLoader-1.52-494.fc37.aarch64 perl-Encode-4:3.19-492.fc37.aarch64 perl-Errno-1.36-494.fc37.aarch64 perl-Error-1:0.17029-10.fc37.noarch perl-Exporter-5.77-489.fc37.noarch perl-Fcntl-1.15-494.fc37.aarch64 perl-File-Basename-2.85-494.fc37.noarch perl-File-Find-1.40-494.fc37.noarch perl-File-Path-2.18-489.fc37.noarch perl-File-Temp-1:0.231.100-489.fc37.noarch perl-File-stat-1.12-494.fc37.noarch perl-Getopt-Long-1:2.54-1.fc37.noarch perl-Getopt-Std-1.13-494.fc37.noarch perl-Git-2.41.0-1.fc37.noarch perl-HTTP-Tiny-0.086-1.fc37.noarch perl-IO-1.50-494.fc37.aarch64 perl-IPC-Open3-1.22-494.fc37.noarch perl-MIME-Base64-3.16-489.fc37.aarch64 perl-POSIX-2.03-494.fc37.aarch64 perl-PathTools-3.84-489.fc37.aarch64 perl-Pod-Escapes-1:1.07-489.fc37.noarch perl-Pod-Perldoc-3.28.01-490.fc37.noarch perl-Pod-Simple-1:3.43-490.fc37.noarch perl-Pod-Usage-4:2.03-3.fc37.noarch perl-Scalar-List-Utils-5:1.63-489.fc37.aarch64 perl-SelectSaver-1.02-494.fc37.noarch perl-Socket-4:2.036-1.fc37.aarch64 perl-Storable-1:3.26-489.fc37.aarch64 perl-Symbol-1.09-494.fc37.noarch perl-Term-ANSIColor-5.01-490.fc37.noarch perl-Term-Cap-1.17-489.fc37.noarch perl-TermReadKey-2.38-14.fc37.aarch64 perl-Text-ParseWords-3.31-489.fc37.noarch perl-Text-Tabs+Wrap-2023.0511-1.fc37.noarch perl-Time-Local-2:1.300-489.fc37.noarch perl-constant-1.33-490.fc37.noarch perl-if-0.61.000-494.fc37.noarch perl-interpreter-4:5.36.1-494.fc37.aarch64 perl-lib-0.65-494.fc37.aarch64 perl-libs-4:5.36.1-494.fc37.aarch64 perl-locale-1.10-494.fc37.noarch perl-mro-1.26-494.fc37.aarch64 perl-overload-1.35-494.fc37.noarch perl-overloading-0.02-494.fc37.noarch perl-parent-1:0.238-489.fc37.noarch perl-podlators-1:4.14-489.fc37.noarch perl-subs-1.04-494.fc37.noarch perl-vars-1.05-494.fc37.noarch pyproject-rpm-macros-1.9.0-1.fc37.noarch python-pip-wheel-22.2.2-3.fc37.noarch python-rpm-macros-3.11-6.fc37.noarch python-setuptools-wheel-62.6.0-3.fc37.noarch python3-3.11.5-1.fc37.aarch64 python3-devel-3.11.5-1.fc37.aarch64 python3-libs-3.11.5-1.fc37.aarch64 python3-packaging-21.3-6.fc37.noarch python3-pyparsing-3.0.9-2.fc37.noarch python3-rpm-generators-13-3.fc37.noarch python3-rpm-macros-3.11-6.fc37.noarch python3-setuptools-62.6.0-3.fc37.noarch Complete! Finish: build setup for litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Start: rpmbuild litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1637193600 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.nogkng + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-rocket + /usr/bin/mkdir -p litex-pythondata-cpu-rocket + cd litex-pythondata-cpu-rocket + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-rocket.git . Cloning into '.'... + git fetch --depth 1 origin d97c0f6bf96790792b03f8f2fcff10a0d82b9d91 From https://github.com/litex-hub/pythondata-cpu-rocket * branch d97c0f6bf96790792b03f8f2fcff10a0d82b9d91 -> FETCH_HEAD + git reset --hard d97c0f6bf96790792b03f8f2fcff10a0d82b9d91 HEAD is now at d97c0f6 Update to chipsalliance/rocket-chip commit #4f197707e + git log --format=fuller commit d97c0f6bf96790792b03f8f2fcff10a0d82b9d91 Author: Gabriel Somlo AuthorDate: Tue Sep 19 20:26:07 2023 -0400 Commit: Gabriel Somlo CommitDate: Tue Sep 19 20:30:20 2023 -0400 Update to chipsalliance/rocket-chip commit #4f197707e + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.ImEmyH + umask 022 + cd /builddir/build/BUILD + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules' + export FCFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_rocket copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket running egg_info creating pythondata_cpu_rocket.egg-info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' /usr/lib/python3.11/site-packages/setuptools/command/build_py.py:153: SetuptoolsDeprecationWarning: Installing 'pythondata_cpu_rocket.verilog' as data is deprecated, please list it in `packages`. !! ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog' as an importable package, but it is not listed in the `packages` configuration of setuptools. 'pythondata_cpu_rocket.verilog' has been automatically added to the distribution only because it may contain data files, but this behavior is likely to change in future versions of setuptools (and therefore is considered deprecated). Please make sure that 'pythondata_cpu_rocket.verilog' is included as a package by using the `packages` configuration field or the proper discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" and "data files" on setuptools documentation page. !! check.warn(importable) /usr/lib/python3.11/site-packages/setuptools/command/build_py.py:153: SetuptoolsDeprecationWarning: Installing 'pythondata_cpu_rocket.verilog.vsrc' as data is deprecated, please list it in `packages`. !! ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog.vsrc' as an importable package, but it is not listed in the `packages` configuration of setuptools. 'pythondata_cpu_rocket.verilog.vsrc' has been automatically added to the distribution only because it may contain data files, but this behavior is likely to change in future versions of setuptools (and therefore is considered deprecated). Please make sure that 'pythondata_cpu_rocket.verilog.vsrc' is included as a package by using the `packages` configuration field or the proper discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" and "data files" on setuptools documentation page. !! check.warn(importable) creating build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog creating build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src creating build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.TjbUvP + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules' + export FCFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-D_FORTIFY_SOURCE=2 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 --prefix /usr running install /usr/lib/python3.11/site-packages/setuptools/command/install.py:34: SetuptoolsDeprecationWarning: setup.py install is deprecated. Use build and pip and other standards-based tools. warnings.warn( running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/vsrc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket/__init__.py to __init__.cpython-311.pyc writing byte-compilation script '/tmp/tmpp6ml8x5h.py' /usr/bin/python3 /tmp/tmpp6ml8x5h.py removing /tmp/tmpp6ml8x5h.py running install_egg_info running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' Copying pythondata_cpu_rocket.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11/site-packages/pythondata_cpu_rocket-0.0.post7146-py3.11.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/bin/__pycache__ + /usr/bin/find-debuginfo -j4 --strict-build-id -m -i --build-id-seed 2023.08-20230919.0.gitd97c0f6b.fc37 --unique-debug-suffix -2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 --unique-debug-src-base litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 50000000 -S debugsourcefiles.list /builddir/build/BUILD/litex-pythondata-cpu-rocket find: 'debug': No such file or directory + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip + /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs + /usr/lib/rpm/brp-remove-la-files + /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/lib/python3.11 using python3.11 + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-rocket-python3-2023.08-20230919.0.gitd97c0f6b.fc37.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.3CkeAc + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + cp -pr README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/doc/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.SWjr1d + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + cp -pr LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-rocket-python3 = 2023.08-20230919.0.gitd97c0f6b.fc37 python3.11dist(pythondata-cpu-rocket) = 0^post7146 python3dist(pythondata-cpu-rocket) = 0^post7146 pythondata-cpu-rocket Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/sh python(abi) = 3.11 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-rocket-python3-2023.08-20230919.0.gitd97c0f6b.fc37.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.B2neQA + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.aarch64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.DLf5pG + umask 022 + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-rocket litex-pythondata-cpu-rocket.gemspec + RPM_EC=0 ++ jobs -p + exit 0 Finish: rpmbuild litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm Finish: build phase for litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.rpm.log /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.librepo.log /var/lib/mock/fedora-37-aarch64-1695260627.623462/root/var/log/dnf.log INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.08-20230919.0.gitd97c0f6b.fc37.src.rpm) Config(child) 3 minutes 45 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-rocket", "epoch": null, "version": "2023.08", "release": "20230919.0.gitd97c0f6b.fc37", "arch": "src" }, { "name": "litex-pythondata-cpu-rocket-python3", "epoch": null, "version": "2023.08", "release": "20230919.0.gitd97c0f6b.fc37", "arch": "noarch" } ] } RPMResults finished