Warning: Permanently added '2620:52:3:1:dead:beef:cafe:c211' (ED25519) to the list of known hosts. You can reproduce this build on your computer by running: sudo dnf install copr-rpmbuild /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/7096668-fedora-39-ppc64le --chroot fedora-39-ppc64le Version: 0.70 PID: 6549 Logging PID: 6550 Task: {'appstream': False, 'background': False, 'build_id': 7096668, 'buildroot_pkgs': [], 'chroot': 'fedora-39-ppc64le', 'enable_net': True, 'fedora_review': False, 'git_hash': 'a57176dae536103f9c43a6afd653e8bf9f74de0d', 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', 'isolation': 'default', 'memory_reqs': 2048, 'package_name': 'litex-pythondata-cpu-rocket', 'package_version': '2023.12-20240219.0.git55d7e429', 'project_dirname': 'HDL', 'project_name': 'HDL', 'project_owner': 'rezso', 'repo_priority': None, 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/HDL/fedora-39-ppc64le/', 'id': 'copr_base', 'name': 'Copr repository', 'priority': None}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/ML/fedora-39-ppc64le/', 'id': 'copr_rezso_ML', 'name': 'Additional repo copr_rezso_ML'}, {'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/CUDA/fedora-39-ppc64le/', 'id': 'copr_rezso_CUDA', 'name': 'Additional repo copr_rezso_CUDA'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/x86_64', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_x86_64'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/sbsa', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_sbsa'}, {'baseurl': 'http://developer.download.nvidia.com/compute/cuda/repos/rhel8/ppc64le', 'id': 'http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le', 'name': 'Additional repo http_developer_download_nvidia_com_compute_cuda_repos_rhel8_ppc64le'}], 'sandbox': 'rezso/HDL--rezso', 'source_json': {}, 'source_type': None, 'submitter': 'rezso', 'tags': [], 'task_id': '7096668-fedora-39-ppc64le', 'timeout': 172800, 'uses_devel_repo': False, 'with_opts': [], 'without_opts': []} Running: git clone https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket --depth 500 --no-single-branch --recursive cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-rocket', '/var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket', '--depth', '500', '--no-single-branch', '--recursive'] cwd: . rc: 0 stdout: stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket'... Running: git checkout a57176dae536103f9c43a6afd653e8bf9f74de0d -- cmd: ['git', 'checkout', 'a57176dae536103f9c43a6afd653e8bf9f74de0d', '--'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket rc: 0 stdout: stderr: Note: switching to 'a57176dae536103f9c43a6afd653e8bf9f74de0d'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at a57176d automatic import of litex-pythondata-cpu-rocket Running: copr-distgit-client sources cmd: ['copr-distgit-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket rc: 0 stdout: /usr/bin/tail: /var/lib/copr-rpmbuild/main.log: file truncated stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources Running (timeout=172800): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342028.223586 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 5.5 starting (python version = 3.12.1, NVR = mock-5.5-1.fc39), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1709342028.223586 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(fedora-39-ppc64le) Start: clean chroot Finish: clean chroot Mock Version: 5.5 INFO: Mock Version: 5.5 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-ppc64le-bootstrap-1709342028.223586/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using bootstrap image: registry.fedoraproject.org/fedora:39 INFO: Pulling image: registry.fedoraproject.org/fedora:39 INFO: Copy content of container registry.fedoraproject.org/fedora:39 to /var/lib/mock/fedora-39-ppc64le-bootstrap-1709342028.223586/root INFO: Checking that registry.fedoraproject.org/fedora:39 image matches host's architecture INFO: mounting registry.fedoraproject.org/fedora:39 with podman image mount INFO: image registry.fedoraproject.org/fedora:39 as /var/lib/containers/storage/overlay/5e71cf379ce8c11c753d74dd3fd8330d085628218bb73dc81a51ff6d47689e47/merged INFO: umounting image registry.fedoraproject.org/fedora:39 (/var/lib/containers/storage/overlay/5e71cf379ce8c11c753d74dd3fd8330d085628218bb73dc81a51ff6d47689e47/merged) with podman image umount INFO: Package manager dnf detected and used (fallback) INFO: Bootstrap image not marked ready Start(bootstrap): installing dnf tooling No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 5.4 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 4.1 MB/s | 800 kB 00:00 Additional repo copr_rezso_CUDA 428 kB/s | 64 kB 00:00 Additional repo http_developer_download_nvidia_ 7.5 MB/s | 3.1 MB 00:00 Additional repo http_developer_download_nvidia_ 10 MB/s | 1.9 MB 00:00 Additional repo http_developer_download_nvidia_ 14 MB/s | 1.7 MB 00:00 fedora 16 MB/s | 83 MB 00:05 updates 6.3 MB/s | 31 MB 00:04 Package python3-dnf-4.18.1-2.fc39.noarch is already installed. Dependencies resolved. ================================================================================ Package Arch Version Repository Size ================================================================================ Installing: python3-dnf-plugins-core noarch 4.5.0-1.fc39 updates 318 k Upgrading: dnf noarch 4.19.0-1.fc39 updates 508 k dnf-data noarch 4.19.0-1.fc39 updates 40 k libdnf ppc64le 0.73.0-1.fc39 updates 685 k python3-dnf noarch 4.19.0-1.fc39 updates 591 k python3-hawkey ppc64le 0.73.0-1.fc39 updates 105 k python3-libdnf ppc64le 0.73.0-1.fc39 updates 849 k yum noarch 4.19.0-1.fc39 updates 37 k Installing dependencies: dbus-libs ppc64le 1:1.14.10-1.fc39 fedora 177 k python3-dateutil noarch 1:2.8.2-10.fc39 fedora 355 k python3-dbus ppc64le 1.3.2-4.fc39 fedora 161 k python3-distro noarch 1.8.0-6.fc39 fedora 49 k python3-six noarch 1.16.0-12.fc39 fedora 41 k python3-systemd ppc64le 235-5.fc39 fedora 108 k Transaction Summary ================================================================================ Install 7 Packages Upgrade 7 Packages Total download size: 3.9 M Downloading Packages: (1/14): python3-dbus-1.3.2-4.fc39.ppc64le.rpm 544 kB/s | 161 kB 00:00 (2/14): dbus-libs-1.14.10-1.fc39.ppc64le.rpm 495 kB/s | 177 kB 00:00 (3/14): python3-distro-1.8.0-6.fc39.noarch.rpm 785 kB/s | 49 kB 00:00 (4/14): python3-six-1.16.0-12.fc39.noarch.rpm 779 kB/s | 41 kB 00:00 (5/14): python3-dateutil-2.8.2-10.fc39.noarch.r 765 kB/s | 355 kB 00:00 (6/14): python3-systemd-235-5.fc39.ppc64le.rpm 993 kB/s | 108 kB 00:00 (7/14): dnf-data-4.19.0-1.fc39.noarch.rpm 221 kB/s | 40 kB 00:00 (8/14): python3-dnf-plugins-core-4.5.0-1.fc39.n 685 kB/s | 318 kB 00:00 (9/14): dnf-4.19.0-1.fc39.noarch.rpm 618 kB/s | 508 kB 00:00 (10/14): libdnf-0.73.0-1.fc39.ppc64le.rpm 1.0 MB/s | 685 kB 00:00 (11/14): python3-dnf-4.19.0-1.fc39.noarch.rpm 884 kB/s | 591 kB 00:00 (12/14): python3-hawkey-0.73.0-1.fc39.ppc64le.r 415 kB/s | 105 kB 00:00 (13/14): yum-4.19.0-1.fc39.noarch.rpm 412 kB/s | 37 kB 00:00 (14/14): python3-libdnf-0.73.0-1.fc39.ppc64le.r 847 kB/s | 849 kB 00:01 -------------------------------------------------------------------------------- Total 1.6 MB/s | 3.9 MB 00:02 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Upgrading : libdnf-0.73.0-1.fc39.ppc64le 1/21 Upgrading : python3-libdnf-0.73.0-1.fc39.ppc64le 2/21 Upgrading : python3-hawkey-0.73.0-1.fc39.ppc64le 3/21 Upgrading : dnf-data-4.19.0-1.fc39.noarch 4/21 Upgrading : python3-dnf-4.19.0-1.fc39.noarch 5/21 Upgrading : dnf-4.19.0-1.fc39.noarch 6/21 Running scriptlet: dnf-4.19.0-1.fc39.noarch 6/21 Installing : python3-systemd-235-5.fc39.ppc64le 7/21 Installing : python3-six-1.16.0-12.fc39.noarch 8/21 Installing : python3-dateutil-1:2.8.2-10.fc39.noarch 9/21 Installing : python3-distro-1.8.0-6.fc39.noarch 10/21 Installing : dbus-libs-1:1.14.10-1.fc39.ppc64le 11/21 Installing : python3-dbus-1.3.2-4.fc39.ppc64le 12/21 Installing : python3-dnf-plugins-core-4.5.0-1.fc39.noarch 13/21 Upgrading : yum-4.19.0-1.fc39.noarch 14/21 Cleanup : yum-4.18.1-2.fc39.noarch 15/21 Running scriptlet: dnf-4.18.1-2.fc39.noarch 16/21 Cleanup : dnf-4.18.1-2.fc39.noarch 16/21 Running scriptlet: dnf-4.18.1-2.fc39.noarch 16/21 Cleanup : python3-dnf-4.18.1-2.fc39.noarch 17/21 Cleanup : python3-hawkey-0.72.0-1.fc39.ppc64le 18/21 Cleanup : dnf-data-4.18.1-2.fc39.noarch 19/21 Cleanup : python3-libdnf-0.72.0-1.fc39.ppc64le 20/21 Cleanup : libdnf-0.72.0-1.fc39.ppc64le 21/21 Running scriptlet: libdnf-0.72.0-1.fc39.ppc64le 21/21 Verifying : dbus-libs-1:1.14.10-1.fc39.ppc64le 1/21 Verifying : python3-dateutil-1:2.8.2-10.fc39.noarch 2/21 Verifying : python3-dbus-1.3.2-4.fc39.ppc64le 3/21 Verifying : python3-distro-1.8.0-6.fc39.noarch 4/21 Verifying : python3-six-1.16.0-12.fc39.noarch 5/21 Verifying : python3-systemd-235-5.fc39.ppc64le 6/21 Verifying : python3-dnf-plugins-core-4.5.0-1.fc39.noarch 7/21 Verifying : dnf-4.19.0-1.fc39.noarch 8/21 Verifying : dnf-4.18.1-2.fc39.noarch 9/21 Verifying : dnf-data-4.19.0-1.fc39.noarch 10/21 Verifying : dnf-data-4.18.1-2.fc39.noarch 11/21 Verifying : libdnf-0.73.0-1.fc39.ppc64le 12/21 Verifying : libdnf-0.72.0-1.fc39.ppc64le 13/21 Verifying : python3-dnf-4.19.0-1.fc39.noarch 14/21 Verifying : python3-dnf-4.18.1-2.fc39.noarch 15/21 Verifying : python3-hawkey-0.73.0-1.fc39.ppc64le 16/21 Verifying : python3-hawkey-0.72.0-1.fc39.ppc64le 17/21 Verifying : python3-libdnf-0.73.0-1.fc39.ppc64le 18/21 Verifying : python3-libdnf-0.72.0-1.fc39.ppc64le 19/21 Verifying : yum-4.19.0-1.fc39.noarch 20/21 Verifying : yum-4.18.1-2.fc39.noarch 21/21 Upgraded: dnf-4.19.0-1.fc39.noarch dnf-data-4.19.0-1.fc39.noarch libdnf-0.73.0-1.fc39.ppc64le python3-dnf-4.19.0-1.fc39.noarch python3-hawkey-0.73.0-1.fc39.ppc64le python3-libdnf-0.73.0-1.fc39.ppc64le yum-4.19.0-1.fc39.noarch Installed: dbus-libs-1:1.14.10-1.fc39.ppc64le python3-dateutil-1:2.8.2-10.fc39.noarch python3-dbus-1.3.2-4.fc39.ppc64le python3-distro-1.8.0-6.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch python3-six-1.16.0-12.fc39.noarch python3-systemd-235-5.fc39.ppc64le Complete! Finish(bootstrap): installing dnf tooling Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.0-1.fc39.ppc64le rpm-sequoia-1.5.0-1.fc39.ppc64le python3-dnf-4.19.0-1.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch yum-4.19.0-1.fc39.noarch Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 6.4 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 5.2 MB/s | 800 kB 00:00 Additional repo copr_rezso_CUDA 531 kB/s | 64 kB 00:00 Additional repo http_developer_download_nvidia_ 21 MB/s | 3.1 MB 00:00 Additional repo http_developer_download_nvidia_ 14 MB/s | 1.9 MB 00:00 Additional repo http_developer_download_nvidia_ 11 MB/s | 1.7 MB 00:00 fedora 16 MB/s | 83 MB 00:05 updates 9.5 MB/s | 31 MB 00:03 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing group/module packages: bash ppc64le 5.2.26-1.fc39 updates 1.9 M bzip2 ppc64le 1.0.8-16.fc39 fedora 53 k coreutils ppc64le 9.3-5.fc39 updates 1.4 M cpio ppc64le 2.14-4.fc39 fedora 286 k diffutils ppc64le 3.10-3.fc39 fedora 408 k fedora-release-common noarch 39-36 updates 19 k findutils ppc64le 1:4.9.0-5.fc39 fedora 541 k gawk ppc64le 5.2.2-2.fc39 fedora 1.1 M glibc-minimal-langpack ppc64le 2.38-16.fc39 updates 71 k grep ppc64le 3.11-3.fc39 fedora 308 k gzip ppc64le 1.12-6.fc39 fedora 170 k info ppc64le 7.0.3-3.fc39 fedora 200 k patch ppc64le 2.7.6-22.fc39 fedora 137 k redhat-rpm-config noarch 265-1.fc39 updates 78 k rpm-build ppc64le 4.19.1.1-1.fc39 updates 80 k sed ppc64le 4.8-14.fc39 fedora 312 k shadow-utils ppc64le 2:4.14.0-2.fc39 updates 1.3 M tar ppc64le 2:1.35-2.fc39 fedora 884 k unzip ppc64le 6.0-62.fc39 fedora 190 k util-linux ppc64le 2.39.3-6.fc39 updates 1.3 M which ppc64le 2.21-40.fc39 fedora 43 k xz ppc64le 5.4.4-1.fc39 fedora 559 k Installing dependencies: alternatives ppc64le 1.26-1.fc39 updates 41 k ansible-srpm-macros noarch 1-12.fc39 updates 21 k audit-libs ppc64le 3.1.2-8.fc39 updates 132 k authselect ppc64le 1.4.3-1.fc39 fedora 151 k authselect-libs ppc64le 1.4.3-1.fc39 fedora 253 k basesystem noarch 11-18.fc39 fedora 7.2 k binutils ppc64le 2.40-14.fc39 updates 6.4 M binutils-gold ppc64le 2.40-14.fc39 updates 1.1 M bzip2-libs ppc64le 1.0.8-16.fc39 fedora 47 k ca-certificates noarch 2023.2.60_v7.0.306-2.fc39 fedora 837 k coreutils-common ppc64le 9.3-5.fc39 updates 2.1 M cracklib ppc64le 2.9.11-2.fc39 fedora 96 k crypto-policies noarch 20231204-1.git1e3a2e4.fc39 updates 100 k curl ppc64le 8.2.1-4.fc39 updates 347 k cyrus-sasl-lib ppc64le 2.1.28-11.fc39 fedora 877 k debugedit ppc64le 5.0-12.fc39 updates 81 k dwz ppc64le 0.15-3.fc39 fedora 147 k ed ppc64le 1.19-4.fc39 fedora 81 k efi-srpm-macros noarch 5-9.fc39 fedora 22 k elfutils ppc64le 0.190-4.fc39 updates 582 k elfutils-debuginfod-client ppc64le 0.190-4.fc39 updates 39 k elfutils-default-yama-scope noarch 0.190-4.fc39 updates 13 k elfutils-libelf ppc64le 0.190-4.fc39 updates 203 k elfutils-libs ppc64le 0.190-4.fc39 updates 295 k fedora-gpg-keys noarch 39-1 fedora 130 k fedora-release noarch 39-36 updates 8.6 k fedora-release-identity-basic noarch 39-36 updates 9.4 k fedora-repos noarch 39-1 fedora 9.3 k file ppc64le 5.44-5.fc39 fedora 50 k file-libs ppc64le 5.44-5.fc39 fedora 742 k filesystem ppc64le 3.18-6.fc39 fedora 1.1 M fonts-srpm-macros noarch 1:2.0.5-12.fc39 fedora 26 k forge-srpm-macros noarch 0.2.0-3.fc39 updates 19 k fpc-srpm-macros noarch 1.3-8.fc39 fedora 7.4 k gdb-minimal ppc64le 14.1-4.fc39 updates 4.3 M gdbm-libs ppc64le 1:1.23-4.fc39 fedora 62 k ghc-srpm-macros noarch 1.6.1-2.fc39 fedora 7.8 k glibc ppc64le 2.38-16.fc39 updates 2.2 M glibc-common ppc64le 2.38-16.fc39 updates 367 k glibc-gconv-extra ppc64le 2.38-16.fc39 updates 2.0 M gmp ppc64le 1:6.2.1-5.fc39 fedora 304 k gnat-srpm-macros noarch 6-3.fc39 fedora 8.8 k go-srpm-macros noarch 3.4.0-2.fc39 updates 27 k jansson ppc64le 2.13.1-7.fc39 fedora 49 k kernel-srpm-macros noarch 1.0-20.fc39 fedora 10 k keyutils-libs ppc64le 1.6.1-7.fc39 fedora 32 k krb5-libs ppc64le 1.21.2-3.fc39 updates 850 k libacl ppc64le 2.3.1-9.fc39 updates 26 k libarchive ppc64le 3.7.1-1.fc39 fedora 477 k libattr ppc64le 2.5.1-8.fc39 fedora 19 k libblkid ppc64le 2.39.3-6.fc39 updates 134 k libbrotli ppc64le 1.1.0-1.fc39 fedora 380 k libcap ppc64le 2.48-9.fc39 updates 73 k libcap-ng ppc64le 0.8.3-8.fc39 fedora 33 k libcom_err ppc64le 1.47.0-2.fc39 fedora 27 k libcurl ppc64le 8.2.1-4.fc39 updates 358 k libdb ppc64le 5.3.28-56.fc39 fedora 838 k libeconf ppc64le 0.5.2-1.fc39 fedora 34 k libevent ppc64le 2.1.12-9.fc39 fedora 275 k libfdisk ppc64le 2.39.3-6.fc39 updates 179 k libffi ppc64le 3.4.4-4.fc39 fedora 38 k libgcc ppc64le 13.2.1-6.fc39 updates 107 k libgomp ppc64le 13.2.1-6.fc39 updates 335 k libidn2 ppc64le 2.3.7-1.fc39 updates 122 k libmount ppc64le 2.39.3-6.fc39 updates 177 k libnghttp2 ppc64le 1.55.1-4.fc39 updates 86 k libnsl2 ppc64le 2.0.0-6.fc39 fedora 32 k libpkgconf ppc64le 1.9.5-2.fc39 fedora 42 k libpsl ppc64le 0.21.2-4.fc39 fedora 65 k libpwquality ppc64le 1.4.5-6.fc39 fedora 123 k librtas ppc64le 2.0.4-3.fc39 fedora 70 k libselinux ppc64le 3.5-5.fc39 fedora 100 k libsemanage ppc64le 3.5-4.fc39 fedora 131 k libsepol ppc64le 3.5-2.fc39 fedora 356 k libsigsegv ppc64le 2.14-5.fc39 fedora 28 k libsmartcols ppc64le 2.39.3-6.fc39 updates 74 k libssh ppc64le 0.10.6-2.fc39 updates 240 k libssh-config noarch 0.10.6-2.fc39 updates 9.0 k libstdc++ ppc64le 13.2.1-6.fc39 updates 1.0 M libtasn1 ppc64le 4.19.0-3.fc39 fedora 80 k libtirpc ppc64le 1.3.4-0.rc2.fc39 updates 109 k libunistring ppc64le 1.1-5.fc39 fedora 578 k libutempter ppc64le 1.2.1-10.fc39 fedora 27 k libuuid ppc64le 2.39.3-6.fc39 updates 30 k libverto ppc64le 0.3.2-6.fc39 fedora 22 k libxcrypt ppc64le 4.4.36-2.fc39 fedora 132 k libxml2 ppc64le 2.10.4-3.fc39 fedora 780 k libzstd ppc64le 1.5.5-4.fc39 fedora 336 k lua-libs ppc64le 5.4.6-3.fc39 fedora 149 k lua-srpm-macros noarch 1-13.fc39 updates 8.7 k lz4-libs ppc64le 1.9.4-4.fc39 fedora 85 k mpfr ppc64le 4.2.0-3.fc39 fedora 353 k ncurses-base noarch 6.4-7.20230520.fc39.1 updates 88 k ncurses-libs ppc64le 6.4-7.20230520.fc39.1 updates 380 k ocaml-srpm-macros noarch 8-2.fc39 fedora 14 k openblas-srpm-macros noarch 2-14.fc39 fedora 7.5 k openldap ppc64le 2.6.6-1.fc39 fedora 287 k openssl-libs ppc64le 1:3.1.1-4.fc39 fedora 2.3 M p11-kit ppc64le 0.25.3-1.fc39 updates 521 k p11-kit-trust ppc64le 0.25.3-1.fc39 updates 155 k package-notes-srpm-macros noarch 0.5-9.fc39 fedora 11 k pam ppc64le 1.5.3-3.fc39 updates 586 k pam-libs ppc64le 1.5.3-3.fc39 updates 63 k pcre2 ppc64le 10.42-1.fc39.2 fedora 241 k pcre2-syntax noarch 10.42-1.fc39.2 fedora 143 k perl-srpm-macros noarch 1-51.fc39 fedora 8.0 k pkgconf ppc64le 1.9.5-2.fc39 fedora 43 k pkgconf-m4 noarch 1.9.5-2.fc39 fedora 14 k pkgconf-pkg-config ppc64le 1.9.5-2.fc39 fedora 9.6 k popt ppc64le 1.19-3.fc39 fedora 71 k publicsuffix-list-dafsa noarch 20240107-1.fc39 updates 58 k pyproject-srpm-macros noarch 1.12.0-1.fc39 updates 14 k python-srpm-macros noarch 3.12-4.fc39 fedora 25 k qt5-srpm-macros noarch 5.15.12-1.fc39 updates 8.4 k qt6-srpm-macros noarch 6.6.2-1.fc39 updates 8.9 k readline ppc64le 8.2-6.fc39 updates 229 k rpm ppc64le 4.19.1.1-1.fc39 updates 539 k rpm-build-libs ppc64le 4.19.1.1-1.fc39 updates 102 k rpm-libs ppc64le 4.19.1.1-1.fc39 updates 356 k rpm-sequoia ppc64le 1.6.0-1.fc39 updates 1.5 M rpmautospec-rpm-macros noarch 0.6.3-1.fc39 updates 10 k rust-srpm-macros noarch 26.1-1.fc39 updates 13 k setup noarch 2.14.4-1.fc39 fedora 154 k sqlite-libs ppc64le 3.42.0-7.fc39 fedora 789 k systemd-libs ppc64le 254.9-1.fc39 updates 732 k util-linux-core ppc64le 2.39.3-6.fc39 updates 550 k xxhash-libs ppc64le 0.8.2-1.fc39 fedora 37 k xz-libs ppc64le 5.4.4-1.fc39 fedora 121 k zip ppc64le 3.0-39.fc39 fedora 274 k zlib ppc64le 1.2.13-4.fc39 fedora 100 k zstd ppc64le 1.5.5-4.fc39 fedora 499 k Installing Groups: Buildsystem building group Transaction Summary ================================================================================ Install 153 Packages Total download size: 57 M Installed size: 325 M Downloading Packages: (1/153): basesystem-11-18.fc39.noarch.rpm 77 kB/s | 7.2 kB 00:00 (2/153): bzip2-1.0.8-16.fc39.ppc64le.rpm 601 kB/s | 53 kB 00:00 (3/153): authselect-1.4.3-1.fc39.ppc64le.rpm 678 kB/s | 151 kB 00:00 (4/153): authselect-libs-1.4.3-1.fc39.ppc64le.r 1.0 MB/s | 253 kB 00:00 (5/153): bzip2-libs-1.0.8-16.fc39.ppc64le.rpm 815 kB/s | 47 kB 00:00 (6/153): cracklib-2.9.11-2.fc39.ppc64le.rpm 1.6 MB/s | 96 kB 00:00 (7/153): cpio-2.14-4.fc39.ppc64le.rpm 4.4 MB/s | 286 kB 00:00 (8/153): diffutils-3.10-3.fc39.ppc64le.rpm 8.8 MB/s | 408 kB 00:00 (9/153): ca-certificates-2023.2.60_v7.0.306-2.f 6.1 MB/s | 837 kB 00:00 (10/153): dwz-0.15-3.fc39.ppc64le.rpm 4.0 MB/s | 147 kB 00:00 (11/153): ed-1.19-4.fc39.ppc64le.rpm 2.3 MB/s | 81 kB 00:00 (12/153): efi-srpm-macros-5-9.fc39.noarch.rpm 636 kB/s | 22 kB 00:00 (13/153): fedora-gpg-keys-39-1.noarch.rpm 3.7 MB/s | 130 kB 00:00 (14/153): cyrus-sasl-lib-2.1.28-11.fc39.ppc64le 6.3 MB/s | 877 kB 00:00 (15/153): fedora-repos-39-1.noarch.rpm 319 kB/s | 9.3 kB 00:00 (16/153): file-5.44-5.fc39.ppc64le.rpm 1.6 MB/s | 50 kB 00:00 (17/153): file-libs-5.44-5.fc39.ppc64le.rpm 14 MB/s | 742 kB 00:00 (18/153): findutils-4.9.0-5.fc39.ppc64le.rpm 9.8 MB/s | 541 kB 00:00 (19/153): filesystem-3.18-6.fc39.ppc64le.rpm 16 MB/s | 1.1 MB 00:00 (20/153): fonts-srpm-macros-2.0.5-12.fc39.noarc 802 kB/s | 26 kB 00:00 (21/153): fpc-srpm-macros-1.3-8.fc39.noarch.rpm 162 kB/s | 7.4 kB 00:00 (22/153): gdbm-libs-1.23-4.fc39.ppc64le.rpm 1.6 MB/s | 62 kB 00:00 (23/153): gawk-5.2.2-2.fc39.ppc64le.rpm 20 MB/s | 1.1 MB 00:00 (24/153): ghc-srpm-macros-1.6.1-2.fc39.noarch.r 205 kB/s | 7.8 kB 00:00 (25/153): gmp-6.2.1-5.fc39.ppc64le.rpm 4.3 MB/s | 304 kB 00:00 (26/153): gnat-srpm-macros-6-3.fc39.noarch.rpm 165 kB/s | 8.8 kB 00:00 (27/153): grep-3.11-3.fc39.ppc64le.rpm 6.9 MB/s | 308 kB 00:00 (28/153): jansson-2.13.1-7.fc39.ppc64le.rpm 1.2 MB/s | 49 kB 00:00 (29/153): info-7.0.3-3.fc39.ppc64le.rpm 2.1 MB/s | 200 kB 00:00 (30/153): kernel-srpm-macros-1.0-20.fc39.noarch 222 kB/s | 10 kB 00:00 (31/153): gzip-1.12-6.fc39.ppc64le.rpm 1.2 MB/s | 170 kB 00:00 (32/153): keyutils-libs-1.6.1-7.fc39.ppc64le.rp 798 kB/s | 32 kB 00:00 (33/153): libarchive-3.7.1-1.fc39.ppc64le.rpm 10 MB/s | 477 kB 00:00 (34/153): libattr-2.5.1-8.fc39.ppc64le.rpm 465 kB/s | 19 kB 00:00 (35/153): libcap-ng-0.8.3-8.fc39.ppc64le.rpm 967 kB/s | 33 kB 00:00 (36/153): libbrotli-1.1.0-1.fc39.ppc64le.rpm 8.3 MB/s | 380 kB 00:00 (37/153): libcom_err-1.47.0-2.fc39.ppc64le.rpm 901 kB/s | 27 kB 00:00 (38/153): libeconf-0.5.2-1.fc39.ppc64le.rpm 832 kB/s | 34 kB 00:00 (39/153): libdb-5.3.28-56.fc39.ppc64le.rpm 16 MB/s | 838 kB 00:00 (40/153): libevent-2.1.12-9.fc39.ppc64le.rpm 8.3 MB/s | 275 kB 00:00 (41/153): libffi-3.4.4-4.fc39.ppc64le.rpm 990 kB/s | 38 kB 00:00 (42/153): libnsl2-2.0.0-6.fc39.ppc64le.rpm 1.0 MB/s | 32 kB 00:00 (43/153): libpkgconf-1.9.5-2.fc39.ppc64le.rpm 1.4 MB/s | 42 kB 00:00 (44/153): libpsl-0.21.2-4.fc39.ppc64le.rpm 2.0 MB/s | 65 kB 00:00 (45/153): libpwquality-1.4.5-6.fc39.ppc64le.rpm 3.7 MB/s | 123 kB 00:00 (46/153): librtas-2.0.4-3.fc39.ppc64le.rpm 2.3 MB/s | 70 kB 00:00 (47/153): libselinux-3.5-5.fc39.ppc64le.rpm 2.7 MB/s | 100 kB 00:00 (48/153): libsemanage-3.5-4.fc39.ppc64le.rpm 3.5 MB/s | 131 kB 00:00 (49/153): libsepol-3.5-2.fc39.ppc64le.rpm 9.7 MB/s | 356 kB 00:00 (50/153): libsigsegv-2.14-5.fc39.ppc64le.rpm 912 kB/s | 28 kB 00:00 (51/153): libtasn1-4.19.0-3.fc39.ppc64le.rpm 2.5 MB/s | 80 kB 00:00 (52/153): libunistring-1.1-5.fc39.ppc64le.rpm 15 MB/s | 578 kB 00:00 (53/153): libutempter-1.2.1-10.fc39.ppc64le.rpm 894 kB/s | 27 kB 00:00 (54/153): libverto-0.3.2-6.fc39.ppc64le.rpm 732 kB/s | 22 kB 00:00 (55/153): libxcrypt-4.4.36-2.fc39.ppc64le.rpm 3.8 MB/s | 132 kB 00:00 (56/153): libzstd-1.5.5-4.fc39.ppc64le.rpm 9.1 MB/s | 336 kB 00:00 (57/153): lua-libs-5.4.6-3.fc39.ppc64le.rpm 4.3 MB/s | 149 kB 00:00 (58/153): libxml2-2.10.4-3.fc39.ppc64le.rpm 13 MB/s | 780 kB 00:00 (59/153): lz4-libs-1.9.4-4.fc39.ppc64le.rpm 2.8 MB/s | 85 kB 00:00 (60/153): mpfr-4.2.0-3.fc39.ppc64le.rpm 8.9 MB/s | 353 kB 00:00 (61/153): ocaml-srpm-macros-8-2.fc39.noarch.rpm 448 kB/s | 14 kB 00:00 (62/153): openblas-srpm-macros-2-14.fc39.noarch 260 kB/s | 7.5 kB 00:00 (63/153): openldap-2.6.6-1.fc39.ppc64le.rpm 8.5 MB/s | 287 kB 00:00 (64/153): package-notes-srpm-macros-0.5-9.fc39. 389 kB/s | 11 kB 00:00 (65/153): patch-2.7.6-22.fc39.ppc64le.rpm 4.4 MB/s | 137 kB 00:00 (66/153): pcre2-10.42-1.fc39.2.ppc64le.rpm 6.4 MB/s | 241 kB 00:00 (67/153): openssl-libs-3.1.1-4.fc39.ppc64le.rpm 25 MB/s | 2.3 MB 00:00 (68/153): pcre2-syntax-10.42-1.fc39.2.noarch.rp 4.4 MB/s | 143 kB 00:00 (69/153): perl-srpm-macros-1-51.fc39.noarch.rpm 277 kB/s | 8.0 kB 00:00 (70/153): pkgconf-1.9.5-2.fc39.ppc64le.rpm 1.1 MB/s | 43 kB 00:00 (71/153): pkgconf-m4-1.9.5-2.fc39.noarch.rpm 396 kB/s | 14 kB 00:00 (72/153): pkgconf-pkg-config-1.9.5-2.fc39.ppc64 306 kB/s | 9.6 kB 00:00 (73/153): popt-1.19-3.fc39.ppc64le.rpm 2.2 MB/s | 71 kB 00:00 (74/153): python-srpm-macros-3.12-4.fc39.noarch 774 kB/s | 25 kB 00:00 (75/153): sed-4.8-14.fc39.ppc64le.rpm 8.3 MB/s | 312 kB 00:00 (76/153): setup-2.14.4-1.fc39.noarch.rpm 4.5 MB/s | 154 kB 00:00 (77/153): sqlite-libs-3.42.0-7.fc39.ppc64le.rpm 17 MB/s | 789 kB 00:00 (78/153): tar-1.35-2.fc39.ppc64le.rpm 13 MB/s | 884 kB 00:00 (79/153): unzip-6.0-62.fc39.ppc64le.rpm 4.8 MB/s | 190 kB 00:00 (80/153): which-2.21-40.fc39.ppc64le.rpm 1.2 MB/s | 43 kB 00:00 (81/153): xxhash-libs-0.8.2-1.fc39.ppc64le.rpm 1.1 MB/s | 37 kB 00:00 (82/153): xz-libs-5.4.4-1.fc39.ppc64le.rpm 3.5 MB/s | 121 kB 00:00 (83/153): xz-5.4.4-1.fc39.ppc64le.rpm 13 MB/s | 559 kB 00:00 (84/153): zip-3.0-39.fc39.ppc64le.rpm 7.1 MB/s | 274 kB 00:00 (85/153): zlib-1.2.13-4.fc39.ppc64le.rpm 2.7 MB/s | 100 kB 00:00 (86/153): zstd-1.5.5-4.fc39.ppc64le.rpm 11 MB/s | 499 kB 00:00 (87/153): ansible-srpm-macros-1-12.fc39.noarch. 109 kB/s | 21 kB 00:00 (88/153): alternatives-1.26-1.fc39.ppc64le.rpm 146 kB/s | 41 kB 00:00 (89/153): audit-libs-3.1.2-8.fc39.ppc64le.rpm 393 kB/s | 132 kB 00:00 (90/153): binutils-gold-2.40-14.fc39.ppc64le.rp 3.0 MB/s | 1.1 MB 00:00 (91/153): coreutils-9.3-5.fc39.ppc64le.rpm 3.7 MB/s | 1.4 MB 00:00 (92/153): bash-5.2.26-1.fc39.ppc64le.rpm 1.3 MB/s | 1.9 MB 00:01 (93/153): coreutils-common-9.3-5.fc39.ppc64le.r 3.6 MB/s | 2.1 MB 00:00 (94/153): crypto-policies-20231204-1.git1e3a2e4 1.6 MB/s | 100 kB 00:00 (95/153): debugedit-5.0-12.fc39.ppc64le.rpm 1.9 MB/s | 81 kB 00:00 (96/153): curl-8.2.1-4.fc39.ppc64le.rpm 3.3 MB/s | 347 kB 00:00 (97/153): elfutils-debuginfod-client-0.190-4.fc 510 kB/s | 39 kB 00:00 (98/153): elfutils-default-yama-scope-0.190-4.f 311 kB/s | 13 kB 00:00 (99/153): elfutils-0.190-4.fc39.ppc64le.rpm 2.4 MB/s | 582 kB 00:00 (100/153): elfutils-libelf-0.190-4.fc39.ppc64le 2.7 MB/s | 203 kB 00:00 (101/153): fedora-release-39-36.noarch.rpm 170 kB/s | 8.6 kB 00:00 (102/153): elfutils-libs-0.190-4.fc39.ppc64le.r 3.1 MB/s | 295 kB 00:00 (103/153): fedora-release-common-39-36.noarch.r 329 kB/s | 19 kB 00:00 (104/153): fedora-release-identity-basic-39-36. 121 kB/s | 9.4 kB 00:00 (105/153): forge-srpm-macros-0.2.0-3.fc39.noarc 306 kB/s | 19 kB 00:00 (106/153): glibc-2.38-16.fc39.ppc64le.rpm 3.7 MB/s | 2.2 MB 00:00 (107/153): binutils-2.40-14.fc39.ppc64le.rpm 2.5 MB/s | 6.4 MB 00:02 (108/153): glibc-common-2.38-16.fc39.ppc64le.rp 3.6 MB/s | 367 kB 00:00 (109/153): glibc-minimal-langpack-2.38-16.fc39. 1.4 MB/s | 71 kB 00:00 (110/153): go-srpm-macros-3.4.0-2.fc39.noarch.r 642 kB/s | 27 kB 00:00 (111/153): gdb-minimal-14.1-4.fc39.ppc64le.rpm 4.7 MB/s | 4.3 MB 00:00 (112/153): glibc-gconv-extra-2.38-16.fc39.ppc64 7.0 MB/s | 2.0 MB 00:00 (113/153): libacl-2.3.1-9.fc39.ppc64le.rpm 351 kB/s | 26 kB 00:00 (114/153): krb5-libs-1.21.2-3.fc39.ppc64le.rpm 4.0 MB/s | 850 kB 00:00 (115/153): libblkid-2.39.3-6.fc39.ppc64le.rpm 3.0 MB/s | 134 kB 00:00 (116/153): libcap-2.48-9.fc39.ppc64le.rpm 1.6 MB/s | 73 kB 00:00 (117/153): libgcc-13.2.1-6.fc39.ppc64le.rpm 2.4 MB/s | 107 kB 00:00 (118/153): libfdisk-2.39.3-6.fc39.ppc64le.rpm 3.9 MB/s | 179 kB 00:00 (119/153): libcurl-8.2.1-4.fc39.ppc64le.rpm 4.0 MB/s | 358 kB 00:00 (120/153): libidn2-2.3.7-1.fc39.ppc64le.rpm 2.5 MB/s | 122 kB 00:00 (121/153): libgomp-13.2.1-6.fc39.ppc64le.rpm 6.5 MB/s | 335 kB 00:00 (122/153): libmount-2.39.3-6.fc39.ppc64le.rpm 4.1 MB/s | 177 kB 00:00 (123/153): libnghttp2-1.55.1-4.fc39.ppc64le.rpm 1.7 MB/s | 86 kB 00:00 (124/153): libsmartcols-2.39.3-6.fc39.ppc64le.r 1.5 MB/s | 74 kB 00:00 (125/153): libssh-0.10.6-2.fc39.ppc64le.rpm 4.3 MB/s | 240 kB 00:00 (126/153): libssh-config-0.10.6-2.fc39.noarch.r 151 kB/s | 9.0 kB 00:00 (127/153): libtirpc-1.3.4-0.rc2.fc39.ppc64le.rp 1.6 MB/s | 109 kB 00:00 (128/153): libuuid-2.39.3-6.fc39.ppc64le.rpm 608 kB/s | 30 kB 00:00 (129/153): lua-srpm-macros-1-13.fc39.noarch.rpm 182 kB/s | 8.7 kB 00:00 (130/153): libstdc++-13.2.1-6.fc39.ppc64le.rpm 5.6 MB/s | 1.0 MB 00:00 (131/153): ncurses-base-6.4-7.20230520.fc39.1.n 1.3 MB/s | 88 kB 00:00 (132/153): p11-kit-trust-0.25.3-1.fc39.ppc64le. 2.6 MB/s | 155 kB 00:00 (133/153): ncurses-libs-6.4-7.20230520.fc39.1.p 2.6 MB/s | 380 kB 00:00 (134/153): p11-kit-0.25.3-1.fc39.ppc64le.rpm 3.7 MB/s | 521 kB 00:00 (135/153): pam-libs-1.5.3-3.fc39.ppc64le.rpm 887 kB/s | 63 kB 00:00 (136/153): pam-1.5.3-3.fc39.ppc64le.rpm 3.9 MB/s | 586 kB 00:00 (137/153): publicsuffix-list-dafsa-20240107-1.f 860 kB/s | 58 kB 00:00 (138/153): pyproject-srpm-macros-1.12.0-1.fc39. 247 kB/s | 14 kB 00:00 (139/153): qt5-srpm-macros-5.15.12-1.fc39.noarc 98 kB/s | 8.4 kB 00:00 (140/153): qt6-srpm-macros-6.6.2-1.fc39.noarch. 103 kB/s | 8.9 kB 00:00 (141/153): readline-8.2-6.fc39.ppc64le.rpm 4.3 MB/s | 229 kB 00:00 (142/153): redhat-rpm-config-265-1.fc39.noarch. 1.5 MB/s | 78 kB 00:00 (143/153): rpm-build-4.19.1.1-1.fc39.ppc64le.rp 1.6 MB/s | 80 kB 00:00 (144/153): rpm-4.19.1.1-1.fc39.ppc64le.rpm 5.7 MB/s | 539 kB 00:00 (145/153): rpm-build-libs-4.19.1.1-1.fc39.ppc64 2.3 MB/s | 102 kB 00:00 (146/153): rpm-libs-4.19.1.1-1.fc39.ppc64le.rpm 4.0 MB/s | 356 kB 00:00 (147/153): rpmautospec-rpm-macros-0.6.3-1.fc39. 198 kB/s | 10 kB 00:00 (148/153): rust-srpm-macros-26.1-1.fc39.noarch. 279 kB/s | 13 kB 00:00 (149/153): rpm-sequoia-1.6.0-1.fc39.ppc64le.rpm 11 MB/s | 1.5 MB 00:00 (150/153): shadow-utils-4.14.0-2.fc39.ppc64le.r 9.5 MB/s | 1.3 MB 00:00 (151/153): systemd-libs-254.9-1.fc39.ppc64le.rp 5.0 MB/s | 732 kB 00:00 (152/153): util-linux-core-2.39.3-6.fc39.ppc64l 8.1 MB/s | 550 kB 00:00 (153/153): util-linux-2.39.3-6.fc39.ppc64le.rpm 10 MB/s | 1.3 MB 00:00 -------------------------------------------------------------------------------- Total 9.4 MB/s | 57 MB 00:06 fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x18B8E74C: Userid : "Fedora (39) " Fingerprint: E8F2 3996 F232 1864 0CB4 4CBE 75CF 5AC4 18B8 E74C From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-6.fc39.ppc64le 1/1 Preparing : 1/1 Installing : libgcc-13.2.1-6.fc39.ppc64le 1/153 Running scriptlet: libgcc-13.2.1-6.fc39.ppc64le 1/153 Installing : crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 2/153 Running scriptlet: crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 2/153 Installing : fedora-release-identity-basic-39-36.noarch 3/153 Installing : fedora-gpg-keys-39-1.noarch 4/153 Installing : fedora-repos-39-1.noarch 5/153 Installing : fedora-release-common-39-36.noarch 6/153 Installing : fedora-release-39-36.noarch 7/153 Installing : setup-2.14.4-1.fc39.noarch 8/153 Running scriptlet: setup-2.14.4-1.fc39.noarch 8/153 Installing : filesystem-3.18-6.fc39.ppc64le 9/153 Installing : basesystem-11-18.fc39.noarch 10/153 Installing : rust-srpm-macros-26.1-1.fc39.noarch 11/153 Installing : qt6-srpm-macros-6.6.2-1.fc39.noarch 12/153 Installing : qt5-srpm-macros-5.15.12-1.fc39.noarch 13/153 Installing : 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libgomp-13.2.1-6.fc39.ppc64le 83/153 Installing : libnghttp2-1.55.1-4.fc39.ppc64le 84/153 Installing : libssh-config-0.10.6-2.fc39.noarch 85/153 Installing : coreutils-common-9.3-5.fc39.ppc64le 86/153 Installing : ansible-srpm-macros-1-12.fc39.noarch 87/153 Installing : pkgconf-m4-1.9.5-2.fc39.noarch 88/153 Installing : pkgconf-pkg-config-1.9.5-2.fc39.ppc64le 89/153 Installing : perl-srpm-macros-1-51.fc39.noarch 90/153 Installing : pcre2-syntax-10.42-1.fc39.2.noarch 91/153 Installing : pcre2-10.42-1.fc39.2.ppc64le 92/153 Installing : libselinux-3.5-5.fc39.ppc64le 93/153 Installing : sed-4.8-14.fc39.ppc64le 94/153 Installing : grep-3.11-3.fc39.ppc64le 95/153 Installing : findutils-1:4.9.0-5.fc39.ppc64le 96/153 Installing : xz-5.4.4-1.fc39.ppc64le 97/153 Installing : libmount-2.39.3-6.fc39.ppc64le 98/153 Installing : util-linux-core-2.39.3-6.fc39.ppc64le 99/153 Installing : openssl-libs-1:3.1.1-4.fc39.ppc64le 100/153 Installing : coreutils-9.3-5.fc39.ppc64le 101/153 Running scriptlet: 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Installing : elfutils-libs-0.190-4.fc39.ppc64le 117/153 Installing : elfutils-debuginfod-client-0.190-4.fc39.ppc64le 118/153 Installing : binutils-gold-2.40-14.fc39.ppc64le 119/153 Running scriptlet: binutils-gold-2.40-14.fc39.ppc64le 119/153 Installing : binutils-2.40-14.fc39.ppc64le 120/153 Running scriptlet: binutils-2.40-14.fc39.ppc64le 120/153 Installing : elfutils-0.190-4.fc39.ppc64le 121/153 Installing : gdb-minimal-14.1-4.fc39.ppc64le 122/153 Installing : debugedit-5.0-12.fc39.ppc64le 123/153 Installing : curl-8.2.1-4.fc39.ppc64le 124/153 Installing : rpm-sequoia-1.6.0-1.fc39.ppc64le 125/153 Installing : rpm-libs-4.19.1.1-1.fc39.ppc64le 126/153 Running scriptlet: rpm-4.19.1.1-1.fc39.ppc64le 127/153 Installing : rpm-4.19.1.1-1.fc39.ppc64le 127/153 Installing : efi-srpm-macros-5-9.fc39.noarch 128/153 Installing : lua-srpm-macros-1-13.fc39.noarch 129/153 Installing : rpmautospec-rpm-macros-0.6.3-1.fc39.noarch 130/153 Installing : rpm-build-libs-4.19.1.1-1.fc39.ppc64le 131/153 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redhat-rpm-config-265-1.fc39.noarch 148/153 Installing : rpm-build-4.19.1.1-1.fc39.ppc64le 149/153 Installing : pyproject-srpm-macros-1.12.0-1.fc39.noarch 150/153 Installing : util-linux-2.39.3-6.fc39.ppc64le 151/153 Running scriptlet: util-linux-2.39.3-6.fc39.ppc64le 151/153 Installing : which-2.21-40.fc39.ppc64le 152/153 Installing : info-7.0.3-3.fc39.ppc64le 153/153 Running scriptlet: filesystem-3.18-6.fc39.ppc64le 153/153 Running scriptlet: ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 153/153 Running scriptlet: authselect-libs-1.4.3-1.fc39.ppc64le 153/153 Running scriptlet: rpm-4.19.1.1-1.fc39.ppc64le 153/153 Running scriptlet: info-7.0.3-3.fc39.ppc64le 153/153 Verifying : authselect-1.4.3-1.fc39.ppc64le 1/153 Verifying : authselect-libs-1.4.3-1.fc39.ppc64le 2/153 Verifying : basesystem-11-18.fc39.noarch 3/153 Verifying : bzip2-1.0.8-16.fc39.ppc64le 4/153 Verifying : bzip2-libs-1.0.8-16.fc39.ppc64le 5/153 Verifying : ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch 6/153 Verifying : cpio-2.14-4.fc39.ppc64le 7/153 Verifying : cracklib-2.9.11-2.fc39.ppc64le 8/153 Verifying : cyrus-sasl-lib-2.1.28-11.fc39.ppc64le 9/153 Verifying : diffutils-3.10-3.fc39.ppc64le 10/153 Verifying : dwz-0.15-3.fc39.ppc64le 11/153 Verifying : ed-1.19-4.fc39.ppc64le 12/153 Verifying : efi-srpm-macros-5-9.fc39.noarch 13/153 Verifying : fedora-gpg-keys-39-1.noarch 14/153 Verifying : fedora-repos-39-1.noarch 15/153 Verifying : file-5.44-5.fc39.ppc64le 16/153 Verifying : file-libs-5.44-5.fc39.ppc64le 17/153 Verifying : filesystem-3.18-6.fc39.ppc64le 18/153 Verifying : findutils-1:4.9.0-5.fc39.ppc64le 19/153 Verifying : fonts-srpm-macros-1:2.0.5-12.fc39.noarch 20/153 Verifying : fpc-srpm-macros-1.3-8.fc39.noarch 21/153 Verifying : gawk-5.2.2-2.fc39.ppc64le 22/153 Verifying : gdbm-libs-1:1.23-4.fc39.ppc64le 23/153 Verifying : ghc-srpm-macros-1.6.1-2.fc39.noarch 24/153 Verifying : gmp-1:6.2.1-5.fc39.ppc64le 25/153 Verifying : gnat-srpm-macros-6-3.fc39.noarch 26/153 Verifying : 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libselinux-3.5-5.fc39.ppc64le 47/153 Verifying : libsemanage-3.5-4.fc39.ppc64le 48/153 Verifying : libsepol-3.5-2.fc39.ppc64le 49/153 Verifying : libsigsegv-2.14-5.fc39.ppc64le 50/153 Verifying : libtasn1-4.19.0-3.fc39.ppc64le 51/153 Verifying : libunistring-1.1-5.fc39.ppc64le 52/153 Verifying : libutempter-1.2.1-10.fc39.ppc64le 53/153 Verifying : libverto-0.3.2-6.fc39.ppc64le 54/153 Verifying : libxcrypt-4.4.36-2.fc39.ppc64le 55/153 Verifying : libxml2-2.10.4-3.fc39.ppc64le 56/153 Verifying : libzstd-1.5.5-4.fc39.ppc64le 57/153 Verifying : lua-libs-5.4.6-3.fc39.ppc64le 58/153 Verifying : lz4-libs-1.9.4-4.fc39.ppc64le 59/153 Verifying : mpfr-4.2.0-3.fc39.ppc64le 60/153 Verifying : ocaml-srpm-macros-8-2.fc39.noarch 61/153 Verifying : openblas-srpm-macros-2-14.fc39.noarch 62/153 Verifying : openldap-2.6.6-1.fc39.ppc64le 63/153 Verifying : openssl-libs-1:3.1.1-4.fc39.ppc64le 64/153 Verifying : package-notes-srpm-macros-0.5-9.fc39.noarch 65/153 Verifying : patch-2.7.6-22.fc39.ppc64le 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alternatives-1.26-1.fc39.ppc64le 87/153 Verifying : ansible-srpm-macros-1-12.fc39.noarch 88/153 Verifying : audit-libs-3.1.2-8.fc39.ppc64le 89/153 Verifying : bash-5.2.26-1.fc39.ppc64le 90/153 Verifying : binutils-2.40-14.fc39.ppc64le 91/153 Verifying : binutils-gold-2.40-14.fc39.ppc64le 92/153 Verifying : coreutils-9.3-5.fc39.ppc64le 93/153 Verifying : coreutils-common-9.3-5.fc39.ppc64le 94/153 Verifying : crypto-policies-20231204-1.git1e3a2e4.fc39.noarc 95/153 Verifying : curl-8.2.1-4.fc39.ppc64le 96/153 Verifying : debugedit-5.0-12.fc39.ppc64le 97/153 Verifying : elfutils-0.190-4.fc39.ppc64le 98/153 Verifying : elfutils-debuginfod-client-0.190-4.fc39.ppc64le 99/153 Verifying : elfutils-default-yama-scope-0.190-4.fc39.noarch 100/153 Verifying : elfutils-libelf-0.190-4.fc39.ppc64le 101/153 Verifying : elfutils-libs-0.190-4.fc39.ppc64le 102/153 Verifying : fedora-release-39-36.noarch 103/153 Verifying : fedora-release-common-39-36.noarch 104/153 Verifying : fedora-release-identity-basic-39-36.noarch 105/153 Verifying : forge-srpm-macros-0.2.0-3.fc39.noarch 106/153 Verifying : gdb-minimal-14.1-4.fc39.ppc64le 107/153 Verifying : glibc-2.38-16.fc39.ppc64le 108/153 Verifying : glibc-common-2.38-16.fc39.ppc64le 109/153 Verifying : glibc-gconv-extra-2.38-16.fc39.ppc64le 110/153 Verifying : glibc-minimal-langpack-2.38-16.fc39.ppc64le 111/153 Verifying : go-srpm-macros-3.4.0-2.fc39.noarch 112/153 Verifying : krb5-libs-1.21.2-3.fc39.ppc64le 113/153 Verifying : libacl-2.3.1-9.fc39.ppc64le 114/153 Verifying : libblkid-2.39.3-6.fc39.ppc64le 115/153 Verifying : libcap-2.48-9.fc39.ppc64le 116/153 Verifying : libcurl-8.2.1-4.fc39.ppc64le 117/153 Verifying : libfdisk-2.39.3-6.fc39.ppc64le 118/153 Verifying : libgcc-13.2.1-6.fc39.ppc64le 119/153 Verifying : libgomp-13.2.1-6.fc39.ppc64le 120/153 Verifying : libidn2-2.3.7-1.fc39.ppc64le 121/153 Verifying : libmount-2.39.3-6.fc39.ppc64le 122/153 Verifying : libnghttp2-1.55.1-4.fc39.ppc64le 123/153 Verifying : libsmartcols-2.39.3-6.fc39.ppc64le 124/153 Verifying : libssh-0.10.6-2.fc39.ppc64le 125/153 Verifying : libssh-config-0.10.6-2.fc39.noarch 126/153 Verifying : libstdc++-13.2.1-6.fc39.ppc64le 127/153 Verifying : libtirpc-1.3.4-0.rc2.fc39.ppc64le 128/153 Verifying : libuuid-2.39.3-6.fc39.ppc64le 129/153 Verifying : lua-srpm-macros-1-13.fc39.noarch 130/153 Verifying : ncurses-base-6.4-7.20230520.fc39.1.noarch 131/153 Verifying : ncurses-libs-6.4-7.20230520.fc39.1.ppc64le 132/153 Verifying : p11-kit-0.25.3-1.fc39.ppc64le 133/153 Verifying : p11-kit-trust-0.25.3-1.fc39.ppc64le 134/153 Verifying : pam-1.5.3-3.fc39.ppc64le 135/153 Verifying : pam-libs-1.5.3-3.fc39.ppc64le 136/153 Verifying : publicsuffix-list-dafsa-20240107-1.fc39.noarch 137/153 Verifying : pyproject-srpm-macros-1.12.0-1.fc39.noarch 138/153 Verifying : qt5-srpm-macros-5.15.12-1.fc39.noarch 139/153 Verifying : qt6-srpm-macros-6.6.2-1.fc39.noarch 140/153 Verifying : readline-8.2-6.fc39.ppc64le 141/153 Verifying : redhat-rpm-config-265-1.fc39.noarch 142/153 Verifying : rpm-4.19.1.1-1.fc39.ppc64le 143/153 Verifying : rpm-build-4.19.1.1-1.fc39.ppc64le 144/153 Verifying : rpm-build-libs-4.19.1.1-1.fc39.ppc64le 145/153 Verifying : rpm-libs-4.19.1.1-1.fc39.ppc64le 146/153 Verifying : rpm-sequoia-1.6.0-1.fc39.ppc64le 147/153 Verifying : rpmautospec-rpm-macros-0.6.3-1.fc39.noarch 148/153 Verifying : rust-srpm-macros-26.1-1.fc39.noarch 149/153 Verifying : shadow-utils-2:4.14.0-2.fc39.ppc64le 150/153 Verifying : systemd-libs-254.9-1.fc39.ppc64le 151/153 Verifying : util-linux-2.39.3-6.fc39.ppc64le 152/153 Verifying : util-linux-core-2.39.3-6.fc39.ppc64le 153/153 Installed: alternatives-1.26-1.fc39.ppc64le ansible-srpm-macros-1-12.fc39.noarch audit-libs-3.1.2-8.fc39.ppc64le authselect-1.4.3-1.fc39.ppc64le authselect-libs-1.4.3-1.fc39.ppc64le basesystem-11-18.fc39.noarch bash-5.2.26-1.fc39.ppc64le binutils-2.40-14.fc39.ppc64le binutils-gold-2.40-14.fc39.ppc64le bzip2-1.0.8-16.fc39.ppc64le bzip2-libs-1.0.8-16.fc39.ppc64le ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch coreutils-9.3-5.fc39.ppc64le coreutils-common-9.3-5.fc39.ppc64le cpio-2.14-4.fc39.ppc64le cracklib-2.9.11-2.fc39.ppc64le crypto-policies-20231204-1.git1e3a2e4.fc39.noarch curl-8.2.1-4.fc39.ppc64le cyrus-sasl-lib-2.1.28-11.fc39.ppc64le debugedit-5.0-12.fc39.ppc64le diffutils-3.10-3.fc39.ppc64le dwz-0.15-3.fc39.ppc64le ed-1.19-4.fc39.ppc64le efi-srpm-macros-5-9.fc39.noarch elfutils-0.190-4.fc39.ppc64le elfutils-debuginfod-client-0.190-4.fc39.ppc64le elfutils-default-yama-scope-0.190-4.fc39.noarch elfutils-libelf-0.190-4.fc39.ppc64le elfutils-libs-0.190-4.fc39.ppc64le fedora-gpg-keys-39-1.noarch fedora-release-39-36.noarch fedora-release-common-39-36.noarch fedora-release-identity-basic-39-36.noarch fedora-repos-39-1.noarch file-5.44-5.fc39.ppc64le file-libs-5.44-5.fc39.ppc64le filesystem-3.18-6.fc39.ppc64le findutils-1:4.9.0-5.fc39.ppc64le fonts-srpm-macros-1:2.0.5-12.fc39.noarch forge-srpm-macros-0.2.0-3.fc39.noarch fpc-srpm-macros-1.3-8.fc39.noarch gawk-5.2.2-2.fc39.ppc64le gdb-minimal-14.1-4.fc39.ppc64le gdbm-libs-1:1.23-4.fc39.ppc64le ghc-srpm-macros-1.6.1-2.fc39.noarch glibc-2.38-16.fc39.ppc64le glibc-common-2.38-16.fc39.ppc64le glibc-gconv-extra-2.38-16.fc39.ppc64le glibc-minimal-langpack-2.38-16.fc39.ppc64le gmp-1:6.2.1-5.fc39.ppc64le gnat-srpm-macros-6-3.fc39.noarch go-srpm-macros-3.4.0-2.fc39.noarch grep-3.11-3.fc39.ppc64le gzip-1.12-6.fc39.ppc64le info-7.0.3-3.fc39.ppc64le jansson-2.13.1-7.fc39.ppc64le kernel-srpm-macros-1.0-20.fc39.noarch keyutils-libs-1.6.1-7.fc39.ppc64le krb5-libs-1.21.2-3.fc39.ppc64le libacl-2.3.1-9.fc39.ppc64le libarchive-3.7.1-1.fc39.ppc64le libattr-2.5.1-8.fc39.ppc64le libblkid-2.39.3-6.fc39.ppc64le libbrotli-1.1.0-1.fc39.ppc64le libcap-2.48-9.fc39.ppc64le libcap-ng-0.8.3-8.fc39.ppc64le libcom_err-1.47.0-2.fc39.ppc64le libcurl-8.2.1-4.fc39.ppc64le libdb-5.3.28-56.fc39.ppc64le libeconf-0.5.2-1.fc39.ppc64le libevent-2.1.12-9.fc39.ppc64le libfdisk-2.39.3-6.fc39.ppc64le libffi-3.4.4-4.fc39.ppc64le libgcc-13.2.1-6.fc39.ppc64le libgomp-13.2.1-6.fc39.ppc64le libidn2-2.3.7-1.fc39.ppc64le libmount-2.39.3-6.fc39.ppc64le libnghttp2-1.55.1-4.fc39.ppc64le libnsl2-2.0.0-6.fc39.ppc64le libpkgconf-1.9.5-2.fc39.ppc64le libpsl-0.21.2-4.fc39.ppc64le libpwquality-1.4.5-6.fc39.ppc64le librtas-2.0.4-3.fc39.ppc64le libselinux-3.5-5.fc39.ppc64le libsemanage-3.5-4.fc39.ppc64le libsepol-3.5-2.fc39.ppc64le libsigsegv-2.14-5.fc39.ppc64le libsmartcols-2.39.3-6.fc39.ppc64le libssh-0.10.6-2.fc39.ppc64le libssh-config-0.10.6-2.fc39.noarch libstdc++-13.2.1-6.fc39.ppc64le libtasn1-4.19.0-3.fc39.ppc64le libtirpc-1.3.4-0.rc2.fc39.ppc64le libunistring-1.1-5.fc39.ppc64le libutempter-1.2.1-10.fc39.ppc64le libuuid-2.39.3-6.fc39.ppc64le libverto-0.3.2-6.fc39.ppc64le libxcrypt-4.4.36-2.fc39.ppc64le libxml2-2.10.4-3.fc39.ppc64le libzstd-1.5.5-4.fc39.ppc64le lua-libs-5.4.6-3.fc39.ppc64le lua-srpm-macros-1-13.fc39.noarch lz4-libs-1.9.4-4.fc39.ppc64le mpfr-4.2.0-3.fc39.ppc64le ncurses-base-6.4-7.20230520.fc39.1.noarch ncurses-libs-6.4-7.20230520.fc39.1.ppc64le ocaml-srpm-macros-8-2.fc39.noarch openblas-srpm-macros-2-14.fc39.noarch openldap-2.6.6-1.fc39.ppc64le openssl-libs-1:3.1.1-4.fc39.ppc64le p11-kit-0.25.3-1.fc39.ppc64le p11-kit-trust-0.25.3-1.fc39.ppc64le package-notes-srpm-macros-0.5-9.fc39.noarch pam-1.5.3-3.fc39.ppc64le pam-libs-1.5.3-3.fc39.ppc64le patch-2.7.6-22.fc39.ppc64le pcre2-10.42-1.fc39.2.ppc64le pcre2-syntax-10.42-1.fc39.2.noarch perl-srpm-macros-1-51.fc39.noarch pkgconf-1.9.5-2.fc39.ppc64le pkgconf-m4-1.9.5-2.fc39.noarch pkgconf-pkg-config-1.9.5-2.fc39.ppc64le popt-1.19-3.fc39.ppc64le publicsuffix-list-dafsa-20240107-1.fc39.noarch pyproject-srpm-macros-1.12.0-1.fc39.noarch python-srpm-macros-3.12-4.fc39.noarch qt5-srpm-macros-5.15.12-1.fc39.noarch qt6-srpm-macros-6.6.2-1.fc39.noarch readline-8.2-6.fc39.ppc64le redhat-rpm-config-265-1.fc39.noarch rpm-4.19.1.1-1.fc39.ppc64le rpm-build-4.19.1.1-1.fc39.ppc64le rpm-build-libs-4.19.1.1-1.fc39.ppc64le rpm-libs-4.19.1.1-1.fc39.ppc64le rpm-sequoia-1.6.0-1.fc39.ppc64le rpmautospec-rpm-macros-0.6.3-1.fc39.noarch rust-srpm-macros-26.1-1.fc39.noarch sed-4.8-14.fc39.ppc64le setup-2.14.4-1.fc39.noarch shadow-utils-2:4.14.0-2.fc39.ppc64le sqlite-libs-3.42.0-7.fc39.ppc64le systemd-libs-254.9-1.fc39.ppc64le tar-2:1.35-2.fc39.ppc64le unzip-6.0-62.fc39.ppc64le util-linux-2.39.3-6.fc39.ppc64le util-linux-core-2.39.3-6.fc39.ppc64le which-2.21-40.fc39.ppc64le xxhash-libs-0.8.2-1.fc39.ppc64le xz-5.4.4-1.fc39.ppc64le xz-libs-5.4.4-1.fc39.ppc64le zip-3.0-39.fc39.ppc64le zlib-1.2.13-4.fc39.ppc64le zstd-1.5.5-4.fc39.ppc64le Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: alternatives-1.26-1.fc39.ppc64le ansible-srpm-macros-1-12.fc39.noarch audit-libs-3.1.2-8.fc39.ppc64le authselect-1.4.3-1.fc39.ppc64le authselect-libs-1.4.3-1.fc39.ppc64le basesystem-11-18.fc39.noarch bash-5.2.26-1.fc39.ppc64le binutils-2.40-14.fc39.ppc64le binutils-gold-2.40-14.fc39.ppc64le bzip2-1.0.8-16.fc39.ppc64le bzip2-libs-1.0.8-16.fc39.ppc64le ca-certificates-2023.2.60_v7.0.306-2.fc39.noarch coreutils-9.3-5.fc39.ppc64le coreutils-common-9.3-5.fc39.ppc64le cpio-2.14-4.fc39.ppc64le cracklib-2.9.11-2.fc39.ppc64le crypto-policies-20231204-1.git1e3a2e4.fc39.noarch curl-8.2.1-4.fc39.ppc64le cyrus-sasl-lib-2.1.28-11.fc39.ppc64le debugedit-5.0-12.fc39.ppc64le diffutils-3.10-3.fc39.ppc64le dwz-0.15-3.fc39.ppc64le ed-1.19-4.fc39.ppc64le efi-srpm-macros-5-9.fc39.noarch elfutils-0.190-4.fc39.ppc64le elfutils-debuginfod-client-0.190-4.fc39.ppc64le elfutils-default-yama-scope-0.190-4.fc39.noarch elfutils-libelf-0.190-4.fc39.ppc64le elfutils-libs-0.190-4.fc39.ppc64le fedora-gpg-keys-39-1.noarch fedora-release-39-36.noarch fedora-release-common-39-36.noarch fedora-release-identity-basic-39-36.noarch fedora-repos-39-1.noarch file-5.44-5.fc39.ppc64le file-libs-5.44-5.fc39.ppc64le filesystem-3.18-6.fc39.ppc64le findutils-4.9.0-5.fc39.ppc64le fonts-srpm-macros-2.0.5-12.fc39.noarch forge-srpm-macros-0.2.0-3.fc39.noarch fpc-srpm-macros-1.3-8.fc39.noarch gawk-5.2.2-2.fc39.ppc64le gdb-minimal-14.1-4.fc39.ppc64le gdbm-libs-1.23-4.fc39.ppc64le ghc-srpm-macros-1.6.1-2.fc39.noarch glibc-2.38-16.fc39.ppc64le glibc-common-2.38-16.fc39.ppc64le glibc-gconv-extra-2.38-16.fc39.ppc64le glibc-minimal-langpack-2.38-16.fc39.ppc64le gmp-6.2.1-5.fc39.ppc64le gnat-srpm-macros-6-3.fc39.noarch go-srpm-macros-3.4.0-2.fc39.noarch gpg-pubkey-18b8e74c-62f2920f grep-3.11-3.fc39.ppc64le gzip-1.12-6.fc39.ppc64le info-7.0.3-3.fc39.ppc64le jansson-2.13.1-7.fc39.ppc64le kernel-srpm-macros-1.0-20.fc39.noarch keyutils-libs-1.6.1-7.fc39.ppc64le krb5-libs-1.21.2-3.fc39.ppc64le libacl-2.3.1-9.fc39.ppc64le libarchive-3.7.1-1.fc39.ppc64le libattr-2.5.1-8.fc39.ppc64le libblkid-2.39.3-6.fc39.ppc64le libbrotli-1.1.0-1.fc39.ppc64le libcap-2.48-9.fc39.ppc64le libcap-ng-0.8.3-8.fc39.ppc64le libcom_err-1.47.0-2.fc39.ppc64le libcurl-8.2.1-4.fc39.ppc64le libdb-5.3.28-56.fc39.ppc64le libeconf-0.5.2-1.fc39.ppc64le libevent-2.1.12-9.fc39.ppc64le libfdisk-2.39.3-6.fc39.ppc64le libffi-3.4.4-4.fc39.ppc64le libgcc-13.2.1-6.fc39.ppc64le libgomp-13.2.1-6.fc39.ppc64le libidn2-2.3.7-1.fc39.ppc64le libmount-2.39.3-6.fc39.ppc64le libnghttp2-1.55.1-4.fc39.ppc64le libnsl2-2.0.0-6.fc39.ppc64le libpkgconf-1.9.5-2.fc39.ppc64le libpsl-0.21.2-4.fc39.ppc64le libpwquality-1.4.5-6.fc39.ppc64le librtas-2.0.4-3.fc39.ppc64le libselinux-3.5-5.fc39.ppc64le libsemanage-3.5-4.fc39.ppc64le libsepol-3.5-2.fc39.ppc64le libsigsegv-2.14-5.fc39.ppc64le libsmartcols-2.39.3-6.fc39.ppc64le libssh-0.10.6-2.fc39.ppc64le libssh-config-0.10.6-2.fc39.noarch libstdc++-13.2.1-6.fc39.ppc64le libtasn1-4.19.0-3.fc39.ppc64le libtirpc-1.3.4-0.rc2.fc39.ppc64le libunistring-1.1-5.fc39.ppc64le libutempter-1.2.1-10.fc39.ppc64le libuuid-2.39.3-6.fc39.ppc64le libverto-0.3.2-6.fc39.ppc64le libxcrypt-4.4.36-2.fc39.ppc64le libxml2-2.10.4-3.fc39.ppc64le libzstd-1.5.5-4.fc39.ppc64le lua-libs-5.4.6-3.fc39.ppc64le lua-srpm-macros-1-13.fc39.noarch lz4-libs-1.9.4-4.fc39.ppc64le mpfr-4.2.0-3.fc39.ppc64le ncurses-base-6.4-7.20230520.fc39.1.noarch ncurses-libs-6.4-7.20230520.fc39.1.ppc64le ocaml-srpm-macros-8-2.fc39.noarch openblas-srpm-macros-2-14.fc39.noarch openldap-2.6.6-1.fc39.ppc64le openssl-libs-3.1.1-4.fc39.ppc64le p11-kit-0.25.3-1.fc39.ppc64le p11-kit-trust-0.25.3-1.fc39.ppc64le package-notes-srpm-macros-0.5-9.fc39.noarch pam-1.5.3-3.fc39.ppc64le pam-libs-1.5.3-3.fc39.ppc64le patch-2.7.6-22.fc39.ppc64le pcre2-10.42-1.fc39.2.ppc64le pcre2-syntax-10.42-1.fc39.2.noarch perl-srpm-macros-1-51.fc39.noarch pkgconf-1.9.5-2.fc39.ppc64le pkgconf-m4-1.9.5-2.fc39.noarch pkgconf-pkg-config-1.9.5-2.fc39.ppc64le popt-1.19-3.fc39.ppc64le publicsuffix-list-dafsa-20240107-1.fc39.noarch pyproject-srpm-macros-1.12.0-1.fc39.noarch python-srpm-macros-3.12-4.fc39.noarch qt5-srpm-macros-5.15.12-1.fc39.noarch qt6-srpm-macros-6.6.2-1.fc39.noarch readline-8.2-6.fc39.ppc64le redhat-rpm-config-265-1.fc39.noarch rpm-4.19.1.1-1.fc39.ppc64le rpm-build-4.19.1.1-1.fc39.ppc64le rpm-build-libs-4.19.1.1-1.fc39.ppc64le rpm-libs-4.19.1.1-1.fc39.ppc64le rpm-sequoia-1.6.0-1.fc39.ppc64le rpmautospec-rpm-macros-0.6.3-1.fc39.noarch rust-srpm-macros-26.1-1.fc39.noarch sed-4.8-14.fc39.ppc64le setup-2.14.4-1.fc39.noarch shadow-utils-4.14.0-2.fc39.ppc64le sqlite-libs-3.42.0-7.fc39.ppc64le systemd-libs-254.9-1.fc39.ppc64le tar-1.35-2.fc39.ppc64le unzip-6.0-62.fc39.ppc64le util-linux-2.39.3-6.fc39.ppc64le util-linux-core-2.39.3-6.fc39.ppc64le which-2.21-40.fc39.ppc64le xxhash-libs-0.8.2-1.fc39.ppc64le xz-5.4.4-1.fc39.ppc64le xz-libs-5.4.4-1.fc39.ppc64le zip-3.0-39.fc39.ppc64le zlib-1.2.13-4.fc39.ppc64le zstd-1.5.5-4.fc39.ppc64le Start: buildsrpm Start: rpmbuild -bs Building target platforms: ppc64le Building for target ppc64le setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Finish: rpmbuild -bs cp: preserving permissions for ‘/var/lib/copr-rpmbuild/results/chroot_scan/var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log’: No such file or directory INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.log /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.librepo.log /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.rpm.log Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-8twjcqd_/litex-pythondata-cpu-rocket/litex-pythondata-cpu-rocket.spec) Config(child) 3 minutes 13 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm) Config(fedora-39-ppc64le) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-ppc64le-bootstrap-1709342028.223586/root. INFO: reusing tmpfs at /var/lib/mock/fedora-39-ppc64le-bootstrap-1709342028.223586/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-4.19.0-1.fc39.ppc64le rpm-sequoia-1.5.0-1.fc39.ppc64le python3-dnf-4.19.0-1.fc39.noarch python3-dnf-plugins-core-4.5.0-1.fc39.noarch yum-4.19.0-1.fc39.noarch Finish: chroot init Start: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Start: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Building target platforms: ppc64le Building for target ppc64le setting SOURCE_DATE_EPOCH=1637193600 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 25 kB/s | 1.5 kB 00:00 Additional repo copr_rezso_ML 22 kB/s | 1.5 kB 00:00 Additional repo copr_rezso_CUDA 27 kB/s | 1.5 kB 00:00 Additional repo http_developer_download_nvidia_ 34 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 39 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 37 kB/s | 3.5 kB 00:00 fedora 41 kB/s | 3.8 kB 00:00 updates 96 kB/s | 4.9 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: git ppc64le 2.44.0-1.fc39 updates 53 k python3-devel ppc64le 3.12.2-1.fc39 updates 313 k python3-setuptools noarch 67.7.2-7.fc39 fedora 1.5 M Installing dependencies: expat ppc64le 2.6.0-1.fc39 updates 119 k git-core ppc64le 2.44.0-1.fc39 updates 4.9 M git-core-doc noarch 2.44.0-1.fc39 updates 2.9 M groff-base ppc64le 1.23.0-3.fc39 updates 1.2 M less ppc64le 633-2.fc39 fedora 189 k libb2 ppc64le 0.98.1-9.fc39 fedora 25 k libcbor ppc64le 0.10.2-2.fc39 fedora 59 k libedit ppc64le 3.1-48.20230828cvs.fc39 fedora 121 k libfido2 ppc64le 1.13.0-3.fc39 fedora 109 k mpdecimal ppc64le 2.5.1-7.fc39 fedora 104 k ncurses ppc64le 6.4-7.20230520.fc39.1 updates 424 k openssh ppc64le 9.3p1-10.fc39 updates 461 k openssh-clients ppc64le 9.3p1-10.fc39 updates 793 k perl-AutoLoader noarch 5.74-502.fc39 updates 21 k perl-B ppc64le 1.88-502.fc39 updates 181 k perl-Carp noarch 1.54-500.fc39 fedora 29 k perl-Class-Struct noarch 0.68-502.fc39 updates 22 k perl-Data-Dumper ppc64le 2.188-501.fc39 fedora 57 k perl-Digest noarch 1.20-500.fc39 fedora 25 k perl-Digest-MD5 ppc64le 2.58-500.fc39 fedora 36 k perl-DynaLoader ppc64le 1.54-502.fc39 updates 26 k perl-Encode ppc64le 4:3.19-500.fc39 fedora 1.7 M perl-Errno ppc64le 1.37-502.fc39 updates 15 k perl-Error noarch 1:0.17029-13.fc39 fedora 40 k perl-Exporter noarch 5.77-500.fc39 fedora 31 k perl-Fcntl ppc64le 1.15-502.fc39 updates 21 k perl-File-Basename noarch 2.86-502.fc39 updates 17 k perl-File-Find noarch 1.43-502.fc39 updates 25 k perl-File-Path noarch 2.18-500.fc39 fedora 35 k perl-File-Temp noarch 1:0.231.100-500.fc39 fedora 58 k perl-File-stat noarch 1.13-502.fc39 updates 17 k perl-FileHandle noarch 2.05-502.fc39 updates 16 k perl-Getopt-Long noarch 1:2.54-500.fc39 fedora 60 k perl-Getopt-Std noarch 1.13-502.fc39 updates 16 k perl-Git noarch 2.44.0-1.fc39 updates 40 k perl-HTTP-Tiny noarch 0.088-3.fc39 fedora 56 k perl-IO ppc64le 1.52-502.fc39 updates 83 k perl-IO-Socket-IP noarch 0.42-1.fc39 fedora 42 k perl-IO-Socket-SSL noarch 2.083-3.fc39 fedora 225 k perl-IPC-Open3 noarch 1.22-502.fc39 updates 22 k perl-MIME-Base64 ppc64le 3.16-500.fc39 fedora 30 k perl-Mozilla-CA noarch 20230801-1.fc39 fedora 13 k perl-Net-SSLeay ppc64le 1.92-10.fc39 fedora 367 k perl-POSIX ppc64le 2.13-502.fc39 updates 117 k perl-PathTools ppc64le 3.89-500.fc39 fedora 88 k perl-Pod-Escapes noarch 1:1.07-500.fc39 fedora 20 k perl-Pod-Perldoc noarch 3.28.01-501.fc39 fedora 86 k perl-Pod-Simple noarch 1:3.45-4.fc39 fedora 218 k perl-Pod-Usage noarch 4:2.03-500.fc39 fedora 39 k perl-Scalar-List-Utils ppc64le 5:1.63-500.fc39 fedora 75 k perl-SelectSaver noarch 1.02-502.fc39 updates 12 k perl-Socket ppc64le 4:2.037-3.fc39 fedora 56 k perl-Storable ppc64le 1:3.32-500.fc39 fedora 103 k perl-Symbol noarch 1.09-502.fc39 updates 14 k perl-Term-ANSIColor noarch 5.01-501.fc39 fedora 47 k perl-Term-Cap noarch 1.18-500.fc39 fedora 22 k perl-TermReadKey ppc64le 2.38-18.fc39 fedora 37 k perl-Text-ParseWords noarch 3.31-500.fc39 fedora 16 k perl-Text-Tabs+Wrap noarch 2023.0511-3.fc39 fedora 22 k perl-Time-Local noarch 2:1.350-3.fc39 fedora 34 k perl-URI noarch 5.21-1.fc39 fedora 125 k perl-base noarch 2.27-502.fc39 updates 16 k perl-constant noarch 1.33-501.fc39 fedora 22 k perl-if noarch 0.61.000-502.fc39 updates 14 k perl-interpreter ppc64le 4:5.38.2-502.fc39 updates 72 k perl-lib ppc64le 0.65-502.fc39 updates 15 k perl-libnet noarch 3.15-501.fc39 fedora 129 k perl-libs ppc64le 4:5.38.2-502.fc39 updates 2.4 M perl-locale noarch 1.10-502.fc39 updates 14 k perl-mro ppc64le 1.28-502.fc39 updates 29 k perl-overload noarch 1.37-502.fc39 updates 46 k perl-overloading noarch 0.02-502.fc39 updates 13 k perl-parent noarch 1:0.241-500.fc39 fedora 14 k perl-podlators noarch 1:5.01-500.fc39 fedora 125 k perl-vars noarch 1.05-502.fc39 updates 13 k pyproject-rpm-macros noarch 1.12.0-1.fc39 updates 41 k python-pip-wheel noarch 23.2.1-1.fc39 fedora 1.5 M python-rpm-macros noarch 3.12-4.fc39 fedora 19 k python3 ppc64le 3.12.2-1.fc39 updates 27 k python3-libs ppc64le 3.12.2-1.fc39 updates 9.4 M python3-packaging noarch 23.1-4.fc39 fedora 114 k python3-rpm-generators noarch 14-7.fc39 fedora 30 k python3-rpm-macros noarch 3.12-4.fc39 fedora 14 k tzdata noarch 2024a-2.fc39 updates 715 k Transaction Summary ================================================================================ Install 87 Packages Total download size: 32 M Installed size: 155 M Downloading Packages: (1/87): libb2-0.98.1-9.fc39.ppc64le.rpm 244 kB/s | 25 kB 00:00 (2/87): libcbor-0.10.2-2.fc39.ppc64le.rpm 431 kB/s | 59 kB 00:00 (3/87): libedit-3.1-48.20230828cvs.fc39.ppc64le 863 kB/s | 121 kB 00:00 (4/87): libfido2-1.13.0-3.fc39.ppc64le.rpm 911 kB/s | 109 kB 00:00 (5/87): less-633-2.fc39.ppc64le.rpm 665 kB/s | 189 kB 00:00 (6/87): perl-Carp-1.54-500.fc39.noarch.rpm 860 kB/s | 29 kB 00:00 (7/87): mpdecimal-2.5.1-7.fc39.ppc64le.rpm 1.8 MB/s | 104 kB 00:00 (8/87): perl-Data-Dumper-2.188-501.fc39.ppc64le 1.3 MB/s | 57 kB 00:00 (9/87): perl-Digest-1.20-500.fc39.noarch.rpm 708 kB/s | 25 kB 00:00 (10/87): perl-Digest-MD5-2.58-500.fc39.ppc64le. 1.0 MB/s | 36 kB 00:00 (11/87): perl-Error-0.17029-13.fc39.noarch.rpm 1.1 MB/s | 40 kB 00:00 (12/87): perl-Exporter-5.77-500.fc39.noarch.rpm 907 kB/s | 31 kB 00:00 (13/87): perl-File-Path-2.18-500.fc39.noarch.rp 998 kB/s | 35 kB 00:00 (14/87): perl-File-Temp-0.231.100-500.fc39.noar 1.4 MB/s | 58 kB 00:00 (15/87): perl-Getopt-Long-2.54-500.fc39.noarch. 1.4 MB/s | 60 kB 00:00 (16/87): perl-HTTP-Tiny-0.088-3.fc39.noarch.rpm 1.4 MB/s | 56 kB 00:00 (17/87): perl-IO-Socket-IP-0.42-1.fc39.noarch.r 1.0 MB/s | 42 kB 00:00 (18/87): perl-Encode-3.19-500.fc39.ppc64le.rpm 10 MB/s | 1.7 MB 00:00 (19/87): perl-MIME-Base64-3.16-500.fc39.ppc64le 872 kB/s | 30 kB 00:00 (20/87): perl-Mozilla-CA-20230801-1.fc39.noarch 431 kB/s | 13 kB 00:00 (21/87): perl-IO-Socket-SSL-2.083-3.fc39.noarch 2.8 MB/s | 225 kB 00:00 (22/87): perl-PathTools-3.89-500.fc39.ppc64le.r 2.6 MB/s | 88 kB 00:00 (23/87): perl-Pod-Escapes-1.07-500.fc39.noarch. 514 kB/s | 20 kB 00:00 (24/87): perl-Pod-Perldoc-3.28.01-501.fc39.noar 1.9 MB/s | 86 kB 00:00 (25/87): perl-Net-SSLeay-1.92-10.fc39.ppc64le.r 3.1 MB/s | 367 kB 00:00 (26/87): perl-Pod-Simple-3.45-4.fc39.noarch.rpm 3.2 MB/s | 218 kB 00:00 (27/87): perl-Pod-Usage-2.03-500.fc39.noarch.rp 1.1 MB/s | 39 kB 00:00 (28/87): perl-Socket-2.037-3.fc39.ppc64le.rpm 1.6 MB/s | 56 kB 00:00 (29/87): perl-Storable-3.32-500.fc39.ppc64le.rp 3.0 MB/s | 103 kB 00:00 (30/87): perl-Scalar-List-Utils-1.63-500.fc39.p 2.0 MB/s | 75 kB 00:00 (31/87): perl-Term-ANSIColor-5.01-501.fc39.noar 1.6 MB/s | 47 kB 00:00 (32/87): perl-Term-Cap-1.18-500.fc39.noarch.rpm 696 kB/s | 22 kB 00:00 (33/87): perl-TermReadKey-2.38-18.fc39.ppc64le. 1.1 MB/s | 37 kB 00:00 (34/87): perl-Text-ParseWords-3.31-500.fc39.noa 502 kB/s | 16 kB 00:00 (35/87): perl-Text-Tabs+Wrap-2023.0511-3.fc39.n 695 kB/s | 22 kB 00:00 (36/87): perl-Time-Local-1.350-3.fc39.noarch.rp 1.1 MB/s | 34 kB 00:00 (37/87): perl-URI-5.21-1.fc39.noarch.rpm 3.8 MB/s | 125 kB 00:00 (38/87): perl-constant-1.33-501.fc39.noarch.rpm 713 kB/s | 22 kB 00:00 (39/87): perl-libnet-3.15-501.fc39.noarch.rpm 3.5 MB/s | 129 kB 00:00 (40/87): perl-parent-0.241-500.fc39.noarch.rpm 470 kB/s | 14 kB 00:00 (41/87): perl-podlators-5.01-500.fc39.noarch.rp 3.3 MB/s | 125 kB 00:00 (42/87): python-rpm-macros-3.12-4.fc39.noarch.r 635 kB/s | 19 kB 00:00 (43/87): python3-packaging-23.1-4.fc39.noarch.r 3.1 MB/s | 114 kB 00:00 (44/87): python3-rpm-generators-14-7.fc39.noarc 1.0 MB/s | 30 kB 00:00 (45/87): python3-rpm-macros-3.12-4.fc39.noarch. 476 kB/s | 14 kB 00:00 (46/87): python-pip-wheel-23.2.1-1.fc39.noarch. 14 MB/s | 1.5 MB 00:00 (47/87): python3-setuptools-67.7.2-7.fc39.noarc 26 MB/s | 1.5 MB 00:00 (48/87): expat-2.6.0-1.fc39.ppc64le.rpm 2.3 MB/s | 119 kB 00:00 (49/87): git-2.44.0-1.fc39.ppc64le.rpm 1.1 MB/s | 53 kB 00:00 (50/87): groff-base-1.23.0-3.fc39.ppc64le.rpm 15 MB/s | 1.2 MB 00:00 (51/87): ncurses-6.4-7.20230520.fc39.1.ppc64le. 7.1 MB/s | 424 kB 00:00 (52/87): git-core-2.44.0-1.fc39.ppc64le.rpm 25 MB/s | 4.9 MB 00:00 (53/87): git-core-doc-2.44.0-1.fc39.noarch.rpm 14 MB/s | 2.9 MB 00:00 (54/87): openssh-9.3p1-10.fc39.ppc64le.rpm 6.5 MB/s | 461 kB 00:00 (55/87): openssh-clients-9.3p1-10.fc39.ppc64le. 12 MB/s | 793 kB 00:00 (56/87): perl-AutoLoader-5.74-502.fc39.noarch.r 376 kB/s | 21 kB 00:00 (57/87): perl-B-1.88-502.fc39.ppc64le.rpm 3.0 MB/s | 181 kB 00:00 (58/87): perl-Class-Struct-0.68-502.fc39.noarch 444 kB/s | 22 kB 00:00 (59/87): perl-DynaLoader-1.54-502.fc39.ppc64le. 520 kB/s | 26 kB 00:00 (60/87): perl-Errno-1.37-502.fc39.ppc64le.rpm 329 kB/s | 15 kB 00:00 (61/87): perl-Fcntl-1.15-502.fc39.ppc64le.rpm 616 kB/s | 21 kB 00:00 (62/87): perl-File-Basename-2.86-502.fc39.noarc 451 kB/s | 17 kB 00:00 (63/87): perl-File-Find-1.43-502.fc39.noarch.rp 495 kB/s | 25 kB 00:00 (64/87): perl-File-stat-1.13-502.fc39.noarch.rp 503 kB/s | 17 kB 00:00 (65/87): perl-FileHandle-2.05-502.fc39.noarch.r 407 kB/s | 16 kB 00:00 (66/87): perl-Getopt-Std-1.13-502.fc39.noarch.r 393 kB/s | 16 kB 00:00 (67/87): perl-Git-2.44.0-1.fc39.noarch.rpm 816 kB/s | 40 kB 00:00 (68/87): perl-IO-1.52-502.fc39.ppc64le.rpm 1.5 MB/s | 83 kB 00:00 (69/87): perl-IPC-Open3-1.22-502.fc39.noarch.rp 674 kB/s | 22 kB 00:00 (70/87): perl-POSIX-2.13-502.fc39.ppc64le.rpm 1.7 MB/s | 117 kB 00:00 (71/87): perl-SelectSaver-1.02-502.fc39.noarch. 155 kB/s | 12 kB 00:00 (72/87): perl-Symbol-1.09-502.fc39.noarch.rpm 187 kB/s | 14 kB 00:00 (73/87): perl-base-2.27-502.fc39.noarch.rpm 274 kB/s | 16 kB 00:00 (74/87): perl-if-0.61.000-502.fc39.noarch.rpm 244 kB/s | 14 kB 00:00 (75/87): perl-interpreter-5.38.2-502.fc39.ppc64 1.2 MB/s | 72 kB 00:00 (76/87): perl-lib-0.65-502.fc39.ppc64le.rpm 256 kB/s | 15 kB 00:00 (77/87): perl-locale-1.10-502.fc39.noarch.rpm 233 kB/s | 14 kB 00:00 (78/87): perl-libs-5.38.2-502.fc39.ppc64le.rpm 21 MB/s | 2.4 MB 00:00 (79/87): perl-mro-1.28-502.fc39.ppc64le.rpm 373 kB/s | 29 kB 00:00 (80/87): perl-overload-1.37-502.fc39.noarch.rpm 647 kB/s | 46 kB 00:00 (81/87): perl-overloading-0.02-502.fc39.noarch. 228 kB/s | 13 kB 00:00 (82/87): pyproject-rpm-macros-1.12.0-1.fc39.noa 916 kB/s | 41 kB 00:00 (83/87): perl-vars-1.05-502.fc39.noarch.rpm 216 kB/s | 13 kB 00:00 (84/87): python3-devel-3.12.2-1.fc39.ppc64le.rp 6.9 MB/s | 313 kB 00:00 (85/87): python3-3.12.2-1.fc39.ppc64le.rpm 595 kB/s | 27 kB 00:00 (86/87): tzdata-2024a-2.fc39.noarch.rpm 13 MB/s | 715 kB 00:00 (87/87): python3-libs-3.12.2-1.fc39.ppc64le.rpm 34 MB/s | 9.4 MB 00:00 -------------------------------------------------------------------------------- Total 16 MB/s | 32 MB 00:02 Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.12-4.fc39.noarch 1/87 Installing : python3-rpm-macros-3.12-4.fc39.noarch 2/87 Installing : expat-2.6.0-1.fc39.ppc64le 3/87 Installing : pyproject-rpm-macros-1.12.0-1.fc39.noarch 4/87 Installing : tzdata-2024a-2.fc39.noarch 5/87 Installing : openssh-9.3p1-10.fc39.ppc64le 6/87 Installing : ncurses-6.4-7.20230520.fc39.1.ppc64le 7/87 Running scriptlet: groff-base-1.23.0-3.fc39.ppc64le 8/87 Installing : groff-base-1.23.0-3.fc39.ppc64le 8/87 Running scriptlet: groff-base-1.23.0-3.fc39.ppc64le 8/87 Installing : perl-Digest-1.20-500.fc39.noarch 9/87 Installing : perl-Digest-MD5-2.58-500.fc39.ppc64le 10/87 Installing : perl-B-1.88-502.fc39.ppc64le 11/87 Installing : perl-FileHandle-2.05-502.fc39.noarch 12/87 Installing : perl-Data-Dumper-2.188-501.fc39.ppc64le 13/87 Installing : perl-libnet-3.15-501.fc39.noarch 14/87 Installing : perl-AutoLoader-5.74-502.fc39.noarch 15/87 Installing : perl-base-2.27-502.fc39.noarch 16/87 Installing : perl-URI-5.21-1.fc39.noarch 17/87 Installing : perl-Pod-Escapes-1:1.07-500.fc39.noarch 18/87 Installing : perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch 19/87 Installing : perl-Time-Local-2:1.350-3.fc39.noarch 20/87 Installing : perl-Net-SSLeay-1.92-10.fc39.ppc64le 21/87 Installing : perl-Mozilla-CA-20230801-1.fc39.noarch 22/87 Installing : perl-File-Path-2.18-500.fc39.noarch 23/87 Installing : perl-if-0.61.000-502.fc39.noarch 24/87 Installing : perl-locale-1.10-502.fc39.noarch 25/87 Installing : perl-IO-Socket-IP-0.42-1.fc39.noarch 26/87 Installing : perl-IO-Socket-SSL-2.083-3.fc39.noarch 27/87 Installing : perl-Term-ANSIColor-5.01-501.fc39.noarch 28/87 Installing : perl-Term-Cap-1.18-500.fc39.noarch 29/87 Installing : perl-Class-Struct-0.68-502.fc39.noarch 30/87 Installing : perl-POSIX-2.13-502.fc39.ppc64le 31/87 Installing : perl-File-Temp-1:0.231.100-500.fc39.noarch 32/87 Installing : perl-HTTP-Tiny-0.088-3.fc39.noarch 33/87 Installing : perl-Pod-Simple-1:3.45-4.fc39.noarch 34/87 Installing : perl-IPC-Open3-1.22-502.fc39.noarch 35/87 Installing : perl-Socket-4:2.037-3.fc39.ppc64le 36/87 Installing : perl-SelectSaver-1.02-502.fc39.noarch 37/87 Installing : perl-Symbol-1.09-502.fc39.noarch 38/87 Installing : perl-podlators-1:5.01-500.fc39.noarch 39/87 Installing : perl-Pod-Perldoc-3.28.01-501.fc39.noarch 40/87 Installing : perl-File-stat-1.13-502.fc39.noarch 41/87 Installing : perl-Text-ParseWords-3.31-500.fc39.noarch 42/87 Installing : perl-Fcntl-1.15-502.fc39.ppc64le 43/87 Installing : perl-mro-1.28-502.fc39.ppc64le 44/87 Installing : perl-Pod-Usage-4:2.03-500.fc39.noarch 45/87 Installing : perl-IO-1.52-502.fc39.ppc64le 46/87 Installing : perl-overloading-0.02-502.fc39.noarch 47/87 Installing : perl-MIME-Base64-3.16-500.fc39.ppc64le 48/87 Installing : perl-Scalar-List-Utils-5:1.63-500.fc39.ppc64le 49/87 Installing : perl-constant-1.33-501.fc39.noarch 50/87 Installing : perl-parent-1:0.241-500.fc39.noarch 51/87 Installing : perl-Errno-1.37-502.fc39.ppc64le 52/87 Installing : perl-File-Basename-2.86-502.fc39.noarch 53/87 Installing : perl-Getopt-Std-1.13-502.fc39.noarch 54/87 Installing : perl-Storable-1:3.32-500.fc39.ppc64le 55/87 Installing : perl-Getopt-Long-1:2.54-500.fc39.noarch 56/87 Installing : perl-overload-1.37-502.fc39.noarch 57/87 Installing : perl-vars-1.05-502.fc39.noarch 58/87 Installing : perl-Exporter-5.77-500.fc39.noarch 59/87 Installing : perl-PathTools-3.89-500.fc39.ppc64le 60/87 Installing : perl-Encode-4:3.19-500.fc39.ppc64le 61/87 Installing : perl-DynaLoader-1.54-502.fc39.ppc64le 62/87 Installing : perl-Carp-1.54-500.fc39.noarch 63/87 Installing : perl-libs-4:5.38.2-502.fc39.ppc64le 64/87 Installing : perl-interpreter-4:5.38.2-502.fc39.ppc64le 65/87 Installing : perl-Error-1:0.17029-13.fc39.noarch 66/87 Installing : perl-TermReadKey-2.38-18.fc39.ppc64le 67/87 Installing : perl-File-Find-1.43-502.fc39.noarch 68/87 Installing : perl-lib-0.65-502.fc39.ppc64le 69/87 Installing : python-pip-wheel-23.2.1-1.fc39.noarch 70/87 Installing : mpdecimal-2.5.1-7.fc39.ppc64le 71/87 Installing : libedit-3.1-48.20230828cvs.fc39.ppc64le 72/87 Installing : libcbor-0.10.2-2.fc39.ppc64le 73/87 Installing : libfido2-1.13.0-3.fc39.ppc64le 74/87 Installing : openssh-clients-9.3p1-10.fc39.ppc64le 75/87 Running scriptlet: openssh-clients-9.3p1-10.fc39.ppc64le 75/87 Installing : libb2-0.98.1-9.fc39.ppc64le 76/87 Installing : python3-3.12.2-1.fc39.ppc64le 77/87 Installing : python3-libs-3.12.2-1.fc39.ppc64le 78/87 Installing : python3-packaging-23.1-4.fc39.noarch 79/87 Installing : python3-rpm-generators-14-7.fc39.noarch 80/87 Installing : less-633-2.fc39.ppc64le 81/87 Installing : git-core-2.44.0-1.fc39.ppc64le 82/87 Installing : git-core-doc-2.44.0-1.fc39.noarch 83/87 Installing : perl-Git-2.44.0-1.fc39.noarch 84/87 Installing : git-2.44.0-1.fc39.ppc64le 85/87 Installing : python3-devel-3.12.2-1.fc39.ppc64le 86/87 Installing : python3-setuptools-67.7.2-7.fc39.noarch 87/87 Running scriptlet: python3-setuptools-67.7.2-7.fc39.noarch 87/87 Verifying : less-633-2.fc39.ppc64le 1/87 Verifying : libb2-0.98.1-9.fc39.ppc64le 2/87 Verifying : libcbor-0.10.2-2.fc39.ppc64le 3/87 Verifying : libedit-3.1-48.20230828cvs.fc39.ppc64le 4/87 Verifying : libfido2-1.13.0-3.fc39.ppc64le 5/87 Verifying : mpdecimal-2.5.1-7.fc39.ppc64le 6/87 Verifying : perl-Carp-1.54-500.fc39.noarch 7/87 Verifying : perl-Data-Dumper-2.188-501.fc39.ppc64le 8/87 Verifying : perl-Digest-1.20-500.fc39.noarch 9/87 Verifying : perl-Digest-MD5-2.58-500.fc39.ppc64le 10/87 Verifying : perl-Encode-4:3.19-500.fc39.ppc64le 11/87 Verifying : perl-Error-1:0.17029-13.fc39.noarch 12/87 Verifying : perl-Exporter-5.77-500.fc39.noarch 13/87 Verifying : perl-File-Path-2.18-500.fc39.noarch 14/87 Verifying : perl-File-Temp-1:0.231.100-500.fc39.noarch 15/87 Verifying : perl-Getopt-Long-1:2.54-500.fc39.noarch 16/87 Verifying : perl-HTTP-Tiny-0.088-3.fc39.noarch 17/87 Verifying : perl-IO-Socket-IP-0.42-1.fc39.noarch 18/87 Verifying : perl-IO-Socket-SSL-2.083-3.fc39.noarch 19/87 Verifying : perl-MIME-Base64-3.16-500.fc39.ppc64le 20/87 Verifying : perl-Mozilla-CA-20230801-1.fc39.noarch 21/87 Verifying : perl-Net-SSLeay-1.92-10.fc39.ppc64le 22/87 Verifying : perl-PathTools-3.89-500.fc39.ppc64le 23/87 Verifying : perl-Pod-Escapes-1:1.07-500.fc39.noarch 24/87 Verifying : perl-Pod-Perldoc-3.28.01-501.fc39.noarch 25/87 Verifying : perl-Pod-Simple-1:3.45-4.fc39.noarch 26/87 Verifying : perl-Pod-Usage-4:2.03-500.fc39.noarch 27/87 Verifying : perl-Scalar-List-Utils-5:1.63-500.fc39.ppc64le 28/87 Verifying : perl-Socket-4:2.037-3.fc39.ppc64le 29/87 Verifying : perl-Storable-1:3.32-500.fc39.ppc64le 30/87 Verifying : perl-Term-ANSIColor-5.01-501.fc39.noarch 31/87 Verifying : perl-Term-Cap-1.18-500.fc39.noarch 32/87 Verifying : perl-TermReadKey-2.38-18.fc39.ppc64le 33/87 Verifying : perl-Text-ParseWords-3.31-500.fc39.noarch 34/87 Verifying : perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch 35/87 Verifying : perl-Time-Local-2:1.350-3.fc39.noarch 36/87 Verifying : perl-URI-5.21-1.fc39.noarch 37/87 Verifying : perl-constant-1.33-501.fc39.noarch 38/87 Verifying : perl-libnet-3.15-501.fc39.noarch 39/87 Verifying : perl-parent-1:0.241-500.fc39.noarch 40/87 Verifying : perl-podlators-1:5.01-500.fc39.noarch 41/87 Verifying : python-pip-wheel-23.2.1-1.fc39.noarch 42/87 Verifying : python-rpm-macros-3.12-4.fc39.noarch 43/87 Verifying : python3-packaging-23.1-4.fc39.noarch 44/87 Verifying : python3-rpm-generators-14-7.fc39.noarch 45/87 Verifying : python3-rpm-macros-3.12-4.fc39.noarch 46/87 Verifying : python3-setuptools-67.7.2-7.fc39.noarch 47/87 Verifying : expat-2.6.0-1.fc39.ppc64le 48/87 Verifying : git-2.44.0-1.fc39.ppc64le 49/87 Verifying : git-core-2.44.0-1.fc39.ppc64le 50/87 Verifying : git-core-doc-2.44.0-1.fc39.noarch 51/87 Verifying : groff-base-1.23.0-3.fc39.ppc64le 52/87 Verifying : ncurses-6.4-7.20230520.fc39.1.ppc64le 53/87 Verifying : openssh-9.3p1-10.fc39.ppc64le 54/87 Verifying : openssh-clients-9.3p1-10.fc39.ppc64le 55/87 Verifying : perl-AutoLoader-5.74-502.fc39.noarch 56/87 Verifying : perl-B-1.88-502.fc39.ppc64le 57/87 Verifying : perl-Class-Struct-0.68-502.fc39.noarch 58/87 Verifying : perl-DynaLoader-1.54-502.fc39.ppc64le 59/87 Verifying : perl-Errno-1.37-502.fc39.ppc64le 60/87 Verifying : perl-Fcntl-1.15-502.fc39.ppc64le 61/87 Verifying : perl-File-Basename-2.86-502.fc39.noarch 62/87 Verifying : perl-File-Find-1.43-502.fc39.noarch 63/87 Verifying : perl-File-stat-1.13-502.fc39.noarch 64/87 Verifying : perl-FileHandle-2.05-502.fc39.noarch 65/87 Verifying : perl-Getopt-Std-1.13-502.fc39.noarch 66/87 Verifying : perl-Git-2.44.0-1.fc39.noarch 67/87 Verifying : perl-IO-1.52-502.fc39.ppc64le 68/87 Verifying : perl-IPC-Open3-1.22-502.fc39.noarch 69/87 Verifying : perl-POSIX-2.13-502.fc39.ppc64le 70/87 Verifying : perl-SelectSaver-1.02-502.fc39.noarch 71/87 Verifying : perl-Symbol-1.09-502.fc39.noarch 72/87 Verifying : perl-base-2.27-502.fc39.noarch 73/87 Verifying : perl-if-0.61.000-502.fc39.noarch 74/87 Verifying : perl-interpreter-4:5.38.2-502.fc39.ppc64le 75/87 Verifying : perl-lib-0.65-502.fc39.ppc64le 76/87 Verifying : perl-libs-4:5.38.2-502.fc39.ppc64le 77/87 Verifying : perl-locale-1.10-502.fc39.noarch 78/87 Verifying : perl-mro-1.28-502.fc39.ppc64le 79/87 Verifying : perl-overload-1.37-502.fc39.noarch 80/87 Verifying : perl-overloading-0.02-502.fc39.noarch 81/87 Verifying : perl-vars-1.05-502.fc39.noarch 82/87 Verifying : pyproject-rpm-macros-1.12.0-1.fc39.noarch 83/87 Verifying : python3-3.12.2-1.fc39.ppc64le 84/87 Verifying : python3-devel-3.12.2-1.fc39.ppc64le 85/87 Verifying : python3-libs-3.12.2-1.fc39.ppc64le 86/87 Verifying : tzdata-2024a-2.fc39.noarch 87/87 Installed: expat-2.6.0-1.fc39.ppc64le git-2.44.0-1.fc39.ppc64le git-core-2.44.0-1.fc39.ppc64le git-core-doc-2.44.0-1.fc39.noarch groff-base-1.23.0-3.fc39.ppc64le less-633-2.fc39.ppc64le libb2-0.98.1-9.fc39.ppc64le libcbor-0.10.2-2.fc39.ppc64le libedit-3.1-48.20230828cvs.fc39.ppc64le libfido2-1.13.0-3.fc39.ppc64le mpdecimal-2.5.1-7.fc39.ppc64le ncurses-6.4-7.20230520.fc39.1.ppc64le openssh-9.3p1-10.fc39.ppc64le openssh-clients-9.3p1-10.fc39.ppc64le perl-AutoLoader-5.74-502.fc39.noarch perl-B-1.88-502.fc39.ppc64le perl-Carp-1.54-500.fc39.noarch perl-Class-Struct-0.68-502.fc39.noarch perl-Data-Dumper-2.188-501.fc39.ppc64le perl-Digest-1.20-500.fc39.noarch perl-Digest-MD5-2.58-500.fc39.ppc64le perl-DynaLoader-1.54-502.fc39.ppc64le perl-Encode-4:3.19-500.fc39.ppc64le perl-Errno-1.37-502.fc39.ppc64le perl-Error-1:0.17029-13.fc39.noarch perl-Exporter-5.77-500.fc39.noarch perl-Fcntl-1.15-502.fc39.ppc64le perl-File-Basename-2.86-502.fc39.noarch perl-File-Find-1.43-502.fc39.noarch perl-File-Path-2.18-500.fc39.noarch perl-File-Temp-1:0.231.100-500.fc39.noarch perl-File-stat-1.13-502.fc39.noarch perl-FileHandle-2.05-502.fc39.noarch perl-Getopt-Long-1:2.54-500.fc39.noarch perl-Getopt-Std-1.13-502.fc39.noarch perl-Git-2.44.0-1.fc39.noarch perl-HTTP-Tiny-0.088-3.fc39.noarch perl-IO-1.52-502.fc39.ppc64le perl-IO-Socket-IP-0.42-1.fc39.noarch perl-IO-Socket-SSL-2.083-3.fc39.noarch perl-IPC-Open3-1.22-502.fc39.noarch perl-MIME-Base64-3.16-500.fc39.ppc64le perl-Mozilla-CA-20230801-1.fc39.noarch perl-Net-SSLeay-1.92-10.fc39.ppc64le perl-POSIX-2.13-502.fc39.ppc64le perl-PathTools-3.89-500.fc39.ppc64le perl-Pod-Escapes-1:1.07-500.fc39.noarch perl-Pod-Perldoc-3.28.01-501.fc39.noarch perl-Pod-Simple-1:3.45-4.fc39.noarch perl-Pod-Usage-4:2.03-500.fc39.noarch perl-Scalar-List-Utils-5:1.63-500.fc39.ppc64le perl-SelectSaver-1.02-502.fc39.noarch perl-Socket-4:2.037-3.fc39.ppc64le perl-Storable-1:3.32-500.fc39.ppc64le perl-Symbol-1.09-502.fc39.noarch perl-Term-ANSIColor-5.01-501.fc39.noarch perl-Term-Cap-1.18-500.fc39.noarch perl-TermReadKey-2.38-18.fc39.ppc64le perl-Text-ParseWords-3.31-500.fc39.noarch perl-Text-Tabs+Wrap-2023.0511-3.fc39.noarch perl-Time-Local-2:1.350-3.fc39.noarch perl-URI-5.21-1.fc39.noarch perl-base-2.27-502.fc39.noarch perl-constant-1.33-501.fc39.noarch perl-if-0.61.000-502.fc39.noarch perl-interpreter-4:5.38.2-502.fc39.ppc64le perl-lib-0.65-502.fc39.ppc64le perl-libnet-3.15-501.fc39.noarch perl-libs-4:5.38.2-502.fc39.ppc64le perl-locale-1.10-502.fc39.noarch perl-mro-1.28-502.fc39.ppc64le perl-overload-1.37-502.fc39.noarch perl-overloading-0.02-502.fc39.noarch perl-parent-1:0.241-500.fc39.noarch perl-podlators-1:5.01-500.fc39.noarch perl-vars-1.05-502.fc39.noarch pyproject-rpm-macros-1.12.0-1.fc39.noarch python-pip-wheel-23.2.1-1.fc39.noarch python-rpm-macros-3.12-4.fc39.noarch python3-3.12.2-1.fc39.ppc64le python3-devel-3.12.2-1.fc39.ppc64le python3-libs-3.12.2-1.fc39.ppc64le python3-packaging-23.1-4.fc39.noarch python3-rpm-generators-14-7.fc39.noarch python3-rpm-macros-3.12-4.fc39.noarch python3-setuptools-67.7.2-7.fc39.noarch tzdata-2024a-2.fc39.noarch Complete! Finish: build setup for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Start: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Building target platforms: ppc64le Building for target ppc64le setting SOURCE_DATE_EPOCH=1637193600 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.GO4aMD + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-rocket + /usr/bin/mkdir -p litex-pythondata-cpu-rocket + cd litex-pythondata-cpu-rocket + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-rocket.git . Cloning into '.'... + git fetch --depth 1 origin 55d7e42913e46ba33e2ade792eef13191c895852 From https://github.com/litex-hub/pythondata-cpu-rocket * branch 55d7e42913e46ba33e2ade792eef13191c895852 -> FETCH_HEAD + git reset --hard 55d7e42913e46ba33e2ade792eef13191c895852 Updating files: 100% (1059/1059), done. HEAD is now at 55d7e42 update.sh: factor out variant generation and build + git log --format=fuller commit 55d7e42913e46ba33e2ade792eef13191c895852 Author: Gabriel Somlo AuthorDate: Mon Feb 19 18:29:01 2024 -0500 Commit: Gabriel Somlo CommitDate: Mon Feb 19 19:48:33 2024 -0500 update.sh: factor out variant generation and build Signed-off-by: Gabriel Somlo + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.EkNKgj + umask 022 + cd /builddir/build/BUILD + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_rocket copying pythondata_cpu_rocket/__init__.py -> build/lib/pythondata_cpu_rocket running egg_info creating pythondata_cpu_rocket.egg-info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_rocket.verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_rocket.verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_rocket.verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_rocket.verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_rocket.verilog.vsrc' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_rocket.verilog.vsrc' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_rocket.verilog.vsrc' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_rocket.verilog.vsrc' to be distributed and are already explicitly excluding 'pythondata_cpu_rocket.verilog.vsrc' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/.gitignore -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/README.md -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/_upstream.rev -> build/lib/pythondata_cpu_rocket/verilog copying pythondata_cpu_rocket/verilog/update.sh -> build/lib/pythondata_cpu_rocket/verilog creating build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> build/lib/pythondata_cpu_rocket/verilog/generated-src copying pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> build/lib/pythondata_cpu_rocket/verilog/generated-src creating build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc copying pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> build/lib/pythondata_cpu_rocket/verilog/vsrc + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.Ri6bb4 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-rocket + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le --prefix /usr running install /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket copying build/lib/pythondata_cpu_rocket/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/_upstream.rev -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog copying build/lib/pythondata_cpu_rocket/verilog/update.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x2010000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.l2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_medium_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_1_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_2_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_4_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_1.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_4.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x0.1.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x2000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0x40.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.0xc000000.0.regmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.anno.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.behav_srams.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.d -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.graphml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.memmap.json -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.plusArgs -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.rom.conf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src copying build/lib/pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_small_8_8.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/generated-src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/AsyncResetReg.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider2.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/ClockDivider3.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/EICG_wrapper.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/RoccBlackBox.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimDTM.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/SimJTAG.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/TestDriver.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc copying build/lib/pythondata_cpu_rocket/verilog/vsrc/plusarg_reader.v -> /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/verilog/vsrc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpd5nysxc4.py' /usr/bin/python3 /tmp/tmpd5nysxc4.py removing /tmp/tmpd5nysxc4.py running install_egg_info running egg_info writing pythondata_cpu_rocket.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_rocket.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_rocket.egg-info/top_level.txt reading manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_rocket.egg-info/SOURCES.txt' Copying pythondata_cpu_rocket.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_rocket-0.0.post7146-py3.12.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/bin/__pycache__ + /usr/bin/find-debuginfo -j2 --strict-build-id -m -i --build-id-seed 2023.12-20240219.0.git55d7e429.fc39 --unique-debug-suffix -2023.12-20240219.0.git55d7e429.fc39.ppc64le --unique-debug-src-base litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 50000000 -S debugsourcefiles.list /builddir/build/BUILD/litex-pythondata-cpu-rocket find-debuginfo: starting Extracting debug info from 0 files Creating .debug symlinks for symlinks to ELF files find: ‘debug’: No such file or directory find-debuginfo: done + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip + /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j2 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/lib/python3.12 using python3.12 + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.8ZQYEg Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.rrf8wO + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-rocket-python3 + export LC_ALL= + LC_ALL= + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-rocket-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-rocket/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + export LC_ALL= + LC_ALL= + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-rocket/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-rocket-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-rocket-python3 = 2023.12-20240219.0.git55d7e429.fc39 python3.12dist(pythondata-cpu-rocket) = 0^post7146 python3dist(pythondata-cpu-rocket) = 0^post7146 pythondata-cpu-rocket Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/sh python(abi) = 3.12 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le Wrote: /builddir/build/RPMS/litex-pythondata-cpu-rocket-python3-2023.12-20240219.0.git55d7e429.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.JgGGz9 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-rocket + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.ppc64le + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.8fgh3P + umask 022 + cd /builddir/build/BUILD + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-rocket-SPECPARTS + rm -rf litex-pythondata-cpu-rocket litex-pythondata-cpu-rocket.gemspec + RPM_EC=0 ++ jobs -p + exit 0 Finish: rpmbuild litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm Finish: build phase for litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.log /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.librepo.log /var/lib/mock/fedora-39-ppc64le-1709342028.223586/root/var/log/dnf.rpm.log INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-rocket-2023.12-20240219.0.git55d7e429.fc39.src.rpm) Config(child) 5 minutes 42 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-rocket", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.fc39", "arch": "src" }, { "name": "litex-pythondata-cpu-rocket-python3", "epoch": null, "version": "2023.12", "release": "20240219.0.git55d7e429.fc39", "arch": "noarch" } ] } RPMResults finished