LICENSE
MANIFEST.in
README.md
pyproject.toml
setup.py
pythondata_cpu_rocket/__init__.py
pythondata_cpu_rocket.egg-info/PKG-INFO
pythondata_cpu_rocket.egg-info/SOURCES.txt
pythondata_cpu_rocket.egg-info/dependency_links.txt
pythondata_cpu_rocket.egg-info/not-zip-safe
pythondata_cpu_rocket.egg-info/top_level.txt
pythondata_cpu_rocket/verilog/.gitignore
pythondata_cpu_rocket/verilog/README.md
pythondata_cpu_rocket/verilog/_upstream.rev
pythondata_cpu_rocket/verilog/update.sh
pythondata_cpu_rocket/verilog/generated-src/TestHarness.anno.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_full_1_1.anno.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_2.memmap.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0x2000000.0.regmap.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.0xc000000.0.regmap.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.json
pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_4.memmap.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x2000000.0.regmap.json
pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0x40.0.regmap.json
pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.0xc000000.0.regmap.json
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pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.json
pythondata_cpu_rocket/verilog/generated-src/freechips.rocketchip.system.LitexConfig_linux_2_8.memmap.json
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