[globcfg]
base_address = 0
data_width = 32
address_width = 16
register_reset = sync_pos
address_increment = none
address_alignment = data_width
force_name_case = none
regmap_path = regs.yaml

[v_module]
path = hw/regs.v
read_filler = 0
interface = axil
generator = Verilog

[vhdl_module]
path = hw/regs.vhd
read_filler = 0
interface = axil
generator = Vhdl

[v_header]
path = hw/regs.vh
prefix = CSR
generator = VerilogHeader

[sv_pkg]
path = hw/regs_pkg.sv
prefix = CSR
generator = SystemVerilogPackage

[py]
path = sw/regs.py
generator = Python

[c_header]
path = sw/regs.h
prefix = CSR
generator = CHeader

[md_doc]
path = doc/regs.md
title = Register map
print_images = True
image_dir = md_img
print_conventions = True
generator = Markdown

[asciidoc_doc]
path = doc/regs.adoc
title = Register map
print_images = True
image_dir = adoc_img
print_conventions = True
generator = Asciidoc

