Warning: Permanently added '13.222.58.69' (ED25519) to the list of known hosts. You can reproduce this build on your computer by running: sudo dnf install copr-rpmbuild /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/11009165-fedora-rawhide-aarch64 --chroot fedora-rawhide-aarch64 Version: 1.9 PID: 56571 Logging PID: 56573 Task: {'allow_user_ssh': False, 'appstream': False, 'background': False, 'build_id': 11009165, 'buildroot_pkgs': [], 'chroot': 'fedora-rawhide-aarch64', 'enable_net': True, 'fedora_review': False, 'git_hash': 'de7cee888f9b010852e7403fe11d3a013bf625e2', 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6', 'isolation': 'default', 'memory_reqs': 2048, 'package_name': 'litex-pythondata-cpu-cva6', 'package_version': '2026.04-20260917.0.git2b51ea6a', 'project_dirname': 'HDL', 'project_name': 'HDL', 'project_owner': 'rezso', 'repo_priority': None, 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/rezso/HDL/fedora-rawhide-aarch64/', 'id': 'copr_base', 'name': 'Copr repository', 'priority': None, 'repo_gpgcheck': False}], 'sandbox': 'rezso/HDL--rezso', 'source_json': {}, 'source_type': None, 'ssh_public_keys': None, 'storage': 0, 'submitter': 'rezso', 'tags': [], 'task_id': '11009165-fedora-rawhide-aarch64', 'timeout': 180000, 'uses_devel_repo': False, 'with_opts': [], 'without_opts': []} Running: git clone https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6 /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6 --depth 500 --no-single-branch --recursive cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/rezso/HDL/litex-pythondata-cpu-cva6', '/var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6', '--depth', '500', '--no-single-branch', '--recursive'] cwd: . rc: 0 stdout: stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6'... Running: git checkout de7cee888f9b010852e7403fe11d3a013bf625e2 -- cmd: ['git', 'checkout', 'de7cee888f9b010852e7403fe11d3a013bf625e2', '--'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6 rc: 0 stdout: stderr: Note: switching to 'de7cee888f9b010852e7403fe11d3a013bf625e2'. You are in 'detached HEAD' state. You can look around, make experimental changes and commit them, and you can discard any commits you make in this state without impacting any branches by switching back to a branch. If you want to create a new branch to retain commits you create, you may do so (now or later) by using -c with the switch command. Example: git switch -c Or undo this operation with: git switch - Turn off this advice by setting config variable advice.detachedHead to false HEAD is now at de7cee8 automatic import of litex-pythondata-cpu-cva6 Running: dist-git-client sources cmd: ['dist-git-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6 rc: 0 stdout: stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources tail: /var/lib/copr-rpmbuild/main.log: file truncated Running (timeout=180000): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1789969120.434794 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 6.8 starting (python version = 3.14.5, NVR = mock-6.8-1.fc44), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1789969120.434794 -r /var/lib/copr-rpmbuild/results/configs/child.cfg Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(fedora-rawhide-aarch64) Start: clean chroot Finish: clean chroot Mock Version: 6.8 INFO: Mock Version: 6.8 Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-aarch64-bootstrap-1789969120.434794/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: Guessed host environment type: unknown INFO: Using container image: registry.fedoraproject.org/fedora:rawhide INFO: Pulling image: registry.fedoraproject.org/fedora:rawhide INFO: Tagging container image as mock-bootstrap-3827e3be-62af-4b0f-ae8e-a7458e59d74f INFO: Checking that 74fe6d824f13f19a564911bfb7581c8f2dc7a5b35986316eb2925a524f1d905f image matches host's architecture INFO: Copy content of container 74fe6d824f13f19a564911bfb7581c8f2dc7a5b35986316eb2925a524f1d905f to /var/lib/mock/fedora-rawhide-aarch64-bootstrap-1789969120.434794/root INFO: mounting 74fe6d824f13f19a564911bfb7581c8f2dc7a5b35986316eb2925a524f1d905f with podman image mount INFO: image 74fe6d824f13f19a564911bfb7581c8f2dc7a5b35986316eb2925a524f1d905f as /var/lib/containers/storage/overlay/b03127b68b96b80327ceed6a992e0654b5f0fca9f3d74e6dc493ba833090ec53/merged INFO: umounting image 74fe6d824f13f19a564911bfb7581c8f2dc7a5b35986316eb2925a524f1d905f (/var/lib/containers/storage/overlay/b03127b68b96b80327ceed6a992e0654b5f0fca9f3d74e6dc493ba833090ec53/merged) with podman image umount INFO: Removing image mock-bootstrap-3827e3be-62af-4b0f-ae8e-a7458e59d74f INFO: Package manager dnf5 detected and used (fallback) INFO: Not updating bootstrap chroot, bootstrap_image_ready=True Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-aarch64-1789969120.434794/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Package manager dnf5 detected and used (direct choice) INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-6.1.0-1.fc46.aarch64 rpm-sequoia-1.10.3-1.fc46.aarch64 dnf5-5.4.5.0-1.fc46.aarch64 dnf5-plugins-5.4.5.0-1.fc46.aarch64 Start: installing minimal buildroot with dnf5 Updating and loading repositories: Copr repository 100% | 571.3 KiB/s | 157.1 KiB | 00m00s fedora 100% | 32.7 MiB/s | 20.9 MiB | 00m01s Repositories loaded. Package Arch Version Repository Size Installing group/module packages: bash aarch64 0:5.3.15-2.fc45 fedora 8.4 MiB bzip2 aarch64 0:1.0.8-24.fc45 fedora 171.2 KiB coreutils aarch64 0:9.11-6.fc45 fedora 8.2 MiB cpio aarch64 0:2.15-10.fc45 fedora 1.1 MiB diffutils aarch64 0:3.12-6.fc45 fedora 1.6 MiB fedora-release-common noarch 0:46-0.1 fedora 4.6 KiB findutils aarch64 1:4.11.0-2.fc45 fedora 2.0 MiB gawk aarch64 0:5.4.1-1.fc45 fedora 2.9 MiB glibc-minimal-langpack aarch64 0:2.44.9000-2.fc46 fedora 0.0 B grep aarch64 0:3.12-4.fc45 fedora 1.0 MiB gzip aarch64 0:1.14-4.fc45 fedora 437.6 KiB info aarch64 0:7.3-3.fc45 fedora 424.4 KiB patch aarch64 0:2.8-5.fc45 fedora 262.4 KiB redhat-rpm-config noarch 0:345-4.fc46 fedora 184.2 KiB rpm-build aarch64 0:6.1.0-1.fc46 fedora 616.1 KiB sed aarch64 0:4.10-2.fc45 fedora 878.4 KiB shadow-utils aarch64 2:4.20.0-1.fc45 fedora 4.4 MiB tar aarch64 2:1.35-9.fc45 fedora 3.0 MiB unzip aarch64 0:6.0-71.fc45 fedora 469.9 KiB util-linux aarch64 0:2.42.2-3.fc45 fedora 6.9 MiB which aarch64 0:2.25-2.fc45 fedora 123.6 KiB xz aarch64 1:5.8.4-1.fc46 fedora 1.5 MiB Installing dependencies: R-srpm-macros noarch 0:1.3.7-3.fc45 fedora 3.5 KiB add-determinism aarch64 0:0.7.3-3.fc45 fedora 1.9 MiB alternatives aarch64 0:1.33-6.fc45 fedora 90.1 KiB ansible-srpm-macros noarch 0:1-22.fc45 fedora 35.7 KiB audit-libs aarch64 0:4.2.1-2.fc45 fedora 486.7 KiB binutils aarch64 0:2.47.50-7.fc46 fedora 27.2 MiB build-reproducibility-srpm-macros noarch 0:0.7.3-3.fc45 fedora 1.2 KiB bzip2-libs aarch64 0:1.0.8-24.fc45 fedora 72.5 KiB ca-certificates noarch 0:2026.2.90_v9.0.317-1.fc46 fedora 2.6 MiB cmake-srpm-macros noarch 0:4.3.0-5.fc45 fedora 524.0 B coreutils-common aarch64 0:9.11-6.fc45 fedora 10.9 MiB crypto-policies noarch 0:20260713-2.gitc42da77.fc45 fedora 134.3 KiB curl aarch64 0:8.22.0-1.fc46 fedora 526.8 KiB cyrus-sasl-lib aarch64 0:2.1.28-37.fc45 fedora 2.4 MiB debugedit aarch64 0:5.3-3.fc45 fedora 320.9 KiB dwz aarch64 0:0.17-3.fc45 fedora 322.7 KiB ed aarch64 0:1.22.6-1.fc46 fedora 158.9 KiB efi-srpm-macros noarch 0:6-9.fc45 fedora 40.3 KiB elfutils aarch64 0:0.196-1.fc46 fedora 3.8 MiB elfutils-debuginfod-client aarch64 0:0.196-1.fc46 fedora 144.0 KiB elfutils-libelf aarch64 0:0.196-1.fc46 fedora 1.5 MiB elfutils-libs aarch64 0:0.196-1.fc46 fedora 746.6 KiB erlang-srpm-macros noarch 0:0.3.11-2.fc45 fedora 1.9 KiB fedora-gpg-keys noarch 0:46-0.3 fedora 130.3 KiB fedora-release noarch 0:46-0.1 fedora 0.0 B fedora-release-identity-basic noarch 0:46-0.1 fedora 664.0 B fedora-repos noarch 0:46-0.3 fedora 4.9 KiB fedora-repos-rawhide noarch 0:46-0.3 fedora 2.2 KiB file aarch64 0:5.48-3.fc46 fedora 141.9 KiB file-libs aarch64 0:5.48-3.fc46 fedora 12.4 MiB filesystem aarch64 0:3.18-59.fc45 fedora 112.0 B filesystem-srpm-macros noarch 0:3.18-59.fc45 fedora 38.2 KiB fips-provider aarch64 0:1.5.2-6.fc46 fedora 3.7 MiB fonts-srpm-macros noarch 1:5.0.0-4.fc45 fedora 55.8 KiB forge-srpm-macros noarch 0:0.4.0-5.fc45 fedora 38.9 KiB fpc-srpm-macros noarch 0:1.3-17.fc45 fedora 144.0 B gap-srpm-macros noarch 0:2-3.fc45 fedora 2.1 KiB gdb-minimal aarch64 0:17.2-6.fc46 fedora 13.5 MiB gdbm-libs aarch64 1:1.23-12.fc45 fedora 233.8 KiB ghc-srpm-macros noarch 0:1.10-2.fc45 fedora 792.0 B glibc aarch64 0:2.44.9000-2.fc46 fedora 6.6 MiB glibc-common aarch64 0:2.44.9000-2.fc46 fedora 1.3 MiB glibc-gconv-extra aarch64 0:2.44.9000-2.fc46 fedora 18.6 MiB gmp aarch64 1:6.3.0-6.fc45 fedora 657.9 KiB gnat-srpm-macros noarch 0:7-3.fc45 fedora 1.0 KiB gnome-srpm-macros noarch 0:1.0-2.fc45 fedora 3.5 KiB gnulib-l10n noarch 0:20241231-4.fc45 fedora 655.0 KiB gnupg2 aarch64 0:2.4.9-18.fc45 fedora 6.4 MiB gnupg2-dirmngr aarch64 0:2.4.9-18.fc45 fedora 646.1 KiB gnupg2-gpg-agent aarch64 0:2.4.9-18.fc45 fedora 846.9 KiB gnupg2-gpgconf aarch64 0:2.4.9-18.fc45 fedora 321.8 KiB gnupg2-keyboxd aarch64 0:2.4.9-18.fc45 fedora 233.2 KiB gnupg2-verify aarch64 0:2.4.9-18.fc45 fedora 364.3 KiB gnutls aarch64 0:3.8.13-5.fc46 fedora 3.7 MiB go-srpm-macros noarch 0:3.8.0-3.fc45 fedora 61.9 KiB gpgverify noarch 0:2.2-5.fc45 fedora 8.7 KiB ima-evm-utils-libs aarch64 0:1.6.2-12.fc45 fedora 92.6 KiB jansson aarch64 0:2.14-5.fc45 fedora 93.0 KiB java-srpm-macros noarch 0:1-9.fc45 fedora 870.0 B json-c aarch64 0:0.18-9.fc45 fedora 138.5 KiB kernel-srpm-macros noarch 0:1.0-30.fc45 fedora 1.9 KiB keyutils-libs aarch64 0:1.6.3-8.fc45 fedora 98.2 KiB krb5-libs aarch64 0:1.22.2-9.fc45 fedora 2.5 MiB libacl aarch64 0:2.4.0-2.fc45 fedora 67.9 KiB libarchive aarch64 0:3.8.9-2.fc46 fedora 975.7 KiB libassuan aarch64 0:2.5.7-6.fc45 fedora 215.9 KiB libattr aarch64 0:2.6.0-2.fc45 fedora 68.4 KiB libblkid aarch64 0:2.42.2-3.fc45 fedora 290.3 KiB libbrotli aarch64 0:1.2.0-6.fc45 fedora 909.2 KiB libcap aarch64 0:2.78-2.fc45 fedora 508.4 KiB libcap-ng aarch64 0:0.9.6-1.fc46 fedora 160.9 KiB libcbor aarch64 0:0.14.0-3.fc45 fedora 139.6 KiB libcom_err aarch64 0:1.47.4-2.fc45 fedora 111.1 KiB libcurl aarch64 0:8.22.0-1.fc46 fedora 1.0 MiB libeconf aarch64 0:0.7.9-4.fc45 fedora 80.8 KiB libevent aarch64 0:2.1.13-1.fc46 fedora 1.1 MiB libfdisk aarch64 0:2.42.2-3.fc45 fedora 418.8 KiB libffi aarch64 0:3.8.0-1.fc46 fedora 159.6 KiB libfido2 aarch64 0:1.17.0-5.fc45 fedora 280.7 KiB libfsverity aarch64 0:1.7-4.fc45 fedora 68.4 KiB libgcc aarch64 0:16.2.1-2.fc46.1 fedora 222.3 KiB libgcrypt aarch64 0:1.12.4-1.fc46 fedora 1.2 MiB libgomp aarch64 0:16.2.1-2.fc46.1 fedora 592.9 KiB libgpg-error aarch64 0:1.61-2.fc45 fedora 997.9 KiB libidn2 aarch64 0:2.3.8-4.fc45 fedora 560.5 KiB libksba aarch64 0:1.8.1-1.fc46 fedora 407.8 KiB liblastlog2 aarch64 0:2.42.2-3.fc45 fedora 137.8 KiB libmount aarch64 0:2.42.2-3.fc45 fedora 420.3 KiB libnghttp2 aarch64 0:1.69.0-6.fc46 fedora 197.9 KiB libnghttp3 aarch64 0:1.18.0-1.fc45 fedora 206.8 KiB libpfm aarch64 0:4.13.0-23.fc45 fedora 252.0 KiB libpkgconf aarch64 0:2.5.1-2.fc45 fedora 134.0 KiB libpsl aarch64 0:0.23.3-1.fc46 fedora 132.5 KiB libselinux aarch64 0:3.11-5.fc46 fedora 265.2 KiB libselinux-utils aarch64 0:3.11-5.fc46 fedora 1.3 MiB libsemanage aarch64 0:3.11-4.fc46 fedora 360.3 KiB libsepol aarch64 0:3.11-2.fc45 fedora 809.9 KiB libsmartcols aarch64 0:2.42.2-3.fc45 fedora 224.4 KiB libssh aarch64 0:0.12.2-1.fc45 fedora 721.4 KiB libssh-config noarch 0:0.12.2-1.fc45 fedora 277.0 B libstdc++ aarch64 0:16.2.1-2.fc46.1 fedora 3.0 MiB libtasn1 aarch64 0:4.21.0-2.fc45 fedora 220.7 KiB libtool-ltdl aarch64 0:2.6.2-1.fc46 fedora 93.9 KiB libunistring aarch64 0:1.1-12.fc45 fedora 1.7 MiB libusb1 aarch64 0:1.0.30-2.fc45 fedora 179.7 KiB libuuid aarch64 0:2.42.2-3.fc45 fedora 69.3 KiB libverto aarch64 0:0.3.2-13.fc45 fedora 69.3 KiB libxcrypt aarch64 0:4.5.2-4.fc45 fedora 273.2 KiB libxml2 aarch64 0:2.15.4-1.fc46 fedora 1.7 MiB libzstd aarch64 0:1.5.7-6.fc45 fedora 860.3 KiB linkdupes aarch64 0:0.7.3-3.fc45 fedora 711.0 KiB lua-libs aarch64 0:5.5.1-2.fc46 fedora 330.0 KiB lua-srpm-macros noarch 0:1-18.fc45 fedora 1.3 KiB lz4-libs aarch64 0:1.10.0-5.fc45 fedora 197.3 KiB meson-srpm-macros noarch 0:1.12.0-2.fc46 fedora 1.7 KiB mpfr aarch64 0:4.2.2-4.fc45 fedora 755.4 KiB ncurses-base noarch 0:6.6-3.fc45 fedora 329.7 KiB ncurses-libs aarch64 0:6.6-3.fc45 fedora 1.2 MiB nettle aarch64 0:4.0-5.fc45 fedora 836.7 KiB ngtcp2 aarch64 0:1.22.1-3.fc45 fedora 341.1 KiB ngtcp2-crypto-ossl aarch64 0:1.22.1-3.fc45 fedora 67.5 KiB npth aarch64 0:1.8-5.fc45 fedora 93.4 KiB ocaml-srpm-macros noarch 0:11-4.fc45 fedora 1.9 KiB openblas-srpm-macros noarch 0:2-22.fc45 fedora 112.0 B openldap aarch64 0:2.6.14-1.fc46 fedora 765.1 KiB openssl-libs aarch64 1:4.0.2-3.fc46 fedora 5.8 MiB p11-kit aarch64 0:0.26.5-1.fc45 fedora 2.8 MiB p11-kit-trust aarch64 0:0.26.5-1.fc45 fedora 530.1 KiB package-notes-srpm-macros noarch 0:0.20-2.fc45 fedora 1.6 KiB pam-libs aarch64 0:1.7.2-4.fc45 fedora 222.7 KiB pcre2 aarch64 0:10.47-1.fc45.2 fedora 714.4 KiB pcre2-syntax noarch 0:10.47-1.fc45.2 fedora 281.9 KiB perl-srpm-macros noarch 0:1-65.fc45 fedora 861.0 B pkgconf aarch64 0:2.5.1-2.fc45 fedora 116.8 KiB pkgconf-m4 noarch 0:2.5.1-2.fc45 fedora 14.3 KiB pkgconf-pkg-config aarch64 0:2.5.1-2.fc45 fedora 990.0 B policycoreutils aarch64 0:3.11-2.fc45 fedora 1.5 MiB popt aarch64 0:1.19-11.fc45 fedora 144.7 KiB publicsuffix-list-dafsa noarch 0:20260624-2.fc45 fedora 71.3 KiB pyproject-srpm-macros noarch 0:1.23.2-1.fc45 fedora 3.4 KiB python-srpm-macros noarch 0:3.15-2.fc45 fedora 51.6 KiB qt5-srpm-macros noarch 0:5.15.18-3.fc45 fedora 500.0 B qt6-srpm-macros noarch 0:6.11.2-1.fc46 fedora 472.0 B readline aarch64 0:8.3-6.fc45 fedora 563.6 KiB redhat-systemd-presets noarch 0:102-3.fc45 fedora 1.0 KiB redhat-systemd-presets-common noarch 0:102-3.fc45 fedora 16.9 KiB rpm aarch64 0:6.1.0-1.fc46 fedora 3.3 MiB rpm-build-libs aarch64 0:6.1.0-1.fc46 fedora 264.0 KiB rpm-libs aarch64 0:6.1.0-1.fc46 fedora 1.1 MiB rpm-plugin-selinux aarch64 0:6.1.0-1.fc46 fedora 67.9 KiB rpm-sequoia aarch64 0:1.10.3-1.fc46 fedora 2.3 MiB rpm-sign-libs aarch64 0:6.1.0-1.fc46 fedora 67.7 KiB rust-srpm-macros noarch 0:28.5-2.fc45 fedora 5.5 KiB selinux-policy noarch 0:45.17-1.fc46 fedora 32.1 KiB selinux-policy-targeted noarch 0:45.17-1.fc46 fedora 19.0 MiB setup noarch 0:2.15.1-2.fc45 fedora 725.6 KiB sqlite-libs aarch64 0:3.53.4-1.fc45 fedora 1.6 MiB systemd-libs aarch64 0:262~rc3-1.fc46 fedora 2.8 MiB systemd-standalone-sysusers aarch64 0:262~rc3-1.fc46 fedora 979.3 KiB tpm2-tss aarch64 0:4.2.0-1.fc45 fedora 2.2 MiB tree-sitter-srpm-macros noarch 0:0.4.6-2.fc45 fedora 8.6 KiB util-linux-core aarch64 0:2.42.2-3.fc45 fedora 2.5 MiB xxhash-libs aarch64 0:0.8.4-1.fc46 fedora 85.8 KiB xz-libs aarch64 1:5.8.4-1.fc46 fedora 265.5 KiB zig-srpm-macros noarch 0:1-9.fc45 fedora 1.3 KiB zip aarch64 0:3.0-46.fc45 fedora 762.2 KiB zlib-ng-compat aarch64 0:2.3.3-6.fc45 fedora 133.4 KiB zstd aarch64 0:1.5.7-6.fc45 fedora 562.3 KiB Installing groups: Buildsystem building group Transaction Summary: Installing: 190 packages Total size of inbound packages is 68 MiB. Need to download 68 MiB. After this operation, 252 MiB extra will be used (install 252 MiB, remove 0 B). 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00m00s [155/190] libksba-0:1.8.1-1.fc46.aarch6 100% | 26.4 MiB/s | 162.3 KiB | 00m00s [156/190] openldap-0:2.6.14-1.fc46.aarc 100% | 49.3 MiB/s | 252.2 KiB | 00m00s [157/190] libusb1-0:1.0.30-2.fc45.aarch 100% | 38.6 MiB/s | 79.2 KiB | 00m00s [158/190] libidn2-0:2.3.8-4.fc45.aarch6 100% | 85.1 MiB/s | 174.3 KiB | 00m00s [159/190] libunistring-0:1.1-12.fc45.aa 100% | 175.3 MiB/s | 538.4 KiB | 00m00s [160/190] nettle-0:4.0-5.fc45.aarch64 100% | 104.6 MiB/s | 428.3 KiB | 00m00s [161/190] cyrus-sasl-lib-0:2.1.28-37.fc 100% | 124.8 MiB/s | 766.6 KiB | 00m00s [162/190] libevent-0:2.1.13-1.fc46.aarc 100% | 66.6 MiB/s | 272.8 KiB | 00m00s [163/190] libtool-ltdl-0:2.6.2-1.fc46.a 100% | 11.6 MiB/s | 35.6 KiB | 00m00s [164/190] gdbm-libs-1:1.23-12.fc45.aarc 100% | 27.5 MiB/s | 56.3 KiB | 00m00s [165/190] fedora-release-0:46-0.1.noarc 100% | 5.8 MiB/s | 11.9 KiB | 00m00s [166/190] systemd-standalone-sysusers-0 100% | 128.8 MiB/s | 395.6 KiB | 00m00s [167/190] xxhash-libs-0:0.8.4-1.fc46.aa 100% | 3.7 MiB/s | 34.0 KiB | 00m00s [168/190] fedora-release-identity-basic 100% | 1.4 MiB/s | 12.7 KiB | 00m00s [169/190] gdb-minimal-0:17.2-6.fc46.aar 100% | 255.4 MiB/s | 4.3 MiB | 00m00s [170/190] krb5-libs-0:1.22.2-9.fc45.aar 100% | 106.1 MiB/s | 760.6 KiB | 00m00s [171/190] libcurl-0:8.22.0-1.fc46.aarch 100% | 45.1 MiB/s | 462.1 KiB | 00m00s [172/190] libbrotli-0:1.2.0-6.fc45.aarc 100% | 85.2 MiB/s | 348.8 KiB | 00m00s [173/190] libnghttp2-0:1.69.0-6.fc46.aa 100% | 24.3 MiB/s | 74.7 KiB | 00m00s [174/190] libnghttp3-0:1.18.0-1.fc45.aa 100% | 34.2 MiB/s | 70.1 KiB | 00m00s [175/190] libpsl-0:0.23.3-1.fc46.aarch6 100% | 65.8 MiB/s | 67.4 KiB | 00m00s [176/190] libssh-0:0.12.2-1.fc45.aarch6 100% | 90.2 MiB/s | 277.2 KiB | 00m00s [177/190] ngtcp2-0:1.22.1-3.fc45.aarch6 100% | 48.0 MiB/s | 147.5 KiB | 00m00s [178/190] ngtcp2-crypto-ossl-0:1.22.1-3 100% | 12.8 MiB/s | 26.2 KiB | 00m00s [179/190] keyutils-libs-0:1.6.3-8.fc45. 100% | 10.3 MiB/s | 31.5 KiB | 00m00s [180/190] libcom_err-0:1.47.4-2.fc45.aa 100% | 8.6 MiB/s | 26.5 KiB | 00m00s [181/190] libverto-0:0.3.2-13.fc45.aarc 100% | 6.7 MiB/s | 20.4 KiB | 00m00s [182/190] publicsuffix-list-dafsa-0:202 100% | 29.8 MiB/s | 61.1 KiB | 00m00s [183/190] libfido2-0:1.17.0-5.fc45.aarc 100% | 48.4 MiB/s | 99.1 KiB | 00m00s [184/190] libssh-config-0:0.12.2-1.fc45 100% | 4.4 MiB/s | 8.9 KiB | 00m00s [185/190] libcbor-0:0.14.0-3.fc45.aarch 100% | 17.2 MiB/s | 35.1 KiB | 00m00s [186/190] policycoreutils-0:3.11-2.fc45 100% | 25.6 MiB/s | 262.3 KiB | 00m00s [187/190] selinux-policy-0:45.17-1.fc46 100% | 2.6 MiB/s | 40.2 KiB | 00m00s [188/190] libselinux-utils-0:3.11-5.fc4 100% | 20.7 MiB/s | 127.0 KiB | 00m00s [189/190] selinux-policy-targeted-0:45. 100% | 235.1 MiB/s | 6.8 MiB | 00m00s [190/190] rpm-plugin-selinux-0:6.1.0-1. 100% | 1.5 MiB/s | 18.0 KiB | 00m00s -------------------------------------------------------------------------------- [190/190] Total 100% | 210.2 MiB/s | 68.3 MiB | 00m00s Running transaction Importing OpenPGP key 0x91211FCE: UserID : "Fedora (46) " Fingerprint: D924B10D3E810DABDD8B56B596E7E91491211FCE From : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-46-primary The key was successfully imported. Importing OpenPGP key 0x91211FCE: UserID : "Fedora (46) " Fingerprint: D924B10D3E810DABDD8B56B596E7E91491211FCE From : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-46-primary The key was successfully imported. Importing OpenPGP key 0xF577861E: UserID : "Fedora (45) " Fingerprint: 4F50A6114CD5C6976A7F1179655A4B02F577861E From : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-45-primary The key was successfully imported. Importing OpenPGP key 0x9488FB64: UserID : "Fedora (47) " Fingerprint: B2E766FA50CA6FA2D5ED06FC09D879E09488FB64 From : file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-47-primary The key was successfully imported. [ 1/192] Verify package files 100% | 748.0 B/s | 190.0 B | 00m00s >>> Running %pretrans scriptlet: filesystem-0:3.18-59.fc45.aarch64 >>> Finished %pretrans scriptlet: filesystem-0:3.18-59.fc45.aarch64 >>> [RPM] failed to open /var/lib/mock/fedora-rawhide-aarch64-1789969120.434794/root/etc/group for id/name lookup: No such file or directory [ 2/192] Prepare transaction 100% | 2.3 KiB/s | 190.0 B | 00m00s [ 3/192] Installing libgcc-0:16.2.1-2. 100% | 109.4 MiB/s | 224.0 KiB | 00m00s [ 4/192] Installing redhat-systemd-pre 100% | 0.0 B/s | 1.5 KiB | 00m00s [ 5/192] Installing redhat-systemd-pre 100% | 17.7 MiB/s | 18.1 KiB | 00m00s [ 6/192] Installing libssh-config-0:0. 100% | 0.0 B/s | 816.0 B | 00m00s [ 7/192] Installing publicsuffix-list- 100% | 70.3 MiB/s | 72.0 KiB | 00m00s [ 8/192] Installing fedora-release-ide 100% | 898.4 KiB/s | 920.0 B | 00m00s [ 9/192] Installing fedora-gpg-keys-0: 100% | 29.6 MiB/s | 181.7 KiB | 00m00s [ 10/192] Installing fedora-repos-rawhi 100% | 0.0 B/s | 2.5 KiB | 00m00s [ 11/192] Installing fedora-repos-0:46- 100% | 0.0 B/s | 5.9 KiB | 00m00s [ 12/192] Installing fedora-release-com 100% | 7.8 MiB/s | 8.0 KiB | 00m00s [ 13/192] Installing fedora-release-0:4 100% | 24.2 KiB/s | 124.0 B | 00m00s >>> Running sysusers scriptlet: setup-0:2.15.1-2.fc45.noarch >>> Finished sysusers scriptlet: setup-0:2.15.1-2.fc45.noarch >>> Scriptlet output: >>> Creating group 'adm' with GID 4. >>> Creating group 'audio' with GID 63. >>> Creating group 'cdrom' with GID 11. >>> Creating group 'clock' with GID 103. >>> Creating group 'dialout' with GID 18. >>> Creating group 'disk' with GID 6. >>> Creating group 'floppy' with GID 19. >>> Creating group 'ftp' with GID 50. >>> Creating group 'games' with GID 20. >>> Creating group 'input' with GID 104. >>> Creating group 'kmem' with GID 9. >>> Creating group 'kvm' with GID 36. >>> Creating group 'lock' with GID 54. >>> Creating group 'lp' with GID 7. >>> Creating group 'mail' with GID 12. >>> Creating group 'man' with GID 15. >>> Creating group 'mem' with GID 8. >>> Creating group 'nobody' with GID 65534. >>> Creating group 'render' with GID 105. >>> Creating group 'root' with GID 0. >>> Creating group 'sgx' with GID 106. >>> Creating group 'sys' with GID 3. >>> Creating group 'tape' with GID 33. >>> Creating group 'tty' with GID 5. >>> Creating group 'users' with GID 100. >>> Creating group 'utmp' with GID 22. >>> Creating group 'video' with GID 39. >>> Creating group 'wheel' with GID 10. >>> Creating user 'adm' (adm) with UID 3 and GID 4. >>> Creating group 'bin' with GID 1. >>> Creating user 'bin' (bin) with UID 1 and GID 1. >>> Creating group 'daemon' with GID 2. >>> Creating user 'daemon' (daemon) with UID 2 and GID 2. >>> Creating user 'ftp' (FTP User) with UID 14 and GID 50. >>> Creating user 'games' (games) with UID 12 and GID 100. >>> Creating user 'halt' (halt) with UID 7 and GID 0. >>> Creating user 'lp' (lp) with UID 4 and GID 7. >>> Creating user 'mail' (mail) with UID 8 and GID 12. >>> Creating user 'nobody' (Kernel Overflow User) with UID 65534 and GID 65534. >>> Creating user 'operator' (operator) with UID 11 and GID 0. >>> Creating user 'root' (Super User) with UID 0 and GID 0. >>> Creating user 'shutdown' (shutdown) with UID 6 and GID 0. >>> Creating user 'sync' (sync) with UID 5 and GID 0. >>> [ 14/192] Installing setup-0:2.15.1-2.f 100% | 29.8 MiB/s | 731.3 KiB | 00m00s [ 15/192] Installing filesystem-0:3.18- 100% | 1.7 MiB/s | 253.6 KiB | 00m00s [ 16/192] Installing pkgconf-m4-0:2.5.1 100% | 14.4 MiB/s | 14.7 KiB | 00m00s [ 17/192] Installing pcre2-syntax-0:10. 100% | 138.8 MiB/s | 284.3 KiB | 00m00s [ 18/192] Installing gnulib-l10n-0:2024 100% | 129.3 MiB/s | 661.9 KiB | 00m00s [ 19/192] Installing coreutils-common-0 100% | 296.1 MiB/s | 11.0 MiB | 00m00s [ 20/192] Installing ncurses-base-0:6.6 100% | 43.4 MiB/s | 355.3 KiB | 00m00s [ 21/192] Installing bash-0:5.3.15-2.fc 100% | 175.7 MiB/s | 8.4 MiB | 00m00s [ 22/192] Installing glibc-common-0:2.4 100% | 44.3 MiB/s | 1.3 MiB | 00m00s [ 23/192] Installing glibc-gconv-extra- 100% | 359.3 MiB/s | 18.7 MiB | 00m00s [ 24/192] Installing glibc-0:2.44.9000- 100% | 129.2 MiB/s | 6.6 MiB | 00m00s [ 25/192] Installing ncurses-libs-0:6.6 100% | 207.6 MiB/s | 1.2 MiB | 00m00s [ 26/192] Installing glibc-minimal-lang 100% | 0.0 B/s | 124.0 B | 00m00s [ 27/192] Installing zlib-ng-compat-0:2 100% | 131.1 MiB/s | 134.3 KiB | 00m00s [ 28/192] Installing bzip2-libs-0:1.0.8 100% | 71.9 MiB/s | 73.6 KiB | 00m00s [ 29/192] Installing libgpg-error-0:1.6 100% | 36.3 MiB/s | 1.0 MiB | 00m00s [ 30/192] Installing readline-0:8.3-6.f 100% | 184.1 MiB/s | 565.7 KiB | 00m00s [ 31/192] Installing libstdc++-0:16.2.1 100% | 297.2 MiB/s | 3.0 MiB | 00m00s [ 32/192] Installing libzstd-0:1.5.7-6. 100% | 280.5 MiB/s | 861.6 KiB | 00m00s [ 33/192] Installing elfutils-libelf-0: 100% | 291.7 MiB/s | 1.5 MiB | 00m00s [ 34/192] Installing libassuan-0:2.5.7- 100% | 212.6 MiB/s | 217.7 KiB | 00m00s [ 35/192] Installing libgcrypt-0:1.12.4 100% | 240.7 MiB/s | 1.2 MiB | 00m00s [ 36/192] Installing gmp-1:6.3.0-6.fc45 100% | 214.9 MiB/s | 660.1 KiB | 00m00s [ 37/192] Installing libacl-0:2.4.0-2.f 100% | 67.1 MiB/s | 68.8 KiB | 00m00s [ 38/192] Installing systemd-libs-0:262 100% | 309.0 MiB/s | 2.8 MiB | 00m00s [ 39/192] Installing libuuid-0:2.42.2-3 100% | 68.8 MiB/s | 70.4 KiB | 00m00s [ 40/192] Installing popt-0:1.19-11.fc4 100% | 36.9 MiB/s | 151.3 KiB | 00m00s [ 41/192] Installing xz-libs-1:5.8.4-1. 100% | 260.3 MiB/s | 266.6 KiB | 00m00s [ 42/192] Installing sqlite-libs-0:3.53 100% | 261.4 MiB/s | 1.6 MiB | 00m00s [ 43/192] Installing npth-0:1.8-5.fc45. 100% | 92.3 MiB/s | 94.5 KiB | 00m00s [ 44/192] Installing elfutils-libs-0:0. 100% | 243.7 MiB/s | 748.5 KiB | 00m00s [ 45/192] Installing libblkid-0:2.42.2- 100% | 142.3 MiB/s | 291.4 KiB | 00m00s [ 46/192] Installing libsepol-0:3.11-2. 100% | 264.0 MiB/s | 810.9 KiB | 00m00s [ 47/192] Installing gnupg2-gpgconf-0:2 100% | 13.2 MiB/s | 323.9 KiB | 00m00s [ 48/192] Installing pcre2-0:10.47-1.fc 100% | 233.0 MiB/s | 715.8 KiB | 00m00s [ 49/192] Installing libselinux-0:3.11- 100% | 130.1 MiB/s | 266.5 KiB | 00m00s [ 50/192] Installing grep-0:3.12-4.fc45 100% | 35.8 MiB/s | 1.0 MiB | 00m00s [ 51/192] Installing sed-0:4.10-2.fc45. 100% | 30.9 MiB/s | 886.9 KiB | 00m00s [ 52/192] Installing findutils-1:4.11.0 100% | 65.0 MiB/s | 2.0 MiB | 00m00s [ 53/192] Installing libxcrypt-0:4.5.2- 100% | 134.7 MiB/s | 275.9 KiB | 00m00s [ 54/192] Installing json-c-0:0.18-9.fc 100% | 136.5 MiB/s | 139.8 KiB | 00m00s [ 55/192] Installing libtasn1-0:4.21.0- 100% | 108.6 MiB/s | 222.5 KiB | 00m00s [ 56/192] Installing libunistring-0:1.1 100% | 291.0 MiB/s | 1.7 MiB | 00m00s [ 57/192] Installing libidn2-0:2.3.8-4. 100% | 61.5 MiB/s | 566.6 KiB | 00m00s [ 58/192] Installing crypto-policies-0: 100% | 19.5 MiB/s | 159.5 KiB | 00m00s [ 59/192] Installing xz-1:5.8.4-1.fc46. 100% | 47.0 MiB/s | 1.5 MiB | 00m00s [ 60/192] Installing libmount-0:2.42.2- 100% | 205.8 MiB/s | 421.4 KiB | 00m00s [ 61/192] Installing gnupg2-verify-0:2. 100% | 14.9 MiB/s | 365.7 KiB | 00m00s [ 62/192] Installing mpfr-0:4.2.2-4.fc4 100% | 184.8 MiB/s | 757.1 KiB | 00m00s [ 63/192] Installing gawk-0:5.4.1-1.fc4 100% | 91.4 MiB/s | 2.9 MiB | 00m00s [ 64/192] Installing dwz-0:0.17-3.fc45. 100% | 13.2 MiB/s | 324.0 KiB | 00m00s [ 65/192] Installing libksba-0:1.8.1-1. 100% | 200.3 MiB/s | 410.3 KiB | 00m00s [ 66/192] Installing unzip-0:6.0-71.fc4 100% | 18.5 MiB/s | 473.4 KiB | 00m00s [ 67/192] Installing file-libs-0:5.48-3 100% | 588.6 MiB/s | 12.4 MiB | 00m00s [ 68/192] Installing file-0:5.48-3.fc46 100% | 6.1 MiB/s | 143.4 KiB | 00m00s [ 69/192] Installing diffutils-0:3.12-6 100% | 54.1 MiB/s | 1.6 MiB | 00m00s [ 70/192] Installing libattr-0:2.6.0-2. 100% | 67.7 MiB/s | 69.3 KiB | 00m00s [ 71/192] Installing libeconf-0:0.7.9-4 100% | 80.6 MiB/s | 82.5 KiB | 00m00s [ 72/192] Installing libcap-ng-0:0.9.6- 100% | 159.0 MiB/s | 162.8 KiB | 00m00s [ 73/192] Installing audit-libs-0:4.2.1 100% | 238.9 MiB/s | 489.3 KiB | 00m00s [ 74/192] Installing pam-libs-0:1.7.2-4 100% | 109.9 MiB/s | 225.1 KiB | 00m00s [ 75/192] Installing libcap-0:2.78-2.fc 100% | 20.1 MiB/s | 513.5 KiB | 00m00s [ 76/192] Installing libsemanage-0:3.11 100% | 176.8 MiB/s | 362.0 KiB | 00m00s [ 77/192] Installing libsmartcols-0:2.4 100% | 220.1 MiB/s | 225.4 KiB | 00m00s [ 78/192] Installing alternatives-0:1.3 100% | 3.9 MiB/s | 91.7 KiB | 00m00s [ 79/192] Installing lua-libs-0:5.5.1-2 100% | 161.9 MiB/s | 331.5 KiB | 00m00s [ 80/192] Installing libffi-0:3.8.0-1.f 100% | 157.2 MiB/s | 161.0 KiB | 00m00s [ 81/192] Installing p11-kit-0:0.26.5-1 100% | 80.0 MiB/s | 2.8 MiB | 00m00s [ 82/192] Installing p11-kit-trust-0:0. 100% | 17.9 MiB/s | 531.9 KiB | 00m00s [ 83/192] Installing ngtcp2-0:1.22.1-3. 100% | 167.3 MiB/s | 342.7 KiB | 00m00s [ 84/192] Installing util-linux-core-0: 100% | 76.8 MiB/s | 2.5 MiB | 00m00s [ 85/192] Installing liblastlog2-0:2.42 100% | 27.3 MiB/s | 139.8 KiB | 00m00s [ 86/192] Installing zip-0:3.0-46.fc45. 100% | 28.8 MiB/s | 766.1 KiB | 00m00s [ 87/192] Installing gnupg2-keyboxd-0:2 100% | 45.8 MiB/s | 234.5 KiB | 00m00s [ 88/192] Installing libpsl-0:0.23.3-1. 100% | 130.4 MiB/s | 133.6 KiB | 00m00s [ 89/192] Installing tar-2:1.35-9.fc45. 100% | 88.4 MiB/s | 3.0 MiB | 00m00s [ 90/192] Installing linkdupes-0:0.7.3- 100% | 27.8 MiB/s | 712.4 KiB | 00m00s [ 91/192] Installing libselinux-utils-0 100% | 50.3 MiB/s | 1.4 MiB | 00m00s [ 92/192] Installing libfdisk-0:2.42.2- 100% | 205.0 MiB/s | 419.9 KiB | 00m00s [ 93/192] Installing fips-provider-0:1. 100% | 312.4 MiB/s | 3.7 MiB | 00m00s [ 94/192] Installing openssl-libs-1:4.0 100% | 305.9 MiB/s | 5.8 MiB | 00m00s [ 95/192] Installing coreutils-0:9.11-6 100% | 161.3 MiB/s | 8.2 MiB | 00m00s [ 96/192] Installing ca-certificates-0: 100% | 1.5 MiB/s | 2.5 MiB | 00m02s [ 97/192] Installing gzip-0:1.14-4.fc45 100% | 16.0 MiB/s | 443.1 KiB | 00m00s [ 98/192] Installing util-linux-0:2.42. 100% | 123.0 MiB/s | 7.0 MiB | 00m00s [ 99/192] Installing policycoreutils-0: 100% | 38.2 MiB/s | 1.5 MiB | 00m00s [100/192] Installing selinux-policy-0:4 100% | 1.9 MiB/s | 34.5 KiB | 00m00s [101/192] Installing selinux-policy-tar 100% | 130.6 MiB/s | 15.1 MiB | 00m00s [102/192] Installing rpm-sequoia-0:1.10 100% | 286.5 MiB/s | 2.3 MiB | 00m00s [103/192] Installing libfsverity-0:1.7- 100% | 67.8 MiB/s | 69.4 KiB | 00m00s [104/192] Installing libevent-0:2.1.13- 100% | 271.7 MiB/s | 1.1 MiB | 00m00s [105/192] Installing ngtcp2-crypto-ossl 100% | 66.7 MiB/s | 68.3 KiB | 00m00s [106/192] Installing libusb1-0:1.0.30-2 100% | 14.8 MiB/s | 181.4 KiB | 00m00s >>> Running sysusers scriptlet: tpm2-tss-0:4.2.0-1.fc45.aarch64 >>> Finished sysusers scriptlet: tpm2-tss-0:4.2.0-1.fc45.aarch64 >>> Scriptlet output: >>> Creating group 'tss' with GID 59. >>> Creating user 'tss' (Account used for TPM access) with UID 59 and GID 59. >>> [107/192] Installing tpm2-tss-0:4.2.0-1 100% | 248.3 MiB/s | 2.2 MiB | 00m00s [108/192] Installing ima-evm-utils-libs 100% | 91.7 MiB/s | 93.9 KiB | 00m00s [109/192] Installing gnupg2-gpg-agent-0 100% | 26.8 MiB/s | 850.8 KiB | 00m00s [110/192] Installing nettle-0:4.0-5.fc4 100% | 205.0 MiB/s | 839.8 KiB | 00m00s [111/192] Installing gnutls-0:3.8.13-5. 100% | 309.1 MiB/s | 3.7 MiB | 00m00s [112/192] Installing zstd-0:1.5.7-6.fc4 100% | 21.3 MiB/s | 565.9 KiB | 00m00s [113/192] Installing libxml2-0:2.15.4-1 100% | 59.3 MiB/s | 1.7 MiB | 00m00s [114/192] Installing bzip2-0:1.0.8-24.f 100% | 7.1 MiB/s | 175.7 KiB | 00m00s [115/192] Installing add-determinism-0: 100% | 65.7 MiB/s | 1.9 MiB | 00m00s [116/192] Installing build-reproducibil 100% | 1.5 MiB/s | 1.5 KiB | 00m00s [117/192] Installing cpio-0:2.15-10.fc4 100% | 39.1 MiB/s | 1.1 MiB | 00m00s [118/192] Installing ed-0:1.22.6-1.fc46 100% | 6.6 MiB/s | 161.2 KiB | 00m00s [119/192] Installing patch-0:2.8-5.fc45 100% | 10.7 MiB/s | 263.9 KiB | 00m00s [120/192] Installing jansson-0:2.14-5.f 100% | 92.2 MiB/s | 94.4 KiB | 00m00s [121/192] Installing libpfm-0:4.13.0-23 100% | 247.4 MiB/s | 253.3 KiB | 00m00s [122/192] Installing lz4-libs-0:1.10.0- 100% | 193.8 MiB/s | 198.4 KiB | 00m00s [123/192] Installing libarchive-0:3.8.9 100% | 238.7 MiB/s | 977.6 KiB | 00m00s [124/192] Installing libgomp-0:16.2.1-2 100% | 290.2 MiB/s | 594.3 KiB | 00m00s [125/192] Installing libpkgconf-0:2.5.1 100% | 132.0 MiB/s | 135.2 KiB | 00m00s [126/192] Installing pkgconf-0:2.5.1-2. 100% | 4.9 MiB/s | 119.3 KiB | 00m00s [127/192] Installing pkgconf-pkg-config 100% | 80.6 KiB/s | 1.8 KiB | 00m00s [128/192] Installing libtool-ltdl-0:2.6 100% | 92.8 MiB/s | 95.0 KiB | 00m00s [129/192] Installing gdbm-libs-1:1.23-1 100% | 230.0 MiB/s | 235.5 KiB | 00m00s [130/192] Installing cyrus-sasl-lib-0:2 100% | 78.0 MiB/s | 2.4 MiB | 00m00s [131/192] Installing openldap-0:2.6.14- 100% | 187.7 MiB/s | 768.9 KiB | 00m00s [132/192] Installing gnupg2-dirmngr-0:2 100% | 21.1 MiB/s | 648.9 KiB | 00m00s [133/192] Installing gnupg2-0:2.4.9-18. 100% | 143.5 MiB/s | 6.5 MiB | 00m00s [134/192] Installing gpgverify-0:2.2-5. 100% | 9.2 MiB/s | 9.4 KiB | 00m00s [135/192] Installing systemd-standalone 100% | 36.8 MiB/s | 979.9 KiB | 00m00s [136/192] Installing rpm-libs-0:6.1.0-1 100% | 220.1 MiB/s | 1.1 MiB | 00m00s [137/192] Installing rpm-sign-libs-0:6. 100% | 66.9 MiB/s | 68.5 KiB | 00m00s [138/192] Installing rpm-build-libs-0:6 100% | 129.3 MiB/s | 264.9 KiB | 00m00s [139/192] Installing xxhash-libs-0:0.8. 100% | 85.1 MiB/s | 87.2 KiB | 00m00s [140/192] Installing libbrotli-0:1.2.0- 100% | 222.5 MiB/s | 911.5 KiB | 00m00s [141/192] Installing libnghttp2-0:1.69. 100% | 194.4 MiB/s | 199.0 KiB | 00m00s [142/192] Installing libnghttp3-0:1.18. 100% | 203.3 MiB/s | 208.2 KiB | 00m00s [143/192] Installing keyutils-libs-0:1. 100% | 97.3 MiB/s | 99.7 KiB | 00m00s [144/192] Installing libcom_err-0:1.47. 100% | 109.6 MiB/s | 112.2 KiB | 00m00s [145/192] Installing libverto-0:0.3.2-1 100% | 69.5 MiB/s | 71.1 KiB | 00m00s [146/192] Installing krb5-libs-0:1.22.2 100% | 253.4 MiB/s | 2.5 MiB | 00m00s [147/192] Installing libcbor-0:0.14.0-3 100% | 137.7 MiB/s | 141.0 KiB | 00m00s [148/192] Installing libfido2-0:1.17.0- 100% | 137.8 MiB/s | 282.2 KiB | 00m00s [149/192] Installing libssh-0:0.12.2-1. 100% | 235.5 MiB/s | 723.4 KiB | 00m00s [150/192] Installing libcurl-0:8.22.0-1 100% | 255.7 MiB/s | 1.0 MiB | 00m00s [151/192] Installing elfutils-debuginfo 100% | 6.0 MiB/s | 146.3 KiB | 00m00s [152/192] Installing binutils-0:2.47.50 100% | 272.1 MiB/s | 27.2 MiB | 00m00s [153/192] Installing elfutils-0:0.196-1 100% | 108.0 MiB/s | 3.8 MiB | 00m00s [154/192] Installing gdb-minimal-0:17.2 100% | 218.3 MiB/s | 13.5 MiB | 00m00s [155/192] Installing debugedit-0:5.3-3. 100% | 12.7 MiB/s | 324.2 KiB | 00m00s [156/192] Installing curl-0:8.22.0-1.fc 100% | 16.2 MiB/s | 529.4 KiB | 00m00s [157/192] Installing rpm-0:6.1.0-1.fc46 100% | 55.1 MiB/s | 2.8 MiB | 00m00s [158/192] Installing cmake-srpm-macros- 100% | 785.2 KiB/s | 804.0 B | 00m00s [159/192] Installing efi-srpm-macros-0: 100% | 40.3 MiB/s | 41.3 KiB | 00m00s [160/192] Installing java-srpm-macros-0 100% | 0.0 B/s | 1.1 KiB | 00m00s [161/192] Installing lua-srpm-macros-0: 100% | 0.0 B/s | 1.9 KiB | 00m00s [162/192] Installing tree-sitter-srpm-m 100% | 9.4 MiB/s | 9.6 KiB | 00m00s [163/192] Installing zig-srpm-macros-0: 100% | 0.0 B/s | 1.9 KiB | 00m00s [164/192] Installing filesystem-srpm-ma 100% | 38.0 MiB/s | 38.9 KiB | 00m00s [165/192] Installing rust-srpm-macros-0 100% | 6.2 MiB/s | 6.4 KiB | 00m00s [166/192] Installing qt6-srpm-macros-0: 100% | 0.0 B/s | 748.0 B | 00m00s [167/192] Installing qt5-srpm-macros-0: 100% | 0.0 B/s | 776.0 B | 00m00s [168/192] Installing perl-srpm-macros-0 100% | 185.5 KiB/s | 1.1 KiB | 00m00s [169/192] Installing package-notes-srpm 100% | 0.0 B/s | 2.1 KiB | 00m00s [170/192] Installing openblas-srpm-macr 100% | 0.0 B/s | 392.0 B | 00m00s [171/192] Installing ocaml-srpm-macros- 100% | 0.0 B/s | 2.1 KiB | 00m00s [172/192] Installing meson-srpm-macros- 100% | 0.0 B/s | 1.9 KiB | 00m00s [173/192] Installing kernel-srpm-macros 100% | 0.0 B/s | 2.3 KiB | 00m00s [174/192] Installing gnome-srpm-macros- 100% | 0.0 B/s | 4.1 KiB | 00m00s [175/192] Installing gnat-srpm-macros-0 100% | 0.0 B/s | 1.3 KiB | 00m00s [176/192] Installing ghc-srpm-macros-0: 100% | 0.0 B/s | 1.0 KiB | 00m00s [177/192] Installing gap-srpm-macros-0: 100% | 0.0 B/s | 2.7 KiB | 00m00s [178/192] Installing fpc-srpm-macros-0: 100% | 0.0 B/s | 420.0 B | 00m00s [179/192] Installing ansible-srpm-macro 100% | 35.4 MiB/s | 36.2 KiB | 00m00s [180/192] Installing redhat-rpm-config- 100% | 62.0 MiB/s | 190.4 KiB | 00m00s [181/192] Installing forge-srpm-macros- 100% | 39.3 MiB/s | 40.3 KiB | 00m00s [182/192] Installing rpm-build-0:6.1.0- 100% | 21.8 MiB/s | 626.1 KiB | 00m00s [183/192] Installing erlang-srpm-macros 100% | 2.4 MiB/s | 2.5 KiB | 00m00s [184/192] Installing pyproject-srpm-mac 100% | 0.0 B/s | 4.0 KiB | 00m00s [185/192] Installing fonts-srpm-macros- 100% | 55.7 MiB/s | 57.0 KiB | 00m00s [186/192] Installing go-srpm-macros-0:3 100% | 61.6 MiB/s | 63.0 KiB | 00m00s [187/192] Installing R-srpm-macros-0:1. 100% | 4.3 MiB/s | 4.4 KiB | 00m00s [188/192] Installing python-srpm-macros 100% | 51.7 MiB/s | 52.9 KiB | 00m00s [189/192] Installing rpm-plugin-selinux 100% | 67.3 MiB/s | 68.9 KiB | 00m00s [190/192] Installing which-0:2.25-2.fc4 100% | 4.9 MiB/s | 125.8 KiB | 00m00s [191/192] Installing shadow-utils-2:4.2 100% | 88.9 MiB/s | 4.4 MiB | 00m00s [192/192] Installing info-0:7.3-3.fc45. 100% | 52.1 KiB/s | 424.8 KiB | 00m08s Complete! Finish: installing minimal buildroot with dnf5 Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: R-srpm-macros-1.3.7-3.fc45.noarch add-determinism-0.7.3-3.fc45.aarch64 alternatives-1.33-6.fc45.aarch64 ansible-srpm-macros-1-22.fc45.noarch audit-libs-4.2.1-2.fc45.aarch64 bash-5.3.15-2.fc45.aarch64 binutils-2.47.50-7.fc46.aarch64 build-reproducibility-srpm-macros-0.7.3-3.fc45.noarch bzip2-1.0.8-24.fc45.aarch64 bzip2-libs-1.0.8-24.fc45.aarch64 ca-certificates-2026.2.90_v9.0.317-1.fc46.noarch cmake-srpm-macros-4.3.0-5.fc45.noarch coreutils-9.11-6.fc45.aarch64 coreutils-common-9.11-6.fc45.aarch64 cpio-2.15-10.fc45.aarch64 crypto-policies-20260713-2.gitc42da77.fc45.noarch curl-8.22.0-1.fc46.aarch64 cyrus-sasl-lib-2.1.28-37.fc45.aarch64 debugedit-5.3-3.fc45.aarch64 diffutils-3.12-6.fc45.aarch64 dwz-0.17-3.fc45.aarch64 ed-1.22.6-1.fc46.aarch64 efi-srpm-macros-6-9.fc45.noarch elfutils-0.196-1.fc46.aarch64 elfutils-debuginfod-client-0.196-1.fc46.aarch64 elfutils-libelf-0.196-1.fc46.aarch64 elfutils-libs-0.196-1.fc46.aarch64 erlang-srpm-macros-0.3.11-2.fc45.noarch fedora-gpg-keys-46-0.3.noarch fedora-release-46-0.1.noarch fedora-release-common-46-0.1.noarch fedora-release-identity-basic-46-0.1.noarch fedora-repos-46-0.3.noarch fedora-repos-rawhide-46-0.3.noarch file-5.48-3.fc46.aarch64 file-libs-5.48-3.fc46.aarch64 filesystem-3.18-59.fc45.aarch64 filesystem-srpm-macros-3.18-59.fc45.noarch findutils-4.11.0-2.fc45.aarch64 fips-provider-1.5.2-6.fc46.aarch64 fonts-srpm-macros-5.0.0-4.fc45.noarch forge-srpm-macros-0.4.0-5.fc45.noarch fpc-srpm-macros-1.3-17.fc45.noarch gap-srpm-macros-2-3.fc45.noarch gawk-5.4.1-1.fc45.aarch64 gdb-minimal-17.2-6.fc46.aarch64 gdbm-libs-1.23-12.fc45.aarch64 ghc-srpm-macros-1.10-2.fc45.noarch glibc-2.44.9000-2.fc46.aarch64 glibc-common-2.44.9000-2.fc46.aarch64 glibc-gconv-extra-2.44.9000-2.fc46.aarch64 glibc-minimal-langpack-2.44.9000-2.fc46.aarch64 gmp-6.3.0-6.fc45.aarch64 gnat-srpm-macros-7-3.fc45.noarch gnome-srpm-macros-1.0-2.fc45.noarch gnulib-l10n-20241231-4.fc45.noarch gnupg2-2.4.9-18.fc45.aarch64 gnupg2-dirmngr-2.4.9-18.fc45.aarch64 gnupg2-gpg-agent-2.4.9-18.fc45.aarch64 gnupg2-gpgconf-2.4.9-18.fc45.aarch64 gnupg2-keyboxd-2.4.9-18.fc45.aarch64 gnupg2-verify-2.4.9-18.fc45.aarch64 gnutls-3.8.13-5.fc46.aarch64 go-srpm-macros-3.8.0-3.fc45.noarch gpg-pubkey-4f50a6114cd5c6976a7f1179655a4b02f577861e-6888bc98 gpg-pubkey-b2e766fa50ca6fa2d5ed06fc09d879e09488fb64-6a6b46b4 gpg-pubkey-d924b10d3e810dabdd8b56b596e7e91491211fce-697c9899 gpgverify-2.2-5.fc45.noarch grep-3.12-4.fc45.aarch64 gzip-1.14-4.fc45.aarch64 ima-evm-utils-libs-1.6.2-12.fc45.aarch64 info-7.3-3.fc45.aarch64 jansson-2.14-5.fc45.aarch64 java-srpm-macros-1-9.fc45.noarch json-c-0.18-9.fc45.aarch64 kernel-srpm-macros-1.0-30.fc45.noarch keyutils-libs-1.6.3-8.fc45.aarch64 krb5-libs-1.22.2-9.fc45.aarch64 libacl-2.4.0-2.fc45.aarch64 libarchive-3.8.9-2.fc46.aarch64 libassuan-2.5.7-6.fc45.aarch64 libattr-2.6.0-2.fc45.aarch64 libblkid-2.42.2-3.fc45.aarch64 libbrotli-1.2.0-6.fc45.aarch64 libcap-2.78-2.fc45.aarch64 libcap-ng-0.9.6-1.fc46.aarch64 libcbor-0.14.0-3.fc45.aarch64 libcom_err-1.47.4-2.fc45.aarch64 libcurl-8.22.0-1.fc46.aarch64 libeconf-0.7.9-4.fc45.aarch64 libevent-2.1.13-1.fc46.aarch64 libfdisk-2.42.2-3.fc45.aarch64 libffi-3.8.0-1.fc46.aarch64 libfido2-1.17.0-5.fc45.aarch64 libfsverity-1.7-4.fc45.aarch64 libgcc-16.2.1-2.fc46.1.aarch64 libgcrypt-1.12.4-1.fc46.aarch64 libgomp-16.2.1-2.fc46.1.aarch64 libgpg-error-1.61-2.fc45.aarch64 libidn2-2.3.8-4.fc45.aarch64 libksba-1.8.1-1.fc46.aarch64 liblastlog2-2.42.2-3.fc45.aarch64 libmount-2.42.2-3.fc45.aarch64 libnghttp2-1.69.0-6.fc46.aarch64 libnghttp3-1.18.0-1.fc45.aarch64 libpfm-4.13.0-23.fc45.aarch64 libpkgconf-2.5.1-2.fc45.aarch64 libpsl-0.23.3-1.fc46.aarch64 libselinux-3.11-5.fc46.aarch64 libselinux-utils-3.11-5.fc46.aarch64 libsemanage-3.11-4.fc46.aarch64 libsepol-3.11-2.fc45.aarch64 libsmartcols-2.42.2-3.fc45.aarch64 libssh-0.12.2-1.fc45.aarch64 libssh-config-0.12.2-1.fc45.noarch libstdc++-16.2.1-2.fc46.1.aarch64 libtasn1-4.21.0-2.fc45.aarch64 libtool-ltdl-2.6.2-1.fc46.aarch64 libunistring-1.1-12.fc45.aarch64 libusb1-1.0.30-2.fc45.aarch64 libuuid-2.42.2-3.fc45.aarch64 libverto-0.3.2-13.fc45.aarch64 libxcrypt-4.5.2-4.fc45.aarch64 libxml2-2.15.4-1.fc46.aarch64 libzstd-1.5.7-6.fc45.aarch64 linkdupes-0.7.3-3.fc45.aarch64 lua-libs-5.5.1-2.fc46.aarch64 lua-srpm-macros-1-18.fc45.noarch lz4-libs-1.10.0-5.fc45.aarch64 meson-srpm-macros-1.12.0-2.fc46.noarch mpfr-4.2.2-4.fc45.aarch64 ncurses-base-6.6-3.fc45.noarch ncurses-libs-6.6-3.fc45.aarch64 nettle-4.0-5.fc45.aarch64 ngtcp2-1.22.1-3.fc45.aarch64 ngtcp2-crypto-ossl-1.22.1-3.fc45.aarch64 npth-1.8-5.fc45.aarch64 ocaml-srpm-macros-11-4.fc45.noarch openblas-srpm-macros-2-22.fc45.noarch openldap-2.6.14-1.fc46.aarch64 openssl-libs-4.0.2-3.fc46.aarch64 p11-kit-0.26.5-1.fc45.aarch64 p11-kit-trust-0.26.5-1.fc45.aarch64 package-notes-srpm-macros-0.20-2.fc45.noarch pam-libs-1.7.2-4.fc45.aarch64 patch-2.8-5.fc45.aarch64 pcre2-10.47-1.fc45.2.aarch64 pcre2-syntax-10.47-1.fc45.2.noarch perl-srpm-macros-1-65.fc45.noarch pkgconf-2.5.1-2.fc45.aarch64 pkgconf-m4-2.5.1-2.fc45.noarch pkgconf-pkg-config-2.5.1-2.fc45.aarch64 policycoreutils-3.11-2.fc45.aarch64 popt-1.19-11.fc45.aarch64 publicsuffix-list-dafsa-20260624-2.fc45.noarch pyproject-srpm-macros-1.23.2-1.fc45.noarch python-srpm-macros-3.15-2.fc45.noarch qt5-srpm-macros-5.15.18-3.fc45.noarch qt6-srpm-macros-6.11.2-1.fc46.noarch readline-8.3-6.fc45.aarch64 redhat-rpm-config-345-4.fc46.noarch redhat-systemd-presets-102-3.fc45.noarch redhat-systemd-presets-common-102-3.fc45.noarch rpm-6.1.0-1.fc46.aarch64 rpm-build-6.1.0-1.fc46.aarch64 rpm-build-libs-6.1.0-1.fc46.aarch64 rpm-libs-6.1.0-1.fc46.aarch64 rpm-plugin-selinux-6.1.0-1.fc46.aarch64 rpm-sequoia-1.10.3-1.fc46.aarch64 rpm-sign-libs-6.1.0-1.fc46.aarch64 rust-srpm-macros-28.5-2.fc45.noarch sed-4.10-2.fc45.aarch64 selinux-policy-45.17-1.fc46.noarch selinux-policy-targeted-45.17-1.fc46.noarch setup-2.15.1-2.fc45.noarch shadow-utils-4.20.0-1.fc45.aarch64 sqlite-libs-3.53.4-1.fc45.aarch64 systemd-libs-262~rc3-1.fc46.aarch64 systemd-standalone-sysusers-262~rc3-1.fc46.aarch64 tar-1.35-9.fc45.aarch64 tpm2-tss-4.2.0-1.fc45.aarch64 tree-sitter-srpm-macros-0.4.6-2.fc45.noarch unzip-6.0-71.fc45.aarch64 util-linux-2.42.2-3.fc45.aarch64 util-linux-core-2.42.2-3.fc45.aarch64 which-2.25-2.fc45.aarch64 xxhash-libs-0.8.4-1.fc46.aarch64 xz-5.8.4-1.fc46.aarch64 xz-libs-5.8.4-1.fc46.aarch64 zig-srpm-macros-1-9.fc45.noarch zip-3.0-46.fc45.aarch64 zlib-ng-compat-2.3.3-6.fc45.aarch64 zstd-1.5.7-6.fc45.aarch64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Finish: rpmbuild -bs INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-rawhide-aarch64-1789969120.434794/root/var/log/dnf5.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-bnav10e1/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(child) 0 minutes 25 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm) Config(fedora-rawhide-aarch64) Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-aarch64-bootstrap-1789969120.434794/root. INFO: reusing tmpfs at /var/lib/mock/fedora-rawhide-aarch64-bootstrap-1789969120.434794/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-aarch64-1789969120.434794/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin INFO: Buildroot is handled by package management downloaded with a bootstrap image: rpm-6.1.0-1.fc46.aarch64 rpm-sequoia-1.10.3-1.fc46.aarch64 dnf5-5.4.5.0-1.fc46.aarch64 dnf5-plugins-5.4.5.0-1.fc46.aarch64 Finish: chroot init Start: build phase for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Start: build setup for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Building target platforms: aarch64 Building for target aarch64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Updating and loading repositories: fedora 100% | 73.1 KiB/s | 8.4 KiB | 00m00s Copr repository 100% | 25.6 KiB/s | 2.1 KiB | 00m00s Repositories loaded. Package Arch Version Repository Size Installing: git aarch64 0:2.55.0-2.fc45 fedora 57.7 KiB python3-devel aarch64 0:3.15.0~rc2-1.fc46 fedora 2.5 MiB python3-setuptools noarch 0:84.0.0-1.fc46 fedora 7.4 MiB Installing dependencies: expat aarch64 0:2.8.3-1.fc46 fedora 378.4 KiB git-core aarch64 0:2.55.0-2.fc45 fedora 24.8 MiB git-core-doc noarch 0:2.55.0-2.fc45 fedora 18.9 MiB groff-base aarch64 0:1.24.1-2.fc45 fedora 4.5 MiB less aarch64 0:704-5.fc46 fedora 608.2 KiB libedit aarch64 0:3.1-60.20260512cvs.fc45 fedora 280.3 KiB mpdecimal aarch64 0:4.0.1-4.fc45 fedora 281.1 KiB ncurses aarch64 0:6.6-3.fc45 fedora 895.8 KiB openssh aarch64 0:10.5p1-1.fc46 fedora 1.6 MiB openssh-clients aarch64 0:10.5p1-1.fc46 fedora 2.6 MiB perl-AutoLoader noarch 0:5.74-527.fc45 fedora 20.6 KiB perl-B aarch64 0:1.92-527.fc45 fedora 557.5 KiB perl-Carp noarch 0:1.54-527.fc45 fedora 46.6 KiB perl-Class-Struct noarch 0:0.68-527.fc45 fedora 25.4 KiB perl-Data-Dumper aarch64 0:2.192-528.fc45 fedora 135.5 KiB perl-Digest noarch 0:1.20-527.fc45 fedora 35.2 KiB perl-Digest-MD5 aarch64 0:2.59-527.fc45 fedora 103.6 KiB perl-DynaLoader aarch64 0:1.57-527.fc45 fedora 32.1 KiB perl-Encode aarch64 4:3.24-527.fc45 fedora 4.8 MiB perl-Errno aarch64 0:1.39-527.fc45 fedora 8.4 KiB perl-Error noarch 1:0.17030-4.fc45 fedora 76.8 KiB perl-Exporter noarch 0:5.79-527.fc45 fedora 54.2 KiB perl-Fcntl aarch64 0:1.20-527.fc45 fedora 92.7 KiB perl-File-Basename noarch 0:2.86-527.fc45 fedora 14.0 KiB perl-File-Path noarch 0:2.18-527.fc45 fedora 63.4 KiB perl-File-Temp noarch 1:0.231.200-527.fc45 fedora 163.7 KiB perl-File-stat noarch 0:1.15-527.fc45 fedora 13.7 KiB perl-FileHandle noarch 0:2.05-527.fc45 fedora 9.4 KiB perl-Getopt-Long noarch 1:2.58-527.fc45 fedora 144.5 KiB perl-Getopt-Std noarch 0:1.15-527.fc45 fedora 12.5 KiB perl-Git noarch 0:2.55.0-2.fc45 fedora 64.4 KiB perl-HTTP-Tiny noarch 0:0.096-528.fc45 fedora 162.4 KiB perl-IO aarch64 0:1.56-527.fc45 fedora 191.3 KiB perl-IO-Socket-IP noarch 0:0.44-527.fc45 fedora 100.5 KiB perl-IO-Socket-SSL noarch 0:2.099-2.fc45 fedora 726.9 KiB perl-IPC-Open3 noarch 0:1.24-527.fc45 fedora 27.7 KiB perl-MIME-Base32 noarch 0:1.303-26.fc45 fedora 30.7 KiB perl-MIME-Base64 aarch64 0:3.16-527.fc45 fedora 93.9 KiB perl-Net-SSLeay aarch64 0:1.96-5.fc45 fedora 1.4 MiB perl-POSIX aarch64 0:2.26-527.fc45 fedora 261.4 KiB perl-PathTools aarch64 0:3.95-527.fc45 fedora 224.0 KiB perl-Pod-Escapes noarch 1:1.07-527.fc45 fedora 24.9 KiB perl-Pod-Perldoc noarch 0:3.28.01-527.fc45 fedora 163.8 KiB perl-Pod-Simple noarch 1:3.48-527.fc45 fedora 565.2 KiB perl-Pod-Usage noarch 4:2.05-527.fc45 fedora 86.3 KiB perl-Scalar-List-Utils aarch64 5:1.70-527.fc45 fedora 152.9 KiB perl-SelectSaver noarch 0:1.03-527.fc45 fedora 2.1 KiB perl-Socket aarch64 4:2.043-1.fc46 fedora 145.8 KiB perl-Storable aarch64 1:3.41-527.fc45 fedora 242.9 KiB perl-Symbol noarch 0:1.09-527.fc45 fedora 6.8 KiB perl-Term-ANSIColor noarch 0:5.01-527.fc45 fedora 97.5 KiB perl-Term-Cap noarch 0:1.18-527.fc45 fedora 29.3 KiB perl-TermReadKey aarch64 0:2.38-29.fc45 fedora 107.9 KiB perl-Text-ParseWords noarch 0:3.31-527.fc45 fedora 13.6 KiB perl-Text-Tabs+Wrap noarch 0:2024.001-527.fc45 fedora 22.6 KiB perl-Time-HiRes aarch64 4:1.9780-527.fc45 fedora 151.7 KiB perl-Time-Local noarch 2:1.350-527.fc45 fedora 69.0 KiB perl-URI noarch 0:5.37-1.fc46 fedora 275.5 KiB perl-Unicode-Normalize aarch64 0:1.32-527.fc45 fedora 524.5 KiB perl-base noarch 0:2.27-527.fc45 fedora 12.6 KiB perl-constant noarch 0:1.33-528.fc45 fedora 26.3 KiB perl-if noarch 0:0.61.000-527.fc45 fedora 5.8 KiB perl-interpreter aarch64 4:5.44.0-527.fc45 fedora 175.8 KiB perl-lib aarch64 0:0.65-527.fc45 fedora 8.5 KiB perl-libnet noarch 0:3.15-528.fc45 fedora 288.4 KiB perl-libs aarch64 4:5.44.0-527.fc45 fedora 12.0 MiB perl-locale noarch 0:1.13-527.fc45 fedora 6.1 KiB perl-mro aarch64 0:1.30-527.fc45 fedora 81.5 KiB perl-overload noarch 0:1.40-527.fc45 fedora 71.6 KiB perl-overloading noarch 0:0.03-527.fc45 fedora 4.8 KiB perl-parent noarch 1:0.244-527.fc45 fedora 10.3 KiB perl-podlators noarch 1:6.1.1-1.fc46 fedora 327.2 KiB perl-vars noarch 0:1.05-527.fc45 fedora 3.9 KiB pyproject-rpm-macros noarch 0:1.23.2-1.fc45 fedora 156.3 KiB python-pip-wheel noarch 0:26.2.1-1.fc46 fedora 1.3 MiB python-rpm-macros noarch 0:3.15-2.fc45 fedora 28.0 KiB python3 aarch64 0:3.15.0~rc2-1.fc46 fedora 84.8 KiB python3-libs aarch64 0:3.15.0~rc2-1.fc46 fedora 49.8 MiB python3-packaging noarch 0:26.3-1.fc46 fedora 1.3 MiB python3-rpm-generators noarch 0:14-35.fc46 fedora 81.9 KiB python3-rpm-macros noarch 0:3.15-2.fc45 fedora 6.5 KiB tzdata noarch 0:2026c-2.fc46 fedora 1.2 MiB Transaction Summary: Installing: 85 packages Total size of inbound packages is 34 MiB. Need to download 34 MiB. After this operation, 144 MiB extra will be used (install 144 MiB, remove 0 B). [ 1/85] git-0:2.55.0-2.fc45.aarch64 100% | 104.9 KiB/s | 41.4 KiB | 00m00s [ 2/85] python3-devel-0:3.15.0~rc2-1.fc 100% | 517.2 KiB/s | 482.6 KiB | 00m01s [ 3/85] perl-File-Basename-0:2.86-527.f 100% | 195.8 KiB/s | 16.8 KiB | 00m00s [ 4/85] perl-Getopt-Long-1:2.58-527.fc4 100% | 734.9 KiB/s | 63.2 KiB | 00m00s [ 5/85] perl-Git-0:2.55.0-2.fc45.noarch 100% | 441.5 KiB/s | 38.0 KiB | 00m00s [ 6/85] perl-IPC-Open3-0:1.24-527.fc45. 100% | 275.8 KiB/s | 23.7 KiB | 00m00s [ 7/85] perl-PathTools-0:3.95-527.fc45. 100% | 575.3 KiB/s | 88.0 KiB | 00m00s [ 8/85] perl-TermReadKey-0:2.38-29.fc45 100% | 363.5 KiB/s | 35.3 KiB | 00m00s [ 9/85] perl-interpreter-4:5.44.0-527.f 100% | 478.6 KiB/s | 72.8 KiB | 00m00s [10/85] perl-lib-0:0.65-527.fc45.aarch6 100% | 155.1 KiB/s | 14.6 KiB | 00m00s [11/85] git-core-doc-0:2.55.0-2.fc45.no 100% | 1.0 MiB/s | 3.2 MiB | 00m03s [12/85] python3-0:3.15.0~rc2-1.fc46.aar 100% | 322.2 KiB/s | 27.7 KiB | 00m00s [13/85] perl-libs-4:5.44.0-527.fc45.aar 100% | 1.2 MiB/s | 2.6 MiB | 00m02s [14/85] expat-0:2.8.3-1.fc46.aarch64 100% | 837.0 KiB/s | 127.2 KiB | 00m00s [15/85] less-0:704-5.fc46.aarch64 100% | 785.0 KiB/s | 222.2 KiB | 00m00s [16/85] git-core-0:2.55.0-2.fc45.aarch6 100% | 1.1 MiB/s | 5.3 MiB | 00m05s [17/85] perl-Carp-0:1.54-527.fc45.noarc 100% | 320.9 KiB/s | 28.6 KiB | 00m00s [18/85] openssh-clients-0:10.5p1-1.fc46 100% | 1.1 MiB/s | 816.1 KiB | 00m01s [19/85] perl-Exporter-0:5.79-527.fc45.n 100% | 340.1 KiB/s | 30.6 KiB | 00m00s [20/85] perl-Pod-Usage-4:2.05-527.fc45. 100% | 448.7 KiB/s | 40.4 KiB | 00m00s [21/85] perl-Text-ParseWords-0:3.31-527 100% | 126.5 KiB/s | 16.2 KiB | 00m00s [22/85] perl-base-0:2.27-527.fc45.noarc 100% | 178.6 KiB/s | 15.9 KiB | 00m00s [23/85] perl-constant-0:1.33-528.fc45.n 100% | 261.2 KiB/s | 22.7 KiB | 00m00s [24/85] perl-overload-0:1.40-527.fc45.n 100% | 508.3 KiB/s | 45.2 KiB | 00m00s [25/85] perl-Error-1:0.17030-4.fc45.noa 100% | 469.5 KiB/s | 40.4 KiB | 00m00s [26/85] perl-Fcntl-0:1.20-527.fc45.aarc 100% | 331.6 KiB/s | 29.5 KiB | 00m00s [27/85] perl-IO-0:1.56-527.fc45.aarch64 100% | 546.3 KiB/s | 83.0 KiB | 00m00s [28/85] perl-POSIX-0:2.26-527.fc45.aarc 100% | 610.6 KiB/s | 96.5 KiB | 00m00s [29/85] perl-Symbol-0:1.09-527.fc45.noa 100% | 161.5 KiB/s | 13.9 KiB | 00m00s [30/85] perl-Errno-0:1.39-527.fc45.aarc 100% | 164.0 KiB/s | 14.6 KiB | 00m00s [31/85] perl-DynaLoader-0:1.57-527.fc45 100% | 288.2 KiB/s | 25.6 KiB | 00m00s [32/85] perl-Scalar-List-Utils-5:1.70-5 100% | 485.0 KiB/s | 73.7 KiB | 00m00s [33/85] perl-vars-0:1.05-527.fc45.noarc 100% | 142.3 KiB/s | 12.7 KiB | 00m00s [34/85] mpdecimal-0:4.0.1-4.fc45.aarch6 100% | 604.0 KiB/s | 95.4 KiB | 00m00s [35/85] perl-Encode-4:3.24-527.fc45.aar 100% | 1.2 MiB/s | 1.0 MiB | 00m01s [36/85] python-pip-wheel-0:26.2.1-1.fc4 100% | 1.1 MiB/s | 1.2 MiB | 00m01s [37/85] libedit-0:3.1-60.20260512cvs.fc 100% | 673.3 KiB/s | 106.4 KiB | 00m00s [38/85] tzdata-0:2026c-2.fc46.noarch 100% | 1.1 MiB/s | 712.1 KiB | 00m01s [39/85] perl-Pod-Perldoc-0:3.28.01-527. 100% | 553.5 KiB/s | 84.7 KiB | 00m00s [40/85] perl-podlators-1:6.1.1-1.fc46.n 100% | 870.7 KiB/s | 132.4 KiB | 00m00s [41/85] openssh-0:10.5p1-1.fc46.aarch64 100% | 1.0 MiB/s | 371.4 KiB | 00m00s [42/85] perl-mro-0:1.30-527.fc45.aarch6 100% | 321.5 KiB/s | 28.9 KiB | 00m00s [43/85] perl-overloading-0:0.03-527.fc4 100% | 145.7 KiB/s | 12.5 KiB | 00m00s [44/85] perl-File-stat-0:1.15-527.fc45. 100% | 193.1 KiB/s | 17.2 KiB | 00m00s [45/85] perl-SelectSaver-0:1.03-527.fc4 100% | 130.4 KiB/s | 11.3 KiB | 00m00s [46/85] perl-Socket-4:2.043-1.fc46.aarc 100% | 622.9 KiB/s | 55.4 KiB | 00m00s [47/85] perl-locale-0:1.13-527.fc45.noa 100% | 153.3 KiB/s | 13.2 KiB | 00m00s [48/85] perl-Getopt-Std-0:1.15-527.fc45 100% | 172.6 KiB/s | 15.4 KiB | 00m00s [49/85] perl-MIME-Base64-0:3.16-527.fc4 100% | 346.5 KiB/s | 29.8 KiB | 00m00s [50/85] perl-parent-1:0.244-527.fc45.no 100% | 171.3 KiB/s | 14.7 KiB | 00m00s [51/85] perl-Storable-1:3.41-527.fc45.a 100% | 605.9 KiB/s | 95.7 KiB | 00m00s [52/85] perl-File-Temp-1:0.231.200-527. 100% | 658.6 KiB/s | 59.3 KiB | 00m00s [53/85] perl-HTTP-Tiny-0:0.096-528.fc45 100% | 655.7 KiB/s | 58.4 KiB | 00m00s [54/85] perl-Pod-Simple-1:3.48-527.fc45 100% | 982.5 KiB/s | 222.0 KiB | 00m00s [55/85] perl-Term-ANSIColor-0:5.01-527. 100% | 531.8 KiB/s | 47.3 KiB | 00m00s [56/85] perl-Term-Cap-0:1.18-527.fc45.n 100% | 244.1 KiB/s | 21.7 KiB | 00m00s [57/85] perl-Class-Struct-0:0.68-527.fc 100% | 244.5 KiB/s | 21.8 KiB | 00m00s [58/85] perl-File-Path-0:2.18-527.fc45. 100% | 391.4 KiB/s | 34.8 KiB | 00m00s [59/85] groff-base-0:1.24.1-2.fc45.aarc 100% | 1.1 MiB/s | 1.2 MiB | 00m01s [60/85] perl-IO-Socket-SSL-0:2.099-2.fc 100% | 800.6 KiB/s | 236.2 KiB | 00m00s [61/85] perl-Time-HiRes-4:1.9780-527.fc 100% | 635.6 KiB/s | 57.2 KiB | 00m00s [62/85] perl-Time-Local-2:1.350-527.fc4 100% | 384.6 KiB/s | 34.2 KiB | 00m00s [63/85] perl-Pod-Escapes-1:1.07-527.fc4 100% | 219.7 KiB/s | 19.6 KiB | 00m00s [64/85] perl-Net-SSLeay-0:1.96-5.fc45.a 100% | 1.1 MiB/s | 378.8 KiB | 00m00s [65/85] perl-Text-Tabs+Wrap-0:2024.001- 100% | 242.1 KiB/s | 21.5 KiB | 00m00s [66/85] perl-if-0:0.61.000-527.fc45.noa 100% | 159.1 KiB/s | 13.7 KiB | 00m00s [67/85] perl-IO-Socket-IP-0:0.44-527.fc 100% | 488.7 KiB/s | 42.0 KiB | 00m00s [68/85] perl-URI-0:5.37-1.fc46.noarch 100% | 993.4 KiB/s | 151.0 KiB | 00m00s [69/85] perl-AutoLoader-0:5.74-527.fc45 100% | 243.4 KiB/s | 20.9 KiB | 00m00s [70/85] perl-Data-Dumper-0:2.192-528.fc 100% | 639.5 KiB/s | 55.0 KiB | 00m00s [71/85] ncurses-0:6.6-3.fc45.aarch64 100% | 992.5 KiB/s | 428.8 KiB | 00m00s [72/85] perl-Unicode-Normalize-0:1.32-5 100% | 838.5 KiB/s | 72.1 KiB | 00m00s [73/85] perl-MIME-Base32-0:1.303-26.fc4 100% | 229.8 KiB/s | 20.4 KiB | 00m00s [74/85] perl-libnet-0:3.15-528.fc45.noa 100% | 812.2 KiB/s | 128.3 KiB | 00m00s [75/85] perl-B-0:1.92-527.fc45.aarch64 100% | 835.3 KiB/s | 182.1 KiB | 00m00s [76/85] perl-Digest-MD5-0:2.59-527.fc45 100% | 398.7 KiB/s | 35.5 KiB | 00m00s [77/85] perl-FileHandle-0:2.05-527.fc45 100% | 176.6 KiB/s | 15.2 KiB | 00m00s [78/85] perl-Digest-0:1.20-527.fc45.noa 100% | 278.3 KiB/s | 24.8 KiB | 00m00s [79/85] pyproject-rpm-macros-0:1.23.2-1 100% | 616.3 KiB/s | 54.8 KiB | 00m00s [80/85] python-rpm-macros-0:3.15-2.fc45 100% | 222.1 KiB/s | 19.8 KiB | 00m00s [81/85] python3-rpm-generators-0:14-35. 100% | 323.9 KiB/s | 28.8 KiB | 00m00s [82/85] python3-rpm-macros-0:3.15-2.fc4 100% | 137.4 KiB/s | 12.2 KiB | 00m00s [83/85] python3-packaging-0:26.3-1.fc46 100% | 995.2 KiB/s | 293.6 KiB | 00m00s [84/85] python3-setuptools-0:84.0.0-1.f 100% | 1.2 MiB/s | 1.7 MiB | 00m01s [85/85] python3-libs-0:3.15.0~rc2-1.fc4 100% | 1.2 MiB/s | 10.9 MiB | 00m09s -------------------------------------------------------------------------------- [85/85] Total 100% | 2.7 MiB/s | 34.2 MiB | 00m13s Running transaction [ 1/87] Verify package files 100% | 732.0 B/s | 85.0 B | 00m00s [ 2/87] Prepare transaction 100% | 1.2 KiB/s | 85.0 B | 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Building target platforms: aarch64 Building for target aarch64 warning: The %py3_build macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ warning: The %py3_install macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm RPM build warnings: The %py3_build macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ The %py3_install macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ Updating and loading repositories: fedora 100% | 109.2 KiB/s | 8.4 KiB | 00m00s Copr repository 100% | 89.4 KiB/s | 2.1 KiB | 00m00s Repositories loaded. Package "git-2.55.0-2.fc45.aarch64" is already installed. Package "python3-devel-3.15.0~rc2-1.fc46.aarch64" is already installed. Package "python3-setuptools-84.0.0-1.fc46.noarch" is already installed. Nothing to do. Finish: build setup for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Start: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Building target platforms: aarch64 Building for target aarch64 warning: The %py3_build macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ warning: The %py3_install macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ setting SOURCE_DATE_EPOCH=1654300800 Executing(mkbuilddir): /bin/sh -e /var/tmp/rpm-tmp.GCJ3DV Creating(rpmbuild.env): /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/rpmbuild.env RPM_SOURCE_DIR="/builddir/build/SOURCES" RPM_BUILD_DIR="/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build" RPM_OPT_FLAGS="-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer" RPM_LD_FLAGS="-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes " RPM_ARCH="aarch64" RPM_OS="linux" RPM_BUILD_NCPUS="4" RPM_SPECPARTS_DIR="/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/SPECPARTS" export RPM_SOURCE_DIR RPM_BUILD_DIR RPM_OPT_FLAGS RPM_ARCH RPM_OS RPM_BUILD_NCPUS RPM_SPECPARTS_DIR RPM_LD_FLAGS RPM_DOC_DIR="/usr/share/doc" export RPM_DOC_DIR RPM_PACKAGE_NAME="litex-pythondata-cpu-cva6" RPM_PACKAGE_VERSION="2026.04" RPM_PACKAGE_RELEASE="20260917.0.git2b51ea6a.fc46" export RPM_PACKAGE_NAME RPM_PACKAGE_VERSION RPM_PACKAGE_RELEASE LANG=C.UTF-8 export LANG unset CDPATH DISPLAY ||: unset DEBUGINFOD_URLS ||: unset RPM_CONFIG_DIR ||: RPM_BUILD_ROOT="/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT" export RPM_BUILD_ROOT PKG_CONFIG_PATH="${PKG_CONFIG_PATH}:/usr/lib64/pkgconfig:/usr/share/pkgconfig" export PKG_CONFIG_PATH CONFIG_SITE=${CONFIG_SITE:-NONE} export CONFIG_SITE Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.lEbIGa + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + rm -rf litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p litex-pythondata-cpu-cva6 + cd litex-pythondata-cpu-cva6 + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git . Cloning into '.'... + git fetch --depth 1 origin 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 From https://github.com/litex-hub/pythondata-cpu-cva6 * branch 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 -> FETCH_HEAD + git reset --hard 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 HEAD is now at 2b51ea6 Merge pull request #2 from shenki/update-cva6-c4c412a9 + git log --format=fuller commit 2b51ea6a4778d4ea62bc4feb68afe5a64b7bcfd0 Author: enjoy-digital AuthorDate: Thu Sep 17 09:27:25 2026 +0200 Commit: GitHub CommitDate: Thu Sep 17 09:27:25 2026 +0200 Merge pull request #2 from shenki/update-cva6-c4c412a9 Update cva6 c4c412a9 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.DBAfqg + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' /usr/lib/python3.15/site-packages/setuptools/dist.py:765: SetuptoolsDeprecationWarning: License classifiers are deprecated. !! ******************************************************************************** Please consider removing the following classifiers in favor of a SPDX license expression: License :: OSI Approved :: Apache Software License See https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license for details. ******************************************************************************** !! self._finalize_license_expression() running build running build_py creating build/lib/pythondata_cpu_cva6 copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6 running egg_info creating pythondata_cpu_cva6.egg-info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a60x.spike' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.csr' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.isa' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.cv32a65x.spike' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.linker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.scripts.libs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.templates' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config.gen_from_riscv_config.updaters.cv32a65x' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.config' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.config' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.config' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.config' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.config' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cva6_mmu' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include.deprecated_packages' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.ip' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.altera.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.axi_dw_adapter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_dpti_clk.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.DPTI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Decapsuler' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.cva6_iti' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.ITI.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.Pictures' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.instr_tracing.SW.Receiver_DPTI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.spyglass' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.spyglass' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.spyglass' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.spyglass' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.spyglass' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.spyglass.sg_setup.cva6' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.tutorials' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.tutorials' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.tutorials' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.tutorials' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.tutorials' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util.sanitize' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util.sanitize' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util.sanitize' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util.sanitize' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util.sanitize' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.util.sanitize.systemverilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.patches' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.patches' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.patches' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.patches' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.patches' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.patches.riscv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.vendor.riscv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.vendor.riscv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.vendor.riscv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.vendor.riscv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.vendor.riscv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.bsp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.bsp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.bsp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.bsp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.bsp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.figures' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.Protocols.wavedrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.AXI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.CVXIF' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FENCEI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.FRONTEND' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.ISA_RV32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.MMU_SV32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.PMP' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_access' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.csr_embedded_access' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.VerifPlans.traps' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.coverage_status' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.docs.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.docs.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.docs.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.docs.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.docs.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.cvxif_vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.reg' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.cov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.uvma_interrupt.seq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.env.uvme.vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.regress' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.regress' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.regress' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.regress' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.regress' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.sim' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.sim' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.sim' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.sim' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.sim' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.core.tb_components' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tb.uvmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_failing_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.CSR.csr_access_yaml' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.ITI' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.Zcmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.coremark' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.csr_embedded' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.cv_xif' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.debug_test.bsp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.dhrystone' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.env' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.hello_world' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.interrupt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.isacov' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.issues' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.return0' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.spike_params' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.sv39' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.trigger_tests' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.custom.zcmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.15/site-packages/setuptools/command/build_py.py:215: _Warning: Package 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.verif.tests.uvmt.vseq' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.readthedocs.yaml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ACKNOWLEDGEMENTS.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CITATION.cff -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/RESOURCES.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/SECURITY.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/verilator_config.vlt -> build/lib/pythondata_cpu_cva6/system_verilog creating build/lib/pythondata_cpu_cva6/system_verilog/.github copying pythondata_cpu_cva6/system_verilog/.github/dependabot.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github copying pythondata_cpu_cva6/system_verilog/.github/pull_request_template.md -> build/lib/pythondata_cpu_cva6/system_verilog/.github creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/1-bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/2-task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/3-other.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env copying pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env/action.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts copying pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static creating build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates copying pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates/index.html -> build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/bender-up-to-date.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/dashboard-done.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier1.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier2.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-tier-dashboard.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/stale.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/verible.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/expected_synth.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example creating build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-prereq.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_1rw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_wbyteenable_1rw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram_cache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper_cache_techno.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.rst -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/isa_template.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/spike.mako -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates creating build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config copying pythondata_cpu_cva6/system_verilog/config/riscv-config/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config copying pythondata_cpu_cva6/system_verilog/config/riscv-config/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/custom_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/isa_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/platform_gen.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/custom_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/isa_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/platform_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec creating build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/custom_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/debug_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/isa_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/platform_spec.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec creating build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cva6 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cva6_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/acc_dispatcher.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/aes.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_fpga.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_accel_first_pass_decoder_stub.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_fifo_v3.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_rvfi.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6_rvfi_probes.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_compressed_if_driver.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_issue_register_commit_if_driver.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/macro_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/raw_checker.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/trigger_module.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/zcmt_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_if_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem creating build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_shared_tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work/work.rlx -> build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/compressed_instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/copro_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht2lvl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend creating build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/aes_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/build_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a65x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdcv_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/dummy_l15_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/rvfi_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/triggers_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_data_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/altera.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/io_standard_constraints.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip_files.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/loc_constraints.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/search_paths.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/settings.csv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/u-boot-spl-dtb.hex -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints/SDC1.sdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/emif_cal.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/hps_cva6_altera.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iddr_intel.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/interconnect.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/io_pll.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iobuf.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/oddr_intel.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/test_mm_ccb_0.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/vJTAG.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag_tap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/nexys_video.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/agilex7.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/nexys_video.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_errno.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_io.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_time.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/cache.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dma-mapping.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dw_mmc.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dwmmc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/memalign.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/mmc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_nexys_video.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/Digilent.licence -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_types.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/EEPROM.PNG -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Gen2_wired.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_dark.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_light.svg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/decoded_trace.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys-2.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/receiver.png -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src copying pythondata_cpu_cva6/system_verilog/corev_apu/src/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_gate_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs creating build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/AXI_Interface.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Cache_Control.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Performance_Counters.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV64A6_Control_Status_Registers.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVA6_user_guide.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVX_Interface_Coprocessor.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Compiler_Command_Lines.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Core_Integration.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Custom_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Interfaces.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Introduction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMA.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMP.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Parameters_Configuration.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Programmer_View.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32A.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32C.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32I.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32M.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZba.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Trigger_Module.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/rtype_format.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/user_cfg_doc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user creating build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements copying pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/cva6_requirements_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/MMU.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/LZC.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/RR.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/apb_uart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi2mem.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi_adapter.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bht2lvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bootrom.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/clint.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_hit.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dm_top_slave.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/in_out_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_control_flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_major_blocks.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/nested_translation.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic_top.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plru_tree_indexing.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw_s.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_idle.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_iptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_mis_sup.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_nlvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_flowchart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_state_diagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/replacement_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_set.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/test_harness.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/timer.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/update_tree.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/design.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/README.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_environment.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_process.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/frontendsb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/funccovresults.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/hvp.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image2.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image3.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image4.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image5.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image6.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image7.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/interrupt_uvm_agent.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparam.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparamgates.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/toggleresults.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/verif-strategy.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/README.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-edited.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures creating build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_apu.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_testharness.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/apb_uart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/ariane.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi2mem.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi_adapter.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/bootrom.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/clint.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dm_top_slave.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic_top.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/sram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/test_harness.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/timer.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/priv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/unpriv.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/theme_overrides.css -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/common copying pythondata_cpu_cva6/system_verilog/docs/common/config_define.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/common creating build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax creating build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr_list.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design copying pythondata_cpu_cva6/system_verilog/docs/design/build.mk -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI_Interface.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CSRs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVXIF.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/architecture.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_caches.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_commit_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_controller.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_csr_regfile.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_execute.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_frontend.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_id_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_issue_stage.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/design.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/functionality.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/glossary.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/instructions.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/intro.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/mmu.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/subsystem.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/traps.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/LZC.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/RR.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ZoominFrontend.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/caches.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_hit.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ex_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/id_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/in_out_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/issue_stage_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/load_store_unit_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_control_flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_major_blocks.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mult_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/plru_tree_indexing.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw_s.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_idle.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_iptw.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_mis_sup.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_nlvl.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_1.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_flowchart.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_state_diagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/replacement_entry.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/schema_fsm_load_control.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_asid.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_x0.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_in_out.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_set.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/update_tree.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/build.mk -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/a-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/bfloat16.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/calling-convention.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/cmo.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/colophon.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/counters.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/d-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/f-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/hypervisor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/indirect-csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/machine.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/mm-formal.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-cfi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-csrs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-preface.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/q-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-privileged.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-unprivileged.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rnmi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv-32-64g.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv128.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv32e.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv64.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/scalar-crypto.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcdeleg.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcntrpmf.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smctr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smdbltrp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smepmp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smstateen.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sscofpmf.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ssdbltrp.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sstc.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/supervisor.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/unpriv-cfi.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/v-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-crypto.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-examples.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zabha.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zacas.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zawrs.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfa.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfh.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfinx.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zicond.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zifencei.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintntl.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintpause.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zimop.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zpm.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ztso-st-ext.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images/ohg_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes copying pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes/riscv-spec.yml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes creating build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts copying pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/isa.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/model.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model copying pythondata_cpu_cva6/system_verilog/perf-model/profile.py -> build/lib/pythondata_cpu_cva6/system_verilog/perf-model creating build/lib/pythondata_cpu_cva6/system_verilog/spyglass copying pythondata_cpu_cva6/system_verilog/spyglass/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass copying pythondata_cpu_cva6/system_verilog/spyglass/reference_summary.rpt -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass creating build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6.sgdc -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_waiver.awl -> build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 creating build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/asic.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/fpga.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials copying pythondata_cpu_cva6/system_verilog/tutorials/running_sim.md -> build/lib/pythondata_cpu_cva6/system_verilog/tutorials creating build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/flist_flattener.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/init_gate.do -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/user_config.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/vendor.py -> build/lib/pythondata_cpu_cva6/system_verilog/util copying pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util creating build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize copying pythondata_cpu_cva6/system_verilog/util/sanitize/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize copying pythondata_cpu_cva6/system_verilog/util/sanitize/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize creating build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog/xlen_misuse.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog creating build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/gcc-cva6-tune.patch -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/get-toolchain.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-13.1.0-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-14.1.0-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-master-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-18-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-master-baremetal.sh -> build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.lock.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor copying pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.vendor.hjson -> build/lib/pythondata_cpu_cva6/system_verilog/vendor creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0001-enable-implied-B-ext.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0002-add-mstatus-UBE-bit.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/VERSION -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/typedef.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_atop_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_burst_splitter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_dst.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_src.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cut.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_delayer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_converter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_err_slv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_prepend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_remap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_serialize.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_isolate.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_iw_converter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_regs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_modify_address.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_multicut.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_serializer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_sim_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/assertions.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/registers.svh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/addr_decode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/binary_to_gray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cc_onehot.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_2phase.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/clk_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/delta_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_decode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_encode.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_detect.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/exp_backoff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fall_through_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fifo_v3.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/gray_to_binary.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/id_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lzc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/max_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/mv_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/plru_tree.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/popcount.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/serial_deglitch.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/shift_reg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_delay.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_demux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fifo.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_filter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_join.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_mux.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_omega_net.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_register.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_to_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_xbar.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sub_per_hash.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync_wedge.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/unread.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider_counter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_LFSR_8bit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo_adv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/prioarbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync_wedge.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Testbench.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run_gui.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/waves.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/expresp.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/stim.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include/assertions.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules/ClkRstGen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiBramLogger.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiToAxiLitePc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramDwc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramLogger.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramPort.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/TdpBramArray.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramDwc.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramPort.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/synthesize.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src/Top.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/synthesize.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_pwr_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_memory.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_rom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pad_functional.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/pad_functional_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_sram_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CONTRIBUTING.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/MANIFEST.in -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/README.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/CONTRIBUTING.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/code-doc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/new-extensions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/overview.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/quickstart.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/revisions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/riscv_config-flow.png -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/schema_custom.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/yaml-specs.rst -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/Tall_2.png -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/custom.css -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/theme_overrides.css -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/breadcrumbs.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/layout.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/versions.html -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform_checked.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_debug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_platform.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas creating build/lib/pythondata_cpu_cva6/system_verilog/verif copying pythondata_cpu_cva6/system_verilog/verif/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif copying pythondata_cpu_cva6/system_verilog/verif/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif creating build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/crt0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/useful_sites.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp copying pythondata_cpu_cva6/system_verilog/verif/bsp/vectors.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs copying pythondata_cpu_cva6/system_verilog/verif/docs/UVM_verif_env.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs copying pythondata_cpu_cva6/system_verilog/verif/docs/verif-approvals.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/interrupt-verification.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures/interrupt-ack-uvm.svg -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom copying pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom/interrupt-ack-uvm.wave -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/cvxif_VP.xlsx -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/install-prerequisites.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/custom_instruction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP016.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP017.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP018.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP019.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP020.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP021.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP022.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP012.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP013.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP014.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP015.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP016.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP017.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP018.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP019.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP021.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP022.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP023.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP024.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP025.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP031.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP004.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/cva6_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_AXI.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_CVXIF.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FENCEI.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FRONTEND.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_PMP.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_traps.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP000.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP002.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP003.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP005.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP006.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP007.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP008.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP009.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP010.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP011.yml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/runme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status copying pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status/isacov_status.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status creating build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images copying pythondata_cpu_cva6/system_verilog/verif/docs/images/CVA6_env.drawio.drawio.png -> build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6-files.f -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_asm_program_gen.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_defines.svh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_ecall_instr_stream.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_illegal_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_base_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_config.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_tb_top.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_hazard_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_sequence.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_test_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_load_store_instr_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_reg_hazard_stream.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_signature_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_unsupported_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/simulator.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/cvxif_custom_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcmp_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zicond_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32x_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcmp_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zicond_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv64zcb_instr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/user_define.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/x_extn_user_define.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_core_cntrl_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_env.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_prd.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_sb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_vsqr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvml_mem_vp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_ext_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_config_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_cov_model.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cvxif_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_exception_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_illegal_instr_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_interrupt_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_isa_covg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instruction.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_block.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_file.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_predictor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_agent.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cntxt.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_drv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_sqr.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_base_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq_item.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq creating build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/benchmark.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/coremark.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cv32a6_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cv64a6_imafdc_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/cvxif_verif_regression.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/debug_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone_smoke.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-csr-embedded-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-xif-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-interrupt-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-arch-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-csr-access-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-mmu-sv32-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/hwconfig_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-arch-test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/iss-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/issue-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/iti_test.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/linux.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/pmp_cv32a65x_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-compliance.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-dv.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests-env.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-gen_tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a65x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a6_imac_sv32.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a60x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a65x.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/veri-testharness-pk-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress copying pythondata_cpu_cva6/system_verilog/verif/regress/verilator-v5.patch -> build/lib/pythondata_cpu_cva6/system_verilog/verif/regress creating build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cov-exclude-mod.lst -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6-simulator.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.hvp -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6_base_testlist.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_fsdb.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_vpd.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/init_uvm.do -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/setup-env.sh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim copying pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/sim creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/Flist.cva6_tb -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/custom_uvm_macros.svh -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/cva6_tb_verilator.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_core_cntrl_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_reference_model_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core copying pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/cva6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components copying pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components/axi_master_connect.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/cva6_tb_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_assert.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_switch_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6.flist -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_axi_assert.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_constants.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_macros.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tdefs.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_default_inputs_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_csr_embedded.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_custom.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_cvxif.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_hwconfig.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_interrupt.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_isacov.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_issues.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_pmp-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-rv32ima.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a6_imac_sv32.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a65x-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-p.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-v.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests copying pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_marchid_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mstatus_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mvendorid_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr0_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr1_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr2_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr3_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr4_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr5_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr6_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr7_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg0_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg1_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_sstatus_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/readme.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_ro_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cva6_mscratch_csr_access.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/iti_asm.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mva01s_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mvsa01_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popret_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popretz_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_push_pop_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/readme.txt -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/riscv_test.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/util.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/crt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_32.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_64.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/util.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/LICENSE.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_list_join.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_matrix.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_util.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark_main.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_counters_overflow.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcs_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcsi_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrst_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fields_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fullrandom_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_ro_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_unmapped_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrwi_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_add_nop.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_exc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_full.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_illegal.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_issexc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_macros.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_multi.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_nopexc.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_rs3.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_s_mode.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_u_mode.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debug_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger_exception.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/single_step.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/test.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/trigger_code.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/bsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/corev_uvmt.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/crt0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/handlers.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link_corev-dv.ld -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/syscalls.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/vectors.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone_main.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/custom_test_template.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/hello_world.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt/jump_to_zero.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/branch_to_zero.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/illegal_isa.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/isa_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/jump_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_reg_hazard.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_store_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/seq_hazard.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/decreasing_entries_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/defined_matches_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/double_entries_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/exact_csrr_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/granularity_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_napot_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_tor_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_napot_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_tor_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0/return0.c -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params/misa_csr_we.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/macros.h -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_misaligned_superpage.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_nonleaf_pte.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_01.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_02.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_03.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_04.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_01.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_02.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_03.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_04.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_access.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_asid.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_mode_set.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_0.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_1.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39/noncanonical.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/etrigger_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_break_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_debug_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/itrigger_test.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/mcontrol6_tests.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_csrs_access.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_main.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long_ret.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_ret.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt_long.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/jvt_csr.S -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests creating build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq copying pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv -> build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq + RPM_EC=0 ++ jobs -p + exit 0 Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.Y2PC9L + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + '[' /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT '!=' / ']' + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT ++ dirname /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT + mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + mkdir /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -mbranch-protection=standard -fasynchronous-unwind-tables -fstack-clash-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-hardened-ld-errors -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT --prefix /usr /usr/lib/python3.15/site-packages/setuptools/dist.py:765: SetuptoolsDeprecationWarning: License classifiers are deprecated. !! ******************************************************************************** Please consider removing the following classifiers in favor of a SPDX license expression: License :: OSI Approved :: Apache Software License See https://packaging.python.org/en/latest/guides/writing-pyproject-toml/#license for details. ******************************************************************************** !! self._finalize_license_expression() running install /usr/lib/python3.15/site-packages/setuptools/_distutils/cmd.py:90: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. This deprecation is overdue, please update your project and remove deprecated calls to avoid build errors in the future. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq/uvmt_cva6_vseq_lib.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/vseq creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests/uvmt_cva6_firmware_test.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/compliance-tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_test_cfg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests/uvmt_cva6_base_test.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/uvmt/base-tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/jvt_csr.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt_long.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jt.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_ret.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long_ret.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt_long.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt/cm_jalt.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/zcmt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_main.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/trigger_csrs_access.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/mcontrol6_tests.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/itrigger_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_debug_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/icount_break_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests/etrigger_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/trigger_tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39/noncanonical.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv39 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_set_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_sum_clear_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_mode_set.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_asid.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_satp_access.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_reserved_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_04.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_03.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_02.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_rwx_access_smode_01.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_unset_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_04.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_03.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_02.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_u_bit_set_01.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pte_pmp_check_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_pmp_check_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_nonleaf_pte.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_set_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mxr_clear_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_mstatus_tvm_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_misaligned_superpage.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_invalid_pte_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_dirty_bit_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_bare_mode_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_1.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/vm_access_bit_level_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32/macros.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/sv32 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params/misa_csr_we.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/spike_params creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0/return0.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/return0 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_tor_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/lsu_napot_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_tor_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/locked_outside_napot_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/granularity_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/exact_csrr_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/double_entries_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/defined_matches_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp/decreasing_entries_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/pmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv64.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues/compressed-fpreg-commits-rv32.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/issues creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/seq_hazard.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_store_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/load_reg_hazard.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/jump_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/isa_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/illegal_isa.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov/branch_to_zero.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/isacov creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt/jump_to_zero.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/interrupt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/hello_world.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world/custom_test_template.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/hello_world creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/env creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone_main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone/dhrystone.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/dhrystone creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/vectors.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/syscalls.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link_corev-dv.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/handlers.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/crt0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/corev_uvmt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/bsp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/trigger_code.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/test.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/single_step.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/handlers.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger_exception.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debugger.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test/debug_test.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/debug_test creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_u_mode.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_s_mode.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_rs3.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_nopexc.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_multi.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_macros.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_issexc.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_illegal.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_full.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_exc.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif/cvxif_add_nop.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/cv_xif creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrwi_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_unmapped_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_ro_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fullrandom_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrw_fields_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrrst_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcsi_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csrcs_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded/csr_counters_overflow.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/csr_embedded creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark_main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/coremark.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_util.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_state.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_portme.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_matrix.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/core_list_join.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark/LICENSE.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/coremark creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/util.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/syscalls.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_64.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/cva6_csr_access_test_32.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common/crt.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/util.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/syscalls.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/riscv_test.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/readme.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_push_pop_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popretz_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_popret_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mvsa01_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp/cm_mva01s_test.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/Zcmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/iti_asm.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cva6_mscratch_csr_access.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_s_rw_csr_test.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_rw_csr_test.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/cv32a6_m_ro_csr_test.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_yaml creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_s_rw_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstreth_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_minstret_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycleh_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_mcycle_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_rw_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_m_ro_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_instret_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/riscv_cycle_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests/readme.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_sstatus_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg1_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpcfg0_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr7_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr6_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr5_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr4_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr3_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr2_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr1_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_pmpaddr0_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mvendorid_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_mstatus_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/riscv_marchid_csr_test_0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/CSR/csr_access_failing_tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a65x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_sdtrig-tests-cv32a60x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-v.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-rv32ima-p.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-v.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv64a6_imafdc_sv39-p.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-v.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a6_imac_sv0-p.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a65x-p.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-v.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-tests-cv32a60x-p.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-mmu-sv32-arch-test-cv32a6_imac_sv32.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a65x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-csr-access-test-cv32a60x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-rv32ima.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv64a6_imafdc_sv39.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a6_imac_sv0.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a65x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-compliance-cv32a60x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv64a6_imafdc_sv39.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a65x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_riscv-arch-test-cv32a60x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_pmp-cv32a65x.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_issues.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_isacov.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_interrupt.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_hwconfig.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_cvxif.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_custom.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tests/testlist_csr_embedded.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_default_inputs_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tdefs.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb_ifs.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_macros.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_dut_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_constants.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6_axi_assert.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_cva6.flist -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_switch_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/uvmt_axi_assert.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt/cva6_tb_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/uvmt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components/axi_master_connect.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/tb_components creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/cva6.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_scoreboard_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvmc_rvfi_reference_model_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_rvfi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_cva6pkg_utils.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/uvma_core_cntrl_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/cva6_tb_verilator.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/custom_uvm_macros.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core copying build/lib/pythondata_cpu_cva6/system_verilog/verif/tb/core/Flist.cva6_tb -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/setup-env.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_uvm.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_vpd.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/init_run_uvm_fsdb.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_base_testlist.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.hvp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cva6-simulator.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/cov-exclude-mod.lst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim copying build/lib/pythondata_cpu_cva6/system_verilog/verif/sim/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/verilator-v5.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/veri-testharness-pk-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a65x.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/triggers-tests-cv32a60x.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv64a6_imafdc_sv39.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a6_imac_sv32.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-tests-cv32a65x.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/smoke-gen_tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-tests-env.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-dv.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/riscv-compliance.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/pmp_cv32a65x_tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/linux.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/iti_test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/issue-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/iss-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-arch-test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/hwconfig_tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-mmu-sv32-test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-csr-access-test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-arch-test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-interrupt-test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-xif-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-generated-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dv-csr-embedded-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone_smoke.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/dhrystone.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/debug_test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cvxif_verif_regression.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cv64a6_imafdc_tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/cv32a6_tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/coremark.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/benchmark.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress copying build/lib/pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_vseq_lib.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_reset_vseq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_cva6_base_vseq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq/uvme_axi_fw_preload_seq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/vseq creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq_item.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_seq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq/uvma_interrupt_base_seq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/seq creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov/uvma_interrupt_cov_model.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_tdefs.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_sqr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_pkg.flist -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_mon.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_macros.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_if.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_drv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_constants.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cntxt.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_cfg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/uvma_interrupt_agent.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_interrupt creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_predictor.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_file.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_block.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg/cva6_csr_reg_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/reg creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_vseq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/uvme_cvxif_base_vseq.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instructions_cvxif_1_0_0.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq/custom_instruction.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cvxif_vseq creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_isa_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_interrupt_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_illegal_instr_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_exception_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cvxif_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_cov_model.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_cva6_config_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_ext_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov/uvme_axi_covg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme/cov copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvml_mem_vp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_vsqr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_tdefs.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_sb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_prd.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_pkg.flist -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_macros.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_env.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_core_cntrl_if.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_constants.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cntxt.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvme_cva6_cfg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_drv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_cntxt.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/uvme/uvma_cva6_core_cntrl_agent.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/uvme creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/x_extn_user_define.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension/user_define.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/user_extension creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc/riscv_core_setting.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64imafdc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc/riscv_core_setting.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv64gc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb/riscv_core_setting.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imcb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac/riscv_core_setting.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/target/rv32imac creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv64zcb_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zicond_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcmp_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32zcb_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/rv32x_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zicond_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcmp_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_zcb_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/riscv_custom_instr_enum.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom/cvxif_custom_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/custom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/simulator.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_unsupported_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_signature_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_reg_hazard_stream.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_load_store_instr_lib.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_test_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_sequence.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_hazard_test.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_tb_top.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_gen_config.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_instr_base_test.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_illegal_instr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_ecall_instr_stream.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_defines.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6_asm_program_gen.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/cva6-files.f -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv copying build/lib/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/env/corev-dv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/images copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/images/CVA6_env.drawio.drawio.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/images creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status/isacov_status.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/coverage_status creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP011.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP010.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP009.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP008.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP007.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/traps creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_traps.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-embedded-access.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_csr-access.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_PMP.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_MMU_SV32.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_ISA_RV32.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FRONTEND.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_FENCEI.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_CVXIF.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/dvplan_AXI.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/images creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/dvplan_csr-embedded-access.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/cva6_embedded_csr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_embedded_access creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/cva6_csr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP004.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/csr_access creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan_features.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/pmp_verif_plan.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP031.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP025.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP024.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP023.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP022.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP021.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP019.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP018.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP017.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP016.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP015.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP014.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP013.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP012.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP011.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP010.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP004.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/PMP creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP022.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP021.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP020.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP019.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP018.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP017.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP016.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP015.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP014.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP013.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP012.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP011.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP010.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP009.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP008.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP007.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP004.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32/RISCV_Instructions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/ISA_RV32 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP010.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP009.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP008.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP007.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP004.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FRONTEND creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP004.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/FENCEI creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/custom_instruction.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP003.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP002.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP001.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF/VP_IP000.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/CVXIF creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/runme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP009.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP008.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP007.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP006.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI/VP_IP005.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/AXI copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/make.bat -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/install-prerequisites.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/cvxif_VP.xlsx -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/VPTOOL-VerifPlan-HOWTO.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom/interrupt-ack-uvm.wave -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/wavedrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures/interrupt-ack-uvm.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/figures copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/interrupt-verification.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/Protocols copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/verif-approvals.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs copying build/lib/pythondata_cpu_cva6/system_verilog/verif/docs/UVM_verif_env.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/vectors.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/useful_sites.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/syscalls.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/handlers.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/crt0.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/bsp/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/bsp copying build/lib/pythondata_cpu_cva6/system_verilog/verif/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif copying build/lib/pythondata_cpu_cva6/system_verilog/verif/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_platform.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_isa.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_debug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas/schema_custom.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemas copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform_checked.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_platform.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa_checked.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_isa.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_debug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv64i_custom.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform_checked.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_platform.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa_checked.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_isa.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_debug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples/rv32i_custom.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/examples creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/versions.html -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/layout.html -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates/breadcrumbs.html -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_templates creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/theme_overrides.css -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/custom.css -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static/Tall_2.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/_static copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/yaml-specs.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/schema_custom.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/riscv_config-flow.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/revisions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/quickstart.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/overview.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/new-extensions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/code-doc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/CONTRIBUTING.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/README.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/MANIFEST.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CONTRIBUTING.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_sram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl/tc_clk.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/rtl creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_sram_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/tc_clk_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga/pad_functional_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_pwr_cells.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clock_gating_async.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_clk_cells.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pulp_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/pad_functional.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_rom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/generic_memory.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_pwr_cells.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated/cluster_clk_cells.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src/tc_pwr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/tech_cells_generic creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/synthesize.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts/setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src/Top.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/synthesize.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts/setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramPort.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/BramDwc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/deps copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/synth/BramDwc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/TdpBramArray.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncTpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncThreePortRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncSpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam_ind_r_w.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/SyncDpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramPort.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramLogger.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/BramDwc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiToAxiLitePc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AxiBramLogger.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncThreePortRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl/AsyncDpRam.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/rtl creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules/ClkRstGen.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/modules creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include/assertions.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/include copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/stim.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors/expresp.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/vectors creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/waves.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run_gui.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Testbench.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/BramDwc copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/behav copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/fpga-support creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/sram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/rrarbiter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync_wedge.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/pulp_sync.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/prioarbiter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo_adv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_fifo.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/generic_LFSR_8bit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/find_first_one.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v2.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/fifo_v1.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider_counter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated/clock_divider.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/deprecated copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/unread.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync_wedge.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sync.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/sub_per_hash.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_xbar.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_to_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_register.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_omega_net.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_mux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_join.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork_dynamic.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fork.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_filter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_fifo.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_demux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_delay.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter_flushable.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/stream_arbiter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register_flushable.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/spill_register.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/shift_reg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/serial_deglitch.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen_bypass.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rstgen.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/rr_arb_tree.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/popcount.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/plru_tree.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/onehot_to_bin.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/mv_filter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/max_counter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lzc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_8bit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr_16bit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/lfsr.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_spill_register.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/isochronous_4phase_handshake.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/id_queue.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/gray_to_binary.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fifo_v3.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/fall_through_register.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/exp_backoff.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_tx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator_rx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_propagator.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/edge_detect.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_encode.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/ecc_decode.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/delta_counter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/counter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/clk_div.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cf_math_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_gray.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_fifo_2phase.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cdc_2phase.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cc_onehot.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/cb_filter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/binary_to_gray.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src/addr_decode.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/registers.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells/assertions.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/include/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/common_cells creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_lrsc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_atomics.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos_alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_riscv_amos.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src/axi_res_tbl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi_riscv_atomics creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_xbar.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_to_axi_lite.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_test.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_sim_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_serializer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_mux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_multicut.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_modify_address.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_xbar.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_axi.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_to_apb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_regs.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_mailbox.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_join.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_lite_demux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_join.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_iw_converter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_isolate.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_serialize.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_remap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_id_prepend.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_err_slv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_upsizer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_downsizer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_dw_converter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_demux.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_delayer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cut.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_src.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc_dst.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_cdc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_burst_splitter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src/axi_atop_filter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/typedef.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi/assign.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/include/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/VERSION -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform/axi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0005-add-csr-schema-for-mconfigptr.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0004-fix-mstatush-and-nonascii-chars.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0003-add-mtval-roconst0-schema.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0002-add-mstatus-UBE-bit.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config/0001-enable-implied-B-ext.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/riscv/riscv-config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells/00001-spyglass-no-multiple-assignement-same-block-padded_input.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/patches/pulp-platform/common_cells copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/riscv_riscv-config.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_tech_cells_generic.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_fpga-support.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_common_cells.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi_riscv_atomics.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.vendor.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor copying build/lib/pythondata_cpu_cva6/system_verilog/vendor/pulp-platform_axi.lock.hjson -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-master-baremetal.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/llvm-18-baremetal.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-master-baremetal.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-14.1.0-baremetal.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/gcc-13.1.0-baremetal.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/get-toolchain.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/gcc-cva6-tune.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder copying build/lib/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog/xlen_misuse.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize/systemverilog copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize copying build/lib/pythondata_cpu_cva6/system_verilog/util/sanitize/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/sanitize copying build/lib/pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/vendor.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/user_config.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/init_testharness.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/init_gate.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util copying build/lib/pythondata_cpu_cva6/system_verilog/util/CODEOWNERS -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/running_sim.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/fpga.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/tutorials copying build/lib/pythondata_cpu_cva6/system_verilog/tutorials/asic.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/tutorials creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_waiver.awl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6.sgdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6 copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/reference_summary.rpt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass copying build/lib/pythondata_cpu_cva6/system_verilog/spyglass/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/profile.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/model.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/isa.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model copying build/lib/pythondata_cpu_cva6/system_verilog/perf-model/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_wbyteenable_1rw_00000007_00000020_00000080_00000002.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/hpdcache_sram_1rw_00000006_0000001c_00000040_00000001.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes/riscv-spec.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/resources/themes creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images/ohg_logo.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ztso-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zpm.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zimop.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintpause.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zihintntl.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zifencei.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zicond.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfinx.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfh.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zfa.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zawrs.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zacas.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/zabha.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-examples.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/vector-crypto.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/v-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/unpriv-cfi.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/supervisor.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sstc.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/ssdbltrp.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/sscofpmf.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smstateen.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smepmp.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smdbltrp.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smctr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcntrpmf.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/smcdeleg.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/scalar-crypto.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv64.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv32e.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv128.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rv-32-64g.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/rnmi.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-unprivileged.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/riscv-privileged.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/q-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-preface.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-csrs.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/priv-cfi.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/mm-formal.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/machine.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/indirect-csr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/hypervisor.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/f-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/d-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/counters.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/colophon.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/cmo.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/calling-convention.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/bfloat16.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src/a-st-ext.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/src copying build/lib/pythondata_cpu_cva6/system_verilog/docs/riscv-isa/build.mk -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/riscv-isa creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/update_tree.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_set.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/shared_tlb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_x0.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_x0_asid.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_x0.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/sfence_vaddr_asid.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/schema_fsm_load_control.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/replacement_entry.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_state_diagram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_flowchart.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_pte_1.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_nlvl.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_mis_sup.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_iptw.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_idle.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw_s.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ptw_dptw.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/plru_tree_indexing.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mult_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_major_blocks.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/mmu_control_flow.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/load_store_unit_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/issue_stage_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/in_out_tlb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/id_stage_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/frontend_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ex_stage_modules.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_hit.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/cva6_tlb_entry.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/caches.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/bht.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ariane_overview.drawio.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/ZoominFrontend.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/RR.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/LZC.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images/CVA6_subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/traps.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/subsystem.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/mmu.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/intro.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/instructions.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/glossary.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/functionality.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/design.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_issue_stage.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_id_stage.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_frontend.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_execute.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_csr_regfile.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_controller.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_commit_stage.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/cva6_caches.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/architecture.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/Traps_Interrupts_Exceptions.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVX_Interface_Coprocessor.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CVXIF.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/CSRs.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI_Interface.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source/AXI.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/design-manual/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design/design-manual copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design/build.mk -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/design creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.xml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/cv32a60mx_csr.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr_list.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x/csr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.xml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax copying build/lib/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax/cva6_csr.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/csr-from-ip-xact/cv32a60ax creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/common copying build/lib/pythondata_cpu_cva6/system_verilog/docs/common/config_define.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/theme_overrides.css -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/unpriv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/priv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/07_cv32a60x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/unpriv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/priv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/06_cv64a6_mmu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/timer.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/test_harness.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/sram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic_top.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/plic.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/dm_top_slave.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/clint.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/bootrom.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi_adapter.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/axi2mem.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/ariane.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static/apb_uart.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_testharness.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu copying build/lib/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu/cva6_apu.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/05_cva6_apu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/refmodel-step-stages.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/overall-tandem-architecture.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario.wave -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-svg.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/interrupt-tandem-scenario-edited.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures/Spike-simulation-scope.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/figures copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/uvm-tandem-refman.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-user-guide.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/tandem-modifications-for-trl5.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/spike-tandem-refman.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem/README.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/tandem creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/verif-strategy.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/toggleresults.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparamgates.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/rtlparam.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/interrupt_uvm_agent.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image7.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image6.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image5.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image4.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image3.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image2.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/image1.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/hvp.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/funccovresults.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/frontendsb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media/axiagentmerge.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/media copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_process.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/verification_environment.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification/README.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/verification copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/tristan creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/unpriv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/priv.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/riscv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images/CV32A65X_subsystems.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/source/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/design.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/04_cv32a65x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/uvm_fu_tb.ai -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/update_tree.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/timer.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/test_harness.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_set.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/shared_tlb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_x0.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_x0_asid.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_x0.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/sfence_vaddr_asid.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/scoreboard.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/replacement_entry.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_state_diagram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_flowchart.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_pte_1.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_nlvl.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_mis_sup.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_iptw.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_idle.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw_s.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ptw_dptw.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plru_tree_indexing.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic_top.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/plic.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/nested_translation.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_major_blocks.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_in_out.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_control_flow.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/logonav.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/jekyll-dark.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/instr_realign.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/in_out_tlb.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/fpga_bd.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dram.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/dm_top_slave.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_hit.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/cva6_tlb_entry.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/clint.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/branch_prediction.pdf -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bootrom.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bht2lvl.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/bg.jpg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi_adapter.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/axi2mem.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane_overview.drawio.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/ariane.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/apb_uart.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/RR.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static/LZC.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/pcgen_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/issue_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/intro.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/if_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/id_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/ex_stage.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/commit_stage.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design copying build/lib/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design/MMU.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/03_cva6_design creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images/cva6_scope.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements/cva6_requirements_specification.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/02_cva6_requirements creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images/jade_design_automation_logo.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/user_cfg_doc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/rtype_format.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Trigger_Module.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Traps_Interrupts_Exceptions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknh.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZkne.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZknd.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZifencei.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicsr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZicond.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZcmp.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbs.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkx.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbkb.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbc.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZbb.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RVZba.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32ZCb.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32M.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32I.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32C.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions_RV32A.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/RISCV_Instructions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Programmer_View.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Parameters_Configuration.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMP.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/PMA.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Introduction.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Interfaces.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Custom_Instructions.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Core_Integration.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/Compiler_Command_Lines.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVX_Interface_Coprocessor.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CVA6_user_guide.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV64A6_Control_Status_Registers.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CV32A6_Control_Status_Registers.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Performance_Counters.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_Cache_Control.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU_list.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV64A6_MMU.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X_list.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60X.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX_list.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/CSR_CV32A60AX.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user/AXI_Interface.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/01_cva6_user copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv64a6_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/cv32a6_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/axi_intf.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_gate_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/src/ariane.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_resync_counter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_reg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_priority.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_packet_emitter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_filter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/te_branch_map.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/rv_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl/lzc.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/rtl creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include/te_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_tracer-main creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl/encapsulator.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/rtl creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include/encap_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/src/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/rv_encapsulator-main creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/to_script.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/run_timeout.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/clean_csv.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Receiver_DPTI.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/receiver.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys2_DPTI.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/genesys-2.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/decoded_trace.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/TC_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Priority_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Main_tracer_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JB_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/JA_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_single_mode_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_inside_block_mode_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_detailed_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/ITI_diagram_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Gen2_wired.png -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Filter_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encoder_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Encapsulated_Packet_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Emmiter_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/EEPROM.PNG -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_map_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_light.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures/Branch_example_dark.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Pictures creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_types.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include/iti_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/single_retirement.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/iti.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/block_retirement.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/debug_encoder_diff.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/Decapsuler.cpp -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/slicer_DPTI.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/Digilent.licence -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_nexys_video.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_dpti_clk creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/mmc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/memalign.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dwmmc.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dw_mmc.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/dma-mapping.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/cache.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bouncebuf.c -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_types.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_time.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_io.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/bootrom_errno.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6_agilex.dts.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6_agilex.dts.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts.in -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_wr.v -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter_rd.v -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter/axi_dw_adapter.v -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/axi_dw_adapter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/nexys_video.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/agilex7.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/nexys_video.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag_tap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/dmi_vjtag.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera_peripherals.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src/cva6_altera.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/vJTAG.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/test_mm_ccb_0.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/oddr_intel.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iobuf.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/io_pll.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/interconnect.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/iddr_intel.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/hps_cva6_altera.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/emif_cal.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/ed_synth_emif_fm_0.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip/cva6_intel_jtag_uart_0.tcl -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints/SDC1.sdc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/u-boot-spl-dtb.hex -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/settings.csv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/search_paths.csv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/loc_constraints.csv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/ip_files.csv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/io_standard_constraints.csv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/altera.cfg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/altera/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/altera creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_data_if.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_mmu_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv64a6_imadfcv_sv39_polara_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages/cv32a6_embedded_config_pkg_deprecated.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include/deprecated_packages copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/triggers_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/rvfi_types.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/dummy_l15_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_types.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdcv_sv39_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_wb_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdch_sv39_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_wb_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_wb_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_hpdcache_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg_cvfpu-uvm.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a60ax_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_ima_sv32_fpga_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a65x_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/build_config_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/aes_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht2lvl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/copro_alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/compressed_instr_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work/work.rlx -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/xsim.dir/work copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_tlb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_shared_tlb.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_ptw.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_mmu/cva6_mmu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cva6_mmu creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_l15_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem_axi_arbiter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_subsystem.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_hpdcache_if_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/axi_adapter.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/zcmt_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/trigger_module.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/raw_checker.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/macro_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_issue_register_commit_if_driver.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_compressed_if_driver.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_rvfi_probes.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_rvfi.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_fifo_v3.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6_accel_first_pass_decoder_stub.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_fpga.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/aes.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/acc_dispatcher.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cva6_gate -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cva6 -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/platform_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/isa_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/debug_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec/custom_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv64a60ax/spec creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/platform_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/isa_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec/custom_spec.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/spec creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/platform_gen.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/isa_gen.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated/custom_gen.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config/cv32a65x/generated copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config copying build/lib/pythondata_cpu_cva6/system_verilog/config/riscv-config/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/riscv-config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/spike_updater.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/isa_updater.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x/csr_updater.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/updaters/cv32a65x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/spike.mako -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates/isa_template.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/templates creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/linker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike/spike.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/spike creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/linker creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa/isa.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/isa creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.rst -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr/csr.adoc -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a65x/csr creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike/spike.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/spike creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker/link.ld -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/cv32a60x/linker copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/requirements.txt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config copying build/lib/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper_cache_techno.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram_cache.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_wbyteenable_1rw.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/hpdcache_sram_1rw.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-toolchain.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-prereq.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example/core-v-verif-cva6.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/setup-ci-example creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/expected_synth.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/verible.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/stale.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-tier-dashboard.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier2.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/openhw-cva6-ci-tier1.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/dashboard-done.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/bender-up-to-date.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates/index.html -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/templates creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static/openhw-landscape.svg -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/static copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers copying build/lib/pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env copying build/lib/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env/action.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/actions/setup-cva6-env creating /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/3-other.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/2-task.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/1-bug.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/pull_request_template.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github copying build/lib/pythondata_cpu_cva6/system_verilog/.github/dependabot.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github copying build/lib/pythondata_cpu_cva6/system_verilog/verilator_config.vlt -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/SECURITY.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/RESOURCES.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CITATION.cff -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ACKNOWLEDGEMENTS.md -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.readthedocs.yaml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6 byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py to gen_rom.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py to verilator_log_to_trace_csv.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py to cva6_spike_log_to_trace_csv.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6.py to cva6.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/conf.py to conf.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/vp_config.py to vp_config.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py to warl.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/utils.py to utils.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/schemaValidator.py to schemaValidator.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/main.py to main.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py to isa_validator.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/errors.py to errors.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/constants.py to constants.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py to checker.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__init__.py to __init__.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py to conf.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/setup.py to setup.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/vendor.py to vendor.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/user_config.py to user_config.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py to parse_ila_trace.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py to flist_flattener.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/profile.py to profile.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/model.py to model.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/isa.py to isa.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/perf-model/cycle_diff.py to cycle_diff.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py to spec_builder.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/parameters_extractor.py to parameters_extractor.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/define_blacklist.py to define_blacklist.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/classes.py to classes.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/SW/Receiver_DPTI/script.py to script.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/diff_color.py to diff_color.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/affiche_csv.py to affiche_csv.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py to utils.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/spike_updater.py to spike_updater.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/isa_updater.py to isa_updater.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_updater.py to csr_updater.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/csr_factorizer.py to csr_factorizer.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/riscv_config_gen.py to riscv_config_gen.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_tandem.py to report_tandem.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py to report_synth.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: "\ " is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\ "? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_spyglass_lint.py to report_spyglass_lint.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_simu.py to report_simu.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_pass.py to report_pass.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga_boot.py to report_fpga_boot.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py to report_fpga.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fail.py to report_fail.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_envfail.py to report_envfail.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_coverage.py to report_coverage.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_builder.py to report_builder.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_benchmark.py to report_benchmark.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py to merge_job_reports.cpython-315.pyc /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/github_integration.py to github_integration.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/parser.py to parser.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/generate_dashboard.py to generate_dashboard.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/collect_data.py to collect_data.cpython-315.pyc byte-compiling /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-315.pyc writing byte-compilation script '/tmp/tmpwa2jyyq2.py' /usr/bin/python3 /tmp/tmpwa2jyyq2.py /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: "\ " is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\ "? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. removing /tmp/tmpwa2jyyq2.py running install_egg_info running egg_info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution warning: no previously-included files matching '__pycache__/*' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6-4.2.0.post5856-py3.15.egg-info running install_scripts + rm -rfv /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/bin/__pycache__ + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + COMPRESS='gzip -9 -n' + COMPRESS_EXT=.gz + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/run-tier-regression.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-hyp-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/DPTI/dpti_ctrl.vhd is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/Decapsuler/compare_encoder.sh from /usr/bin/env bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/instr_tracing/ITI/cva6_iti/itype_detector.sv is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/docs/scripts/spec_builder.py is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_goals_setup.tcl is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/spyglass/sg_setup/cva6/cva6_options.tcl is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/flist_flattener.py from /bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/parse_ila_trace.py is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/write-zephyr-sd.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/build-toolchain.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/util/toolchain-builder/config/global.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/.git_hooks/pre-commit from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/MMU_SV32/runme.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/Instr_tracing_test.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-compliance.sh is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/dv-riscv-tests.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-pk.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-compliance.sh is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-riscv-tests.sh is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/regress/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 + /usr/lib/rpm/brp-remove-la-files + /usr/lib/rpm/redhat/brp-python-rpm-in-distinfo + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j4 Bytecompiling .py files below /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15 using python3.15 /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/merge_job_reports.py:115: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_fpga.py:19: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: "\ " is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\ "? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:50: SyntaxWarning: "\ " is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\ "? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/report_synth.py:55: SyntaxWarning: "\w" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\w"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:663: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/config/gen_from_riscv_config/scripts/libs/utils.py:713: SyntaxWarning: "\|" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\|"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/docs/source/conf.py:15: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/isa_validator.py:15: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:56: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:57: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:87: SyntaxWarning: "\[" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\["? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:204: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:229: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:230: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:382: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:407: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:408: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:431: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:491: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:562: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:620: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/warl.py:621: SyntaxWarning: "\s" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\s"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1335: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1343: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/cva6_spike_log_to_trace_csv.py:31: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1461: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/verilator_log_to_trace_csv.py:32: SyntaxWarning: "\(" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\("? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1491: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/checker.py:1496: SyntaxWarning: "\d" is an invalid escape sequence. Such sequences will not work in the future. Did you mean "\\d"? A raw string is also an option. + /usr/lib/rpm/redhat/brp-python-hardlink + /usr/bin/add-det --brp -j4 /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/__pycache__/__init__.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.github/scripts/dashboard_tiers/__pycache__/parser.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci/scripts/__pycache__/report_tandem.cpython-315.opt-1.pyc: rewriting with normalized contents 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rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__pycache__/__init__.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__pycache__/errors.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/__pycache__/vp_config.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/docs/VerifPlans/source/__pycache__/conf.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__pycache__/isa_validator.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/__pycache__/verilator_log_to_trace_csv.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/__pycache__/cva6_spike_log_to_trace_csv.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tb/core/bootrom/__pycache__/gen_rom.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/vendor/riscv/riscv-config/riscv_config/__pycache__/checker.cpython-315.opt-1.pyc: rewriting with normalized contents /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/__pycache__/cva6.cpython-315.pyc: replacing with normalized version /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/sim/__pycache__/cva6.cpython-315.opt-1.pyc: replacing with normalized version Scanned 334 directories and 1877 files, processed 77 inodes, 73 modified (20 replaced + 53 rewritten), 0 unsupported format, 0 errors + /usr/bin/linkdupes --brp /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr Scanned 333 directories and 1877 files, considered 1877 files, read 385 files, linked 65 files, 0 errors sum of sizes of linked files: 3226659 bytes Processing files: litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.fc46.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.aqyfxf + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + DOCDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C.UTF-8 + LC_ALL=C.UTF-8 + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/doc/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.GQae7d + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + cd litex-pythondata-cpu-cva6 + LICENSEDIR=/builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C.UTF-8 + LC_ALL=C.UTF-8 + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cva6-python3 = 2026.04-20260917.0.git2b51ea6a.fc46 pythondata-cpu-cva6 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 warning: Arch dependent binaries in noarch package (litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.fc46.noarch): /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o (ELF 32-bit) Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build/BUILDROOT Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.fc46.noarch.rpm Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.dyz5hy + umask 022 + cd /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + test -d /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + rm -rf /builddir/build/BUILD/litex-pythondata-cpu-cva6-2026.04-build + RPM_EC=0 ++ jobs -p + exit 0 RPM build warnings: The %py3_build macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ The %py3_install macro is deprecated and will likely stop working in Fedora 45. See the current Python packaging guidelines: https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ Arch dependent binaries in noarch package (litex-pythondata-cpu-cva6-python3-2026.04-20260917.0.git2b51ea6a.fc46.noarch): /usr/lib/python3.15/site-packages/pythondata_cpu_cva6/system_verilog/verif/tests/custom/ITI/test_iti_asm.o (ELF 32-bit) Finish: rpmbuild litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm Finish: build phase for litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-rawhide-aarch64-1789969120.434794/root/var/log/dnf5.log INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz /bin/tar: Removing leading `/' from member names INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2026.04-20260917.0.git2b51ea6a.fc46.src.rpm) Config(child) 0 minutes 50 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool Package info: { "packages": [ { "name": "litex-pythondata-cpu-cva6", "epoch": null, "version": "2026.04", "release": "20260917.0.git2b51ea6a.fc46", "arch": "src" }, { "name": "litex-pythondata-cpu-cva6-python3", "epoch": null, "version": "2026.04", "release": "20260917.0.git2b51ea6a.fc46", "arch": "noarch" } ] } RPMResults finished