Mock Version: 4.1 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target ppc64le --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e41p.spec'], chrootPath='/var/lib/mock/fedora-rawhide-ppc64le-1688732340.760801/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1001gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '7a0c0cb94cb44b04a780c3b5350e6723', '-D', '/var/lib/mock/fedora-rawhide-ppc64le-1688732340.760801/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target ppc64le --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e41p.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: ppc64le Building for target ppc64le setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.src.rpm Child return code was: 0 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target ppc64le --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e41p.spec'], chrootPath='/var/lib/mock/fedora-rawhide-ppc64le-1688732340.760801/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1001gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '68d9034ab57a401bbf0ad57131398011', '-D', '/var/lib/mock/fedora-rawhide-ppc64le-1688732340.760801/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.kaqk8bf9:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target ppc64le --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cv32e41p.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: ppc64le Building for target ppc64le setting SOURCE_DATE_EPOCH=1654300800 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.UDnCk9 + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cv32e41p + /usr/bin/mkdir -p litex-pythondata-cpu-cv32e41p + cd litex-pythondata-cpu-cv32e41p + /usr/bin/mkdir -p SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + find /builddir/build/BUILD -name SPECPARTS -exec rm -rf '{}' + + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cv32e41p.git . Cloning into '.'... + git fetch --depth 1 origin a48ddd9fc6f1cabfb3a7ac679774d4eff1f296fc From https://github.com/litex-hub/pythondata-cpu-cv32e41p * branch a48ddd9fc6f1cabfb3a7ac679774d4eff1f296fc -> FETCH_HEAD + git reset --hard a48ddd9fc6f1cabfb3a7ac679774d4eff1f296fc HEAD is now at a48ddd9 Updating pythondata-cpu-cv32e41p to 0.0.post1883 + git log --format=fuller commit a48ddd9fc6f1cabfb3a7ac679774d4eff1f296fc Author: LiteX Robot AuthorDate: Mon May 30 19:55:58 2022 +0000 Commit: LiteX Robot CommitDate: Mon May 30 19:55:58 2022 +0000 Updating pythondata-cpu-cv32e41p to 0.0.post1883 Updated data to v0.0-1741-gbda060e based on bda060eee5bfb22fdbe55029c5e3cf1b62724fff from https://github.com/openhwgroup/cv32e41p. > commit bda060eee5bfb22fdbe55029c5e3cf1b62724fff > Author: Ibrahim Abu Kharmeh > Date: Thu Apr 7 11:28:49 2022 +0100 > > Remove PULP build status from README (#25) > Updated using 0.0.post142 from https://github.com/litex-hub/litex-data-auto + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.I9srlu + umask 022 + cd /builddir/build/BUILD + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-cv32e41p + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_cv32e41p copying pythondata_cpu_cv32e41p/__init__.py -> build/lib/pythondata_cpu_cv32e41p running egg_info creating pythondata_cpu_cv32e41p.egg-info writing pythondata_cpu_cv32e41p.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cv32e41p.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cv32e41p.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cv32e41p.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cv32e41p.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cv32e41p.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.bhv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.bhv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.bhv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.bhv' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.bhv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.bhv.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.bhv.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.bhv.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.bhv.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.bhv.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.docs.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.docs.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.docs.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.docs.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.docs.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.docs.images.image_sources' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.docs.images.image_sources' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.docs.images.image_sources' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.docs.images.image_sources' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.docs.images.image_sources' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.docs.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.docs.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.docs.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.docs.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.docs.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/.dir-locals.el -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/.gitignore -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/.travis.yml -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/LICENSE -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/README.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/cv32e41p_manifest.flist -> build/lib/pythondata_cpu_cv32e41p/system_verilog copying pythondata_cpu_cv32e41p/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cv32e41p/system_verilog creating build/lib/pythondata_cpu_cv32e41p/system_verilog/.github creating build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/bug.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/enhancement.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/question.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/task.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_apu_tracer.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_core_log.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_instr_trace.svh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_sim_clock_gate.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_tracer.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv copying pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_wrapper.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv creating build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/include copying pythondata_cpu_cv32e41p/system_verilog/bhv/include/cv32e41p_tracer_pkg.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/include creating build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/Jenkinsfile -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/download-pulp-gcc.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/get-openocd.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/openocd-to-junit.py -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/run-openocd-compliance.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/rv32tests-to-junit.py -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci copying pythondata_cpu_cv32e41p/system_verilog/ci/veri-run-openocd-compliance.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/ci creating build/lib/pythondata_cpu_cv32e41p/system_verilog/constraints copying pythondata_cpu_cv32e41p/system_verilog/constraints/cv32e41p_core.sdc -> build/lib/pythondata_cpu_cv32e41p/system_verilog/constraints creating build/lib/pythondata_cpu_cv32e41p/system_verilog/docs copying pythondata_cpu_cv32e41p/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs copying pythondata_cpu_cv32e41p/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs copying pythondata_cpu_cv32e41p/system_verilog/docs/make.bat -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs copying pythondata_cpu_cv32e41p/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs creating build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/Back_to_Back_Memory_Transaction.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/Basic_Memory_Transaction.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Block_Diagram.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Block_Diagram.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Pipeline.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/Events_PCCR_PCMR_PCER.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/Slow_Response_Memory_Transaction.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/blockdiagram.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/debug_halted.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/debug_running.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/load_event.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_back_to_back.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_basic.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_multiple_outstanding.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_slow_response.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_instruction_basic.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_instruction_multiple_outstanding.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/openhw-circle.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/riscv_prefetch_buffer.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/rtl_freeze_rules.png -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images copying pythondata_cpu_cv32e41p/system_verilog/docs/images/wfi.svg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images creating build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/Events_PCCR_PCMR_and_PCER.odg -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/debug_halted.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/debug_running.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/load_event.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_back_to_back.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_basic.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_multiple_outstanding.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_slow_response.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_instruction_basic.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_instruction_multiple_outstanding.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/wfi.tim -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources creating build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/apu.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/conf.py -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/control_status_registers.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/core_versions.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/corev_hw_loop.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/debug.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/exceptions_interrupts.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/fpu.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/getting_started.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/glossary.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/index.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/instruction_fetch.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/instruction_set_extensions.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/integration.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/intro.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/list.issue -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/load_store_unit.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/perf_counters.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom_fp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom_fp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom_fp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom_fp' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.custom_fp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.firmware' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.firmware' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.firmware' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.firmware' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.firmware' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.hwlp_test' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.hwlp_test' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.hwlp_test' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.hwlp_test' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.hwlp_test' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.interrupt' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.interrupt' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.interrupt' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.interrupt' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.interrupt' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.mem_stall' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.mem_stall' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.mem_stall' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.mem_stall' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.core.mem_stall' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.example_tb.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.example_tb.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.example_tb.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.example_tb.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.example_tb.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.rtl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.rtl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.rtl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.rtl' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.rtl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.rtl.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.rtl.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.rtl.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.rtl.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.rtl.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.scripts.cadence_conformal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.scripts.cadence_conformal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.scripts.cadence_conformal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.scripts.cadence_conformal' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.scripts.cadence_conformal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cv32e41p.system_verilog.sva' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cv32e41p.system_verilog.sva' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cv32e41p.system_verilog.sva' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cv32e41p.system_verilog.sva' to be distributed and are already explicitly excluding 'pythondata_cpu_cv32e41p.system_verilog.sva' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) copying pythondata_cpu_cv32e41p/system_verilog/docs/source/pipeline.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/register_file.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/sleep.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source copying pythondata_cpu_cv32e41p/system_verilog/docs/source/tracer.rst -> build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb copying pythondata_cpu_cv32e41p/system_verilog/example_tb/README.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/.clang-format -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/.gitignore -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/Makefile -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/README.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/amo_shim.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_fp_wrapper.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_random_interrupt_generator.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_tb_subsystem.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/dp_ram.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mm_ram.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_gnt_stall.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_rvalid_stall.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/software.tcl -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/tb_top.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/vsim.tcl -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/waves.tcl -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/crt0.S -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/hello_world.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/link.ld -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/syscalls.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/vectors.S -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/main.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/matmulNxN.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware/stats.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp.h -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp_test.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include/perturbation_pkg.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/interrupt.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/isr.h -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/matrix.h -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/vectors.S -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.c -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall copying pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.h -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall creating build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts copying pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts/pulptrace -> build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts creating build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_aligner.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu_div.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_apu_disp.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_controller.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_core.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_cs_registers.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ex_stage.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ff_one.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_fifo.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_hwloop_regs.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_id_stage.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_if_stage.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_int_controller.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_load_store_unit.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_merged_decoder.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_mult.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_obi_interface.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_popcnt.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_buffer.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_controller.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_ff.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_latch.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl copying pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_sleep_unit.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl creating build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_apu_core_pkg.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_fpu_pkg.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_pkg.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include creating build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts creating build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/README.md -> build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_cmp.csh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_conformal.sh -> build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal creating build/lib/pythondata_cpu_cv32e41p/system_verilog/sva copying pythondata_cpu_cv32e41p/system_verilog/sva/cv32e41p_prefetch_controller_sva.sv -> build/lib/pythondata_cpu_cv32e41p/system_verilog/sva Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.AOSMoZ + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CFLAGS + CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + export CXXFLAGS + FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FFLAGS + FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection -I/usr/lib64/gfortran/modules ' + export FCFLAGS + VALAFLAGS=-g + export VALAFLAGS + RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Clink-arg=-Wl,-z,relro -Clink-arg=-Wl,-z,now -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn' + export RUSTFLAGS + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + export LDFLAGS + LT_SYS_LIBRARY_PATH=/usr/lib64: + export LT_SYS_LIBRARY_PATH + CC=gcc + export CC + CXX=g++ + export CXX + cd litex-pythondata-cpu-cv32e41p + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mcpu=power8 -mtune=power8 -fasynchronous-unwind-tables -fstack-clash-protection ' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le --prefix /usr running install /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/sva copying build/lib/pythondata_cpu_cv32e41p/system_verilog/sva/cv32e41p_prefetch_controller_sva.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/sva creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_conformal.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_cmp.csh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal copying build/lib/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_fpu_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/include/cv32e41p_apu_core_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_sleep_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_latch.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_register_file_ff.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_prefetch_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_popcnt.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_obi_interface.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_mult.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_merged_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_int_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_if_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_id_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_hwloop_regs.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_fifo.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ff_one.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_ex_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_cs_registers.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_core.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_apu_disp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl copying build/lib/pythondata_cpu_cv32e41p/system_verilog/rtl/cv32e41p_aligner.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts/pulptrace -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall/mem_stall.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mem_stall creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/matrix.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/isr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt/interrupt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/interrupt creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include/perturbation_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test/hwlp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/hwlp_test creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware/stats.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/firmware creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/matmulNxN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom_fp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/vectors.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/syscalls.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/hello_world.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom/crt0.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/custom copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/waves.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/vsim.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/tb_top.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/software.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_rvalid_stall.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/riscv_gnt_stall.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/mm_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_tb_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_random_interrupt_generator.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/cv32e41p_fp_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/amo_shim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/core/.clang-format -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/core copying build/lib/pythondata_cpu_cv32e41p/system_verilog/example_tb/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/tracer.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/sleep.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/register_file.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/pipeline.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/perf_counters.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/load_store_unit.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/list.issue -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/integration.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/instruction_set_extensions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/instruction_fetch.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/glossary.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/getting_started.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/fpu.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/exceptions_interrupts.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/debug.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/corev_hw_loop.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/core_versions.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/control_status_registers.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/source/apu.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/wfi.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_instruction_multiple_outstanding.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_instruction_basic.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_slow_response.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_multiple_outstanding.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_basic.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/obi_data_back_to_back.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/load_event.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/debug_running.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/debug_halted.tim -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources/Events_PCCR_PCMR_and_PCER.odg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images/image_sources copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/wfi.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/rtl_freeze_rules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/riscv_prefetch_buffer.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/openhw-circle.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_instruction_multiple_outstanding.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_instruction_basic.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_slow_response.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_multiple_outstanding.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_basic.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/obi_data_back_to_back.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/load_event.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/debug_running.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/debug_halted.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/blockdiagram.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/Slow_Response_Memory_Transaction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/Events_PCCR_PCMR_PCER.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Pipeline.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Block_Diagram.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/CV32E40P_Block_Diagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/Basic_Memory_Transaction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/images/Back_to_Back_Memory_Transaction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/images copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs copying build/lib/pythondata_cpu_cv32e41p/system_verilog/docs/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/constraints copying build/lib/pythondata_cpu_cv32e41p/system_verilog/constraints/cv32e41p_core.sdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/constraints creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/veri-run-openocd-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/rv32tests-to-junit.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/run-openocd-compliance.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/openocd-to-junit.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/get-openocd.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/download-pulp-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci copying build/lib/pythondata_cpu_cv32e41p/system_verilog/ci/Jenkinsfile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/include/cv32e41p_tracer_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv/include copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_sim_clock_gate.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_instr_trace.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_core_log.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv copying build/lib/pythondata_cpu_cv32e41p/system_verilog/bhv/cv32e41p_apu_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/bhv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/task.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/question.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/enhancement.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/config.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE/bug.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cv32e41p/system_verilog/src_files.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/cv32e41p_manifest.flist -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.travis.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/system_verilog/.dir-locals.el -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog copying build/lib/pythondata_cpu_cv32e41p/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/rv32tests-to-junit.py to rv32tests-to-junit.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/openocd-to-junit.py to openocd-to-junit.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpng8hlpex.py' /usr/bin/python3 /tmp/tmpng8hlpex.py removing /tmp/tmpng8hlpex.py running install_egg_info running egg_info writing pythondata_cpu_cv32e41p.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cv32e41p.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cv32e41p.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cv32e41p.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cv32e41p.egg-info/SOURCES.txt' Copying pythondata_cpu_cv32e41p.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p-0.0.post1883-py3.12.egg-info running install_scripts + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/bin/__pycache__ + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/brp-strip-static-archive /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/download-pulp-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/get-openocd.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/openocd-to-junit.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/run-openocd-compliance.sh from /usr/bin/env bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/rv32tests-to-junit.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/ci/veri-run-openocd-compliance.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source/getting_started.rst is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/docs/source/tracer.rst is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/example_tb/scripts/pulptrace from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cv32e41p/system_verilog/scripts/cadence_conformal/cv32e41p_lec_cmp.csh from /bin/tcsh -f to #!/usr/bin/tcsh -f + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j5 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/lib/python3.12 using python3.12 + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-cv32e41p-python3-2022.08-20220530.3.gita48ddd9f.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.L0yOlq + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e41p + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-cv32e41p-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-cv32e41p-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cv32e41p/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/doc/litex-pythondata-cpu-cv32e41p-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.kc1ftu + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e41p + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-cv32e41p-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-cv32e41p-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cv32e41p/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le/usr/share/licenses/litex-pythondata-cpu-cv32e41p-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cv32e41p-python3 = 2022.08-20220530.3.gita48ddd9f.fc39 python3.12dist(pythondata-cpu-cv32e41p) = 0^post1883 python3dist(pythondata-cpu-cv32e41p) = 0^post1883 pythondata-cpu-cv32e41p Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 Requires: /usr/bin/bash /usr/bin/python3 /usr/bin/tcsh python(abi) = 3.12 Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cv32e41p-python3-2022.08-20220530.3.gita48ddd9f.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.9dcOci + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cv32e41p + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cv32e41p-2022.08-20220530.3.gita48ddd9f.fc39.ppc64le + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.AfV84Q + umask 022 + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cv32e41p litex-pythondata-cpu-cv32e41p.gemspec + RPM_EC=0 ++ jobs -p + exit 0 Child return code was: 0