Mock Version: 4.1 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva6.spec'], chrootPath='/var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '14140146a42f436cbd90a05f59db0e47', '-D', '/var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bs --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva6.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Child return code was: 0 ENTER ['do_with_status'](['bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva6.spec'], chrootPath='/var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root'env={'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8'}shell=Falselogger=timeout=0uid=1000gid=135user='mockbuild'nspawn_args=['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11']unshare_net=FalseprintOutput=True) Using nspawn with args ['--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11'] Executing command: ['/usr/bin/systemd-nspawn', '-q', '-M', '3ec202ec11534ecb987c694d0d0d2d15', '-D', '/var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root', '-a', '-u', 'mockbuild', '--capability=cap_ipc_lock', '--rlimit=RLIMIT_NOFILE=10240', '--capability=cap_ipc_lock', '--bind=/tmp/mock-resolv.j8l3oxxz:/etc/resolv.conf', '--bind=/dev/btrfs-control', '--bind=/dev/mapper/control', '--bind=/dev/loop-control', '--bind=/dev/loop0', '--bind=/dev/loop1', '--bind=/dev/loop2', '--bind=/dev/loop3', '--bind=/dev/loop4', '--bind=/dev/loop5', '--bind=/dev/loop6', '--bind=/dev/loop7', '--bind=/dev/loop8', '--bind=/dev/loop9', '--bind=/dev/loop10', '--bind=/dev/loop11', '--console=pipe', '--setenv=TERM=vt100', '--setenv=SHELL=/bin/bash', '--setenv=HOME=/builddir', '--setenv=HOSTNAME=mock', '--setenv=PATH=/usr/bin:/bin:/usr/sbin:/sbin', '--setenv=PROMPT_COMMAND=printf "\\033]0;\\007"', '--setenv=PS1= \\s-\\v\\$ ', '--setenv=LANG=C.UTF-8', '--resolv-conf=off', 'bash', '--login', '-c', '/usr/bin/rpmbuild -bb --target x86_64 --nodeps /builddir/build/SPECS/litex-pythondata-cpu-cva6.spec'] with env {'TERM': 'vt100', 'SHELL': '/bin/bash', 'HOME': '/builddir', 'HOSTNAME': 'mock', 'PATH': '/usr/bin:/bin:/usr/sbin:/sbin', 'PROMPT_COMMAND': 'printf "\\033]0;\\007"', 'PS1': ' \\s-\\v\\$ ', 'LANG': 'C.UTF-8', 'SYSTEMD_NSPAWN_TMPFS_TMP': '0', 'SYSTEMD_SECCOMP': '0'} and shell False Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1654300800 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.KvZ4Wx + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p litex-pythondata-cpu-cva6 + cd litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + find /builddir/build/BUILD -name SPECPARTS -exec rm -rf '{}' + + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git . Cloning into '.'... + git fetch --depth 1 origin 13cbe4453e14960a80949f6d0c66b63aabffd3df From https://github.com/litex-hub/pythondata-cpu-cva6 * branch 13cbe4453e14960a80949f6d0c66b63aabffd3df -> FETCH_HEAD + git reset --hard 13cbe4453e14960a80949f6d0c66b63aabffd3df HEAD is now at 13cbe44 Updating .gitmodules file. + git log --format=fuller commit 13cbe4453e14960a80949f6d0c66b63aabffd3df Author: LiteX Robot AuthorDate: Tue Nov 8 23:14:32 2022 +0000 Commit: LiteX Robot CommitDate: Tue Nov 8 23:14:32 2022 +0000 Updating .gitmodules file. Updated using 0.0.post142 from https://github.com/litex-hub/litex-data-auto + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.iJP089 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_cva6 copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6 running egg_info creating pythondata_cpu_cva6.egg-info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog creating build/lib/pythondata_cpu_cva6/system_verilog/.github creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci creating build/lib/pythondata_cpu_cva6/system_verilog/common creating build/lib/pythondata_cpu_cva6/system_verilog/common/local creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util creating build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/re_name.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend creating build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include copying pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications copying pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide creating build/lib/pythondata_cpu_cva6/system_verilog/pd creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/scripts copying pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/scripts Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.U7hLVl running install running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 --prefix /usr /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/re_name.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/init_testharness.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py to parse_ila_trace.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py to testlib.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py to ebreak.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py to config_pkg_generator.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpyafp332t.py' /usr/bin/python3 /tmp/tmpyafp332t.py removing /tmp/tmpyafp332t.py running install_egg_info running egg_info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6-4.2.0.post435-py3.12.egg-info running install_scripts /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/bin/__pycache__ + sed -i /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -e 's|#!/usr/bin/python|#!/usr/bin/python3|' + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/brp-strip-static-archive /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure from /bin/sh to #!/usr/bin/sh *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py is executable but has no shebang, removing executable bit + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j2 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12 using python3.12 /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-cva6-python3-2022.12-20221108.2.git13cbe445.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.SUirFC + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.1fCrkR + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cva6-python3 = 2022.12-20221108.2.git13cbe445.fc39 pythondata-cpu-cva6 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 warning: Arch dependent binaries in noarch package Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2022.12-20221108.2.git13cbe445.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.GT5Y1a + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.QfX2DF + umask 022 + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cva6 litex-pythondata-cpu-cva6.gemspec + RPM_EC=0 ++ jobs -p + exit 0 RPM build warnings: Arch dependent binaries in noarch package Child return code was: 0