Warning: Permanently added '2620:52:3:1:dead:beef:cafe:c18e' (ED25519) to the list of known hosts. cmd: ['copr-distgit-client', 'sources'] cwd: /var/lib/copr-rpmbuild/workspace/workdir-qtr2ma8g/litex-pythondata-cpu-cva6 rc: 0 stdout: stderr: INFO: Reading stdout from command: git rev-parse --abbrev-ref HEAD INFO: Reading stdout from command: git rev-parse HEAD INFO: Reading sources specification file: sources Running (timeout=172800): unbuffer mock --buildsrpm --spec /var/lib/copr-rpmbuild/workspace/workdir-qtr2ma8g/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-qtr2ma8g/litex-pythondata-cpu-cva6 --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1688731775.510429 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 4.1 starting (python version = 3.11.3, NVR = mock-4.1-1.fc38)... Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-qtr2ma8g/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(fedora-rawhide-x86_64) Start: clean chroot Finish: clean chroot Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1688731775.510429/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: enabled HW Info plugin Mock Version: 4.1 INFO: Mock Version: 4.1 INFO: Package manager dnf detected and used (fallback) Start(bootstrap): installing dnf tooling No matches found for the following disable plugin patterns: local, spacewalk, versionlock Updating Subscription Management repositories. Unable to read consumer identity This system is not registered with an entitlement server. You can use subscription-manager to register. Copr repository 8.9 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 7.2 MB/s | 1.0 MB 00:00 Additional repo copr_rezso_CUDA 585 kB/s | 59 kB 00:00 Additional repo http_developer_download_nvidia_ 22 MB/s | 2.4 MB 00:00 Additional repo http_developer_download_nvidia_ 14 MB/s | 1.4 MB 00:00 Additional repo http_developer_download_nvidia_ 13 MB/s | 1.5 MB 00:00 fedora 14 MB/s | 71 MB 00:04 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: dnf-plugins-core noarch 4.4.1-4.fc39 fedora 38 k python3-dnf noarch 4.16.1-3.fc39 fedora 586 k Installing dependencies: alternatives x86_64 1.24-1.fc39 fedora 39 k audit-libs x86_64 3.1.1-3.fc39 fedora 117 k basesystem noarch 11-17.fc39 fedora 7.0 k bash x86_64 5.2.15-3.fc38 fedora 1.8 M bzip2-libs x86_64 1.0.8-13.fc38 fedora 41 k ca-certificates noarch 2023.2.60-2.fc38 fedora 845 k coreutils x86_64 9.3-1.fc39 fedora 1.1 M coreutils-common x86_64 9.3-1.fc39 fedora 2.1 M crypto-policies noarch 20230614-1.git5f3458e.fc39 fedora 94 k curl x86_64 8.1.2-1.fc39 fedora 345 k cyrus-sasl-lib x86_64 2.1.28-10.fc39 fedora 792 k dbus-libs x86_64 1:1.14.8-1.fc39 fedora 156 k dnf-data noarch 4.16.1-3.fc39 fedora 38 k elfutils-default-yama-scope noarch 0.189-3.fc39 fedora 13 k elfutils-libelf x86_64 0.189-3.fc39 fedora 195 k elfutils-libs x86_64 0.189-3.fc39 fedora 258 k expat x86_64 2.5.0-2.fc38 fedora 110 k fedora-gpg-keys noarch 39-0.1 fedora 126 k fedora-release noarch 39-0.14 fedora 6.6 k fedora-release-common noarch 39-0.14 fedora 17 k fedora-release-identity-basic noarch 39-0.14 fedora 7.4 k fedora-repos noarch 39-0.1 fedora 9.4 k fedora-repos-rawhide noarch 39-0.1 fedora 9.0 k file-libs x86_64 5.44-4.fc39 fedora 729 k filesystem x86_64 3.18-4.fc39 fedora 1.1 M findutils x86_64 1:4.9.0-4.fc39 fedora 491 k fmt x86_64 10.0.0-2.fc39 fedora 127 k gawk x86_64 5.2.2-1.fc39 fedora 1.1 M gdbm-libs x86_64 1:1.23-3.fc38 fedora 56 k glib2 x86_64 2.76.3-1.fc39 fedora 2.8 M glibc x86_64 2.37.9000-15.fc39 fedora 2.1 M glibc-common x86_64 2.37.9000-15.fc39 fedora 339 k glibc-minimal-langpack x86_64 2.37.9000-15.fc39 fedora 61 k gmp x86_64 1:6.2.1-4.fc38 fedora 313 k gnupg2 x86_64 2.4.2-2.fc39 fedora 2.6 M gnutls x86_64 3.8.0-6.fc39 fedora 1.1 M gpgme x86_64 1.20.0-4.fc39 fedora 210 k grep x86_64 3.11-1.fc39 fedora 298 k ima-evm-utils x86_64 1.5-1.fc39 fedora 63 k json-c x86_64 0.16-4.fc38 fedora 41 k keyutils-libs x86_64 1.6.1-6.fc38 fedora 31 k krb5-libs x86_64 1.21-1.fc39 fedora 765 k libacl x86_64 2.3.1-7.fc39 fedora 23 k libarchive x86_64 3.6.1-5.fc39 fedora 400 k libassuan x86_64 2.5.6-1.fc39 fedora 67 k libattr x86_64 2.5.1-7.fc39 fedora 18 k libb2 x86_64 0.98.1-8.fc38 fedora 25 k libblkid x86_64 2.39.1-2.fc39 fedora 116 k libbrotli x86_64 1.0.9-12.fc39 fedora 317 k libcap x86_64 2.48-6.fc38 fedora 67 k libcap-ng x86_64 0.8.3-6.fc39 fedora 32 k libcom_err x86_64 1.47.0-1.fc39 fedora 26 k libcomps x86_64 0.1.19-2.fc39 fedora 77 k libcurl x86_64 8.1.2-1.fc39 fedora 323 k libdnf x86_64 0.70.1-4.fc39 fedora 668 k libdnf5 x86_64 5.0.15-3.fc39 fedora 877 k libeconf x86_64 0.4.0-5.fc38 fedora 27 k libevent x86_64 2.1.12-8.fc38 fedora 257 k libffi x86_64 3.4.4-3.fc39 fedora 40 k libfsverity x86_64 1.4-9.fc38 fedora 19 k libgcc x86_64 13.1.1-4.fc39 fedora 107 k libgcrypt x86_64 1.10.2-1.fc39 fedora 514 k libgomp x86_64 13.1.1-4.fc39 fedora 317 k libgpg-error x86_64 1.47-1.fc39 fedora 230 k libidn2 x86_64 2.3.4-2.fc38 fedora 160 k libksba x86_64 1.6.4-1.fc39 fedora 159 k libmodulemd x86_64 2.15.0-4.fc39 fedora 232 k libmount x86_64 2.39.1-2.fc39 fedora 155 k libnghttp2 x86_64 1.54.0-1.fc39 fedora 75 k libnsl2 x86_64 2.0.0-5.fc38 fedora 30 k libpsl x86_64 0.21.2-3.fc39 fedora 63 k librepo x86_64 1.15.1-3.fc39 fedora 95 k libreport-filesystem noarch 2.17.11-2.fc39 fedora 14 k libselinux x86_64 3.5-4.fc39 fedora 87 k libsemanage x86_64 3.5-3.fc39 fedora 119 k libsepol x86_64 3.5-1.fc39 fedora 324 k libsigsegv x86_64 2.14-4.fc38 fedora 27 k libsmartcols x86_64 2.39.1-2.fc39 fedora 67 k libsolv x86_64 0.7.24-5.fc39 fedora 425 k libssh x86_64 0.10.5-1.fc39 fedora 211 k libssh-config noarch 0.10.5-1.fc39 fedora 9.0 k libstdc++ x86_64 13.1.1-4.fc39 fedora 861 k libtasn1 x86_64 4.19.0-2.fc38 fedora 74 k libtirpc x86_64 1.3.3-1.rc1.fc39 fedora 93 k libunistring x86_64 1.1-3.fc38 fedora 545 k libunistring1.0 x86_64 1.0-1.fc38 fedora 539 k libuuid x86_64 2.39.1-2.fc39 fedora 28 k libverto x86_64 0.3.2-5.fc38 fedora 21 k libxcrypt x86_64 4.4.36-1.fc39 fedora 119 k libxml2 x86_64 2.10.4-2.fc39 fedora 701 k libyaml x86_64 0.2.5-9.fc38 fedora 59 k libzstd x86_64 1.5.5-1.fc39 fedora 308 k lua-libs x86_64 5.4.4-9.fc39 fedora 133 k lz4-libs x86_64 1.9.4-3.fc39 fedora 67 k mpdecimal x86_64 2.5.1-6.fc38 fedora 89 k mpfr x86_64 4.1.1-3.fc38 fedora 600 k ncurses-base noarch 6.4-5.20230520.fc39 fedora 88 k ncurses-libs x86_64 6.4-5.20230520.fc39 fedora 336 k nettle x86_64 3.9.1-1.fc39 fedora 425 k npth x86_64 1.6-13.fc39 fedora 24 k openldap x86_64 2.6.4-2.fc39 fedora 255 k openssl-libs x86_64 1:3.0.8-2.fc39 fedora 2.1 M p11-kit x86_64 0.24.1-6.fc38 fedora 359 k p11-kit-trust x86_64 0.24.1-6.fc38 fedora 136 k pcre2 x86_64 10.42-1.fc38.1 fedora 234 k pcre2-syntax noarch 10.42-1.fc38.1 fedora 144 k popt x86_64 1.19-2.fc38 fedora 67 k publicsuffix-list-dafsa noarch 20230614-1.fc39 fedora 57 k python-pip-wheel noarch 23.1.2-2.fc39 fedora 1.4 M python3 x86_64 3.12.0~b3-2.fc39 fedora 26 k python3-dateutil noarch 1:2.8.2-9.fc39 fedora 355 k python3-dbus x86_64 1.3.2-3.fc39 fedora 157 k python3-distro noarch 1.8.0-5.fc39 fedora 49 k python3-dnf-plugins-core noarch 4.4.1-4.fc39 fedora 293 k python3-gpg x86_64 1.20.0-4.fc39 fedora 298 k python3-hawkey x86_64 0.70.1-4.fc39 fedora 107 k python3-libcomps x86_64 0.1.19-2.fc39 fedora 48 k python3-libdnf x86_64 0.70.1-4.fc39 fedora 829 k python3-libs x86_64 3.12.0~b3-2.fc39 fedora 9.2 M python3-rpm x86_64 4.18.91-7.fc39 fedora 67 k python3-six noarch 1.16.0-11.fc39 fedora 41 k python3-systemd x86_64 235-4.fc39 fedora 107 k readline x86_64 8.2-3.fc38 fedora 212 k rpm x86_64 4.18.91-7.fc39 fedora 529 k rpm-build-libs x86_64 4.18.91-7.fc39 fedora 96 k rpm-libs x86_64 4.18.91-7.fc39 fedora 309 k rpm-sequoia x86_64 1.4.1-1.fc39 fedora 843 k rpm-sign-libs x86_64 4.18.91-7.fc39 fedora 26 k sed x86_64 4.8-12.fc38 fedora 306 k setup noarch 2.14.3-3.fc39 fedora 152 k shadow-utils x86_64 2:4.13-7.fc39 fedora 1.3 M sqlite-libs x86_64 3.41.2-3.fc39 fedora 669 k systemd-libs x86_64 253.5-6.fc39 fedora 652 k tpm2-tss x86_64 4.0.1-3.fc38 fedora 675 k tzdata noarch 2023c-1.fc39 fedora 718 k xz-libs x86_64 5.4.3-1.fc39 fedora 108 k zchunk-libs x86_64 1.3.1-1.fc39 fedora 52 k zlib x86_64 1.2.13-3.fc38 fedora 95 k Transaction Summary ================================================================================ Install 140 Packages Total download size: 58 M Installed size: 202 M Downloading Packages: (1/140): basesystem-11-17.fc39.noarch.rpm 60 kB/s | 7.0 kB 00:00 (2/140): alternatives-1.24-1.fc39.x86_64.rpm 226 kB/s | 39 kB 00:00 (3/140): bzip2-libs-1.0.8-13.fc38.x86_64.rpm 987 kB/s | 41 kB 00:00 (4/140): audit-libs-3.1.1-3.fc39.x86_64.rpm 470 kB/s | 117 kB 00:00 (5/140): bash-5.2.15-3.fc38.x86_64.rpm 5.9 MB/s | 1.8 MB 00:00 (6/140): ca-certificates-2023.2.60-2.fc38.noarc 2.3 MB/s | 845 kB 00:00 (7/140): coreutils-common-9.3-1.fc39.x86_64.rpm 13 MB/s | 2.1 MB 00:00 (8/140): crypto-policies-20230614-1.git5f3458e. 1.9 MB/s | 94 kB 00:00 (9/140): curl-8.1.2-1.fc39.x86_64.rpm 6.6 MB/s | 345 kB 00:00 (10/140): dbus-libs-1.14.8-1.fc39.x86_64.rpm 3.6 MB/s | 156 kB 00:00 (11/140): coreutils-9.3-1.fc39.x86_64.rpm 2.3 MB/s | 1.1 MB 00:00 (12/140): dnf-data-4.16.1-3.fc39.noarch.rpm 869 kB/s | 38 kB 00:00 (13/140): elfutils-default-yama-scope-0.189-3.f 325 kB/s | 13 kB 00:00 (14/140): dnf-plugins-core-4.4.1-4.fc39.noarch. 899 kB/s | 38 kB 00:00 (15/140): elfutils-libs-0.189-3.fc39.x86_64.rpm 4.7 MB/s | 258 kB 00:00 (16/140): elfutils-libelf-0.189-3.fc39.x86_64.r 1.9 MB/s | 195 kB 00:00 (17/140): expat-2.5.0-2.fc38.x86_64.rpm 2.4 MB/s | 110 kB 00:00 (18/140): fedora-release-39-0.14.noarch.rpm 124 kB/s | 6.6 kB 00:00 (19/140): fedora-gpg-keys-39-0.1.noarch.rpm 2.2 MB/s | 126 kB 00:00 (20/140): fedora-release-common-39-0.14.noarch. 410 kB/s | 17 kB 00:00 (21/140): fedora-release-identity-basic-39-0.14 182 kB/s | 7.4 kB 00:00 (22/140): cyrus-sasl-lib-2.1.28-10.fc39.x86_64. 2.3 MB/s | 792 kB 00:00 (23/140): fedora-repos-39-0.1.noarch.rpm 210 kB/s | 9.4 kB 00:00 (24/140): fedora-repos-rawhide-39-0.1.noarch.rp 201 kB/s | 9.0 kB 00:00 (25/140): findutils-4.9.0-4.fc39.x86_64.rpm 8.2 MB/s | 491 kB 00:00 (26/140): fmt-10.0.0-2.fc39.x86_64.rpm 2.8 MB/s | 127 kB 00:00 (27/140): gawk-5.2.2-1.fc39.x86_64.rpm 11 MB/s | 1.1 MB 00:00 (28/140): gdbm-libs-1.23-3.fc38.x86_64.rpm 1.1 MB/s | 56 kB 00:00 (29/140): file-libs-5.44-4.fc39.x86_64.rpm 2.4 MB/s | 729 kB 00:00 (30/140): filesystem-3.18-4.fc39.x86_64.rpm 3.5 MB/s | 1.1 MB 00:00 (31/140): glibc-common-2.37.9000-15.fc39.x86_64 3.4 MB/s | 339 kB 00:00 (32/140): glib2-2.76.3-1.fc39.x86_64.rpm 15 MB/s | 2.8 MB 00:00 (33/140): glibc-minimal-langpack-2.37.9000-15.f 1.6 MB/s | 61 kB 00:00 (34/140): gmp-6.2.1-4.fc38.x86_64.rpm 7.4 MB/s | 313 kB 00:00 (35/140): gnutls-3.8.0-6.fc39.x86_64.rpm 14 MB/s | 1.1 MB 00:00 (36/140): gpgme-1.20.0-4.fc39.x86_64.rpm 4.2 MB/s | 210 kB 00:00 (37/140): grep-3.11-1.fc39.x86_64.rpm 5.8 MB/s | 298 kB 00:00 (38/140): ima-evm-utils-1.5-1.fc39.x86_64.rpm 1.4 MB/s | 63 kB 00:00 (39/140): json-c-0.16-4.fc38.x86_64.rpm 289 kB/s | 41 kB 00:00 (40/140): keyutils-libs-1.6.1-6.fc38.x86_64.rpm 573 kB/s | 31 kB 00:00 (41/140): krb5-libs-1.21-1.fc39.x86_64.rpm 7.5 MB/s | 765 kB 00:00 (42/140): libacl-2.3.1-7.fc39.x86_64.rpm 512 kB/s | 23 kB 00:00 (43/140): gnupg2-2.4.2-2.fc39.x86_64.rpm 4.2 MB/s | 2.6 MB 00:00 (44/140): libassuan-2.5.6-1.fc39.x86_64.rpm 1.7 MB/s | 67 kB 00:00 (45/140): libattr-2.5.1-7.fc39.x86_64.rpm 478 kB/s | 18 kB 00:00 (46/140): libb2-0.98.1-8.fc38.x86_64.rpm 639 kB/s | 25 kB 00:00 (47/140): libarchive-3.6.1-5.fc39.x86_64.rpm 1.9 MB/s | 400 kB 00:00 (48/140): libblkid-2.39.1-2.fc39.x86_64.rpm 2.1 MB/s | 116 kB 00:00 (49/140): libbrotli-1.0.9-12.fc39.x86_64.rpm 5.7 MB/s | 317 kB 00:00 (50/140): libcap-ng-0.8.3-6.fc39.x86_64.rpm 664 kB/s | 32 kB 00:00 (51/140): libcap-2.48-6.fc38.x86_64.rpm 682 kB/s | 67 kB 00:00 (52/140): libcom_err-1.47.0-1.fc39.x86_64.rpm 379 kB/s | 26 kB 00:00 (53/140): libcomps-0.1.19-2.fc39.x86_64.rpm 1.0 MB/s | 77 kB 00:00 (54/140): libcurl-8.1.2-1.fc39.x86_64.rpm 4.5 MB/s | 323 kB 00:00 (55/140): libdnf5-5.0.15-3.fc39.x86_64.rpm 9.9 MB/s | 877 kB 00:00 (56/140): libeconf-0.4.0-5.fc38.x86_64.rpm 592 kB/s | 27 kB 00:00 (57/140): glibc-2.37.9000-15.fc39.x86_64.rpm 1.5 MB/s | 2.1 MB 00:01 (58/140): libffi-3.4.4-3.fc39.x86_64.rpm 899 kB/s | 40 kB 00:00 (59/140): libfsverity-1.4-9.fc38.x86_64.rpm 420 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libpsl-0.21.2-3.fc39.x86_64.rpm 760 kB/s | 63 kB 00:00 (75/140): libselinux-3.5-4.fc39.x86_64.rpm 2.1 MB/s | 87 kB 00:00 (76/140): libsemanage-3.5-3.fc39.x86_64.rpm 3.0 MB/s | 119 kB 00:00 (77/140): libsigsegv-2.14-4.fc38.x86_64.rpm 557 kB/s | 27 kB 00:00 (78/140): libsmartcols-2.39.1-2.fc39.x86_64.rpm 1.7 MB/s | 67 kB 00:00 (79/140): libssh-0.10.5-1.fc39.x86_64.rpm 5.0 MB/s | 211 kB 00:00 (80/140): libssh-config-0.10.5-1.fc39.noarch.rp 222 kB/s | 9.0 kB 00:00 (81/140): libsepol-3.5-1.fc39.x86_64.rpm 909 kB/s | 324 kB 00:00 (82/140): libsolv-0.7.24-5.fc39.x86_64.rpm 1.2 MB/s | 425 kB 00:00 (83/140): libtasn1-4.19.0-2.fc38.x86_64.rpm 762 kB/s | 74 kB 00:00 (84/140): libstdc++-13.1.1-4.fc39.x86_64.rpm 2.8 MB/s | 861 kB 00:00 (85/140): libtirpc-1.3.3-1.rc1.fc39.x86_64.rpm 1.1 MB/s | 93 kB 00:00 (86/140): libuuid-2.39.1-2.fc39.x86_64.rpm 674 kB/s | 28 kB 00:00 (87/140): libunistring1.0-1.0-1.fc38.x86_64.rpm 4.0 MB/s | 539 kB 00:00 (88/140): libverto-0.3.2-5.fc38.x86_64.rpm 483 kB/s | 21 kB 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rpm-sequoia-1.4.1-1.fc39.x86_64.rpm 529 kB/s | 843 kB 00:01 (133/140): sqlite-libs-3.41.2-3.fc39.x86_64.rpm 624 kB/s | 669 kB 00:01 (134/140): tpm2-tss-4.0.1-3.fc38.x86_64.rpm 640 kB/s | 675 kB 00:01 (135/140): systemd-libs-253.5-6.fc39.x86_64.rpm 329 kB/s | 652 kB 00:01 (136/140): xz-libs-5.4.3-1.fc39.x86_64.rpm 312 kB/s | 108 kB 00:00 (137/140): zchunk-libs-1.3.1-1.fc39.x86_64.rpm 343 kB/s | 52 kB 00:00 (138/140): zlib-1.2.13-3.fc38.x86_64.rpm 389 kB/s | 95 kB 00:00 (139/140): tzdata-2023c-1.fc39.noarch.rpm 453 kB/s | 718 kB 00:01 (140/140): python3-libs-3.12.0~b3-2.fc39.x86_64 694 kB/s | 9.2 MB 00:13 -------------------------------------------------------------------------------- Total 3.0 MB/s | 58 MB 00:19 fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x18B8E74C: Userid : "Fedora (39) " Fingerprint: E8F2 3996 F232 1864 0CB4 4CBE 75CF 5AC4 18B8 E74C From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary Key imported successfully fedora 1.6 MB/s | 1.6 kB 00:00 GPG key at file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary (0x18B8E74C) is already installed fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0xEB10B464: Userid : "Fedora (38) " Fingerprint: 6A51 BBAB BA3D 5467 B617 1221 809A 8D7C EB10 B464 From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-38-primary Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-4.fc39.x86_64 1/1 Preparing : 1/1 Installing : libgcc-13.1.1-4.fc39.x86_64 1/140 Running scriptlet: libgcc-13.1.1-4.fc39.x86_64 1/140 Installing : tzdata-2023c-1.fc39.noarch 2/140 Installing : crypto-policies-20230614-1.git5f3458e.fc39.noarc 3/140 Running scriptlet: crypto-policies-20230614-1.git5f3458e.fc39.noarc 3/140 Installing : fedora-release-identity-basic-39-0.14.noarch 4/140 Installing : publicsuffix-list-dafsa-20230614-1.fc39.noarch 5/140 Installing : pcre2-syntax-10.42-1.fc38.1.noarch 6/140 Installing : ncurses-base-6.4-5.20230520.fc39.noarch 7/140 Installing : libssh-config-0.10.5-1.fc39.noarch 8/140 Installing : libreport-filesystem-2.17.11-2.fc39.noarch 9/140 Installing : fedora-gpg-keys-39-0.1.noarch 10/140 Installing : fedora-release-39-0.14.noarch 11/140 Installing : fedora-release-common-39-0.14.noarch 12/140 Installing : fedora-repos-rawhide-39-0.1.noarch 13/140 Installing : fedora-repos-39-0.1.noarch 14/140 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dbus-libs-1:1.14.8-1.fc39.x86_64 12/140 Verifying : dnf-data-4.16.1-3.fc39.noarch 13/140 Verifying : dnf-plugins-core-4.4.1-4.fc39.noarch 14/140 Verifying : elfutils-default-yama-scope-0.189-3.fc39.noarch 15/140 Verifying : elfutils-libelf-0.189-3.fc39.x86_64 16/140 Verifying : elfutils-libs-0.189-3.fc39.x86_64 17/140 Verifying : expat-2.5.0-2.fc38.x86_64 18/140 Verifying : fedora-gpg-keys-39-0.1.noarch 19/140 Verifying : fedora-release-39-0.14.noarch 20/140 Verifying : fedora-release-common-39-0.14.noarch 21/140 Verifying : fedora-release-identity-basic-39-0.14.noarch 22/140 Verifying : fedora-repos-39-0.1.noarch 23/140 Verifying : fedora-repos-rawhide-39-0.1.noarch 24/140 Verifying : file-libs-5.44-4.fc39.x86_64 25/140 Verifying : filesystem-3.18-4.fc39.x86_64 26/140 Verifying : findutils-1:4.9.0-4.fc39.x86_64 27/140 Verifying : fmt-10.0.0-2.fc39.x86_64 28/140 Verifying : gawk-5.2.2-1.fc39.x86_64 29/140 Verifying : gdbm-libs-1:1.23-3.fc38.x86_64 30/140 Verifying : glib2-2.76.3-1.fc39.x86_64 31/140 Verifying : glibc-2.37.9000-15.fc39.x86_64 32/140 Verifying : glibc-common-2.37.9000-15.fc39.x86_64 33/140 Verifying : glibc-minimal-langpack-2.37.9000-15.fc39.x86_64 34/140 Verifying : gmp-1:6.2.1-4.fc38.x86_64 35/140 Verifying : gnupg2-2.4.2-2.fc39.x86_64 36/140 Verifying : gnutls-3.8.0-6.fc39.x86_64 37/140 Verifying : gpgme-1.20.0-4.fc39.x86_64 38/140 Verifying : grep-3.11-1.fc39.x86_64 39/140 Verifying : ima-evm-utils-1.5-1.fc39.x86_64 40/140 Verifying : json-c-0.16-4.fc38.x86_64 41/140 Verifying : keyutils-libs-1.6.1-6.fc38.x86_64 42/140 Verifying : krb5-libs-1.21-1.fc39.x86_64 43/140 Verifying : libacl-2.3.1-7.fc39.x86_64 44/140 Verifying : libarchive-3.6.1-5.fc39.x86_64 45/140 Verifying : libassuan-2.5.6-1.fc39.x86_64 46/140 Verifying : libattr-2.5.1-7.fc39.x86_64 47/140 Verifying : libb2-0.98.1-8.fc38.x86_64 48/140 Verifying : libblkid-2.39.1-2.fc39.x86_64 49/140 Verifying : libbrotli-1.0.9-12.fc39.x86_64 50/140 Verifying : libcap-2.48-6.fc38.x86_64 51/140 Verifying : libcap-ng-0.8.3-6.fc39.x86_64 52/140 Verifying : libcom_err-1.47.0-1.fc39.x86_64 53/140 Verifying : libcomps-0.1.19-2.fc39.x86_64 54/140 Verifying : libcurl-8.1.2-1.fc39.x86_64 55/140 Verifying : libdnf-0.70.1-4.fc39.x86_64 56/140 Verifying : libdnf5-5.0.15-3.fc39.x86_64 57/140 Verifying : libeconf-0.4.0-5.fc38.x86_64 58/140 Verifying : libevent-2.1.12-8.fc38.x86_64 59/140 Verifying : libffi-3.4.4-3.fc39.x86_64 60/140 Verifying : libfsverity-1.4-9.fc38.x86_64 61/140 Verifying : libgcc-13.1.1-4.fc39.x86_64 62/140 Verifying : libgcrypt-1.10.2-1.fc39.x86_64 63/140 Verifying : libgomp-13.1.1-4.fc39.x86_64 64/140 Verifying : libgpg-error-1.47-1.fc39.x86_64 65/140 Verifying : libidn2-2.3.4-2.fc38.x86_64 66/140 Verifying : libksba-1.6.4-1.fc39.x86_64 67/140 Verifying : libmodulemd-2.15.0-4.fc39.x86_64 68/140 Verifying : libmount-2.39.1-2.fc39.x86_64 69/140 Verifying : libnghttp2-1.54.0-1.fc39.x86_64 70/140 Verifying : libnsl2-2.0.0-5.fc38.x86_64 71/140 Verifying : libpsl-0.21.2-3.fc39.x86_64 72/140 Verifying : librepo-1.15.1-3.fc39.x86_64 73/140 Verifying : libreport-filesystem-2.17.11-2.fc39.noarch 74/140 Verifying : libselinux-3.5-4.fc39.x86_64 75/140 Verifying : libsemanage-3.5-3.fc39.x86_64 76/140 Verifying : libsepol-3.5-1.fc39.x86_64 77/140 Verifying : libsigsegv-2.14-4.fc38.x86_64 78/140 Verifying : libsmartcols-2.39.1-2.fc39.x86_64 79/140 Verifying : libsolv-0.7.24-5.fc39.x86_64 80/140 Verifying : libssh-0.10.5-1.fc39.x86_64 81/140 Verifying : libssh-config-0.10.5-1.fc39.noarch 82/140 Verifying : libstdc++-13.1.1-4.fc39.x86_64 83/140 Verifying : libtasn1-4.19.0-2.fc38.x86_64 84/140 Verifying : libtirpc-1.3.3-1.rc1.fc39.x86_64 85/140 Verifying : libunistring-1.1-3.fc38.x86_64 86/140 Verifying : libunistring1.0-1.0-1.fc38.x86_64 87/140 Verifying : libuuid-2.39.1-2.fc39.x86_64 88/140 Verifying : libverto-0.3.2-5.fc38.x86_64 89/140 Verifying : libxcrypt-4.4.36-1.fc39.x86_64 90/140 Verifying : libxml2-2.10.4-2.fc39.x86_64 91/140 Verifying : libyaml-0.2.5-9.fc38.x86_64 92/140 Verifying : libzstd-1.5.5-1.fc39.x86_64 93/140 Verifying : lua-libs-5.4.4-9.fc39.x86_64 94/140 Verifying : lz4-libs-1.9.4-3.fc39.x86_64 95/140 Verifying : mpdecimal-2.5.1-6.fc38.x86_64 96/140 Verifying : mpfr-4.1.1-3.fc38.x86_64 97/140 Verifying : ncurses-base-6.4-5.20230520.fc39.noarch 98/140 Verifying : ncurses-libs-6.4-5.20230520.fc39.x86_64 99/140 Verifying : nettle-3.9.1-1.fc39.x86_64 100/140 Verifying : npth-1.6-13.fc39.x86_64 101/140 Verifying : openldap-2.6.4-2.fc39.x86_64 102/140 Verifying : openssl-libs-1:3.0.8-2.fc39.x86_64 103/140 Verifying : p11-kit-0.24.1-6.fc38.x86_64 104/140 Verifying : p11-kit-trust-0.24.1-6.fc38.x86_64 105/140 Verifying : pcre2-10.42-1.fc38.1.x86_64 106/140 Verifying : pcre2-syntax-10.42-1.fc38.1.noarch 107/140 Verifying : popt-1.19-2.fc38.x86_64 108/140 Verifying : publicsuffix-list-dafsa-20230614-1.fc39.noarch 109/140 Verifying : python-pip-wheel-23.1.2-2.fc39.noarch 110/140 Verifying : python3-3.12.0~b3-2.fc39.x86_64 111/140 Verifying : python3-dateutil-1:2.8.2-9.fc39.noarch 112/140 Verifying : python3-dbus-1.3.2-3.fc39.x86_64 113/140 Verifying : python3-distro-1.8.0-5.fc39.noarch 114/140 Verifying : python3-dnf-4.16.1-3.fc39.noarch 115/140 Verifying : python3-dnf-plugins-core-4.4.1-4.fc39.noarch 116/140 Verifying : python3-gpg-1.20.0-4.fc39.x86_64 117/140 Verifying : python3-hawkey-0.70.1-4.fc39.x86_64 118/140 Verifying : python3-libcomps-0.1.19-2.fc39.x86_64 119/140 Verifying : python3-libdnf-0.70.1-4.fc39.x86_64 120/140 Verifying : python3-libs-3.12.0~b3-2.fc39.x86_64 121/140 Verifying : python3-rpm-4.18.91-7.fc39.x86_64 122/140 Verifying : python3-six-1.16.0-11.fc39.noarch 123/140 Verifying : python3-systemd-235-4.fc39.x86_64 124/140 Verifying : readline-8.2-3.fc38.x86_64 125/140 Verifying : rpm-4.18.91-7.fc39.x86_64 126/140 Verifying : rpm-build-libs-4.18.91-7.fc39.x86_64 127/140 Verifying : rpm-libs-4.18.91-7.fc39.x86_64 128/140 Verifying : rpm-sequoia-1.4.1-1.fc39.x86_64 129/140 Verifying : rpm-sign-libs-4.18.91-7.fc39.x86_64 130/140 Verifying : sed-4.8-12.fc38.x86_64 131/140 Verifying : setup-2.14.3-3.fc39.noarch 132/140 Verifying : shadow-utils-2:4.13-7.fc39.x86_64 133/140 Verifying : sqlite-libs-3.41.2-3.fc39.x86_64 134/140 Verifying : systemd-libs-253.5-6.fc39.x86_64 135/140 Verifying : tpm2-tss-4.0.1-3.fc38.x86_64 136/140 Verifying : tzdata-2023c-1.fc39.noarch 137/140 Verifying : xz-libs-5.4.3-1.fc39.x86_64 138/140 Verifying : zchunk-libs-1.3.1-1.fc39.x86_64 139/140 Verifying : zlib-1.2.13-3.fc38.x86_64 140/140 Installed products updated. Installed: alternatives-1.24-1.fc39.x86_64 audit-libs-3.1.1-3.fc39.x86_64 basesystem-11-17.fc39.noarch bash-5.2.15-3.fc38.x86_64 bzip2-libs-1.0.8-13.fc38.x86_64 ca-certificates-2023.2.60-2.fc38.noarch coreutils-9.3-1.fc39.x86_64 coreutils-common-9.3-1.fc39.x86_64 crypto-policies-20230614-1.git5f3458e.fc39.noarch curl-8.1.2-1.fc39.x86_64 cyrus-sasl-lib-2.1.28-10.fc39.x86_64 dbus-libs-1:1.14.8-1.fc39.x86_64 dnf-data-4.16.1-3.fc39.noarch dnf-plugins-core-4.4.1-4.fc39.noarch elfutils-default-yama-scope-0.189-3.fc39.noarch elfutils-libelf-0.189-3.fc39.x86_64 elfutils-libs-0.189-3.fc39.x86_64 expat-2.5.0-2.fc38.x86_64 fedora-gpg-keys-39-0.1.noarch fedora-release-39-0.14.noarch fedora-release-common-39-0.14.noarch fedora-release-identity-basic-39-0.14.noarch fedora-repos-39-0.1.noarch fedora-repos-rawhide-39-0.1.noarch file-libs-5.44-4.fc39.x86_64 filesystem-3.18-4.fc39.x86_64 findutils-1:4.9.0-4.fc39.x86_64 fmt-10.0.0-2.fc39.x86_64 gawk-5.2.2-1.fc39.x86_64 gdbm-libs-1:1.23-3.fc38.x86_64 glib2-2.76.3-1.fc39.x86_64 glibc-2.37.9000-15.fc39.x86_64 glibc-common-2.37.9000-15.fc39.x86_64 glibc-minimal-langpack-2.37.9000-15.fc39.x86_64 gmp-1:6.2.1-4.fc38.x86_64 gnupg2-2.4.2-2.fc39.x86_64 gnutls-3.8.0-6.fc39.x86_64 gpgme-1.20.0-4.fc39.x86_64 grep-3.11-1.fc39.x86_64 ima-evm-utils-1.5-1.fc39.x86_64 json-c-0.16-4.fc38.x86_64 keyutils-libs-1.6.1-6.fc38.x86_64 krb5-libs-1.21-1.fc39.x86_64 libacl-2.3.1-7.fc39.x86_64 libarchive-3.6.1-5.fc39.x86_64 libassuan-2.5.6-1.fc39.x86_64 libattr-2.5.1-7.fc39.x86_64 libb2-0.98.1-8.fc38.x86_64 libblkid-2.39.1-2.fc39.x86_64 libbrotli-1.0.9-12.fc39.x86_64 libcap-2.48-6.fc38.x86_64 libcap-ng-0.8.3-6.fc39.x86_64 libcom_err-1.47.0-1.fc39.x86_64 libcomps-0.1.19-2.fc39.x86_64 libcurl-8.1.2-1.fc39.x86_64 libdnf-0.70.1-4.fc39.x86_64 libdnf5-5.0.15-3.fc39.x86_64 libeconf-0.4.0-5.fc38.x86_64 libevent-2.1.12-8.fc38.x86_64 libffi-3.4.4-3.fc39.x86_64 libfsverity-1.4-9.fc38.x86_64 libgcc-13.1.1-4.fc39.x86_64 libgcrypt-1.10.2-1.fc39.x86_64 libgomp-13.1.1-4.fc39.x86_64 libgpg-error-1.47-1.fc39.x86_64 libidn2-2.3.4-2.fc38.x86_64 libksba-1.6.4-1.fc39.x86_64 libmodulemd-2.15.0-4.fc39.x86_64 libmount-2.39.1-2.fc39.x86_64 libnghttp2-1.54.0-1.fc39.x86_64 libnsl2-2.0.0-5.fc38.x86_64 libpsl-0.21.2-3.fc39.x86_64 librepo-1.15.1-3.fc39.x86_64 libreport-filesystem-2.17.11-2.fc39.noarch libselinux-3.5-4.fc39.x86_64 libsemanage-3.5-3.fc39.x86_64 libsepol-3.5-1.fc39.x86_64 libsigsegv-2.14-4.fc38.x86_64 libsmartcols-2.39.1-2.fc39.x86_64 libsolv-0.7.24-5.fc39.x86_64 libssh-0.10.5-1.fc39.x86_64 libssh-config-0.10.5-1.fc39.noarch libstdc++-13.1.1-4.fc39.x86_64 libtasn1-4.19.0-2.fc38.x86_64 libtirpc-1.3.3-1.rc1.fc39.x86_64 libunistring-1.1-3.fc38.x86_64 libunistring1.0-1.0-1.fc38.x86_64 libuuid-2.39.1-2.fc39.x86_64 libverto-0.3.2-5.fc38.x86_64 libxcrypt-4.4.36-1.fc39.x86_64 libxml2-2.10.4-2.fc39.x86_64 libyaml-0.2.5-9.fc38.x86_64 libzstd-1.5.5-1.fc39.x86_64 lua-libs-5.4.4-9.fc39.x86_64 lz4-libs-1.9.4-3.fc39.x86_64 mpdecimal-2.5.1-6.fc38.x86_64 mpfr-4.1.1-3.fc38.x86_64 ncurses-base-6.4-5.20230520.fc39.noarch ncurses-libs-6.4-5.20230520.fc39.x86_64 nettle-3.9.1-1.fc39.x86_64 npth-1.6-13.fc39.x86_64 openldap-2.6.4-2.fc39.x86_64 openssl-libs-1:3.0.8-2.fc39.x86_64 p11-kit-0.24.1-6.fc38.x86_64 p11-kit-trust-0.24.1-6.fc38.x86_64 pcre2-10.42-1.fc38.1.x86_64 pcre2-syntax-10.42-1.fc38.1.noarch popt-1.19-2.fc38.x86_64 publicsuffix-list-dafsa-20230614-1.fc39.noarch python-pip-wheel-23.1.2-2.fc39.noarch python3-3.12.0~b3-2.fc39.x86_64 python3-dateutil-1:2.8.2-9.fc39.noarch python3-dbus-1.3.2-3.fc39.x86_64 python3-distro-1.8.0-5.fc39.noarch python3-dnf-4.16.1-3.fc39.noarch python3-dnf-plugins-core-4.4.1-4.fc39.noarch python3-gpg-1.20.0-4.fc39.x86_64 python3-hawkey-0.70.1-4.fc39.x86_64 python3-libcomps-0.1.19-2.fc39.x86_64 python3-libdnf-0.70.1-4.fc39.x86_64 python3-libs-3.12.0~b3-2.fc39.x86_64 python3-rpm-4.18.91-7.fc39.x86_64 python3-six-1.16.0-11.fc39.noarch python3-systemd-235-4.fc39.x86_64 readline-8.2-3.fc38.x86_64 rpm-4.18.91-7.fc39.x86_64 rpm-build-libs-4.18.91-7.fc39.x86_64 rpm-libs-4.18.91-7.fc39.x86_64 rpm-sequoia-1.4.1-1.fc39.x86_64 rpm-sign-libs-4.18.91-7.fc39.x86_64 sed-4.8-12.fc38.x86_64 setup-2.14.3-3.fc39.noarch shadow-utils-2:4.13-7.fc39.x86_64 sqlite-libs-3.41.2-3.fc39.x86_64 systemd-libs-253.5-6.fc39.x86_64 tpm2-tss-4.0.1-3.fc38.x86_64 tzdata-2023c-1.fc39.noarch xz-libs-5.4.3-1.fc39.x86_64 zchunk-libs-1.3.1-1.fc39.x86_64 zlib-1.2.13-3.fc38.x86_64 Complete! Finish(bootstrap): installing dnf tooling Start(bootstrap): creating root cache Finish(bootstrap): creating root cache Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin Mock Version: 4.1 INFO: Mock Version: 4.1 INFO: Package manager dnf detected and used (direct choice) Start: installing minimal buildroot with dnf No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 41 kB/s | 2.1 kB 00:00 Copr repository 7.3 MB/s | 1.2 MB 00:00 Additional repo copr_rezso_ML 35 kB/s | 1.8 kB 00:00 Additional repo copr_rezso_CUDA 37 kB/s | 1.8 kB 00:00 Additional repo http_developer_download_nvidia_ 149 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 155 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 147 kB/s | 3.5 kB 00:00 fedora 479 kB/s | 22 kB 00:00 fedora 2.5 MB/s | 3.7 MB 00:01 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing group/module packages: bash x86_64 5.2.15-3.fc38 fedora 1.8 M bzip2 x86_64 1.0.8-13.fc38 fedora 52 k coreutils x86_64 9.3-1.fc39 fedora 1.1 M cpio x86_64 2.14-2.fc39 fedora 279 k diffutils x86_64 3.10-2.fc39 fedora 398 k fedora-release-common noarch 39-0.14 fedora 17 k findutils x86_64 1:4.9.0-4.fc39 fedora 491 k gawk x86_64 5.2.2-1.fc39 fedora 1.1 M glibc-minimal-langpack x86_64 2.37.9000-15.fc39 fedora 61 k grep x86_64 3.11-1.fc39 fedora 298 k gzip x86_64 1.12-3.fc38 fedora 166 k info x86_64 7.0.3-2.fc39 fedora 182 k patch x86_64 2.7.6-21.fc39 fedora 126 k redhat-rpm-config noarch 260-1.fc39 fedora 84 k rpm-build x86_64 4.18.91-7.fc39 fedora 78 k sed x86_64 4.8-12.fc38 fedora 306 k shadow-utils x86_64 2:4.13-7.fc39 fedora 1.3 M tar x86_64 2:1.34-8.fc39 fedora 888 k unzip x86_64 6.0-60.fc38 fedora 184 k util-linux x86_64 2.39.1-2.fc39 fedora 1.2 M which x86_64 2.21-39.fc39 fedora 42 k xz x86_64 5.4.3-1.fc39 fedora 555 k Installing dependencies: alternatives x86_64 1.24-1.fc39 fedora 39 k ansible-srpm-macros noarch 1-10.fc39 fedora 21 k audit-libs x86_64 3.1.1-3.fc39 fedora 117 k authselect x86_64 1.4.2-2.fc38 fedora 144 k authselect-libs x86_64 1.4.2-2.fc38 fedora 249 k basesystem noarch 11-17.fc39 fedora 7.0 k binutils x86_64 2.40-9.fc39 fedora 5.6 M binutils-gold x86_64 2.40-9.fc39 fedora 797 k bzip2-libs x86_64 1.0.8-13.fc38 fedora 41 k ca-certificates noarch 2023.2.60-2.fc38 fedora 845 k coreutils-common x86_64 9.3-1.fc39 fedora 2.1 M cracklib x86_64 2.9.7-31.fc38 fedora 92 k crypto-policies noarch 20230614-1.git5f3458e.fc39 fedora 94 k curl x86_64 8.1.2-1.fc39 fedora 345 k cyrus-sasl-lib x86_64 2.1.28-10.fc39 fedora 792 k debugedit x86_64 5.0-9.fc39 fedora 77 k dwz x86_64 0.15-2.fc38 fedora 135 k ed x86_64 1.19-2.fc38 fedora 78 k efi-srpm-macros noarch 5-8.fc39 fedora 22 k elfutils x86_64 0.189-3.fc39 fedora 537 k elfutils-debuginfod-client x86_64 0.189-3.fc39 fedora 38 k elfutils-default-yama-scope noarch 0.189-3.fc39 fedora 13 k elfutils-libelf x86_64 0.189-3.fc39 fedora 195 k elfutils-libs x86_64 0.189-3.fc39 fedora 258 k fedora-gpg-keys noarch 39-0.1 fedora 126 k fedora-release noarch 39-0.14 fedora 6.6 k fedora-release-identity-basic noarch 39-0.14 fedora 7.4 k fedora-repos noarch 39-0.1 fedora 9.4 k fedora-repos-rawhide noarch 39-0.1 fedora 9.0 k file x86_64 5.44-4.fc39 fedora 49 k file-libs x86_64 5.44-4.fc39 fedora 729 k filesystem x86_64 3.18-4.fc39 fedora 1.1 M fonts-srpm-macros noarch 1:2.0.5-11.fc38 fedora 26 k fpc-srpm-macros noarch 1.3-7.fc38 fedora 7.8 k gdb-minimal x86_64 13.2-2.fc39 fedora 4.2 M gdbm-libs x86_64 1:1.23-3.fc38 fedora 56 k ghc-srpm-macros noarch 1.6.1-1.fc38 fedora 8.0 k glibc x86_64 2.37.9000-15.fc39 fedora 2.1 M glibc-common x86_64 2.37.9000-15.fc39 fedora 339 k glibc-gconv-extra x86_64 2.37.9000-15.fc39 fedora 1.6 M gmp x86_64 1:6.2.1-4.fc38 fedora 313 k gnat-srpm-macros noarch 6-2.fc38 fedora 8.8 k go-srpm-macros noarch 3.2.0-3.fc39 fedora 27 k jansson x86_64 2.13.1-6.fc38 fedora 44 k kernel-srpm-macros noarch 1.0-19.fc39 fedora 10 k keyutils-libs x86_64 1.6.1-6.fc38 fedora 31 k krb5-libs x86_64 1.21-1.fc39 fedora 765 k libacl x86_64 2.3.1-7.fc39 fedora 23 k libarchive x86_64 3.6.1-5.fc39 fedora 400 k libattr x86_64 2.5.1-7.fc39 fedora 18 k libblkid x86_64 2.39.1-2.fc39 fedora 116 k libbrotli x86_64 1.0.9-12.fc39 fedora 317 k libcap x86_64 2.48-6.fc38 fedora 67 k libcap-ng x86_64 0.8.3-6.fc39 fedora 32 k libcom_err x86_64 1.47.0-1.fc39 fedora 26 k libcurl x86_64 8.1.2-1.fc39 fedora 323 k libdb x86_64 5.3.28-55.fc38 fedora 758 k libeconf x86_64 0.4.0-5.fc38 fedora 27 k libevent x86_64 2.1.12-8.fc38 fedora 257 k libfdisk x86_64 2.39.1-2.fc39 fedora 162 k libffi x86_64 3.4.4-3.fc39 fedora 40 k libgcc x86_64 13.1.1-4.fc39 fedora 107 k libgomp x86_64 13.1.1-4.fc39 fedora 317 k libidn2 x86_64 2.3.4-2.fc38 fedora 160 k libmount x86_64 2.39.1-2.fc39 fedora 155 k libnghttp2 x86_64 1.54.0-1.fc39 fedora 75 k libnsl2 x86_64 2.0.0-5.fc38 fedora 30 k libpkgconf x86_64 1.9.4-2.fc39 fedora 38 k libpsl x86_64 0.21.2-3.fc39 fedora 63 k libpwquality x86_64 1.4.5-5.fc39 fedora 119 k libselinux x86_64 3.5-4.fc39 fedora 87 k libsemanage x86_64 3.5-3.fc39 fedora 119 k libsepol x86_64 3.5-1.fc39 fedora 324 k libsigsegv x86_64 2.14-4.fc38 fedora 27 k libsmartcols x86_64 2.39.1-2.fc39 fedora 67 k libssh x86_64 0.10.5-1.fc39 fedora 211 k libssh-config noarch 0.10.5-1.fc39 fedora 9.0 k libstdc++ x86_64 13.1.1-4.fc39 fedora 861 k libtasn1 x86_64 4.19.0-2.fc38 fedora 74 k libtirpc x86_64 1.3.3-1.rc1.fc39 fedora 93 k libunistring x86_64 1.1-3.fc38 fedora 545 k libunistring1.0 x86_64 1.0-1.fc38 fedora 539 k libutempter x86_64 1.2.1-9.fc39 fedora 26 k libuuid x86_64 2.39.1-2.fc39 fedora 28 k libverto x86_64 0.3.2-5.fc38 fedora 21 k libxcrypt x86_64 4.4.36-1.fc39 fedora 119 k libxml2 x86_64 2.10.4-2.fc39 fedora 701 k libzstd x86_64 1.5.5-1.fc39 fedora 308 k lua-libs x86_64 5.4.4-9.fc39 fedora 133 k lua-srpm-macros noarch 1-8.fc38 fedora 8.6 k lz4-libs x86_64 1.9.4-3.fc39 fedora 67 k mpfr x86_64 4.1.1-3.fc38 fedora 600 k ncurses-base noarch 6.4-5.20230520.fc39 fedora 88 k ncurses-libs x86_64 6.4-5.20230520.fc39 fedora 336 k ocaml-srpm-macros noarch 7-3.fc38 fedora 13 k openblas-srpm-macros noarch 2-13.fc38 fedora 7.5 k openldap x86_64 2.6.4-2.fc39 fedora 255 k openssl-libs x86_64 1:3.0.8-2.fc39 fedora 2.1 M p11-kit x86_64 0.24.1-6.fc38 fedora 359 k p11-kit-trust x86_64 0.24.1-6.fc38 fedora 136 k package-notes-srpm-macros noarch 0.5-8.fc39 fedora 11 k pam x86_64 1.5.3-1.fc39 fedora 547 k pam-libs x86_64 1.5.3-1.fc39 fedora 57 k pcre2 x86_64 10.42-1.fc38.1 fedora 234 k pcre2-syntax noarch 10.42-1.fc38.1 fedora 144 k perl-srpm-macros noarch 1-48.fc38 fedora 8.4 k pkgconf x86_64 1.9.4-2.fc39 fedora 42 k pkgconf-m4 noarch 1.9.4-2.fc39 fedora 14 k pkgconf-pkg-config x86_64 1.9.4-2.fc39 fedora 9.5 k popt x86_64 1.19-2.fc38 fedora 67 k publicsuffix-list-dafsa noarch 20230614-1.fc39 fedora 57 k pyproject-srpm-macros noarch 1.9.0-1.fc39 fedora 15 k python-srpm-macros noarch 3.12-1.fc39 fedora 25 k qt5-srpm-macros noarch 5.15.10-1.fc39 fedora 7.8 k qt6-srpm-macros noarch 6.5.1-1.fc39 fedora 9.2 k readline x86_64 8.2-3.fc38 fedora 212 k rpm x86_64 4.18.91-7.fc39 fedora 529 k rpm-build-libs x86_64 4.18.91-7.fc39 fedora 96 k rpm-libs x86_64 4.18.91-7.fc39 fedora 309 k rpm-sequoia x86_64 1.4.1-1.fc39 fedora 843 k rpmautospec-rpm-macros noarch 0.3.5-3.fc39 fedora 8.7 k rust-srpm-macros noarch 24-2.fc39 fedora 12 k setup noarch 2.14.3-3.fc39 fedora 152 k sqlite-libs x86_64 3.41.2-3.fc39 fedora 669 k systemd-libs x86_64 253.5-6.fc39 fedora 652 k tzdata noarch 2023c-1.fc39 fedora 718 k util-linux-core x86_64 2.39.1-2.fc39 fedora 494 k xxhash-libs x86_64 0.8.1-5.fc39 fedora 40 k xz-libs x86_64 5.4.3-1.fc39 fedora 108 k zip x86_64 3.0-36.fc38 fedora 265 k zlib x86_64 1.2.13-3.fc38 fedora 95 k zstd x86_64 1.5.5-1.fc39 fedora 482 k Installing Groups: Buildsystem building group Transaction Summary ================================================================================ Install 154 Packages Total size: 53 M Installed size: 181 M Downloading Packages: [SKIPPED] alternatives-1.24-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] ansible-srpm-macros-1-10.fc39.noarch.rpm: Already downloaded [SKIPPED] audit-libs-3.1.1-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] authselect-1.4.2-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] authselect-libs-1.4.2-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] basesystem-11-17.fc39.noarch.rpm: Already downloaded [SKIPPED] bash-5.2.15-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] binutils-2.40-9.fc39.x86_64.rpm: Already downloaded [SKIPPED] binutils-gold-2.40-9.fc39.x86_64.rpm: Already downloaded [SKIPPED] bzip2-1.0.8-13.fc38.x86_64.rpm: Already downloaded [SKIPPED] bzip2-libs-1.0.8-13.fc38.x86_64.rpm: Already downloaded [SKIPPED] ca-certificates-2023.2.60-2.fc38.noarch.rpm: Already downloaded [SKIPPED] coreutils-9.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] coreutils-common-9.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] cpio-2.14-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] cracklib-2.9.7-31.fc38.x86_64.rpm: Already downloaded [SKIPPED] crypto-policies-20230614-1.git5f3458e.fc39.noarch.rpm: Already downloaded [SKIPPED] curl-8.1.2-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] cyrus-sasl-lib-2.1.28-10.fc39.x86_64.rpm: Already downloaded [SKIPPED] debugedit-5.0-9.fc39.x86_64.rpm: Already downloaded [SKIPPED] diffutils-3.10-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] dwz-0.15-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] ed-1.19-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] efi-srpm-macros-5-8.fc39.noarch.rpm: Already downloaded [SKIPPED] elfutils-0.189-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] elfutils-debuginfod-client-0.189-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] elfutils-default-yama-scope-0.189-3.fc39.noarch.rpm: Already downloaded [SKIPPED] elfutils-libelf-0.189-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] elfutils-libs-0.189-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] fedora-gpg-keys-39-0.1.noarch.rpm: Already downloaded [SKIPPED] fedora-release-39-0.14.noarch.rpm: Already downloaded [SKIPPED] fedora-release-common-39-0.14.noarch.rpm: Already downloaded [SKIPPED] fedora-release-identity-basic-39-0.14.noarch.rpm: Already downloaded [SKIPPED] fedora-repos-39-0.1.noarch.rpm: Already downloaded [SKIPPED] fedora-repos-rawhide-39-0.1.noarch.rpm: Already downloaded [SKIPPED] file-5.44-4.fc39.x86_64.rpm: Already downloaded [SKIPPED] file-libs-5.44-4.fc39.x86_64.rpm: Already downloaded [SKIPPED] filesystem-3.18-4.fc39.x86_64.rpm: Already downloaded [SKIPPED] findutils-4.9.0-4.fc39.x86_64.rpm: Already downloaded [SKIPPED] fonts-srpm-macros-2.0.5-11.fc38.noarch.rpm: Already downloaded [SKIPPED] fpc-srpm-macros-1.3-7.fc38.noarch.rpm: Already downloaded [SKIPPED] gawk-5.2.2-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] gdb-minimal-13.2-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] gdbm-libs-1.23-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] ghc-srpm-macros-1.6.1-1.fc38.noarch.rpm: Already downloaded [SKIPPED] glibc-2.37.9000-15.fc39.x86_64.rpm: Already downloaded [SKIPPED] glibc-common-2.37.9000-15.fc39.x86_64.rpm: Already downloaded [SKIPPED] glibc-gconv-extra-2.37.9000-15.fc39.x86_64.rpm: Already downloaded [SKIPPED] glibc-minimal-langpack-2.37.9000-15.fc39.x86_64.rpm: Already downloaded [SKIPPED] gmp-6.2.1-4.fc38.x86_64.rpm: Already downloaded [SKIPPED] gnat-srpm-macros-6-2.fc38.noarch.rpm: Already downloaded [SKIPPED] go-srpm-macros-3.2.0-3.fc39.noarch.rpm: Already downloaded [SKIPPED] grep-3.11-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] gzip-1.12-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] info-7.0.3-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] jansson-2.13.1-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] kernel-srpm-macros-1.0-19.fc39.noarch.rpm: Already downloaded [SKIPPED] keyutils-libs-1.6.1-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] krb5-libs-1.21-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libacl-2.3.1-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] libarchive-3.6.1-5.fc39.x86_64.rpm: Already downloaded [SKIPPED] libattr-2.5.1-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] libblkid-2.39.1-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] libbrotli-1.0.9-12.fc39.x86_64.rpm: Already downloaded [SKIPPED] libcap-2.48-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] libcap-ng-0.8.3-6.fc39.x86_64.rpm: Already downloaded [SKIPPED] libcom_err-1.47.0-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libcurl-8.1.2-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libdb-5.3.28-55.fc38.x86_64.rpm: Already downloaded [SKIPPED] libeconf-0.4.0-5.fc38.x86_64.rpm: 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libsigsegv-2.14-4.fc38.x86_64.rpm: Already downloaded [SKIPPED] libsmartcols-2.39.1-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] libssh-0.10.5-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libssh-config-0.10.5-1.fc39.noarch.rpm: Already downloaded [SKIPPED] libstdc++-13.1.1-4.fc39.x86_64.rpm: Already downloaded [SKIPPED] libtasn1-4.19.0-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] libtirpc-1.3.3-1.rc1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libunistring-1.1-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] libunistring1.0-1.0-1.fc38.x86_64.rpm: Already downloaded [SKIPPED] libutempter-1.2.1-9.fc39.x86_64.rpm: Already downloaded [SKIPPED] libuuid-2.39.1-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] libverto-0.3.2-5.fc38.x86_64.rpm: Already downloaded [SKIPPED] libxcrypt-4.4.36-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libxml2-2.10.4-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] libzstd-1.5.5-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] lua-libs-5.4.4-9.fc39.x86_64.rpm: Already downloaded [SKIPPED] lua-srpm-macros-1-8.fc38.noarch.rpm: Already downloaded [SKIPPED] lz4-libs-1.9.4-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] mpfr-4.1.1-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] ncurses-base-6.4-5.20230520.fc39.noarch.rpm: Already downloaded [SKIPPED] ncurses-libs-6.4-5.20230520.fc39.x86_64.rpm: Already downloaded [SKIPPED] ocaml-srpm-macros-7-3.fc38.noarch.rpm: Already downloaded [SKIPPED] openblas-srpm-macros-2-13.fc38.noarch.rpm: Already downloaded [SKIPPED] openldap-2.6.4-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] openssl-libs-3.0.8-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] p11-kit-0.24.1-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] p11-kit-trust-0.24.1-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] package-notes-srpm-macros-0.5-8.fc39.noarch.rpm: Already downloaded [SKIPPED] pam-1.5.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] pam-libs-1.5.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] patch-2.7.6-21.fc39.x86_64.rpm: Already downloaded [SKIPPED] pcre2-10.42-1.fc38.1.x86_64.rpm: Already downloaded [SKIPPED] pcre2-syntax-10.42-1.fc38.1.noarch.rpm: Already downloaded [SKIPPED] perl-srpm-macros-1-48.fc38.noarch.rpm: Already downloaded [SKIPPED] pkgconf-1.9.4-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] pkgconf-m4-1.9.4-2.fc39.noarch.rpm: Already downloaded [SKIPPED] pkgconf-pkg-config-1.9.4-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] popt-1.19-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] publicsuffix-list-dafsa-20230614-1.fc39.noarch.rpm: Already downloaded [SKIPPED] pyproject-srpm-macros-1.9.0-1.fc39.noarch.rpm: Already downloaded [SKIPPED] python-srpm-macros-3.12-1.fc39.noarch.rpm: Already downloaded [SKIPPED] qt5-srpm-macros-5.15.10-1.fc39.noarch.rpm: Already downloaded [SKIPPED] qt6-srpm-macros-6.5.1-1.fc39.noarch.rpm: Already downloaded [SKIPPED] readline-8.2-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] redhat-rpm-config-260-1.fc39.noarch.rpm: Already downloaded [SKIPPED] rpm-4.18.91-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] rpm-build-4.18.91-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] rpm-build-libs-4.18.91-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] rpm-libs-4.18.91-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] rpm-sequoia-1.4.1-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] rpmautospec-rpm-macros-0.3.5-3.fc39.noarch.rpm: Already downloaded [SKIPPED] rust-srpm-macros-24-2.fc39.noarch.rpm: Already downloaded [SKIPPED] sed-4.8-12.fc38.x86_64.rpm: Already downloaded [SKIPPED] setup-2.14.3-3.fc39.noarch.rpm: Already downloaded [SKIPPED] shadow-utils-4.13-7.fc39.x86_64.rpm: Already downloaded [SKIPPED] sqlite-libs-3.41.2-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] systemd-libs-253.5-6.fc39.x86_64.rpm: Already downloaded [SKIPPED] tar-1.34-8.fc39.x86_64.rpm: Already downloaded [SKIPPED] tzdata-2023c-1.fc39.noarch.rpm: Already downloaded [SKIPPED] unzip-6.0-60.fc38.x86_64.rpm: Already downloaded [SKIPPED] util-linux-2.39.1-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] util-linux-core-2.39.1-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] which-2.21-39.fc39.x86_64.rpm: Already downloaded [SKIPPED] xxhash-libs-0.8.1-5.fc39.x86_64.rpm: Already downloaded [SKIPPED] xz-5.4.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] xz-libs-5.4.3-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] zip-3.0-36.fc38.x86_64.rpm: Already downloaded [SKIPPED] zlib-1.2.13-3.fc38.x86_64.rpm: Already downloaded [SKIPPED] zstd-1.5.5-1.fc39.x86_64.rpm: Already downloaded fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0x18B8E74C: Userid : "Fedora (39) " Fingerprint: E8F2 3996 F232 1864 0CB4 4CBE 75CF 5AC4 18B8 E74C From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary Key imported successfully fedora 1.6 MB/s | 1.6 kB 00:00 GPG key at file:///usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-39-primary (0x18B8E74C) is already installed fedora 1.6 MB/s | 1.6 kB 00:00 Importing GPG key 0xEB10B464: Userid : "Fedora (38) " Fingerprint: 6A51 BBAB BA3D 5467 B617 1221 809A 8D7C EB10 B464 From : /usr/share/distribution-gpg-keys/fedora/RPM-GPG-KEY-fedora-38-primary Key imported successfully Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Running scriptlet: filesystem-3.18-4.fc39.x86_64 1/1 Preparing : 1/1 Installing : libgcc-13.1.1-4.fc39.x86_64 1/154 Running scriptlet: libgcc-13.1.1-4.fc39.x86_64 1/154 Installing : crypto-policies-20230614-1.git5f3458e.fc39.noarc 2/154 Running scriptlet: crypto-policies-20230614-1.git5f3458e.fc39.noarc 2/154 Installing : tzdata-2023c-1.fc39.noarch 3/154 Installing : fedora-release-identity-basic-39-0.14.noarch 4/154 Installing : rust-srpm-macros-24-2.fc39.noarch 5/154 Installing : qt6-srpm-macros-6.5.1-1.fc39.noarch 6/154 Installing : qt5-srpm-macros-5.15.10-1.fc39.noarch 7/154 Installing : pyproject-srpm-macros-1.9.0-1.fc39.noarch 8/154 Installing : publicsuffix-list-dafsa-20230614-1.fc39.noarch 9/154 Installing : pkgconf-m4-1.9.4-2.fc39.noarch 10/154 Installing : perl-srpm-macros-1-48.fc38.noarch 11/154 Installing : pcre2-syntax-10.42-1.fc38.1.noarch 12/154 Installing : package-notes-srpm-macros-0.5-8.fc39.noarch 13/154 Installing : openblas-srpm-macros-2-13.fc38.noarch 14/154 Installing : ocaml-srpm-macros-7-3.fc38.noarch 15/154 Installing : ncurses-base-6.4-5.20230520.fc39.noarch 16/154 Installing : libssh-config-0.10.5-1.fc39.noarch 17/154 Installing : kernel-srpm-macros-1.0-19.fc39.noarch 18/154 Installing : gnat-srpm-macros-6-2.fc38.noarch 19/154 Installing : ghc-srpm-macros-1.6.1-1.fc38.noarch 20/154 Installing : fpc-srpm-macros-1.3-7.fc38.noarch 21/154 Installing : fedora-gpg-keys-39-0.1.noarch 22/154 Installing : fedora-release-39-0.14.noarch 23/154 Installing : fedora-release-common-39-0.14.noarch 24/154 Installing : fedora-repos-rawhide-39-0.1.noarch 25/154 Installing : fedora-repos-39-0.1.noarch 26/154 Installing : setup-2.14.3-3.fc39.noarch 27/154 Running scriptlet: setup-2.14.3-3.fc39.noarch 27/154 Installing : filesystem-3.18-4.fc39.x86_64 28/154 Installing : basesystem-11-17.fc39.noarch 29/154 Installing : glibc-gconv-extra-2.37.9000-15.fc39.x86_64 30/154 Running scriptlet: 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openssl-libs-1:3.0.8-2.fc39.x86_64 110/154 Verifying : p11-kit-0.24.1-6.fc38.x86_64 111/154 Verifying : p11-kit-trust-0.24.1-6.fc38.x86_64 112/154 Verifying : package-notes-srpm-macros-0.5-8.fc39.noarch 113/154 Verifying : pam-1.5.3-1.fc39.x86_64 114/154 Verifying : pam-libs-1.5.3-1.fc39.x86_64 115/154 Verifying : patch-2.7.6-21.fc39.x86_64 116/154 Verifying : pcre2-10.42-1.fc38.1.x86_64 117/154 Verifying : pcre2-syntax-10.42-1.fc38.1.noarch 118/154 Verifying : perl-srpm-macros-1-48.fc38.noarch 119/154 Verifying : pkgconf-1.9.4-2.fc39.x86_64 120/154 Verifying : pkgconf-m4-1.9.4-2.fc39.noarch 121/154 Verifying : pkgconf-pkg-config-1.9.4-2.fc39.x86_64 122/154 Verifying : popt-1.19-2.fc38.x86_64 123/154 Verifying : publicsuffix-list-dafsa-20230614-1.fc39.noarch 124/154 Verifying : pyproject-srpm-macros-1.9.0-1.fc39.noarch 125/154 Verifying : python-srpm-macros-3.12-1.fc39.noarch 126/154 Verifying : qt5-srpm-macros-5.15.10-1.fc39.noarch 127/154 Verifying : qt6-srpm-macros-6.5.1-1.fc39.noarch 128/154 Verifying : readline-8.2-3.fc38.x86_64 129/154 Verifying : redhat-rpm-config-260-1.fc39.noarch 130/154 Verifying : rpm-4.18.91-7.fc39.x86_64 131/154 Verifying : rpm-build-4.18.91-7.fc39.x86_64 132/154 Verifying : rpm-build-libs-4.18.91-7.fc39.x86_64 133/154 Verifying : rpm-libs-4.18.91-7.fc39.x86_64 134/154 Verifying : rpm-sequoia-1.4.1-1.fc39.x86_64 135/154 Verifying : rpmautospec-rpm-macros-0.3.5-3.fc39.noarch 136/154 Verifying : rust-srpm-macros-24-2.fc39.noarch 137/154 Verifying : sed-4.8-12.fc38.x86_64 138/154 Verifying : setup-2.14.3-3.fc39.noarch 139/154 Verifying : shadow-utils-2:4.13-7.fc39.x86_64 140/154 Verifying : sqlite-libs-3.41.2-3.fc39.x86_64 141/154 Verifying : systemd-libs-253.5-6.fc39.x86_64 142/154 Verifying : tar-2:1.34-8.fc39.x86_64 143/154 Verifying : tzdata-2023c-1.fc39.noarch 144/154 Verifying : unzip-6.0-60.fc38.x86_64 145/154 Verifying : util-linux-2.39.1-2.fc39.x86_64 146/154 Verifying : util-linux-core-2.39.1-2.fc39.x86_64 147/154 Verifying : which-2.21-39.fc39.x86_64 148/154 Verifying : xxhash-libs-0.8.1-5.fc39.x86_64 149/154 Verifying : xz-5.4.3-1.fc39.x86_64 150/154 Verifying : xz-libs-5.4.3-1.fc39.x86_64 151/154 Verifying : zip-3.0-36.fc38.x86_64 152/154 Verifying : zlib-1.2.13-3.fc38.x86_64 153/154 Verifying : zstd-1.5.5-1.fc39.x86_64 154/154 Installed: alternatives-1.24-1.fc39.x86_64 ansible-srpm-macros-1-10.fc39.noarch audit-libs-3.1.1-3.fc39.x86_64 authselect-1.4.2-2.fc38.x86_64 authselect-libs-1.4.2-2.fc38.x86_64 basesystem-11-17.fc39.noarch bash-5.2.15-3.fc38.x86_64 binutils-2.40-9.fc39.x86_64 binutils-gold-2.40-9.fc39.x86_64 bzip2-1.0.8-13.fc38.x86_64 bzip2-libs-1.0.8-13.fc38.x86_64 ca-certificates-2023.2.60-2.fc38.noarch coreutils-9.3-1.fc39.x86_64 coreutils-common-9.3-1.fc39.x86_64 cpio-2.14-2.fc39.x86_64 cracklib-2.9.7-31.fc38.x86_64 crypto-policies-20230614-1.git5f3458e.fc39.noarch curl-8.1.2-1.fc39.x86_64 cyrus-sasl-lib-2.1.28-10.fc39.x86_64 debugedit-5.0-9.fc39.x86_64 diffutils-3.10-2.fc39.x86_64 dwz-0.15-2.fc38.x86_64 ed-1.19-2.fc38.x86_64 efi-srpm-macros-5-8.fc39.noarch elfutils-0.189-3.fc39.x86_64 elfutils-debuginfod-client-0.189-3.fc39.x86_64 elfutils-default-yama-scope-0.189-3.fc39.noarch elfutils-libelf-0.189-3.fc39.x86_64 elfutils-libs-0.189-3.fc39.x86_64 fedora-gpg-keys-39-0.1.noarch fedora-release-39-0.14.noarch fedora-release-common-39-0.14.noarch fedora-release-identity-basic-39-0.14.noarch fedora-repos-39-0.1.noarch fedora-repos-rawhide-39-0.1.noarch file-5.44-4.fc39.x86_64 file-libs-5.44-4.fc39.x86_64 filesystem-3.18-4.fc39.x86_64 findutils-1:4.9.0-4.fc39.x86_64 fonts-srpm-macros-1:2.0.5-11.fc38.noarch fpc-srpm-macros-1.3-7.fc38.noarch gawk-5.2.2-1.fc39.x86_64 gdb-minimal-13.2-2.fc39.x86_64 gdbm-libs-1:1.23-3.fc38.x86_64 ghc-srpm-macros-1.6.1-1.fc38.noarch glibc-2.37.9000-15.fc39.x86_64 glibc-common-2.37.9000-15.fc39.x86_64 glibc-gconv-extra-2.37.9000-15.fc39.x86_64 glibc-minimal-langpack-2.37.9000-15.fc39.x86_64 gmp-1:6.2.1-4.fc38.x86_64 gnat-srpm-macros-6-2.fc38.noarch go-srpm-macros-3.2.0-3.fc39.noarch grep-3.11-1.fc39.x86_64 gzip-1.12-3.fc38.x86_64 info-7.0.3-2.fc39.x86_64 jansson-2.13.1-6.fc38.x86_64 kernel-srpm-macros-1.0-19.fc39.noarch keyutils-libs-1.6.1-6.fc38.x86_64 krb5-libs-1.21-1.fc39.x86_64 libacl-2.3.1-7.fc39.x86_64 libarchive-3.6.1-5.fc39.x86_64 libattr-2.5.1-7.fc39.x86_64 libblkid-2.39.1-2.fc39.x86_64 libbrotli-1.0.9-12.fc39.x86_64 libcap-2.48-6.fc38.x86_64 libcap-ng-0.8.3-6.fc39.x86_64 libcom_err-1.47.0-1.fc39.x86_64 libcurl-8.1.2-1.fc39.x86_64 libdb-5.3.28-55.fc38.x86_64 libeconf-0.4.0-5.fc38.x86_64 libevent-2.1.12-8.fc38.x86_64 libfdisk-2.39.1-2.fc39.x86_64 libffi-3.4.4-3.fc39.x86_64 libgcc-13.1.1-4.fc39.x86_64 libgomp-13.1.1-4.fc39.x86_64 libidn2-2.3.4-2.fc38.x86_64 libmount-2.39.1-2.fc39.x86_64 libnghttp2-1.54.0-1.fc39.x86_64 libnsl2-2.0.0-5.fc38.x86_64 libpkgconf-1.9.4-2.fc39.x86_64 libpsl-0.21.2-3.fc39.x86_64 libpwquality-1.4.5-5.fc39.x86_64 libselinux-3.5-4.fc39.x86_64 libsemanage-3.5-3.fc39.x86_64 libsepol-3.5-1.fc39.x86_64 libsigsegv-2.14-4.fc38.x86_64 libsmartcols-2.39.1-2.fc39.x86_64 libssh-0.10.5-1.fc39.x86_64 libssh-config-0.10.5-1.fc39.noarch libstdc++-13.1.1-4.fc39.x86_64 libtasn1-4.19.0-2.fc38.x86_64 libtirpc-1.3.3-1.rc1.fc39.x86_64 libunistring-1.1-3.fc38.x86_64 libunistring1.0-1.0-1.fc38.x86_64 libutempter-1.2.1-9.fc39.x86_64 libuuid-2.39.1-2.fc39.x86_64 libverto-0.3.2-5.fc38.x86_64 libxcrypt-4.4.36-1.fc39.x86_64 libxml2-2.10.4-2.fc39.x86_64 libzstd-1.5.5-1.fc39.x86_64 lua-libs-5.4.4-9.fc39.x86_64 lua-srpm-macros-1-8.fc38.noarch lz4-libs-1.9.4-3.fc39.x86_64 mpfr-4.1.1-3.fc38.x86_64 ncurses-base-6.4-5.20230520.fc39.noarch ncurses-libs-6.4-5.20230520.fc39.x86_64 ocaml-srpm-macros-7-3.fc38.noarch openblas-srpm-macros-2-13.fc38.noarch openldap-2.6.4-2.fc39.x86_64 openssl-libs-1:3.0.8-2.fc39.x86_64 p11-kit-0.24.1-6.fc38.x86_64 p11-kit-trust-0.24.1-6.fc38.x86_64 package-notes-srpm-macros-0.5-8.fc39.noarch pam-1.5.3-1.fc39.x86_64 pam-libs-1.5.3-1.fc39.x86_64 patch-2.7.6-21.fc39.x86_64 pcre2-10.42-1.fc38.1.x86_64 pcre2-syntax-10.42-1.fc38.1.noarch perl-srpm-macros-1-48.fc38.noarch pkgconf-1.9.4-2.fc39.x86_64 pkgconf-m4-1.9.4-2.fc39.noarch pkgconf-pkg-config-1.9.4-2.fc39.x86_64 popt-1.19-2.fc38.x86_64 publicsuffix-list-dafsa-20230614-1.fc39.noarch pyproject-srpm-macros-1.9.0-1.fc39.noarch python-srpm-macros-3.12-1.fc39.noarch qt5-srpm-macros-5.15.10-1.fc39.noarch qt6-srpm-macros-6.5.1-1.fc39.noarch readline-8.2-3.fc38.x86_64 redhat-rpm-config-260-1.fc39.noarch rpm-4.18.91-7.fc39.x86_64 rpm-build-4.18.91-7.fc39.x86_64 rpm-build-libs-4.18.91-7.fc39.x86_64 rpm-libs-4.18.91-7.fc39.x86_64 rpm-sequoia-1.4.1-1.fc39.x86_64 rpmautospec-rpm-macros-0.3.5-3.fc39.noarch rust-srpm-macros-24-2.fc39.noarch sed-4.8-12.fc38.x86_64 setup-2.14.3-3.fc39.noarch shadow-utils-2:4.13-7.fc39.x86_64 sqlite-libs-3.41.2-3.fc39.x86_64 systemd-libs-253.5-6.fc39.x86_64 tar-2:1.34-8.fc39.x86_64 tzdata-2023c-1.fc39.noarch unzip-6.0-60.fc38.x86_64 util-linux-2.39.1-2.fc39.x86_64 util-linux-core-2.39.1-2.fc39.x86_64 which-2.21-39.fc39.x86_64 xxhash-libs-0.8.1-5.fc39.x86_64 xz-5.4.3-1.fc39.x86_64 xz-libs-5.4.3-1.fc39.x86_64 zip-3.0-36.fc38.x86_64 zlib-1.2.13-3.fc38.x86_64 zstd-1.5.5-1.fc39.x86_64 Complete! Finish: installing minimal buildroot with dnf Start: creating root cache Finish: creating root cache Finish: chroot init INFO: Installed packages: INFO: ocaml-srpm-macros-7-3.fc38.noarch p11-kit-0.24.1-6.fc38.x86_64 libuuid-2.39.1-2.fc39.x86_64 pcre2-10.42-1.fc38.1.x86_64 libmount-2.39.1-2.fc39.x86_64 bash-5.2.15-3.fc38.x86_64 pkgconf-pkg-config-1.9.4-2.fc39.x86_64 cpio-2.14-2.fc39.x86_64 xz-libs-5.4.3-1.fc39.x86_64 libsigsegv-2.14-4.fc38.x86_64 ncurses-libs-6.4-5.20230520.fc39.x86_64 gzip-1.12-3.fc38.x86_64 redhat-rpm-config-260-1.fc39.noarch pkgconf-1.9.4-2.fc39.x86_64 file-libs-5.44-4.fc39.x86_64 kernel-srpm-macros-1.0-19.fc39.noarch patch-2.7.6-21.fc39.x86_64 curl-8.1.2-1.fc39.x86_64 gawk-5.2.2-1.fc39.x86_64 zlib-1.2.13-3.fc38.x86_64 libxcrypt-4.4.36-1.fc39.x86_64 xz-5.4.3-1.fc39.x86_64 unzip-6.0-60.fc38.x86_64 sed-4.8-12.fc38.x86_64 authselect-libs-1.4.2-2.fc38.x86_64 python-srpm-macros-3.12-1.fc39.noarch libnghttp2-1.54.0-1.fc39.x86_64 fedora-repos-rawhide-39-0.1.noarch libarchive-3.6.1-5.fc39.x86_64 cracklib-2.9.7-31.fc38.x86_64 bzip2-1.0.8-13.fc38.x86_64 zip-3.0-36.fc38.x86_64 findutils-4.9.0-4.fc39.x86_64 pcre2-syntax-10.42-1.fc38.1.noarch libidn2-2.3.4-2.fc38.x86_64 basesystem-11-17.fc39.noarch libssh-config-0.10.5-1.fc39.noarch rpm-build-libs-4.18.91-7.fc39.x86_64 libdb-5.3.28-55.fc38.x86_64 mpfr-4.1.1-3.fc38.x86_64 libstdc++-13.1.1-4.fc39.x86_64 ca-certificates-2023.2.60-2.fc38.noarch libsepol-3.5-1.fc39.x86_64 ncurses-base-6.4-5.20230520.fc39.noarch fedora-release-common-39-0.14.noarch popt-1.19-2.fc38.x86_64 krb5-libs-1.21-1.fc39.x86_64 shadow-utils-4.13-7.fc39.x86_64 libpkgconf-1.9.4-2.fc39.x86_64 go-srpm-macros-3.2.0-3.fc39.noarch libsemanage-3.5-3.fc39.x86_64 fedora-gpg-keys-39-0.1.noarch libverto-0.3.2-5.fc38.x86_64 readline-8.2-3.fc38.x86_64 tar-1.34-8.fc39.x86_64 openssl-libs-3.0.8-2.fc39.x86_64 keyutils-libs-1.6.1-6.fc38.x86_64 libbrotli-1.0.9-12.fc39.x86_64 rpm-4.18.91-7.fc39.x86_64 file-5.44-4.fc39.x86_64 pam-1.5.3-1.fc39.x86_64 diffutils-3.10-2.fc39.x86_64 gpg-pubkey-eb10b464-6202d9c6 rpm-libs-4.18.91-7.fc39.x86_64 lua-srpm-macros-1-8.fc38.noarch openblas-srpm-macros-2-13.fc38.noarch p11-kit-trust-0.24.1-6.fc38.x86_64 libxml2-2.10.4-2.fc39.x86_64 libpwquality-1.4.5-5.fc39.x86_64 libselinux-3.5-4.fc39.x86_64 binutils-gold-2.40-9.fc39.x86_64 qt5-srpm-macros-5.15.10-1.fc39.noarch pam-libs-1.5.3-1.fc39.x86_64 libpsl-0.21.2-3.fc39.x86_64 ghc-srpm-macros-1.6.1-1.fc38.noarch util-linux-2.39.1-2.fc39.x86_64 fedora-release-39-0.14.noarch libfdisk-2.39.1-2.fc39.x86_64 ed-1.19-2.fc38.x86_64 binutils-2.40-9.fc39.x86_64 elfutils-default-yama-scope-0.189-3.fc39.noarch grep-3.11-1.fc39.x86_64 libtirpc-1.3.3-1.rc1.fc39.x86_64 setup-2.14.3-3.fc39.noarch libattr-2.5.1-7.fc39.x86_64 glibc-minimal-langpack-2.37.9000-15.fc39.x86_64 coreutils-common-9.3-1.fc39.x86_64 efi-srpm-macros-5-8.fc39.noarch libblkid-2.39.1-2.fc39.x86_64 lua-libs-5.4.4-9.fc39.x86_64 elfutils-libelf-0.189-3.fc39.x86_64 qt6-srpm-macros-6.5.1-1.fc39.noarch libacl-2.3.1-7.fc39.x86_64 audit-libs-3.1.1-3.fc39.x86_64 libsmartcols-2.39.1-2.fc39.x86_64 util-linux-core-2.39.1-2.fc39.x86_64 libnsl2-2.0.0-5.fc38.x86_64 debugedit-5.0-9.fc39.x86_64 gmp-6.2.1-4.fc38.x86_64 rpm-build-4.18.91-7.fc39.x86_64 libcap-ng-0.8.3-6.fc39.x86_64 gpg-pubkey-18b8e74c-62f2920f bzip2-libs-1.0.8-13.fc38.x86_64 xxhash-libs-0.8.1-5.fc39.x86_64 coreutils-9.3-1.fc39.x86_64 tzdata-2023c-1.fc39.noarch libcom_err-1.47.0-1.fc39.x86_64 lz4-libs-1.9.4-3.fc39.x86_64 cyrus-sasl-lib-2.1.28-10.fc39.x86_64 glibc-gconv-extra-2.37.9000-15.fc39.x86_64 libssh-0.10.5-1.fc39.x86_64 systemd-libs-253.5-6.fc39.x86_64 libtasn1-4.19.0-2.fc38.x86_64 libffi-3.4.4-3.fc39.x86_64 libunistring-1.1-3.fc38.x86_64 alternatives-1.24-1.fc39.x86_64 package-notes-srpm-macros-0.5-8.fc39.noarch libcurl-8.1.2-1.fc39.x86_64 jansson-2.13.1-6.fc38.x86_64 dwz-0.15-2.fc38.x86_64 libutempter-1.2.1-9.fc39.x86_64 info-7.0.3-2.fc39.x86_64 zstd-1.5.5-1.fc39.x86_64 libunistring1.0-1.0-1.fc38.x86_64 sqlite-libs-3.41.2-3.fc39.x86_64 fedora-repos-39-0.1.noarch openldap-2.6.4-2.fc39.x86_64 publicsuffix-list-dafsa-20230614-1.fc39.noarch pkgconf-m4-1.9.4-2.fc39.noarch libeconf-0.4.0-5.fc38.x86_64 rust-srpm-macros-24-2.fc39.noarch libzstd-1.5.5-1.fc39.x86_64 glibc-2.37.9000-15.fc39.x86_64 gnat-srpm-macros-6-2.fc38.noarch libgcc-13.1.1-4.fc39.x86_64 authselect-1.4.2-2.fc38.x86_64 rpm-sequoia-1.4.1-1.fc39.x86_64 gdb-minimal-13.2-2.fc39.x86_64 perl-srpm-macros-1-48.fc38.noarch elfutils-0.189-3.fc39.x86_64 rpmautospec-rpm-macros-0.3.5-3.fc39.noarch crypto-policies-20230614-1.git5f3458e.fc39.noarch gdbm-libs-1.23-3.fc38.x86_64 ansible-srpm-macros-1-10.fc39.noarch glibc-common-2.37.9000-15.fc39.x86_64 libgomp-13.1.1-4.fc39.x86_64 fonts-srpm-macros-2.0.5-11.fc38.noarch libcap-2.48-6.fc38.x86_64 fedora-release-identity-basic-39-0.14.noarch pyproject-srpm-macros-1.9.0-1.fc39.noarch which-2.21-39.fc39.x86_64 elfutils-libs-0.189-3.fc39.x86_64 filesystem-3.18-4.fc39.x86_64 fpc-srpm-macros-1.3-7.fc38.noarch elfutils-debuginfod-client-0.189-3.fc39.x86_64 libevent-2.1.12-8.fc38.x86_64 Start: buildsrpm Start: rpmbuild -bs Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Finish: rpmbuild -bs INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.rpm.log /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.librepo.log /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.log Finish: buildsrpm INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-qtr2ma8g/litex-pythondata-cpu-cva6/litex-pythondata-cpu-cva6.spec) Config(child) 1 minutes 35 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running (timeout=172800): unbuffer mock --rebuild /var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1688731775.510429 -r /var/lib/copr-rpmbuild/results/configs/child.cfg INFO: mock.py version 4.1 starting (python version = 3.11.3, NVR = mock-4.1-1.fc38)... Start(bootstrap): init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish(bootstrap): init plugins Start: init plugins INFO: tmpfs initialized INFO: selinux enabled INFO: chroot_scan: initialized INFO: compress_logs: initialized Finish: init plugins INFO: Signal handler active Start: run INFO: Start(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm) Config(fedora-rawhide-x86_64) Start: clean chroot Finish: clean chroot Start(bootstrap): chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1688731775.510429/root. INFO: reusing tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1688731775.510429/root. INFO: calling preinit hooks INFO: enabled root cache INFO: enabled package manager cache Start(bootstrap): cleaning package manager metadata Finish(bootstrap): cleaning package manager metadata INFO: enabled HW Info plugin Mock Version: 4.1 INFO: Mock Version: 4.1 INFO: Package manager dnf detected and used (fallback) Finish(bootstrap): chroot init Start: chroot init INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root. INFO: calling preinit hooks INFO: enabled root cache Start: unpacking root cache Finish: unpacking root cache INFO: enabled package manager cache Start: cleaning package manager metadata Finish: cleaning package manager metadata INFO: enabled HW Info plugin Mock Version: 4.1 INFO: Mock Version: 4.1 INFO: Package manager dnf detected and used (direct choice) Start: dnf update No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 8.6 kB/s | 2.1 kB 00:00 Additional repo copr_rezso_ML 31 kB/s | 1.8 kB 00:00 Additional repo copr_rezso_CUDA 35 kB/s | 1.8 kB 00:00 Additional repo http_developer_download_nvidia_ 138 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 156 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 155 kB/s | 3.5 kB 00:00 fedora 431 kB/s | 22 kB 00:00 Dependencies resolved. Nothing to do. Complete! Finish: dnf update Finish: chroot init Start: build phase for litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Start: build setup for litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1654300800 Wrote: /builddir/build/SRPMS/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm No matches found for the following disable plugin patterns: local, spacewalk, versionlock Copr repository 34 kB/s | 2.1 kB 00:00 Additional repo copr_rezso_ML 30 kB/s | 1.8 kB 00:00 Additional repo copr_rezso_CUDA 30 kB/s | 1.8 kB 00:00 Additional repo http_developer_download_nvidia_ 154 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 157 kB/s | 3.5 kB 00:00 Additional repo http_developer_download_nvidia_ 157 kB/s | 3.5 kB 00:00 fedora 532 kB/s | 22 kB 00:00 Dependencies resolved. ================================================================================ Package Arch Version Repo Size ================================================================================ Installing: git x86_64 2.41.0-1.fc39 fedora 54 k python3-devel x86_64 3.12.0~b3-2.fc39 fedora 310 k python3-setuptools noarch 67.7.2-5.fc39 fedora 1.5 M Installing dependencies: expat x86_64 2.5.0-2.fc38 fedora 110 k git-core x86_64 2.41.0-1.fc39 fedora 4.4 M git-core-doc noarch 2.41.0-1.fc39 fedora 2.8 M groff-base x86_64 1.22.4-11.fc38 fedora 1.1 M less x86_64 633-1.fc39 fedora 175 k libb2 x86_64 0.98.1-8.fc38 fedora 25 k libcbor x86_64 0.10.2-1.fc39 fedora 58 k libedit x86_64 3.1-45.20221030cvs.fc38 fedora 107 k libfido2 x86_64 1.13.0-2.fc39 fedora 98 k mpdecimal x86_64 2.5.1-6.fc38 fedora 89 k ncurses x86_64 6.4-5.20230520.fc39 fedora 416 k openssh x86_64 9.3p1-3.fc39 fedora 437 k openssh-clients x86_64 9.3p1-3.fc39 fedora 734 k perl-Carp noarch 1.54-1.fc39 fedora 29 k perl-Class-Struct noarch 0.66-497.fc39 fedora 23 k perl-DynaLoader x86_64 1.52-497.fc39 fedora 27 k perl-Encode x86_64 4:3.19-493.fc38 fedora 1.7 M perl-Errno x86_64 1.36-497.fc39 fedora 16 k perl-Error noarch 1:0.17029-12.fc39 fedora 40 k perl-Exporter noarch 5.77-490.fc38 fedora 31 k perl-Fcntl x86_64 1.15-497.fc39 fedora 22 k perl-File-Basename noarch 2.85-497.fc39 fedora 18 k perl-File-Find noarch 1.40-497.fc39 fedora 27 k perl-File-Path noarch 2.18-490.fc38 fedora 35 k perl-File-Temp noarch 1:0.231.100-490.fc38 fedora 59 k perl-File-stat noarch 1.12-497.fc39 fedora 18 k perl-Getopt-Long noarch 1:2.54-2.fc38 fedora 60 k perl-Getopt-Std noarch 1.13-497.fc39 fedora 17 k perl-Git noarch 2.41.0-1.fc39 fedora 41 k perl-HTTP-Tiny noarch 0.086-1.fc39 fedora 55 k perl-IO x86_64 1.50-497.fc39 fedora 93 k perl-IPC-Open3 noarch 1.22-497.fc39 fedora 24 k perl-MIME-Base64 x86_64 3.16-490.fc38 fedora 30 k perl-POSIX x86_64 2.03-497.fc39 fedora 99 k perl-PathTools x86_64 3.89-1.fc39 fedora 87 k perl-Pod-Escapes noarch 1:1.07-490.fc38 fedora 20 k perl-Pod-Perldoc noarch 3.28.01-491.fc38 fedora 86 k perl-Pod-Simple noarch 1:3.45-2.fc39 fedora 219 k perl-Pod-Usage noarch 4:2.03-4.fc38 fedora 40 k perl-Scalar-List-Utils x86_64 5:1.63-491.fc39 fedora 72 k perl-SelectSaver noarch 1.02-497.fc39 fedora 13 k perl-Socket x86_64 4:2.037-1.fc39 fedora 55 k perl-Storable x86_64 1:3.32-1.fc39 fedora 98 k perl-Symbol noarch 1.09-497.fc39 fedora 15 k perl-Term-ANSIColor noarch 5.01-491.fc38 fedora 47 k perl-Term-Cap noarch 1.18-1.fc39 fedora 22 k perl-TermReadKey x86_64 2.38-16.fc38 fedora 35 k perl-Text-ParseWords noarch 3.31-490.fc38 fedora 16 k perl-Text-Tabs+Wrap noarch 2023.0511-1.fc39 fedora 22 k perl-Time-Local noarch 2:1.350-1.fc39 fedora 34 k perl-constant noarch 1.33-492.fc39 fedora 23 k perl-if noarch 0.61.000-497.fc39 fedora 15 k perl-interpreter x86_64 4:5.36.1-497.fc39 fedora 73 k perl-lib x86_64 0.65-497.fc39 fedora 16 k perl-libs x86_64 4:5.36.1-497.fc39 fedora 2.2 M perl-locale noarch 1.10-497.fc39 fedora 15 k perl-mro x86_64 1.26-497.fc39 fedora 30 k perl-overload noarch 1.35-497.fc39 fedora 47 k perl-overloading noarch 0.02-497.fc39 fedora 14 k perl-parent noarch 1:0.241-1.fc39 fedora 14 k perl-podlators noarch 1:5.01-2.fc38 fedora 125 k perl-vars noarch 1.05-497.fc39 fedora 14 k pyproject-rpm-macros noarch 1.9.0-1.fc39 fedora 42 k python-pip-wheel noarch 23.1.2-2.fc39 fedora 1.4 M python-rpm-macros noarch 3.12-1.fc39 fedora 19 k python3 x86_64 3.12.0~b3-2.fc39 fedora 26 k python3-libs x86_64 3.12.0~b3-2.fc39 fedora 9.2 M python3-packaging noarch 23.1-3.fc39 fedora 114 k python3-rpm-generators noarch 14-6.fc39 fedora 30 k python3-rpm-macros noarch 3.12-1.fc39 fedora 15 k Transaction Summary ================================================================================ Install 73 Packages Total size: 29 M Installed size: 121 M Downloading Packages: [SKIPPED] expat-2.5.0-2.fc38.x86_64.rpm: Already downloaded [SKIPPED] git-2.41.0-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] git-core-2.41.0-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] git-core-doc-2.41.0-1.fc39.noarch.rpm: Already downloaded [SKIPPED] groff-base-1.22.4-11.fc38.x86_64.rpm: Already downloaded [SKIPPED] less-633-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libb2-0.98.1-8.fc38.x86_64.rpm: Already downloaded [SKIPPED] libcbor-0.10.2-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] libedit-3.1-45.20221030cvs.fc38.x86_64.rpm: Already downloaded [SKIPPED] libfido2-1.13.0-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] mpdecimal-2.5.1-6.fc38.x86_64.rpm: Already downloaded [SKIPPED] ncurses-6.4-5.20230520.fc39.x86_64.rpm: Already downloaded [SKIPPED] openssh-9.3p1-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] openssh-clients-9.3p1-3.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Carp-1.54-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Class-Struct-0.66-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-DynaLoader-1.52-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Encode-3.19-493.fc38.x86_64.rpm: Already downloaded [SKIPPED] perl-Errno-1.36-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Error-0.17029-12.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Exporter-5.77-490.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Fcntl-1.15-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-File-Basename-2.85-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-File-Find-1.40-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-File-Path-2.18-490.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-File-Temp-0.231.100-490.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-File-stat-1.12-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Getopt-Long-2.54-2.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Getopt-Std-1.13-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Git-2.41.0-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-HTTP-Tiny-0.086-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-IO-1.50-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-IPC-Open3-1.22-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-MIME-Base64-3.16-490.fc38.x86_64.rpm: Already downloaded [SKIPPED] perl-POSIX-2.03-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-PathTools-3.89-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Pod-Escapes-1.07-490.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Pod-Perldoc-3.28.01-491.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Pod-Simple-3.45-2.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Pod-Usage-2.03-4.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Scalar-List-Utils-1.63-491.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-SelectSaver-1.02-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Socket-2.037-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Storable-3.32-1.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-Symbol-1.09-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Term-ANSIColor-5.01-491.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Term-Cap-1.18-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-TermReadKey-2.38-16.fc38.x86_64.rpm: Already downloaded [SKIPPED] perl-Text-ParseWords-3.31-490.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-Text-Tabs+Wrap-2023.0511-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-Time-Local-1.350-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-constant-1.33-492.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-if-0.61.000-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-interpreter-5.36.1-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-lib-0.65-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-libs-5.36.1-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-locale-1.10-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-mro-1.26-497.fc39.x86_64.rpm: Already downloaded [SKIPPED] perl-overload-1.35-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-overloading-0.02-497.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-parent-0.241-1.fc39.noarch.rpm: Already downloaded [SKIPPED] perl-podlators-5.01-2.fc38.noarch.rpm: Already downloaded [SKIPPED] perl-vars-1.05-497.fc39.noarch.rpm: Already downloaded [SKIPPED] pyproject-rpm-macros-1.9.0-1.fc39.noarch.rpm: Already downloaded [SKIPPED] python-pip-wheel-23.1.2-2.fc39.noarch.rpm: Already downloaded [SKIPPED] python-rpm-macros-3.12-1.fc39.noarch.rpm: Already downloaded [SKIPPED] python3-3.12.0~b3-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] python3-devel-3.12.0~b3-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] python3-libs-3.12.0~b3-2.fc39.x86_64.rpm: Already downloaded [SKIPPED] python3-packaging-23.1-3.fc39.noarch.rpm: Already downloaded [SKIPPED] python3-rpm-generators-14-6.fc39.noarch.rpm: Already downloaded [SKIPPED] python3-rpm-macros-3.12-1.fc39.noarch.rpm: Already downloaded [SKIPPED] python3-setuptools-67.7.2-5.fc39.noarch.rpm: Already downloaded Running transaction check Transaction check succeeded. Running transaction test Transaction test succeeded. Running transaction Preparing : 1/1 Installing : python-rpm-macros-3.12-1.fc39.noarch 1/73 Installing : python3-rpm-macros-3.12-1.fc39.noarch 2/73 Installing : expat-2.5.0-2.fc38.x86_64 3/73 Installing : pyproject-rpm-macros-1.9.0-1.fc39.noarch 4/73 Installing : python-pip-wheel-23.1.2-2.fc39.noarch 5/73 Installing : openssh-9.3p1-3.fc39.x86_64 6/73 Installing : ncurses-6.4-5.20230520.fc39.x86_64 7/73 Installing : mpdecimal-2.5.1-6.fc38.x86_64 8/73 Installing : libedit-3.1-45.20221030cvs.fc38.x86_64 9/73 Installing : libcbor-0.10.2-1.fc39.x86_64 10/73 Installing : libfido2-1.13.0-2.fc39.x86_64 11/73 Installing : openssh-clients-9.3p1-3.fc39.x86_64 12/73 Running scriptlet: openssh-clients-9.3p1-3.fc39.x86_64 12/73 Installing : libb2-0.98.1-8.fc38.x86_64 13/73 Installing : python3-3.12.0~b3-2.fc39.x86_64 14/73 Installing : python3-libs-3.12.0~b3-2.fc39.x86_64 15/73 Installing : python3-packaging-23.1-3.fc39.noarch 16/73 Installing : python3-rpm-generators-14-6.fc39.noarch 17/73 Installing : less-633-1.fc39.x86_64 18/73 Installing : git-core-2.41.0-1.fc39.x86_64 19/73 Installing : git-core-doc-2.41.0-1.fc39.noarch 20/73 Running scriptlet: groff-base-1.22.4-11.fc38.x86_64 21/73 Installing : groff-base-1.22.4-11.fc38.x86_64 21/73 Running scriptlet: groff-base-1.22.4-11.fc38.x86_64 21/73 Installing : perl-Text-Tabs+Wrap-2023.0511-1.fc39.noarch 22/73 Installing : perl-if-0.61.000-497.fc39.noarch 23/73 Installing : perl-locale-1.10-497.fc39.noarch 24/73 Installing : perl-Time-Local-2:1.350-1.fc39.noarch 25/73 Installing : perl-File-Path-2.18-490.fc38.noarch 26/73 Installing : perl-Pod-Escapes-1:1.07-490.fc38.noarch 27/73 Installing : perl-Class-Struct-0.66-497.fc39.noarch 28/73 Installing : perl-Term-ANSIColor-5.01-491.fc38.noarch 29/73 Installing : perl-POSIX-2.03-497.fc39.x86_64 30/73 Installing : perl-IPC-Open3-1.22-497.fc39.noarch 31/73 Installing : perl-HTTP-Tiny-0.086-1.fc39.noarch 32/73 Installing : perl-File-Temp-1:0.231.100-490.fc38.noarch 33/73 Installing : perl-Term-Cap-1.18-1.fc39.noarch 34/73 Installing : perl-Pod-Simple-1:3.45-2.fc39.noarch 35/73 Installing : perl-Socket-4:2.037-1.fc39.x86_64 36/73 Installing : perl-SelectSaver-1.02-497.fc39.noarch 37/73 Installing : perl-Symbol-1.09-497.fc39.noarch 38/73 Installing : perl-File-stat-1.12-497.fc39.noarch 39/73 Installing : perl-podlators-1:5.01-2.fc38.noarch 40/73 Installing : perl-Pod-Perldoc-3.28.01-491.fc38.noarch 41/73 Installing : perl-Fcntl-1.15-497.fc39.x86_64 42/73 Installing : perl-Text-ParseWords-3.31-490.fc38.noarch 43/73 Installing : perl-mro-1.26-497.fc39.x86_64 44/73 Installing : perl-IO-1.50-497.fc39.x86_64 45/73 Installing : perl-overloading-0.02-497.fc39.noarch 46/73 Installing : perl-Pod-Usage-4:2.03-4.fc38.noarch 47/73 Installing : perl-Errno-1.36-497.fc39.x86_64 48/73 Installing : perl-File-Basename-2.85-497.fc39.noarch 49/73 Installing : perl-Getopt-Std-1.13-497.fc39.noarch 50/73 Installing : perl-MIME-Base64-3.16-490.fc38.x86_64 51/73 Installing : perl-Scalar-List-Utils-5:1.63-491.fc39.x86_64 52/73 Installing : perl-constant-1.33-492.fc39.noarch 53/73 Installing : perl-Storable-1:3.32-1.fc39.x86_64 54/73 Installing : perl-overload-1.35-497.fc39.noarch 55/73 Installing : perl-parent-1:0.241-1.fc39.noarch 56/73 Installing : perl-vars-1.05-497.fc39.noarch 57/73 Installing : perl-Getopt-Long-1:2.54-2.fc38.noarch 58/73 Installing : perl-Carp-1.54-1.fc39.noarch 59/73 Installing : perl-Exporter-5.77-490.fc38.noarch 60/73 Installing : perl-PathTools-3.89-1.fc39.x86_64 61/73 Installing : perl-DynaLoader-1.52-497.fc39.x86_64 62/73 Installing : perl-Encode-4:3.19-493.fc38.x86_64 63/73 Installing : perl-libs-4:5.36.1-497.fc39.x86_64 64/73 Installing : perl-interpreter-4:5.36.1-497.fc39.x86_64 65/73 Installing : perl-Error-1:0.17029-12.fc39.noarch 66/73 Installing : perl-File-Find-1.40-497.fc39.noarch 67/73 Installing : perl-TermReadKey-2.38-16.fc38.x86_64 68/73 Installing : perl-lib-0.65-497.fc39.x86_64 69/73 Installing : perl-Git-2.41.0-1.fc39.noarch 70/73 Installing : git-2.41.0-1.fc39.x86_64 71/73 Installing : python3-devel-3.12.0~b3-2.fc39.x86_64 72/73 Installing : python3-setuptools-67.7.2-5.fc39.noarch 73/73 Running scriptlet: python3-setuptools-67.7.2-5.fc39.noarch 73/73 Verifying : expat-2.5.0-2.fc38.x86_64 1/73 Verifying : git-2.41.0-1.fc39.x86_64 2/73 Verifying : git-core-2.41.0-1.fc39.x86_64 3/73 Verifying : git-core-doc-2.41.0-1.fc39.noarch 4/73 Verifying : groff-base-1.22.4-11.fc38.x86_64 5/73 Verifying : less-633-1.fc39.x86_64 6/73 Verifying : libb2-0.98.1-8.fc38.x86_64 7/73 Verifying : libcbor-0.10.2-1.fc39.x86_64 8/73 Verifying : libedit-3.1-45.20221030cvs.fc38.x86_64 9/73 Verifying : libfido2-1.13.0-2.fc39.x86_64 10/73 Verifying : mpdecimal-2.5.1-6.fc38.x86_64 11/73 Verifying : ncurses-6.4-5.20230520.fc39.x86_64 12/73 Verifying : openssh-9.3p1-3.fc39.x86_64 13/73 Verifying : openssh-clients-9.3p1-3.fc39.x86_64 14/73 Verifying : perl-Carp-1.54-1.fc39.noarch 15/73 Verifying : perl-Class-Struct-0.66-497.fc39.noarch 16/73 Verifying : perl-DynaLoader-1.52-497.fc39.x86_64 17/73 Verifying : perl-Encode-4:3.19-493.fc38.x86_64 18/73 Verifying : perl-Errno-1.36-497.fc39.x86_64 19/73 Verifying : perl-Error-1:0.17029-12.fc39.noarch 20/73 Verifying : perl-Exporter-5.77-490.fc38.noarch 21/73 Verifying : perl-Fcntl-1.15-497.fc39.x86_64 22/73 Verifying : perl-File-Basename-2.85-497.fc39.noarch 23/73 Verifying : perl-File-Find-1.40-497.fc39.noarch 24/73 Verifying : perl-File-Path-2.18-490.fc38.noarch 25/73 Verifying : perl-File-Temp-1:0.231.100-490.fc38.noarch 26/73 Verifying : perl-File-stat-1.12-497.fc39.noarch 27/73 Verifying : perl-Getopt-Long-1:2.54-2.fc38.noarch 28/73 Verifying : perl-Getopt-Std-1.13-497.fc39.noarch 29/73 Verifying : perl-Git-2.41.0-1.fc39.noarch 30/73 Verifying : perl-HTTP-Tiny-0.086-1.fc39.noarch 31/73 Verifying : perl-IO-1.50-497.fc39.x86_64 32/73 Verifying : perl-IPC-Open3-1.22-497.fc39.noarch 33/73 Verifying : perl-MIME-Base64-3.16-490.fc38.x86_64 34/73 Verifying : perl-POSIX-2.03-497.fc39.x86_64 35/73 Verifying : perl-PathTools-3.89-1.fc39.x86_64 36/73 Verifying : perl-Pod-Escapes-1:1.07-490.fc38.noarch 37/73 Verifying : perl-Pod-Perldoc-3.28.01-491.fc38.noarch 38/73 Verifying : perl-Pod-Simple-1:3.45-2.fc39.noarch 39/73 Verifying : perl-Pod-Usage-4:2.03-4.fc38.noarch 40/73 Verifying : perl-Scalar-List-Utils-5:1.63-491.fc39.x86_64 41/73 Verifying : perl-SelectSaver-1.02-497.fc39.noarch 42/73 Verifying : perl-Socket-4:2.037-1.fc39.x86_64 43/73 Verifying : perl-Storable-1:3.32-1.fc39.x86_64 44/73 Verifying : perl-Symbol-1.09-497.fc39.noarch 45/73 Verifying : perl-Term-ANSIColor-5.01-491.fc38.noarch 46/73 Verifying : perl-Term-Cap-1.18-1.fc39.noarch 47/73 Verifying : perl-TermReadKey-2.38-16.fc38.x86_64 48/73 Verifying : perl-Text-ParseWords-3.31-490.fc38.noarch 49/73 Verifying : perl-Text-Tabs+Wrap-2023.0511-1.fc39.noarch 50/73 Verifying : perl-Time-Local-2:1.350-1.fc39.noarch 51/73 Verifying : perl-constant-1.33-492.fc39.noarch 52/73 Verifying : perl-if-0.61.000-497.fc39.noarch 53/73 Verifying : perl-interpreter-4:5.36.1-497.fc39.x86_64 54/73 Verifying : perl-lib-0.65-497.fc39.x86_64 55/73 Verifying : perl-libs-4:5.36.1-497.fc39.x86_64 56/73 Verifying : perl-locale-1.10-497.fc39.noarch 57/73 Verifying : perl-mro-1.26-497.fc39.x86_64 58/73 Verifying : perl-overload-1.35-497.fc39.noarch 59/73 Verifying : perl-overloading-0.02-497.fc39.noarch 60/73 Verifying : perl-parent-1:0.241-1.fc39.noarch 61/73 Verifying : perl-podlators-1:5.01-2.fc38.noarch 62/73 Verifying : perl-vars-1.05-497.fc39.noarch 63/73 Verifying : pyproject-rpm-macros-1.9.0-1.fc39.noarch 64/73 Verifying : python-pip-wheel-23.1.2-2.fc39.noarch 65/73 Verifying : python-rpm-macros-3.12-1.fc39.noarch 66/73 Verifying : python3-3.12.0~b3-2.fc39.x86_64 67/73 Verifying : python3-devel-3.12.0~b3-2.fc39.x86_64 68/73 Verifying : python3-libs-3.12.0~b3-2.fc39.x86_64 69/73 Verifying : python3-packaging-23.1-3.fc39.noarch 70/73 Verifying : python3-rpm-generators-14-6.fc39.noarch 71/73 Verifying : python3-rpm-macros-3.12-1.fc39.noarch 72/73 Verifying : python3-setuptools-67.7.2-5.fc39.noarch 73/73 Installed: expat-2.5.0-2.fc38.x86_64 git-2.41.0-1.fc39.x86_64 git-core-2.41.0-1.fc39.x86_64 git-core-doc-2.41.0-1.fc39.noarch groff-base-1.22.4-11.fc38.x86_64 less-633-1.fc39.x86_64 libb2-0.98.1-8.fc38.x86_64 libcbor-0.10.2-1.fc39.x86_64 libedit-3.1-45.20221030cvs.fc38.x86_64 libfido2-1.13.0-2.fc39.x86_64 mpdecimal-2.5.1-6.fc38.x86_64 ncurses-6.4-5.20230520.fc39.x86_64 openssh-9.3p1-3.fc39.x86_64 openssh-clients-9.3p1-3.fc39.x86_64 perl-Carp-1.54-1.fc39.noarch perl-Class-Struct-0.66-497.fc39.noarch perl-DynaLoader-1.52-497.fc39.x86_64 perl-Encode-4:3.19-493.fc38.x86_64 perl-Errno-1.36-497.fc39.x86_64 perl-Error-1:0.17029-12.fc39.noarch perl-Exporter-5.77-490.fc38.noarch perl-Fcntl-1.15-497.fc39.x86_64 perl-File-Basename-2.85-497.fc39.noarch perl-File-Find-1.40-497.fc39.noarch perl-File-Path-2.18-490.fc38.noarch perl-File-Temp-1:0.231.100-490.fc38.noarch perl-File-stat-1.12-497.fc39.noarch perl-Getopt-Long-1:2.54-2.fc38.noarch perl-Getopt-Std-1.13-497.fc39.noarch perl-Git-2.41.0-1.fc39.noarch perl-HTTP-Tiny-0.086-1.fc39.noarch perl-IO-1.50-497.fc39.x86_64 perl-IPC-Open3-1.22-497.fc39.noarch perl-MIME-Base64-3.16-490.fc38.x86_64 perl-POSIX-2.03-497.fc39.x86_64 perl-PathTools-3.89-1.fc39.x86_64 perl-Pod-Escapes-1:1.07-490.fc38.noarch perl-Pod-Perldoc-3.28.01-491.fc38.noarch perl-Pod-Simple-1:3.45-2.fc39.noarch perl-Pod-Usage-4:2.03-4.fc38.noarch perl-Scalar-List-Utils-5:1.63-491.fc39.x86_64 perl-SelectSaver-1.02-497.fc39.noarch perl-Socket-4:2.037-1.fc39.x86_64 perl-Storable-1:3.32-1.fc39.x86_64 perl-Symbol-1.09-497.fc39.noarch perl-Term-ANSIColor-5.01-491.fc38.noarch perl-Term-Cap-1.18-1.fc39.noarch perl-TermReadKey-2.38-16.fc38.x86_64 perl-Text-ParseWords-3.31-490.fc38.noarch perl-Text-Tabs+Wrap-2023.0511-1.fc39.noarch perl-Time-Local-2:1.350-1.fc39.noarch perl-constant-1.33-492.fc39.noarch perl-if-0.61.000-497.fc39.noarch perl-interpreter-4:5.36.1-497.fc39.x86_64 perl-lib-0.65-497.fc39.x86_64 perl-libs-4:5.36.1-497.fc39.x86_64 perl-locale-1.10-497.fc39.noarch perl-mro-1.26-497.fc39.x86_64 perl-overload-1.35-497.fc39.noarch perl-overloading-0.02-497.fc39.noarch perl-parent-1:0.241-1.fc39.noarch perl-podlators-1:5.01-2.fc38.noarch perl-vars-1.05-497.fc39.noarch pyproject-rpm-macros-1.9.0-1.fc39.noarch python-pip-wheel-23.1.2-2.fc39.noarch python-rpm-macros-3.12-1.fc39.noarch python3-3.12.0~b3-2.fc39.x86_64 python3-devel-3.12.0~b3-2.fc39.x86_64 python3-libs-3.12.0~b3-2.fc39.x86_64 python3-packaging-23.1-3.fc39.noarch python3-rpm-generators-14-6.fc39.noarch python3-rpm-macros-3.12-1.fc39.noarch python3-setuptools-67.7.2-5.fc39.noarch Complete! Finish: build setup for litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Start: rpmbuild litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Building target platforms: x86_64 Building for target x86_64 setting SOURCE_DATE_EPOCH=1654300800 Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.KvZ4Wx + umask 022 + cd /builddir/build/BUILD + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p litex-pythondata-cpu-cva6 + cd litex-pythondata-cpu-cva6 + /usr/bin/mkdir -p SPECPARTS + /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w . + find /builddir/build/BUILD -name SPECPARTS -exec rm -rf '{}' + + git clone --depth 1 -n -b master https://github.com/litex-hub/pythondata-cpu-cva6.git . Cloning into '.'... + git fetch --depth 1 origin 13cbe4453e14960a80949f6d0c66b63aabffd3df From https://github.com/litex-hub/pythondata-cpu-cva6 * branch 13cbe4453e14960a80949f6d0c66b63aabffd3df -> FETCH_HEAD + git reset --hard 13cbe4453e14960a80949f6d0c66b63aabffd3df HEAD is now at 13cbe44 Updating .gitmodules file. + git log --format=fuller commit 13cbe4453e14960a80949f6d0c66b63aabffd3df Author: LiteX Robot AuthorDate: Tue Nov 8 23:14:32 2022 +0000 Commit: LiteX Robot CommitDate: Tue Nov 8 23:14:32 2022 +0000 Updating .gitmodules file. Updated using 0.0.post142 from https://github.com/litex-hub/litex-data-auto + RPM_EC=0 ++ jobs -p + exit 0 Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.iJP089 + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py build '--executable=/usr/bin/python3 -sP' running build running build_py creating build creating build/lib creating build/lib/pythondata_cpu_cva6 copying pythondata_cpu_cva6/__init__.py -> build/lib/pythondata_cpu_cva6 running egg_info creating pythondata_cpu_cva6.egg-info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.ci' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.ci' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.ci' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.ci' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.ci' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.techlib.fpga.rtl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.common.local.util' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.common.local.util' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.common.local.util' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.common.local.util' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.common.local.util' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cache_subsystem' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.cvxif_example.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.example_tb.verilator_results' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.frontend' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.frontend' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.frontend' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.frontend' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.frontend' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv32' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.mmu_sv39' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.core.pmp.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.clint' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.constraints' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.src.bootrom.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_clock_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_master.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_dwidth_converter_dm_slave.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_gpio.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_axi_quad_spi.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_clk_gen.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_ila.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_mig_7_ddr3.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.fpga.xilinx.xlnx_protocol_checker.tcl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.include' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.include' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.include' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.include' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.baremetal' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.openpiton.bootrom.linux.src' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.common' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.dpi' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_cva6_icache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_serdiv.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wb_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_axi_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.tb_wt_dcache.hdl' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.corev_apu.tb.wave' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs._static' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs._static' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs._static' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs._static' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs._static' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.design_spec.source' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.specifications.images' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.docs.user_guide' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.docs.user_guide' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.docs.user_guide' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.docs.user_guide' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) creating build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.editorconfig -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/.gitmodules -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CODEOWNERS -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Flist.ariane -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/README.md -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/ariane.core -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/init_testharness.do -> build/lib/pythondata_cpu_cva6/system_verilog copying pythondata_cpu_cva6/system_verilog/src_files.yml -> build/lib/pythondata_cpu_cva6/system_verilog creating build/lib/pythondata_cpu_cva6/system_verilog/.github creating build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE creating build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows copying pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows creating build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.pd.synth.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) /usr/lib/python3.12/site-packages/setuptools/command/build_py.py:201: _Warning: Package 'pythondata_cpu_cva6.system_verilog.scripts' is absent from the `packages` configuration. !! ******************************************************************************** ############################ # Package would be ignored # ############################ Python recognizes 'pythondata_cpu_cva6.system_verilog.scripts' as an importable package[^1], but it is absent from setuptools' `packages` configuration. This leads to an ambiguous overall configuration. If you want to distribute this package, please make sure that 'pythondata_cpu_cva6.system_verilog.scripts' is explicitly added to the `packages` configuration field. Alternatively, you can also rely on setuptools' discovery methods (for example by using `find_namespace_packages(...)`/`find_namespace:` instead of `find_packages(...)`/`find:`). You can read more about "package discovery" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/package_discovery.html If you don't want 'pythondata_cpu_cva6.system_verilog.scripts' to be distributed and are already explicitly excluding 'pythondata_cpu_cva6.system_verilog.scripts' via `find_namespace_packages(...)/find_namespace` or `find_packages(...)/find`, you can try to use `exclude_package_data`, or `include-package-data=False` in combination with a more fine grained `package-data` configuration. You can read more about "package data files" on setuptools documentation page: - https://setuptools.pypa.io/en/latest/userguide/datafiles.html [^1]: For Python, any directory (with suitable naming) can be imported, even if it does not contain any `.py` files. On the other hand, currently there is no concept of package data directory, all directories are treated like packages. ******************************************************************************** !! check.warn(importable) copying pythondata_cpu_cva6/system_verilog/ci/default.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/float.config -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/setup.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> build/lib/pythondata_cpu_cva6/system_verilog/ci copying pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> build/lib/pythondata_cpu_cva6/system_verilog/ci creating build/lib/pythondata_cpu_cva6/system_verilog/common creating build/lib/pythondata_cpu_cva6/system_verilog/common/local creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util copying pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/common/local/util creating build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/controller.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cva6.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/mult.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/re_name.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core copying pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core creating build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb creating build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend copying pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/frontend creating build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include copying pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp copying pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include copying pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src copying pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src creating build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include copying pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl creating build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> build/lib/pythondata_cpu_cva6/system_verilog/docs copying pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs creating build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static copying pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/_static creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec copying pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications copying pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications creating build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images creating build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide copying pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide creating build/lib/pythondata_cpu_cva6/system_verilog/pd creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth copying pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth creating build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts creating build/lib/pythondata_cpu_cva6/system_verilog/scripts copying pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> build/lib/pythondata_cpu_cva6/system_verilog/scripts Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.U7hLVl running install running install_lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup_filenames.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/dc_setup.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/tc_sram_wrapper_256_64_00000008_00000001_00000001_none_0.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_synth.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/cva6_read.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth copying build/lib/pythondata_cpu_cva6/system_verilog/pd/synth/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide copying build/lib/pythondata_cpu_cva6/system_verilog/docs/user_guide/cva6_ug_csr.adoc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/user_guide creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/images/cva6_scope.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/specifications/cva6_requirement_specification.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/specifications creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_system.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_glossary.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/cva6_frontend.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.xml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/CV32A6_CSR.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/jade_design_automation_logo.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/frontend_modules.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/bht.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/images/CVA6_subsystems.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/images copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec copying build/lib/pythondata_cpu_cva6/system_verilog/docs/design_spec/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/uvm_fu_tb.ai -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/scoreboard.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/openhw-landscape.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/mmu_blockdiagramm.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/lsu_blockdiagram.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/logonav.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ld_pipeline_diagram.svg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/jekyll-dark.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/instr_realign.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/fpga_bd.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/branch_prediction.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/bg.jpg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.png -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/_static/ariane_overview.pdf -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/_static copying build/lib/pythondata_cpu_cva6/system_verilog/docs/requirements.txt -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/pcgen_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/make.bat -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/issue_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/intro.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/index.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/if_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/id_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/ex_stage.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/cva6_soc.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/conf.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/commit_stage.rst -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs copying build/lib/pythondata_cpu_cva6/system_verilog/docs/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave/wave_core.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/wave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_urem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_udiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_rem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb_div.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl + RPM_EC=0 ++ jobs -p + exit 0 + umask 022 + cd /builddir/build/BUILD + '[' /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 '!=' / ']' + rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 ++ dirname /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + mkdir -p /builddir/build/BUILDROOT + mkdir /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + cd litex-pythondata-cpu-cva6 + CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wno-complain-wrong-lang -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer' + LDFLAGS='-Wl,-z,relro -Wl,--as-needed -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes ' + /usr/bin/python3 setup.py install -O1 --skip-build --root /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 --prefix /usr /usr/lib/python3.12/site-packages/setuptools/_distutils/cmd.py:66: SetuptoolsDeprecationWarning: setup.py install is deprecated. !! ******************************************************************************** Please avoid running ``setup.py`` directly. Instead, use pypa/build, pypa/installer, pypa/build or other standards-based tools. Follow the current Python packaging guidelines when building Python RPM packages. See https://blog.ganssle.io/articles/2021/10/setup-py-deprecated.html and https://docs.fedoraproject.org/en-US/packaging-guidelines/Python/ for details. ******************************************************************************** !! self.initialize_options() copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tlb_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl/mem_emul.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/hdl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/wave.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/tb.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.s -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/xspike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/termios-xspike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike_main.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/spike-dasm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main/disasm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/spike_main creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/ui32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/specialize.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_types.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_state.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat_raiseFlags.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/softfloat.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subMagsF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_subM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub1XM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_sub128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightJam128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRightExtendM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftRight128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft64To96M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shortShiftLeft128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128Extra.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_shiftRightJam128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToUI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundToI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToUI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToI32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackToF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundPackMToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToUI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_roundMToI64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_remStepMBy32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF64UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF32UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF16UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_propagateNaNF128UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF64Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF32Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF16Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normSubnormalF128Sig.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_normRoundPackToF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_negXM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mulAddF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64To128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul64ByShifted32To128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128To256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128MTo256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_mul128By32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_lt128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_le128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f64UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f32UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f16UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_f128UIToCommonNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_eq128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros8.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_countLeadingZeros16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare96M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_compare128M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF64UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF32UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF16UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_commonNaNToF128UI.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip_1Ks.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt_1Ks.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecipSqrt32_1.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_approxRecip32_1.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addMagsF128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addComplCarryM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_addCarryM.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add256M.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/s_add128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitives.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/primitiveTypes.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/internals.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/i32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_to_f128.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f16_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_ui32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32_r_minMag.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_i32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f64.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f32.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_to_f16.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sub.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_sqrt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_roundToInt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_rem.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mulAdd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_mul.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_lt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le_quiet.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_le.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_isSignalingNaN.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq_signaling.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_eq.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_div.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_add.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xori.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/xor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/wfi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/subw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sub.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srlw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srliw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srl.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sraiw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/srai.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sra.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sltiu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slti.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sllw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slliw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/slli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sll.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sfence_vma.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sc_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/sb.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remuw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/remu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/rem.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ori.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/or.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulhsu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mulh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mul.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/mret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lwu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lui.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lr_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lhu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lh.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lbu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/lb.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jalr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/jal.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsqrt_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjx_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnjn_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsgnj_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fsd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fnmadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_x_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_w_x.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmv_d_x.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmul_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmsub_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmin_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmax_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fmadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flt_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/flq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fle_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/feq_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence_i.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fence.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fdiv_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_wu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_w_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_s_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_q_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_lu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_l_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_wu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_lu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fcvt_d_l.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fclass_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_s.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_q.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/fadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ecall.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/ebreak.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/dret.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divuw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/divu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/div.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrwi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrsi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrs.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrci.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/csrrc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_xor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_swsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_subw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_sub.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_srai.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_slli.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_or.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_mv.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lwsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_lui.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_li.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jalr.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_jal.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_j.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fswsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsdsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fsd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flwsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_flw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fldsp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_fld.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_ebreak.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_bnez.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_beqz.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_andi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_and.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi4spn.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_addi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/c_add.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bne.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bltu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/blt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bgeu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/bge.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/beq.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/auipc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/andi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/and.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoxor_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoswap_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoor_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amominu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomin_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomaxu_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amomax_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoand_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_w.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/amoadd_d.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addiw.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/addi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns/add.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insns copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/uart.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/trap.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/tracer.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/simif.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/sim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rom.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/rocc.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/riscv.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/remote_bitbang.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/regnames.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/processor.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/opcodes.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mulhi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/mmu.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/memtracer.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/jtag_dtm.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/interactive.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/insn_template.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extensions.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/extension.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/execute.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dump.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/dts.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/disasm.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/devices.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/decode.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_rom_defines.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_module.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/debug_defines.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/common.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/clint.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/cachesim.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc_test.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.mk.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc/dummy_rocc.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/dummy_rocc creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/link.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike_main.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-spike.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-softfloat.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-riscv.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv-dummy_rocc.pc.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure.ac -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/config.h.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/aclocal.m4 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/Makefile.in -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/verilator.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/sim_spike.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/remote_bitbang.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/msim_helper.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/elfloader.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/dromajo_cosim_dpi.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimJTAG.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi/SimDTM.cc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/dpi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_writeport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_readport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_dcache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb_amoport.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/tb.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/string_buffer.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/spike.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/mock_uart.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/dp_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/core_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/assign.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimJTAG.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common/SimDTM.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/common copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/rvfi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_testharness.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_tb.cpp -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/tb/ariane_axi_soc_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/riscv_peripherals.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/ariane_verilog_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/include/traced_instr_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_protocol_checker creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_vc707.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_kc705.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_ila creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_clk_gen creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_quad_spi creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_gpio creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_slave creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter_dm_master creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_dwidth_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/tcl copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_axi_clock_converter copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/common.mk -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/ariane_xlnx_ip.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/uart.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/spi.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/smp.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/sd.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/main.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src/gpt.c -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/startup.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/platform.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/linker.lds -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv64a6.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/cv32a6.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_64.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/bootrom_32.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vcu118.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/vc707.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/kc705.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/genesysii.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/fan_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/ariane_peripherals_xilinx.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/write_cfgmem.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/run.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/prologue.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program_genesys2.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/program.tcl -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/check_fpga_boot.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vcu118.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/vc707.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/kc705.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/genesys-2.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints/ariane.xdc -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/constraints copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/sourceme.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod_tiny.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane_pmod.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/ariane-multi-hart.cfg -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/clint.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/axi_lite_interface.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/clint/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/clint creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/linker.ld -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/encoding.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/dromajo_bootrom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.h -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/bootrom.S -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/ariane.dts -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom copying build/lib/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/tb_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/tb/pmp_tb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp_entry.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/src/pmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/src creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/include/riscv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/formal.sby -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp copying build/lib/pythondata_cpu_cva6/system_verilog/core/pmp/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/pmp creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/tlb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/ptw.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv39/mmu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv39 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_tlb_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_ptw_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 copying build/lib/pythondata_cpu_cva6/system_verilog/core/mmu_sv32/cva6_mmu_sv32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/mmu_sv32 creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/wt_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/std_cache_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/riscv_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/instr_tracer_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cvxif_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_openpiton_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv64a6_imafdc_sv39_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imafc_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv32_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a6_imac_sv0_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/cv32a60x_config_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/axi_intf.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_rvfi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/include/ariane_axi_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/include creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/ras.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_scan.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/instr_queue.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/frontend.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/btb.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend copying build/lib/pythondata_cpu_cva6/system_verilog/core/frontend/bht.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/frontend creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results copying build/lib/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results/Vcva6_core_only_tb -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/example_tb/verilator_results creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include/cvxif_instr_pkg.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example/include copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/instr_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_example/cvxif_example_coprocessor.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cvxif_example creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_l15_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_wbuffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_missunit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_mem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/wt_axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/tag_cmp.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_no_dcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_nbdcache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/std_cache_subsystem.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/miss_handler.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache_axi_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cva6_icache.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/cache_ctrl.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/cache_subsystem/amo_alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core/cache_subsystem copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/store_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/serdiv.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/scoreboard.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/re_name.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/perf_counters.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/multiplier.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/mult.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/lsu_bypass.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/load_store_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/issue_read_operands.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/instr_realign.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/id_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/fpu_wrap.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ex_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/dromajo_ram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cvxif_fu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/cva6.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_regfile.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/csr_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/controller.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/compressed_decoder.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/commit_stage.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/branch_unit.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_shim.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/axi_adapter.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile_ff.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane_regfile.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/ariane.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/amo_buffer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/alu.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39_gate -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv64a6_imafdc_sv39 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imafc_sv32 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv32 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a6_imac_sv0 -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x_gate -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core copying build/lib/pythondata_cpu_cva6/system_verilog/core/Flist.cv32a60x -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/core creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/tc_sram_fpga_wrapper.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/sram.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer_if.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_tracer.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/instr_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/find_first_one.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/util/ex_trace_item.svh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/util creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncTpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRamBeNx32.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl copying build/lib/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/travis-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/torture_make.patch -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-mul-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-fp-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-benchmarks.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-asm-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/riscv-amo-tests.list -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/path-setup.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/float.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/default.config -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci copying build/lib/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/cva6.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci/core-v-verif-cva6.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.gitlab-ci creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows copying build/lib/pythondata_cpu_cva6/system_verilog/.github/workflows/ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/workflows creating /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/task.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE/bug.yaml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/.github/ISSUE_TEMPLATE copying build/lib/pythondata_cpu_cva6/system_verilog/src_files.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/init_testharness.do -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/ariane.core -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/README.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Makefile -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.SiFive -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE.Berkeley -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/LICENSE -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Flist.ariane -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CONTRIBUTING.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CODEOWNERS -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/CHANGELOG.md -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/Bender.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitmodules -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitlab-ci.yml -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.gitignore -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/system_verilog/.editorconfig -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog copying build/lib/pythondata_cpu_cva6/__init__.py -> /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6 byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py to parse_ila_trace.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/pd/synth/scripts/gate_analysis.py to gate_analysis.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/design_spec/source/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/docs/conf.py to conf.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py to testlib.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py to ebreak.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/scripts/linux_boot.py to linux_boot.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py to gen_rom.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py to config_pkg_generator.cpython-312.pyc byte-compiling /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/__init__.py to __init__.cpython-312.pyc writing byte-compilation script '/tmp/tmpyafp332t.py' /usr/bin/python3 /tmp/tmpyafp332t.py removing /tmp/tmpyafp332t.py running install_egg_info running egg_info writing pythondata_cpu_cva6.egg-info/PKG-INFO writing dependency_links to pythondata_cpu_cva6.egg-info/dependency_links.txt writing top-level names to pythondata_cpu_cva6.egg-info/top_level.txt reading manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' reading manifest template 'MANIFEST.in' adding license file 'LICENSE' writing manifest file 'pythondata_cpu_cva6.egg-info/SOURCES.txt' Copying pythondata_cpu_cva6.egg-info to /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6-4.2.0.post435-py3.12.egg-info running install_scripts /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' warning: no previously-included files matching '*.py[cod]' found anywhere in distribution + rm -rfv /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/bin/__pycache__ + sed -i /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/ebreak.py -e 's|#!/usr/bin/python|#!/usr/bin/python3|' + /usr/lib/rpm/check-buildroot + /usr/lib/rpm/redhat/brp-ldconfig + /usr/lib/rpm/brp-compress + /usr/lib/rpm/brp-strip /bin/true + /usr/lib/rpm/brp-strip-comment-note /bin/true /usr/bin/objdump + /usr/lib/rpm/redhat/brp-strip-lto /bin/true + /usr/lib/rpm/brp-strip-static-archive /bin/true + /usr/lib/rpm/check-rpaths + /usr/lib/rpm/redhat/brp-mangle-shebangs mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-gcc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/build-riscv-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/check-tests.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/get-torture.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/gitlab-ci-emul.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-dtc.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-fesvr.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-riscvpk.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-spike.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/install-verilator.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/make-tmp.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/ci/setup.sh from /bin/bash to #!/usr/bin/bash mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/src/bootrom/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/fpga/xilinx/xlnx_mig_7_ddr3/mig_genesys2.prj is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/baremetal/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/openpiton/bootrom/linux/gen_rom.py from /usr/bin/env python3 to #!/usr/bin/python3 mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/configure from /bin/sh to #!/usr/bin/sh *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/debug_rom/debug_rom.S is executable but has no shebang, removing executable bit mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/riscv/gen_icache from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.guess from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/config.sub from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/install.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/mk-install-dirs.sh from /bin/sh to #!/usr/bin/sh mangling shebang in /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/scripts/vcs-version.sh from /bin/bash to #!/usr/bin/bash *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f128_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f32_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/softfloat/f64_classify.c is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_cva6_icache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_serdiv/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wb_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_axi_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/tb_wt_dcache/Makefile is executable but has no shebang, removing executable bit *** WARNING: ./usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/scripts/parse_ila_trace.py is executable but has no shebang, removing executable bit + /usr/lib/rpm/brp-remove-la-files + env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j2 Bytecompiling .py files below /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/lib/python3.12 using python3.12 /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:97: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/config_pkg_generator.py:111: SyntaxWarning: invalid escape sequence '\g' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:86: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:91: SyntaxWarning: invalid escape sequence '\(' /usr/lib/python3.12/site-packages/pythondata_cpu_cva6/system_verilog/corev_apu/tb/riscv-isa-sim/tests/testlib.py:103: SyntaxWarning: invalid escape sequence '\(' + /usr/lib/rpm/redhat/brp-python-hardlink Processing files: litex-pythondata-cpu-cva6-python3-2022.12-20221108.2.git13cbe445.fc39.noarch Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.SUirFC + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + DOCDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C + LC_ALL=C + export DOCDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/README.md /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/doc/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.1fCrkR + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + LICENSEDIR=/builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + export LC_ALL=C + LC_ALL=C + export LICENSEDIR + /usr/bin/mkdir -p /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + cp -pr /builddir/build/BUILD/litex-pythondata-cpu-cva6/LICENSE /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64/usr/share/licenses/litex-pythondata-cpu-cva6-python3 + RPM_EC=0 ++ jobs -p + exit 0 Provides: litex-pythondata-cpu-cva6-python3 = 2022.12-20221108.2.git13cbe445.fc39 pythondata-cpu-cva6 Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PartialHardlinkSets) <= 4.0.4-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1 warning: Arch dependent binaries in noarch package Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 Wrote: /builddir/build/RPMS/litex-pythondata-cpu-cva6-python3-2022.12-20221108.2.git13cbe445.fc39.noarch.rpm Executing(%clean): /bin/sh -e /var/tmp/rpm-tmp.GT5Y1a + umask 022 + cd /builddir/build/BUILD + cd litex-pythondata-cpu-cva6 + /usr/bin/rm -rf /builddir/build/BUILDROOT/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.x86_64 + RPM_EC=0 ++ jobs -p + exit 0 Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.QfX2DF + umask 022 + cd /builddir/build/BUILD + rm -rf litex-pythondata-cpu-cva6 litex-pythondata-cpu-cva6.gemspec + RPM_EC=0 ++ jobs -p + exit 0 RPM build warnings: Arch dependent binaries in noarch package Finish: rpmbuild litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm Finish: build phase for litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm INFO: chroot_scan: 3 files copied to /var/lib/copr-rpmbuild/results/chroot_scan INFO: /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.rpm.log /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.librepo.log /var/lib/mock/fedora-rawhide-x86_64-1688731775.510429/root/var/log/dnf.log INFO: Done(/var/lib/copr-rpmbuild/results/litex-pythondata-cpu-cva6-2022.12-20221108.2.git13cbe445.fc39.src.rpm) Config(child) 0 minutes 22 seconds INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results INFO: Cleaning up build root ('cleanup_on_success=True') Start: clean chroot INFO: unmounting tmpfs. Finish: clean chroot Finish: run Running RPMResults tool