LICENSE
MANIFEST.in
README.md
pyproject.toml
setup.py
pythondata_cpu_cva5/__init__.py
pythondata_cpu_cva5.egg-info/PKG-INFO
pythondata_cpu_cva5.egg-info/SOURCES.txt
pythondata_cpu_cva5.egg-info/dependency_links.txt
pythondata_cpu_cva5.egg-info/not-zip-safe
pythondata_cpu_cva5.egg-info/top_level.txt
pythondata_cpu_cva5/system_verilog/.gitignore
pythondata_cpu_cva5/system_verilog/.gitlab-ci.yml
pythondata_cpu_cva5/system_verilog/LICENSE
pythondata_cpu_cva5/system_verilog/README.md
pythondata_cpu_cva5/system_verilog/TODO.txt
pythondata_cpu_cva5/system_verilog/apu/busses/axi_adapter.sv
pythondata_cpu_cva5/system_verilog/apu/busses/multicore_arbiter.sv
pythondata_cpu_cva5/system_verilog/apu/busses/wishbone_adapter.sv
pythondata_cpu_cva5/system_verilog/apu/clint/clint.sv
pythondata_cpu_cva5/system_verilog/apu/clint/clint_wrapper.sv
pythondata_cpu_cva5/system_verilog/apu/plic/plic.sv
pythondata_cpu_cva5/system_verilog/apu/plic/plic_cmptree.sv
pythondata_cpu_cva5/system_verilog/apu/plic/plic_gateway.sv
pythondata_cpu_cva5/system_verilog/apu/plic/plic_wrapper.sv
pythondata_cpu_cva5/system_verilog/core/core_arbiter.sv
pythondata_cpu_cva5/system_verilog/core/cva5.sv
pythondata_cpu_cva5/system_verilog/core/decode_and_issue.sv
pythondata_cpu_cva5/system_verilog/core/fp_writeback.sv
pythondata_cpu_cva5/system_verilog/core/instruction_metadata_and_id_management.sv
pythondata_cpu_cva5/system_verilog/core/register_file.sv
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pythondata_cpu_cva5/system_verilog/core/renamer.sv
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pythondata_cpu_cva5/system_verilog/core/common_components/clz.sv
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pythondata_cpu_cva5/system_verilog/core/common_components/priority_encoder.sv
pythondata_cpu_cva5/system_verilog/core/common_components/round_robin.sv
pythondata_cpu_cva5/system_verilog/core/common_components/set_clr_reg_with_rst.sv
pythondata_cpu_cva5/system_verilog/core/common_components/toggle_memory.sv
pythondata_cpu_cva5/system_verilog/core/common_components/toggle_memory_set.sv
pythondata_cpu_cva5/system_verilog/core/common_components/ram/lutram_1w_1r.sv
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pythondata_cpu_cva5/system_verilog/core/common_components/ram/sdp_ram.sv
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pythondata_cpu_cva5/system_verilog/core/common_components/ram/tdp_ram.sv
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pythondata_cpu_cva5/system_verilog/core/fetch_stage/icache.sv
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pythondata_cpu_cva5/system_verilog/core/fetch_stage/ras.sv
pythondata_cpu_cva5/system_verilog/core/memory_sub_units/avalon_master.sv
pythondata_cpu_cva5/system_verilog/core/memory_sub_units/axi_master.sv
pythondata_cpu_cva5/system_verilog/core/memory_sub_units/local_mem_sub_unit.sv
pythondata_cpu_cva5/system_verilog/core/memory_sub_units/wishbone_master.sv
pythondata_cpu_cva5/system_verilog/core/mmu/dtlb.sv
pythondata_cpu_cva5/system_verilog/core/mmu/itlb.sv
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pythondata_cpu_cva5/system_verilog/core/mmu/perms_check.sv
pythondata_cpu_cva5/system_verilog/core/types_and_interfaces/csr_types.sv
pythondata_cpu_cva5/system_verilog/core/types_and_interfaces/cva5_config.sv
pythondata_cpu_cva5/system_verilog/core/types_and_interfaces/cva5_types.sv
pythondata_cpu_cva5/system_verilog/core/types_and_interfaces/external_interfaces.sv
pythondata_cpu_cva5/system_verilog/core/types_and_interfaces/fpu_types.sv
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pythondata_cpu_cva5/system_verilog/examples/litex/litex_wrapper.sv
pythondata_cpu_cva5/system_verilog/examples/sw/main.c
pythondata_cpu_cva5/system_verilog/examples/sw/mem.mif
pythondata_cpu_cva5/system_verilog/examples/xilinx/clint.tcl
pythondata_cpu_cva5/system_verilog/examples/xilinx/cva5_top.v
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pythondata_cpu_cva5/system_verilog/examples/xilinx/nexys_sys.tcl
pythondata_cpu_cva5/system_verilog/examples/xilinx/package_as_ip.tcl
pythondata_cpu_cva5/system_verilog/examples/xilinx/plic.tcl
pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXIMem.cc
pythondata_cpu_cva5/system_verilog/test_benches/verilator/AXIMem.h
pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.cc
pythondata_cpu_cva5/system_verilog/test_benches/verilator/CVA5Tracer.h
pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.cc
pythondata_cpu_cva5/system_verilog/test_benches/verilator/SimMem.h
pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.cc
pythondata_cpu_cva5/system_verilog/test_benches/verilator/cva5_sim.sv
pythondata_cpu_cva5/system_verilog/test_benches/verilator/sim_stats.sv
pythondata_cpu_cva5/system_verilog/tools/compile_order
pythondata_cpu_cva5/system_verilog/tools/cva5.mak
pythondata_cpu_cva5/system_verilog/tools/elf-to-hw-init.py