9.0 Statistical Model Reference guideΒΆ

  • 9.1 Introduction
  • 9.2 Model Usage and Syntax
    • 9.2.1 Library invocation
    • 9.2.2 Transistor declaration
    • 9.2.3 Switch definitions
  • 9.3 Statistical MOSFETs Modeling Results
    • 9.3.1 3.3V NMOS and PMOS PROCESS MC
    • 9.3.2 6V NMOS and PMOS PROCESS MC
    • 9.3.3 3.3V SAB NMOS and SAB PMOS PROCESS MC
    • 9.3.4 6V SAB NMOS and SAB PMOS PROCESS MC
  • 9.4 Mismatch MOSFET Modeling Results
    • 9.4.1 3.3V NMOS and PMOS mismatch verification plots
    • 9.4.2 6V NMOS and PMOS mismatch verification plots
  • 9.5 Mismatch Resistor Modeling Results
  • 9.6 Mismatch BJT Modeling Results

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      • FAB3E Spice Model For 0.18um 3.3v/6v High Voltage MCU Process
        • 1.0 Introduction
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        • 9.0 Statistical Model Reference guide
          • 9.1 Introduction
          • 9.2 Model Usage and Syntax
          • 9.3 Statistical MOSFETs Modeling Results
          • 9.4 Mismatch MOSFET Modeling Results
          • 9.5 Mismatch Resistor Modeling Results
          • 9.6 Mismatch BJT Modeling Results
      • FAB3E Spice Model For 0.18um 10v High Voltage MCU Process
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    • Custom Design
      • Model Parameters
        • FAB3E Spice Model For 0.18um 3.3v/6v High Voltage MCU Process
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