4.2. Generated Layer and Generation rules
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Please refer to the generation algorithm spec: YI-141-GR065 or GR-000179
GlobalFoundries GF180MCU PDK
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1.0 Purpose
2.0 Scope
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4.0 Topological Level Definitions
4.1 Drawn layer definition and abbreviation
4.2. Generated Layer and Generation rules
4.3. Mask Layer Numbering
4.4. Topological Truth Table for 3.3V/(5V)6V Process
5.0 DFM (Design For Manufacturability) Guidelines
6.0 Essential Tapeout Checklist
7.0 Layout Rule Description
8.0 Antenna Ratio Rules
9.0 Bond Pad
10.0 Analog Device Related Rules
11.0 SRAM Core Cells
12.0 Scribe Line & Guard Ring Rules And Guidelines
13.0 Dummy Fill Rules And Guidelines
14.0 Reliability Related Rules And Guidelines
Appendix A: Device List for Model and LVS Deck
Appendix B: Rules not coded
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4.0 Topological Level Definitions
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