7.17 Mcell¶
Polarity is Clear
RULE NO. |
DESCRIPTION |
LAYOUT RULE |
Layer |
MC = MTP Cell Implant |
|
MC.1 |
Width |
0.4 |
MC.2 |
Space |
0.4 |
MC.3 |
Minimum Mcell area |
0.35 μm2 |
MC.4 |
Minimum area enclosed by Mcell |
0.35 μm2 |
GlobalFoundries GF180MCU PDK
Navigation
- Digital Libraries
- Custom Design
- IPs / Macros
- Physical Verification
- Design Manual
- 1.0 Purpose
- 2.0 Scope
- 3.0 Layout Information
- 4.0 Topological Level Definitions
- 5.0 DFM (Design For Manufacturability) Guidelines
- 6.0 Essential Tapeout Checklist
- 7.0 Layout Rule Description
- 7.1 Design Geometry Rules
- 7.2 Dnwell
- 7.3 Lvpwell
- 7.4 Nwell
- 7.5 Comp
- 7.6 Dualgate
- 7.7 Poly2
- 7.8 Nplus
- 7.9 Pplus
- 7.10 Salicide Block (SAB)
- 7.11 ESD Implant
- 7.12 Contact
- 7.13 Metaln (where n = 1 to 5)
- 7.14 Vian (where n = 1 to 5)
- 7.15 MetalTop (Thickness 6K/9K*/11K* Å)
- 7.16 3.0um Thick MetalTop Option
- 7.17 Mcell
- 8.0 Antenna Ratio Rules
- 9.0 Bond Pad
- 10.0 Analog Device Related Rules
- 11.0 SRAM Core Cells
- 12.0 Scribe Line & Guard Ring Rules And Guidelines
- 13.0 Dummy Fill Rules And Guidelines
- 14.0 Reliability Related Rules And Guidelines
- Appendix A: Device List for Model and LVS Deck
- Appendix B: Rules not coded
- Design Manual
- Versioning Information
- Naming
- How to Contribute
- Google Open Source Community Guidelines
- Google maintained open source PDKs
- Resources