14.0 Reliability Related Rules And Guidelines

In this section some general guidelines (not all-inclusive) are provided to improve reliability in circuit design. Since reliability involves many aspects of circuit design, it is the responsibility of circuit designers to guarantee design conformance, reliability and manufacturability of their final product designs for intended applications.

• 14.1 Chip Operating Conditions
  • 14.1.1 Temperature Limits
  • 14.1.2 Power Supply Voltage Limits
  • 14.1.3 Chip Burn-in Limits
  • 14.1.4 Device Voltage Limits
    • 14.1.4.1 Voltage Limits Due to Hot Carrier Induced FET Degradation
    • 14.1.4.2. Voltage Limits Due to Gate Oxide Breakdown
• 14.2 Electro-migration
  • 14.2.1 Current
  • 14.2.2 Temperature
• 14.3 Latch-up Rules and Guidelines
  • 14.3.1 Core Latch-up Rules and Guidelines
  • 14.3.2 I/O Latch-up Related Rules and Guidelines
  • 14.3.3 Special Cases in the circuit
  • 14.3.4 other better layout practices (guidelines) for latch-up prevention
• 14.4 ESD Layout Guidelines
  • 14.4.1 Design Guidelines for 3.3V LV SAB MOSFET Device
  • 14.4.2 Design Guidelines for 3.3V LV Diode
  • 14.4.3 Design Guidelines for 5V/6V HV SAB NMOS Device
  • 14.4.4 Design Guidelines for 5V/6V HV SAB PMOS Device
  • 14.4.5 Design Guidelines for 5V/6V HV Diode
• 14.5 ESD Characterization Data
  • 14.5.1 ESD Performance from 3.3V NMOS transistor
  • 14.5.2 ESD Performance from 3.3V LV N+/PWELL diode
  • 14.5.3 ESD Performance from 3.3V LV P+/NWELL diode
  • 14.5.4. ESD Performance from 3.3V LV NWELL/PSUB diode
  • 14.5.5 ESD Performance from 5V/6V NMOS transistor
  • 14.5.6 ESD Performance from 5V/6V PMOS transistor
  • 14.5.7 ESD Performance from 5V/6V HV N+/PWELL diode
  • 14.5.8 ESD Performance from 5V/6V HV P+/NWELL diode
• 14.6 Stress Relief Guidelines
  • 14.6.1 Rules for Location of Metal Line to be slotted
  • 14.6.2 Die Corners Guidelines
  • 14.6.3 Metal Slotting rules