[
    {
        "BriefDescription": "Counts the number of machine clears due to memory ordering caused by a snoop from an external agent. Does not count internally generated machine clears such as those due to memory disambiguation.",
        "Counter": "0,1,2,3",
        "EventCode": "0xc3",
        "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
        "SampleAfterValue": "20003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of misaligned load uops that are 4K page splits.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "MISALIGN_MEM_REF.LOAD_PAGE_SPLIT",
        "PEBS": "1",
        "PublicDescription": "Counts the number of misaligned load uops that are 4K page splits. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Counts the number of misaligned store uops that are 4K page splits.",
        "Counter": "0,1,2,3",
        "EventCode": "0x13",
        "EventName": "MISALIGN_MEM_REF.STORE_PAGE_SPLIT",
        "PEBS": "1",
        "PublicDescription": "Counts the number of misaligned store uops that are 4K page splits. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts all code reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000044",
        "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000044",
        "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000044",
        "PublicDescription": "Counts all code reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all code reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.ALL_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000044",
        "PublicDescription": "Counts all code reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.COREWB_M.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3002184000000",
        "PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.COREWB_M.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x3002184000000",
        "PublicDescription": "Counts modified writebacks from L1 cache and L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_CODE_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "PublicDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000001",
        "PublicDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000001",
        "PublicDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "PublicDescription": "Counts cacheable demand data reads, L1 data cache hardware prefetches and software prefetches (except PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "PublicDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.DRAM Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000001",
        "PublicDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000001",
        "PublicDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.L3_MISS_LOCAL Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM",
        "Counter": "0,1,2,3",
        "Deprecated": "1",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_DATA_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000001",
        "PublicDescription": "This event is deprecated. Refer to new event OCR.DEMAND_DATA_AND_L1PF_RD.LOCAL_DRAM Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.DEMAND_RFO.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000002",
        "PublicDescription": "Counts demand reads for ownership (RFO) and software prefetches for exclusive ownership (PREFETCHW) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x802184000000",
        "PublicDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.FULL_STREAMING_WR.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x802184000000",
        "PublicDescription": "Counts streaming stores which modify a full 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_CODE_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000040",
        "PublicDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000040",
        "PublicDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_CODE_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000040",
        "PublicDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_CODE_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000040",
        "PublicDescription": "Counts L2 cache hardware prefetch code reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_DATA_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000010",
        "PublicDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000010",
        "PublicDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_DATA_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000010",
        "PublicDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_DATA_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000010",
        "PublicDescription": "Counts L2 cache hardware prefetch data reads (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_RFO.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000020",
        "PublicDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_RFO.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000020",
        "PublicDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_RFO.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000020",
        "PublicDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.HWPF_L2_RFO.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000020",
        "PublicDescription": "Counts L2 cache hardware prefetch RFOs (written to the L2 cache only) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.L1WB_M.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1002184000000",
        "PublicDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.L1WB_M.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x1002184000000",
        "PublicDescription": "Counts modified writebacks from L1 cache that miss the L2 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.L2WB_M.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2002184000000",
        "PublicDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.L2WB_M.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2002184000000",
        "PublicDescription": "Counts modified writeBacks from L2 cache that miss the L3 cache that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.OTHER.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184008000",
        "PublicDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.OTHER.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184008000",
        "PublicDescription": "Counts miscellaneous requests, such as I/O accesses, that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x402184000000",
        "PublicDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.PARTIAL_STREAMING_WR.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x402184000000",
        "PublicDescription": "Counts streaming stores which modify only part of a 64 byte cacheline that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.PREFETCHES.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000470",
        "PublicDescription": "Counts all hardware and software prefetches that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.READS_TO_CORE.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000477",
        "PublicDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.READS_TO_CORE.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000477",
        "PublicDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.READS_TO_CORE.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000477",
        "PublicDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.READS_TO_CORE.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x184000477",
        "PublicDescription": "Counts all data read, code read and RFO requests including demands and prefetches to the core caches (L1 or L2) that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.STREAMING_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000800",
        "PublicDescription": "Counts streaming stores that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts streaming stores that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.STREAMING_WR.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x2184000800",
        "PublicDescription": "Counts streaming stores that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x100184000000",
        "PublicDescription": "Counts uncached memory reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x102184000000",
        "PublicDescription": "Counts uncached memory reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x102184000000",
        "PublicDescription": "Counts uncached memory reads that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory reads that were supplied by DRAM.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_RD.LOCAL_DRAM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x100184000000",
        "PublicDescription": "Counts uncached memory reads that were supplied by DRAM. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_WR.L3_MISS",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x202184000000",
        "PublicDescription": "Counts uncached memory writes that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts uncached memory writes that were not supplied by the L3 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0XB7",
        "EventName": "OCR.UC_WR.L3_MISS_LOCAL",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x202184000000",
        "PublicDescription": "Counts uncached memory writes that were not supplied by the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    }
]
