[
    {
        "BriefDescription": "read requests to memory controller. Derived from unc_m_cas_count.rd",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "LLC_MISSES.MEM_READ",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
        "ScaleUnit": "64Bytes",
        "UMask": "0xf",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "write requests to memory controller. Derived from unc_m_cas_count.wr",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "LLC_MISSES.MEM_WRITE",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
        "ScaleUnit": "64Bytes",
        "UMask": "0x30",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : All Activates",
        "Counter": "0,1,2,3",
        "EventCode": "0x01",
        "EventName": "UNC_M_ACT_COUNT.ALL",
        "PerPkg": "1",
        "PublicDescription": "DRAM Activate Count : All Activates : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "UMask": "0xb",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : Activate due to Bypass",
        "Counter": "0,1,2,3",
        "EventCode": "0x01",
        "EventName": "UNC_M_ACT_COUNT.BYP",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM Activate Count : Activate due to Bypass : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM CAS commands issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.ALL",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM CAS commands issued on this channel.",
        "UMask": "0x3f",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM read CAS commands issued (including underfills)",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM Read CAS commands, w/ and w/o auto-pre, issued on this channel.  This includes underfills.",
        "UMask": "0xf",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_PRE_REG",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS commands w/auto-pre : DRAM RD_CAS and WR_CAS Commands : Counts the total number or DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with explicit Precharge.  AutoPre is only used in systems that are using closed page policy.  We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands.",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_PRE_UNDERFILL",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM RD_CAS and WR_CAS Commands",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM read CAS commands issued (does not include underfills)",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_REG",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM Read CAS commands issued on this channel.  This includes both regular RD CAS commands as well as those with implicit Precharge.   We do not filter based on major mode, as RD_CAS is not issued during WMM (with the exception of underfills).",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM underfill read CAS commands issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.RD_UNDERFILL",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Counts the total of DRAM Read CAS commands issued due to an underfill",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "All DRAM write CAS commands issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR",
        "PerPkg": "1",
        "PublicDescription": "Counts the total number of DRAM Write CAS commands issued, w/ and w/o auto-pre, on this channel.",
        "UMask": "0x30",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR_NONPRE",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/o auto-pre : DRAM RD_CAS and WR_CAS Commands",
        "UMask": "0x10",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre",
        "Counter": "0,1,2,3",
        "EventCode": "0x04",
        "EventName": "UNC_M_CAS_COUNT.WR_PRE",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM RD_CAS and WR_CAS Commands. : DRAM WR_CAS commands w/ auto-pre : DRAM RD_CAS and WR_CAS Commands",
        "UMask": "0x20",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Memory controller clock ticks",
        "Counter": "0,1,2,3",
        "EventName": "UNC_M_CLOCKTICKS",
        "PerPkg": "1",
        "PublicDescription": "Clockticks of the integrated memory controller (IMC)",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Free running counter that increments for the Memory Controller",
        "Counter": "4",
        "EventCode": "0xff",
        "EventName": "UNC_M_CLOCKTICKS_FREERUN",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "imc_free_running"
    },
    {
        "BriefDescription": "DRAM Precharge All Commands",
        "Counter": "0,1,2,3",
        "EventCode": "0x44",
        "EventName": "UNC_M_DRAM_PRE_ALL",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge All Commands : Counts the number of times that the precharge all command was sent.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.HIGH",
        "PerPkg": "1",
        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.OPPORTUNISTIC",
        "PerPkg": "1",
        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Number of DRAM Refreshes Issued",
        "Counter": "0,1,2,3",
        "EventCode": "0x45",
        "EventName": "UNC_M_DRAM_REFRESH.PANIC",
        "PerPkg": "1",
        "PublicDescription": "Number of DRAM Refreshes Issued : Counts the number of refreshes issued.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Half clockticks for IMC",
        "Counter": "FIXED",
        "EventCode": "0xff",
        "EventName": "UNC_M_HCLOCKTICKS",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PARITY_ERRORS",
        "Counter": "0,1,2,3",
        "EventCode": "0x2c",
        "EventName": "UNC_M_PARITY_ERRORS",
        "Experimental": "1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.RD",
        "Counter": "0,1,2,3",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.RD",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.TOTAL",
        "Counter": "0,1,2,3",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.TOTAL",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "UNC_M_PCLS.WR",
        "Counter": "0,1,2,3",
        "EventCode": "0xA0",
        "EventName": "UNC_M_PCLS.WR",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles where DRAM ranks are in power down (CKE) mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x85",
        "EventName": "UNC_M_POWER_CHANNEL_PPD",
        "Experimental": "1",
        "MetricExpr": "(UNC_M_POWER_CHANNEL_PPD / UNC_M_CLOCKTICKS) * 100",
        "MetricName": "power_channel_ppd",
        "PerPkg": "1",
        "PublicDescription": "Channel PPD Cycles : Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_2",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "CKE_ON_CYCLES by Rank : DIMM ID",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWER_CKE_CYCLES.LOW_3",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "CKE_ON_CYCLES by Rank : DIMM ID : Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "UNC_M_POWER_CRIT_THROTTLE_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Cycles Memory is in self refresh power mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "UNC_M_POWER_SELF_REFRESH",
        "Experimental": "1",
        "MetricExpr": "(UNC_M_POWER_SELF_REFRESH / UNC_M_CLOCKTICKS) * 100",
        "MetricName": "power_self_refresh",
        "PerPkg": "1",
        "PublicDescription": "Clock-Enabled Self-Refresh : Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1. : Thermal throttling is performed per DIMM.  We support 3 DIMMs per channel.  This ID allows us to filter by ID.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Throttle Cycles for Rank 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Throttle Cycles for Rank 0 : Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands.",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.ALL",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
        "UMask": "0x1c",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charges due to page misses",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.PAGE_MISS",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge commands. : Precharge due to page miss : Counts the number of DRAM Precharge commands sent on this channel. : Pages Misses are due to precharges from bank scheduler (rd/wr requests)",
        "UMask": "0xc",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Precharge due to page table",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.PGT",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge commands. : Precharge due to page table : Counts the number of DRAM Precharge commands sent on this channel. : Precharges from Page Table",
        "UMask": "0x10",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charge for reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.RD",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge commands. : Precharge due to read : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from read bank scheduler",
        "UMask": "0x4",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Pre-charge for writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_PRE_COUNT.WR",
        "PerPkg": "1",
        "PublicDescription": "DRAM Precharge commands. : Precharge due to write : Counts the number of DRAM Precharge commands sent on this channel. : Precharge from write bank scheduler",
        "UMask": "0x8",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Full",
        "Counter": "0,1,2,3",
        "EventCode": "0x19",
        "EventName": "UNC_M_RDB_FULL",
        "Experimental": "1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Inserts",
        "Counter": "0,1,2,3",
        "EventCode": "0x17",
        "EventName": "UNC_M_RDB_INSERTS",
        "Experimental": "1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Not Empty",
        "Counter": "0,1,2,3",
        "EventCode": "0x18",
        "EventName": "UNC_M_RDB_NOT_EMPTY",
        "Experimental": "1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Data Buffer Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x1A",
        "EventName": "UNC_M_RDB_OCCUPANCY",
        "Experimental": "1",
        "PerPkg": "1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x12",
        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x15",
        "EventName": "UNC_M_RPQ_CYCLES_FULL_PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Full Cycles : Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "EventCode": "0x11",
        "EventName": "UNC_M_RPQ_CYCLES_NE.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Not Empty : Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH0",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Read Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x81",
        "EventName": "UNC_M_RPQ_OCCUPANCY_PCH1",
        "PerPkg": "1",
        "PublicDescription": "Read Pending Queue Occupancy : Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Full Cycles",
        "Counter": "0,1,2,3",
        "EventCode": "0x16",
        "EventName": "UNC_M_WPQ_CYCLES_FULL_PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Full Cycles : Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Not Empty",
        "Counter": "0,1,2,3",
        "EventCode": "0x21",
        "EventName": "UNC_M_WPQ_CYCLES_NE.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Not Empty : Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Allocations : Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x82",
        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH0",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue Occupancy",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "UNC_M_WPQ_OCCUPANCY_PCH1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue Occupancy : Accumulates the occupancies of the Write Pending Queue each cycle.  This can then be used to calculate both the average queue occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have posted to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.  So, we provide filtering based on if the request has posted or not.  By using the not posted filter, we can track how long writes spent in the iMC before completions were sent to the HA.  The posted filter, on the other hand, provides information about how much queueing is actually happening in the iMC for writes before they are actually issued to memory.  High average occupancies will generally coincide with high write major mode counts.",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "EventCode": "0x23",
        "EventName": "UNC_M_WPQ_READ_HIT.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "EventCode": "0x23",
        "EventName": "UNC_M_WPQ_READ_HIT.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
        "UMask": "0x2",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
        "UMask": "0x1",
        "Unit": "iMC"
    },
    {
        "BriefDescription": "Write Pending Queue CAM Match",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "UNC_M_WPQ_WRITE_HIT.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "Write Pending Queue CAM Match : Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
        "UMask": "0x2",
        "Unit": "iMC"
    }
]
