[
	{
		"EventCode": "0xB1",
		"EventName": "cycle_wait_icache_fill",
		"BriefDescription": "Cycles waiting for ICACHE fill data"
	},
	{
		"EventCode": "0xC1",
		"EventName": "cycle_wait_dcache_fill",
		"BriefDescription": "Cycles waiting for DCACHE fill data"
	},
	{
		"EventCode": "0xD1",
		"EventName": "uncached_ifetch_from_bus",
		"BriefDescription": "Uncached ifetch data access from bus"
	},
	{
		"EventCode": "0xE1",
		"EventName": "uncached_load_from_bus",
		"BriefDescription": "Uncached load data access from bus"
	},
	{
		"EventCode": "0xF1",
		"EventName": "cycle_wait_uncached_ifetch",
		"BriefDescription": "Cycles waiting for uncached ifetch data from bus"
	},
	{
		"EventCode": "0x101",
		"EventName": "cycle_wait_uncached_load",
		"BriefDescription": "Cycles waiting for uncached load data from bus"
	},
	{
		"EventCode": "0x111",
		"EventName": "main_itlb_access",
		"BriefDescription": "Main ITLB access"
	},
	{
		"EventCode": "0x121",
		"EventName": "main_itlb_miss",
		"BriefDescription": "Main ITLB miss"
	},
	{
		"EventCode": "0x131",
		"EventName": "main_dtlb_access",
		"BriefDescription": "Main DTLB access"
	},
	{
		"EventCode": "0x141",
		"EventName": "main_dtlb_miss",
		"BriefDescription": "Main DTLB miss"
	},
	{
		"EventCode": "0x151",
		"EventName": "cycle_wait_itlb_fill",
		"BriefDescription": "Cycles waiting for Main ITLB fill data"
	},
	{
		"EventCode": "0x161",
		"EventName": "pipe_stall_cycle_dtlb_miss",
		"BriefDescription": "Pipeline stall cycles caused by Main DTLB miss"
	},
	{
		"EventCode": "0x02",
		"EventName": "mispredict_condition_br",
		"BriefDescription": "Misprediction of conditional branches"
	},
	{
		"EventCode": "0x12",
		"EventName": "mispredict_take_condition_br",
		"BriefDescription": "Misprediction of taken conditional branches"
	},
	{
		"EventCode": "0x22",
		"EventName": "mispredict_target_ret_inst",
		"BriefDescription": "Misprediction of targets of Return instructions"
	}
]
