[
    {
        "BriefDescription": "Counts the number of request that were not accepted into the L2Q because the L2Q is FULL.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x31",
        "EventName": "CORE_REJECT_L2Q.ANY",
        "PublicDescription": "Counts the number of (demand and L1 prefetchers) core requests rejected by the L2Q due to a full or nearly full w condition which likely indicates back pressure from L2Q.  It also counts requests that would have gone directly to the XQ, but are rejected due to a full or nearly full condition, indicating back pressure from the IDI link.  The L2Q may also reject transactions  from a core to insure fairness between cores, or to delay a cores dirty eviction when the address conflicts incoming external snoops.  (Note that L2 prefetcher requests that are dropped are not counted by this event.)",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x51",
        "EventName": "DL1.DIRTY_EVICTION",
        "PublicDescription": "Counts the number of L1D cacheline (dirty) evictions caused by load misses, stores, and prefetches.  Does not count evictions or dirty writebacks caused by snoops.  Does not count a replacement unless a (dirty) line was written back.",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines replaced in L0 data cache.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.L0_REPLACEMENT",
        "PublicDescription": "Counts L0 data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cachelines replaced into the L0 and L1 d-cache. Successful replacements only (not blocked) and exclude WB-miss case",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts cachelines replaced into the L0 and L1 d-cache.",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.L2_STALLS",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of demand requests that missed L1D cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x49",
        "EventName": "L1D_MISS.LOAD",
        "PublicDescription": "Count occurrences (rising-edge) of DCACHE_PENDING sub-event0. Impl. sends per-port binary inc-bit the occupancy increases* (at FB alloc or promotion).",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "Counter": "2",
        "EventCode": "0x48",
        "EventName": "L1D_PENDING.LOAD",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "2",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PENDING.LOAD_CYCLES",
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "UMask": "0x1f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Exclusive state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.E",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Forward state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.F",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Invalid state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.I",
        "PublicDescription": "Counts the number of cache lines filled into the L2 cache that are in Invalid state, does not count lines that go Invalid due to an eviction",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Modified state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.M",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cache lines filled into the L2 cache that are in Shared state",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x25",
        "EventName": "L2_LINES_IN.S",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of L2 cache lines that are evicted due to an L2 cache fill. Increments on the core that brought the line in originally.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of L2 cache lines that are silently dropped due to an L2 cache fill.  Increments on the core that brought the line in originally.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PublicDescription": "Counts the number of L2 cache lines that have been L2 hardware prefetched but not used by demand accesses.  Increments on the core that brought the line in originally.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x26",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
        "SampleAfterValue": "200003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were  throttled due to Dynamic Prefetch Throttling. The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor.  Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x28",
        "EventName": "L2_PREFETCHES_THROTTLED.DPT",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream that were throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x28",
        "EventName": "L2_PREFETCHES_THROTTLED.DTP",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 prefetches initiated by the L2 Stream and not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism besides DTP. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x28",
        "EventName": "L2_PREFETCHES_THROTTLED.DTP_OVERRIDE",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 prefetches initiated by either the L2 Stream or AMP that were throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or XQ_THRESHOLD. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x28",
        "EventName": "L2_PREFETCHES_THROTTLED.XQ_THRESH",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x30",
        "EventName": "L2_REJECT_XQ.ANY",
        "PublicDescription": "Counts the number of demand and prefetch transactions that the External Queue (XQ) rejects due to a full or near full condition which likely indicates back pressure from the IDI link.  The XQ may reject transactions from the L2Q (non-cacheable requests), BBL (L2 misses) and WOB (L2 write-back victims).",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only, per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PublicDescription": "Counts the number of L2 Cache Accesses Counts the total number of L2 Cache Accesses - sum of hits, misses, rejects  front door requests for CRd/DRd/RFO/ItoM/L2 Prefetches only.",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES, L2_RQSTS.ANY]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.ALL",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES, L2_RQSTS.ANY]",
        "SampleAfterValue": "200003",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache Accesses that resulted in a Hit from a front door request only (does not include rejects or recycles), per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of total L2 Cache Accesses that resulted in a Miss from a front door request only (does not include rejects or recycles), per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_RQSTS.MISS]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.MISS",
        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.MISS]",
        "SampleAfterValue": "200003",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of L2 Cache Accesses that miss the L2 and get BBL reject  short and long rejects (includes those counted in L2_reject_XQ.any), per core event",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x24",
        "EventName": "L2_REQUEST.REJECTS",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "L2 code requests",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PublicDescription": "Counts the total number of L2 code requests.",
        "SampleAfterValue": "200003",
        "UMask": "0xe4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read access L2 cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
        "SampleAfterValue": "200003",
        "UMask": "0xe1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache [This event is alias to L2_RQSTS.REFERENCES, L2_REQUEST.ALL]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ANY",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_RQSTS.REFERENCES, L2_REQUEST.ALL]",
        "SampleAfterValue": "200003",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
        "SampleAfterValue": "200003",
        "UMask": "0x44",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "L2 cache misses when fetching instructions",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x24",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read miss L2 cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
        "SampleAfterValue": "200003",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache [This event is alias to L2_REQUEST.MISS]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.MISS",
        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.MISS]",
        "SampleAfterValue": "200003",
        "UMask": "0x3f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All accesses to L2 cache [This event is alias to L2_REQUEST.ALL,L2_RQSTS.ANY]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.REFERENCES",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. [This event is alias to L2_REQUEST.ALL,L2_RQSTS.ANY]",
        "SampleAfterValue": "200003",
        "UMask": "0xff",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that hit L2 cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_HIT",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x42",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "RFO requests that miss L2 cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_MISS",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x22",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of LLC prefetches that were  throttled due to Dynamic Prefetch Throttling.  The throttle requestor/source could be from the uncore/SOC or the Dead Block Predictor. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x29",
        "EventName": "LLC_PREFETCHES_THROTTLED.DPT",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of LLC prefetches throttled due to Demand Throttle Prefetcher.  DTP Global Triggered with no Local Override. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x29",
        "EventName": "LLC_PREFETCHES_THROTTLED.DTP",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of LLC prefetches not throttled by DTP due to local override.  These prefetches may still be throttled due to another throttler mechanism. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x29",
        "EventName": "LLC_PREFETCHES_THROTTLED.DTP_OVERRIDE",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of LLC prefetches throttled due to LLC hit rate in <insert knob name here>. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x29",
        "EventName": "LLC_PREFETCHES_THROTTLED.HIT_RATE",
        "SampleAfterValue": "1000003",
        "UMask": "0x10",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of LLC prefetches throttled due to exceeding the XQ threshold set by either XQ_THRESOLD_DTP or LLC_XQ_THRESHOLD. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x29",
        "EventName": "LLC_PREFETCHES_THROTTLED.XQ_THRESH",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Cycles when L1D is locked",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x42",
        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
        "PublicDescription": "This event counts the number of cycles when the L1D is locked.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that miss in the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts the number of cacheable memory requests that miss in the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
        "SampleAfterValue": "100003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cacheable memory requests that access the LLC. Counts on a per core basis.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts the number of cacheable memory requests that access the Last Level Cache (LLC). Requests include demand loads, reads for ownership (RFO), instruction fetches and L1 HW prefetches. If the core has access to an L3 cache, the LLC is the L3 cache, otherwise it is the L2 cache. Counts on a per core basis.",
        "SampleAfterValue": "200003",
        "UMask": "0x4f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that refer to L3 (Except hardware prefetches to the L3)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.REFERENCE",
        "PublicDescription": "Counts core-originated cacheable requests to the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
        "SampleAfterValue": "100003",
        "UMask": "0x4f",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.L2_HIT",
        "PublicDescription": "Counts the number of cycles the core is stalled due to an instruction cache or Translation Lookaside Buffer (TLB) miss which hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to an instruction cache or TLB miss which missed in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x35",
        "EventName": "MEM_BOUND_STALLS_IFETCH.L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x7e",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to an L1 demand load miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7f",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which hit in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.L2_HIT",
        "PublicDescription": "Counts the number of cycles a core is stalled due to a demand load which hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles the core is stalled due to a demand load which missed in the L2 cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x7e",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled due to a demand load miss which missed all the local caches.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.LLC_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x78",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of unhalted cycles when the core is stalled to a store buffer full condition",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x34",
        "EventName": "MEM_BOUND_STALLS_LOAD.SBFULL",
        "SampleAfterValue": "1000003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts all retired load instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "PublicDescription": "Counts Instructions with at least one architecturally visible load retired. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x81",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "PublicDescription": "Counts all retired store instructions. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x82",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired software prefetch instructions.",
        "Counter": "0,1,2,3",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_SWPF",
        "PublicDescription": "Counts all retired software prefetch instructions. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x84",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "All retired memory instructions.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ANY",
        "PublicDescription": "Counts all retired memory instructions - loads and stores. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x87",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with locked access.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "PublicDescription": "Counts retired load instructions with locked access. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x21",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x41",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x42",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that hit the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_HIT_LOADS",
        "PublicDescription": "Number of retired load instructions with a clean hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x9",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that hit the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_HIT_STORES",
        "PublicDescription": "Number of retired store instructions that hit in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0xa",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x11",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired store instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB). Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x12",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$)",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
        "PublicDescription": "Counts retired load instructions whose data sources were a cross-core Snoop hits and forwards data from an in on-package core cache (induced by NI$) Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_HITM",
        "PublicDescription": "Counts retired load instructions whose data sources were HitM responses from shared L3, Hit-with-FWD is normally excluded. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
        "PublicDescription": "Counts retired load instructions whose data sources were L3 and cross-core snoop hits in on-pkg core cache. Available PDIST counters: 0",
        "SampleAfterValue": "20011",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions which data source is memory side cache.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_L3_MISS_RETIRED.MEMSIDE_CACHE",
        "PublicDescription": "Retired load instructions which data source is memory side cache. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access (Bus Lock). Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready. Available PDIST counters: 0",
        "SampleAfterValue": "100007",
        "UMask": "0x40",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x101",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT_L0",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the Level 0 of the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT_L1",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the Level 1 of the L1 data cache. Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources. Available PDIST counters: 0",
        "SampleAfterValue": "200003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources. Available PDIST counters: 0",
        "SampleAfterValue": "100021",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "100021",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache. Available PDIST counters: 0",
        "SampleAfterValue": "50021",
        "UMask": "0x20",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
        "Counter": "0,1,2,3,4,5,6,7",
        "Deprecated": "1",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This event is deprecated. Refer to new event MEM_LOAD_UOPS_LLC_MISS_RETIRED.MEMSIDE_CACHE",
        "Counter": "0,1,2,3,4,5,6,7",
        "Deprecated": "1",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.MEMSIDE_CACHE",
        "SampleAfterValue": "1000003",
        "UMask": "0x40",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss the L2 cache, missed the Memory Side Cache and hit in DRAM",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.LOCAL_DRAM",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss the LLC cache and hit in the Memory Side Cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd3",
        "EventName": "MEM_LOAD_UOPS_LLC_MISS_RETIRED.MEMSIDE_CACHE",
        "SampleAfterValue": "1000003",
        "UMask": "0x40",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that hit the L1 data cache",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss in the L1 data cache",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x40",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that hit in the L2 cache",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
        "PublicDescription": "Counts the number of load ops retired that hit in the L2 cache.  Includes L2 Hit resulting from and L1D eviction of another core in the same module which is longer latency than a typical L2 hit.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that miss in the L2 cache",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
        "SampleAfterValue": "1000003",
        "UMask": "0x80",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of loads that hit in a write combining buffer (WCB), excluding the first load that caused the WCB to allocate.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_UOPS_RETIRED.WCB_HIT",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked for any of the following reasons:  load buffer, store buffer or RSV full.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to load buffer full",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.LD_BUF",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to RSV full",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.RSV",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of cycles that uops are blocked due to store buffer full",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x04",
        "EventName": "MEM_SCHEDULER_BLOCK.ST_BUF",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "MEM_STORE_RETIRED.L2_HIT",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x44",
        "EventName": "MEM_STORE_RETIRED.L2_HIT",
        "SampleAfterValue": "200003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of cache-lines required by retired stores whose Data Source is: Memory Side Cache",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x44",
        "EventName": "MEM_STORE_RETIRED.MEMSIDE_CACHE",
        "SampleAfterValue": "100021",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of memory uops retired.  A single uop that performs both a load AND a store will be counted as 1, not 2 (e.g. ADD [mem], CONST)",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL",
        "SampleAfterValue": "200003",
        "UMask": "0x83",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x81",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of store uops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.ALL_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x82",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_128",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x80",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_16",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x10",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_256",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x100",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_32",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x20",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_4",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x4",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_512",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x200",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_64",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x40",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of tagged load uops retired that exceed the latency threshold defined in MEC_CR_PEBS_LD_LAT_THRESHOLD - Only counts with PEBS enabled",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOAD_LATENCY_GT_8",
        "MSRIndex": "0x3F6",
        "MSRValue": "0x8",
        "SampleAfterValue": "200003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load uops retired that performed one or more locks",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x21",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory renamed load uops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.MRN_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x9",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory renamed store uops retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.MRN_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0xa",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory uops retired that were splits.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT",
        "SampleAfterValue": "200003",
        "UMask": "0x43",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired split load uops.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x41",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retired split store uops.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x42",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of memory uops retired that missed in the second level TLB.",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS",
        "SampleAfterValue": "200003",
        "UMask": "0x13",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of load ops retired that filled the STLB - includes those in DTLB_LOAD_MISSES submasks",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
        "SampleAfterValue": "200003",
        "UMask": "0x11",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of store ops retired (store STLB miss)",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
        "SampleAfterValue": "200003",
        "UMask": "0x12",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of  stores uops retired same as MEM_UOPS_RETIRED.ALL_STORES",
        "Counter": "0,1,2,3,4,5,6,7",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_UOPS_RETIRED.STORE_LATENCY",
        "SampleAfterValue": "200003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Retired memory uops for any access",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xe5",
        "EventName": "MEM_UOP_RETIRED.ANY",
        "PublicDescription": "Number of retired micro-operations (uops) for load or store memory accesses",
        "SampleAfterValue": "1000003",
        "UMask": "0xf",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts writebacks of modified cachelines that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.COREWB_M.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10008",
        "PublicDescription": "Counts writebacks of modified cachelines that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts writebacks of non-modified cachelines that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.COREWB_NONM.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x11000",
        "PublicDescription": "Counts writebacks of non-modified cachelines that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by mem side cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_CODE_RD.MEMSIDE_CACHE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x11F80000004",
        "PublicDescription": "Counts demand instruction fetches and L1 instruction cache prefetches that were supplied by mem side cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand data reads that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10001",
        "PublicDescription": "Counts demand data reads that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x40001E00001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x20001E00001",
        "PublicDescription": "Counts demand data reads that were supplied by the L3 cache where a snoop hit in another cores caches which forwarded the unmodified data to the requesting core. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand data reads that were supplied by mem side cache.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_DATA_RD.MEMSIDE_CACHE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x11F80000001",
        "PublicDescription": "Counts demand data reads that were supplied by mem side cache. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xB7",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.ANY_RESPONSE",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10002",
        "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that have any type of response. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0x2A,0x2B",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x40001E00002",
        "PublicDescription": "Counts demand read for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that were supplied by the L3 cache where a snoop hit in another cores caches, data forwarding is required as the data is modified. Available PDIST counters: 0",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Any memory transaction that reached the SQ.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
        "SampleAfterValue": "100003",
        "UMask": "0x80",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand and prefetch data reads",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DATA_RD",
        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cacheable and Non-Cacheable code read requests",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
        "PublicDescription": "Counts both cacheable and Non-Cacheable code read requests.",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x21",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles where at least 1 outstanding demand data read request is pending.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DATA_RD",
        "SampleAfterValue": "1000003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore, every cycle.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "PublicDescription": "For every cycle, increments by the number of outstanding demand data read requests pending.   Requests are considered outstanding from the time they miss the core's L2 cache until the transaction completion message is sent to the requestor.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
        "Counter": "0,1,2,3",
        "EventCode": "0x20",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x2c",
        "EventName": "SQ_MISC.BUS_LOCK",
        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
        "SampleAfterValue": "100003",
        "UMask": "0x10",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.ANY",
        "SampleAfterValue": "100003",
        "UMask": "0xf",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x8",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x40",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of issue slots every cycle that were not delivered by the frontend due to an icache miss",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x71",
        "EventName": "TOPDOWN_FE_BOUND.ICACHE",
        "SampleAfterValue": "1000003",
        "UMask": "0x20",
        "Unit": "cpu_atom"
    }
]
