[
    {
        "BriefDescription": "DRAM Activate Count : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_ACT_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0xf7",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_ACT_COUNT.RD",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : Underfill Read transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_ACT_COUNT.UFILL",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Activate Count : Write transaction on Page Empty or Page Miss : Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
        "Counter": "0,1,2,3",
        "EventCode": "0x02",
        "EventName": "UNC_M_ACT_COUNT.WR",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0, all CAS operations",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.ALL",
        "PerPkg": "1",
        "UMask": "0xff",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0, all reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.RD",
        "PerPkg": "1",
        "UMask": "0xcf",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0 regular reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.RD_REG",
        "PerPkg": "1",
        "UMask": "0xc1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0 underfill reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.RD_UNDERFILL",
        "PerPkg": "1",
        "UMask": "0xc4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0, all writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.WR",
        "PerPkg": "1",
        "UMask": "0xf0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0 regular writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.WR_NONPRE",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xd0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 0 auto-precharge writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x05",
        "EventName": "UNC_M_CAS_COUNT_SCH0.WR_PRE",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xe0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1, all CAS operations",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.ALL",
        "PerPkg": "1",
        "UMask": "0xff",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1, all reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.RD",
        "PerPkg": "1",
        "UMask": "0xcf",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1 regular reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.RD_REG",
        "PerPkg": "1",
        "UMask": "0xc1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1 underfill reads",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.RD_UNDERFILL",
        "PerPkg": "1",
        "UMask": "0xc4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1, all writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.WR",
        "PerPkg": "1",
        "UMask": "0xf0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1 regular writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.WR_NONPRE",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xd0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "CAS count for SubChannel 1 auto-precharge writes",
        "Counter": "0,1,2,3",
        "EventCode": "0x06",
        "EventName": "UNC_M_CAS_COUNT_SCH1.WR_PRE",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xe0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Number of DRAM DCLK clock cycles while the event is enabled.  DCLK is 1/4 of DRAM data rate.",
        "Counter": "0,1,2,3",
        "EventCode": "0x01",
        "EventName": "UNC_M_CLOCKTICKS",
        "PerPkg": "1",
        "PublicDescription": "DRAM Clockticks",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Number of DRAM HCLK clock cycles while the event is enabled",
        "Counter": "0,1,2,3",
        "EventCode": "0x01",
        "EventName": "UNC_M_HCLOCKTICKS",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "DRAM Clockticks",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
        "Counter": "0,1,2,3",
        "EventCode": "0xA7",
        "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
        "Counter": "0,1,2,3",
        "EventCode": "0xA7",
        "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH0_DIMM1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
        "Counter": "0,1,2,3",
        "EventCode": "0xA7",
        "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 temp readings forced 2x refresh",
        "Counter": "0,1,2,3",
        "EventCode": "0xA7",
        "EventName": "UNC_M_MR4_2XREF_CYCLES.SCH1_DIMM1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x8",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
        "Counter": "0,1,2,3",
        "EventCode": "0xA6",
        "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
        "Counter": "0,1,2,3",
        "EventCode": "0xA6",
        "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH0_DIMM1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
        "Counter": "0,1,2,3",
        "EventCode": "0xA6",
        "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles MR4 MRRs was triggered/running",
        "Counter": "0,1,2,3",
        "EventCode": "0xA6",
        "EventName": "UNC_M_PDC_MR4ACTIVE_CYCLES.SCH1_DIMM1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x8",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK2",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH0_RANK3",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x8",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x10",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x20",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK2",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x40",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode",
        "Counter": "0,1,2,3",
        "EventCode": "0x47",
        "EventName": "UNC_M_POWERDOWN_CYCLES.SCH1_RANK3",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x80",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles a given rank is in Power Down Mode and all pages are closed",
        "Counter": "0,1,2,3",
        "EventCode": "0x88",
        "EventName": "UNC_M_POWER_CHANNEL_PPD_CYCLES",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM and throttle level is zero.",
        "Counter": "0,1,2,3",
        "EventCode": "0x89",
        "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM and throttle level is zero.",
        "Counter": "0,1,2,3",
        "EventCode": "0x89",
        "EventName": "UNC_M_POWER_CRITICAL_THROTTLE_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT0",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT1",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.BW_SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "MR4 temp reading is throttling",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.MR4BLKEN",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x8",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "RAPL is throttling",
        "Counter": "0,1,2,3",
        "EventCode": "0x46",
        "EventName": "UNC_M_POWER_THROTTLE_CYCLES.RAPLBLK",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
        "Counter": "0,1,2,3",
        "EventCode": "0x03",
        "EventName": "UNC_M_PRE_COUNT.ALL",
        "PerPkg": "1",
        "UMask": "0xff",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Precharge due to (?) : Counts the number of DRAM Precharge commands sent on this channel.",
        "Counter": "0,1,2,3",
        "EventCode": "0x03",
        "EventName": "UNC_M_PRE_COUNT.PGT",
        "PerPkg": "1",
        "UMask": "0xf8",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
        "Counter": "0,1,2,3",
        "EventCode": "0x03",
        "EventName": "UNC_M_PRE_COUNT.RD",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
        "Counter": "0,1,2,3",
        "EventCode": "0x03",
        "EventName": "UNC_M_PRE_COUNT.UFILL",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf4",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "DRAM Precharge commands. : Counts the number of DRAM Precharge commands sent on this channel.",
        "Counter": "0,1,2,3",
        "EventCode": "0x03",
        "EventName": "UNC_M_PRE_COUNT.WR",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xf2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read buffer inserts on subchannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x17",
        "EventName": "UNC_M_RDB_INSERTS.SCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x40",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read buffer inserts on subchannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x17",
        "EventName": "UNC_M_RDB_INSERTS.SCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x80",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read buffer occupancy on subchannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x1a",
        "EventName": "UNC_M_RDB_OCCUPANCY_SCH0",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read buffer occupancy on subchannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x1b",
        "EventName": "UNC_M_RDB_OCCUPANCY_SCH1",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x50",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue Allocations : Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xa0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH0",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue inserts for subchannel 0, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.SCH0_PCH1",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH0",
        "PerPkg": "1",
        "UMask": "0x40",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read Pending Queue inserts for subchannel 1, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x10",
        "EventName": "UNC_M_RPQ_INSERTS.SCH1_PCH1",
        "PerPkg": "1",
        "UMask": "0x80",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH0",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read pending queue occupancy for subchannel 0, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x81",
        "EventName": "UNC_M_RPQ_OCCUPANCY_SCH0_PCH1",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x82",
        "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH0",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Read pending queue occupancy for subchannel 1, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "UNC_M_RPQ_OCCUPANCY_SCH1_PCH1",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "subevent0 - # of cycles all ranks were in SR subevent1 - # of times all ranks went into SR subevent2 -# of times  ps_sr_active asserted (SRE) subevent3 - # of times ps_sr_active deasserted (SRX) subevent4 - # of times PS-&>Refresh ps_sr_req asserted (SRE) subevent5 - # of times PS-&>Refresh ps_sr_req deasserted (SRX) subevent6 - # of cycles PSCtrlr FSM was in FATAL",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "UNC_M_SELF_REFRESH.ENTER_SUCCESS",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles all ranks were in SR",
        "Counter": "0,1,2,3",
        "EventCode": "0x43",
        "EventName": "UNC_M_SELF_REFRESH.ENTER_SUCCESS_CYCLES",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8e",
        "EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Critical level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8e",
        "EventName": "UNC_M_THROTTLE_CRIT_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at High level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8d",
        "EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at High level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8d",
        "EventName": "UNC_M_THROTTLE_HIGH_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Normal level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8b",
        "EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Normal level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8b",
        "EventName": "UNC_M_THROTTLE_LOW_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Mid level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8c",
        "EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT0",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "# of cycles Throttling at Mid level on specified DIMM",
        "Counter": "0,1,2,3",
        "EventCode": "0x8c",
        "EventName": "UNC_M_THROTTLE_MID_CYCLES.SLOT1",
        "Experimental": "1",
        "PerPkg": "1",
        "PublicDescription": "-",
        "UMask": "0x2",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.PCH0",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0x50",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue Allocations",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.PCH1",
        "Experimental": "1",
        "PerPkg": "1",
        "UMask": "0xa0",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH0",
        "PerPkg": "1",
        "UMask": "0x10",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue inserts for subchannel 0, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.SCH0_PCH1",
        "PerPkg": "1",
        "UMask": "0x20",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH0",
        "PerPkg": "1",
        "UMask": "0x40",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write Pending Queue inserts for subchannel 1, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x22",
        "EventName": "UNC_M_WPQ_INSERTS.SCH1_PCH1",
        "PerPkg": "1",
        "UMask": "0x80",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x84",
        "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH0",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write pending queue occupancy for subchannel 0, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x85",
        "EventName": "UNC_M_WPQ_OCCUPANCY_SCH0_PCH1",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x86",
        "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH0",
        "PerPkg": "1",
        "Unit": "IMC"
    },
    {
        "BriefDescription": "Write pending queue occupancy for subchannel 1, pseudochannel 1",
        "Counter": "0,1,2,3",
        "EventCode": "0x87",
        "EventName": "UNC_M_WPQ_OCCUPANCY_SCH1_PCH1",
        "PerPkg": "1",
        "Unit": "IMC"
    }
]
