[
    {
        "BriefDescription": "Counts the number of cache lines replaced in L1 data cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x51",
        "EventName": "L1D.REPLACEMENT",
        "PublicDescription": "Counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.FB_FULL_PERIODS",
        "PublicDescription": "Counts number of phases a demand request has waited due to L1D Fill Buffer (FB) unavailability. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of cycles a demand request has waited due to L1D due to lack of L2 resources.",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.L2_STALL",
        "PublicDescription": "Counts number of cycles a demand request has waited due to L1D due to lack of L2 resources. Demand requests include cacheable/uncacheable demand load, store, lock or SW prefetch accesses.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of L1D misses that are outstanding",
        "Counter": "0,1,2,3",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING",
        "PublicDescription": "Counts number of L1D misses that are outstanding in each cycle, that is each cycle the number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand from the demand Hit FB, if it is allocated by hardware or software prefetch. Note: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with L1D load Misses outstanding.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x48",
        "EventName": "L1D_PEND_MISS.PENDING_CYCLES",
        "PublicDescription": "Counts duration of L1D miss outstanding in cycles.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "L2 cache lines filling L2",
        "Counter": "0,1,2,3",
        "EventCode": "0xf1",
        "EventName": "L2_LINES_IN.ALL",
        "PublicDescription": "Counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
        "SampleAfterValue": "100003",
        "UMask": "0x1f"
    },
    {
        "BriefDescription": "Modified cache lines that are evicted by L2 cache when triggered by an L2 cache fill.",
        "Counter": "0,1,2,3",
        "EventCode": "0xf2",
        "EventName": "L2_LINES_OUT.NON_SILENT",
        "PublicDescription": "Counts the number of lines that are evicted by L2 cache when triggered by an L2 cache fill. Those lines are in Modified state. Modified lines are written back to L3",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Non-modified cache lines that are silently dropped by L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0xf2",
        "EventName": "L2_LINES_OUT.SILENT",
        "PublicDescription": "Counts the number of lines that are silently dropped by L2 cache. These lines are typically in Shared or Exclusive state. A non-threaded event.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cache lines that have been L2 hardware prefetched but not used by demand accesses",
        "Counter": "0,1,2,3",
        "EventCode": "0xf2",
        "EventName": "L2_LINES_OUT.USELESS_HWPF",
        "PublicDescription": "Counts the number of cache lines that have been prefetched by the L2 hardware prefetcher but not used by demand access when evicted from the L2 cache",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "L2 code requests",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_CODE_RD",
        "PublicDescription": "Counts the total number of L2 code requests.",
        "SampleAfterValue": "200003",
        "UMask": "0xe4"
    },
    {
        "BriefDescription": "Demand Data Read access L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
        "PublicDescription": "Counts Demand Data Read requests accessing the L2 cache. These requests may hit or miss L2 cache. True-miss exclude misses that were merged with ongoing L2 misses. An access is counted once.",
        "SampleAfterValue": "200003",
        "UMask": "0xe1"
    },
    {
        "BriefDescription": "RFO requests to L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.ALL_RFO",
        "PublicDescription": "Counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
        "SampleAfterValue": "200003",
        "UMask": "0xe2"
    },
    {
        "BriefDescription": "L2 cache hits when fetching instructions, code reads.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_HIT",
        "PublicDescription": "Counts L2 cache hits when fetching instructions, code reads.",
        "SampleAfterValue": "200003",
        "UMask": "0xc4"
    },
    {
        "BriefDescription": "L2 cache misses when fetching instructions",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.CODE_RD_MISS",
        "PublicDescription": "Counts L2 cache misses when fetching instructions.",
        "SampleAfterValue": "200003",
        "UMask": "0x24"
    },
    {
        "BriefDescription": "Demand Data Read requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
        "PublicDescription": "Counts the number of demand Data Read requests initiated by load instructions that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0xc1"
    },
    {
        "BriefDescription": "Demand Data Read miss L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
        "PublicDescription": "Counts demand Data Read requests with true-miss in the L2 cache. True-miss excludes misses that were merged with ongoing L2 misses. An access is counted once.",
        "SampleAfterValue": "200003",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Read requests with true-miss in L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.MISS",
        "PublicDescription": "Counts read requests of any type with true-miss in the L2 cache. True-miss excludes L2 misses that were merged with ongoing L2 misses.",
        "SampleAfterValue": "200003",
        "UMask": "0x3f"
    },
    {
        "BriefDescription": "All accesses to L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.REFERENCES",
        "PublicDescription": "Counts all requests that were hit or true misses in L2 cache. True-miss excludes misses that were merged with ongoing L2 misses.",
        "SampleAfterValue": "200003",
        "UMask": "0xff"
    },
    {
        "BriefDescription": "RFO requests that hit L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_HIT",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that hit L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0xc2"
    },
    {
        "BriefDescription": "RFO requests that miss L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.RFO_MISS",
        "PublicDescription": "Counts the RFO (Read-for-Ownership) requests that miss L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x22"
    },
    {
        "BriefDescription": "SW prefetch requests that hit L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_HIT",
        "PublicDescription": "Counts Software prefetch requests that hit the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
        "SampleAfterValue": "200003",
        "UMask": "0xc8"
    },
    {
        "BriefDescription": "SW prefetch requests that miss L2 cache.",
        "Counter": "0,1,2,3",
        "EventCode": "0x24",
        "EventName": "L2_RQSTS.SWPF_MISS",
        "PublicDescription": "Counts Software prefetch requests that miss the L2 cache. Accounts for PREFETCHNTA and PREFETCHT0/1/2 instructions when FB is not full.",
        "SampleAfterValue": "200003",
        "UMask": "0x28"
    },
    {
        "BriefDescription": "L2 writebacks that access L2 cache",
        "Counter": "0,1,2,3",
        "EventCode": "0xf0",
        "EventName": "L2_TRANS.L2_WB",
        "PublicDescription": "Counts L2 writebacks that access L2 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Cycles when L1D is locked",
        "Counter": "0,1,2,3",
        "EventCode": "0x63",
        "EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
        "PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Core-originated cacheable requests that missed L3  (Except hardware prefetches to the L3)",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x2e",
        "EventName": "LONGEST_LAT_CACHE.MISS",
        "PublicDescription": "Counts core-originated cacheable requests that miss the L3 cache (Longest Latency cache). Requests include data and code reads, Reads-for-Ownership (RFOs), speculative accesses and hardware prefetches to the L1 and L2.  It does not include hardware prefetches to the L3, and may not count other types of requests to the L3.",
        "SampleAfterValue": "100003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Retired load instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_LOADS",
        "PublicDescription": "Counts all retired load instructions. This event accounts for SW prefetch instructions of PREFETCHNTA or PREFETCHT0/1/2 or PREFETCHW.",
        "SampleAfterValue": "1000003",
        "UMask": "0x81"
    },
    {
        "BriefDescription": "Retired store instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ALL_STORES",
        "PublicDescription": "Counts all retired store instructions.",
        "SampleAfterValue": "1000003",
        "UMask": "0x82"
    },
    {
        "BriefDescription": "All retired memory instructions.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.ANY",
        "PublicDescription": "Counts all retired memory instructions - loads and stores.",
        "SampleAfterValue": "1000003",
        "UMask": "0x83"
    },
    {
        "BriefDescription": "Retired load instructions with locked access.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.LOCK_LOADS",
        "PublicDescription": "Counts retired load instructions with locked access.",
        "SampleAfterValue": "100007",
        "UMask": "0x21"
    },
    {
        "BriefDescription": "Retired load instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_LOADS",
        "PublicDescription": "Counts retired load instructions that split across a cacheline boundary.",
        "SampleAfterValue": "100003",
        "UMask": "0x41"
    },
    {
        "BriefDescription": "Retired store instructions that split across a cacheline boundary.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.SPLIT_STORES",
        "PublicDescription": "Counts retired store instructions that split across a cacheline boundary.",
        "SampleAfterValue": "100003",
        "UMask": "0x42"
    },
    {
        "BriefDescription": "Retired load instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_LOADS",
        "PublicDescription": "Number of retired load instructions that (start a) miss in the 2nd-level TLB (STLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x11"
    },
    {
        "BriefDescription": "Retired store instructions that miss the STLB.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd0",
        "EventName": "MEM_INST_RETIRED.STLB_MISS_STORES",
        "PublicDescription": "Number of retired store instructions that (start a) miss in the 2nd-level TLB (STLB).",
        "SampleAfterValue": "100003",
        "UMask": "0x12"
    },
    {
        "BriefDescription": "Snoop hit a modified(HITM) or clean line(HIT_W_FWD) in another on-pkg core which forwarded the data back due to a retired load instruction.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD",
        "PublicDescription": "Counts retired load instructions where a cross-core snoop hit in another cores caches on this socket, the data was forwarded back to the requesting core as the data was modified (SNOOP_HITM) or the L3 did not have the data(SNOOP_HIT_WITH_FWD).",
        "SampleAfterValue": "20011",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS",
        "PublicDescription": "Counts the retired load instructions whose data sources were L3 hit and cross-core snoop missed in on-pkg core cache.",
        "SampleAfterValue": "20011",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired load instructions whose data sources were hits in L3 without snoops required",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NONE",
        "PublicDescription": "Counts retired load instructions whose data sources were hits in L3 without snoops required.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Snoop hit without forwarding in another on-pkg core due to a retired load instruction, data was supplied by the L3.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd2",
        "EventName": "MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD",
        "PublicDescription": "Counts retired load instructions in which the L3 supplied the data and a cross-core snoop hit in another cores caches on this socket but that other core did not forward the data back (SNOOP_HIT_NO_FWD).",
        "SampleAfterValue": "20011",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired instructions with at least 1 uncacheable load or lock.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd4",
        "EventName": "MEM_LOAD_MISC_RETIRED.UC",
        "PublicDescription": "Retired instructions with at least one load to uncacheable memory-type, or at least one cache-line split locked access",
        "SampleAfterValue": "100007",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Number of completed demand load requests that missed the L1, but hit the FB(fill buffer), because a preceding miss to the same cacheline initiated the line to be brought into L1, but data is not yet ready in L1.",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.FB_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop was load missed in L1 but hit FB (Fill Buffers) due to preceding miss to the same cache line with data not ready.",
        "SampleAfterValue": "100007",
        "UMask": "0x40"
    },
    {
        "BriefDescription": "Retired load instructions with L1 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L1 data cache. This event includes all SW prefetches and lock instructions regardless of the data source.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired load instructions missed L1 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L1_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L1 cache.",
        "SampleAfterValue": "200003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Retired load instructions with L2 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_HIT",
        "PublicDescription": "Counts retired load instructions with L2 cache hits as data sources.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired load instructions missed L2 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L2_MISS",
        "PublicDescription": "Counts retired load instructions missed L2 cache as data sources.",
        "SampleAfterValue": "100021",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Retired load instructions with L3 cache hits as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_HIT",
        "PublicDescription": "Counts retired load instructions with at least one uop that hit in the L3 cache.",
        "SampleAfterValue": "100021",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Retired load instructions missed L3 cache as data sources",
        "Counter": "0,1,2,3",
        "Data_LA": "1",
        "EventCode": "0xd1",
        "EventName": "MEM_LOAD_RETIRED.L3_MISS",
        "PublicDescription": "Counts retired load instructions with at least one uop that missed in the L3 cache.",
        "SampleAfterValue": "50021",
        "UMask": "0x20"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand data reads that hit a cacheline in the L3 where a snoop hit in another cores caches which forwarded the data to the requesting core.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x8003C0001",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Counts demand reads for ownership (RFO) requests and software prefetches for exclusive ownership (PREFETCHW) that hit a cacheline in the L3 where a snoop hit in another cores caches, data forwarding is required as the data is modified.",
        "Counter": "0,1,2,3",
        "EventCode": "0xB7, 0xBB",
        "EventName": "OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM",
        "MSRIndex": "0x1a6,0x1a7",
        "MSRValue": "0x10003C0002",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Demand and prefetch data reads",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
        "PublicDescription": "Counts the demand and prefetch data reads. All Core Data Reads include cacheable 'Demands' and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Any memory transaction that reached the SQ.",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.ALL_REQUESTS",
        "PublicDescription": "Counts memory transactions reached the super queue including requests initiated by the core, all L3 prefetches, page walks, etc..",
        "SampleAfterValue": "100003",
        "UMask": "0x80"
    },
    {
        "BriefDescription": "Demand Data Read requests sent to uncore",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
        "PublicDescription": "Counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
        "Counter": "0,1,2,3",
        "EventCode": "0xb0",
        "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
        "PublicDescription": "Counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
        "PublicDescription": "Counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
        "PublicDescription": "Counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding Code Reads transactions in the SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_CODE_RD",
        "PublicDescription": "Counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
        "PublicDescription": "Counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
        "PublicDescription": "Counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The 'Offcore outstanding' state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Demand Data Read transactions pending for off-core. Highly correlated.",
        "Counter": "0,1,2,3",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
        "PublicDescription": "Counts the number of off-core outstanding Demand Data Read transactions every cycle. A transaction is considered to be in the Off-core outstanding state between L2 cache miss and data-return to the core.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
        "Counter": "0,1,2,3",
        "CounterMask": "6",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Store Read transactions pending for off-core. Highly correlated.",
        "Counter": "0,1,2,3",
        "EventCode": "0x60",
        "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
        "PublicDescription": "Counts the number of off-core outstanding read-for-ownership (RFO) store transactions every cycle. An RFO transaction is considered to be in the Off-core outstanding state between L2 cache miss and transaction completion.",
        "SampleAfterValue": "1000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts bus locks, accounts for cache line split locks and UC locks.",
        "Counter": "0,1,2,3",
        "EventCode": "0xf4",
        "EventName": "SQ_MISC.BUS_LOCK",
        "PublicDescription": "Counts the more expensive bus lock needed to enforce cache coherency for certain memory accesses that need to be done atomically.  Can be created by issuing an atomic instruction (via the LOCK prefix) which causes a cache line split or accesses uncacheable memory.",
        "SampleAfterValue": "100003",
        "UMask": "0x10"
    },
    {
        "BriefDescription": "Cycles the superQ cannot take any more entries.",
        "Counter": "0,1,2,3",
        "EventCode": "0xf4",
        "EventName": "SQ_MISC.SQ_FULL",
        "PublicDescription": "Counts the cycles for which the thread is active and the superQ cannot take any more entries.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Counts the number of PREFETCHNTA, PREFETCHW, PREFETCHT0, PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.ANY",
        "SampleAfterValue": "100003",
        "UMask": "0xf"
    },
    {
        "BriefDescription": "Number of PREFETCHNTA instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.NTA",
        "PublicDescription": "Counts the number of PREFETCHNTA instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of PREFETCHW instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.PREFETCHW",
        "PublicDescription": "Counts the number of PREFETCHW instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Number of PREFETCHT0 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T0",
        "PublicDescription": "Counts the number of PREFETCHT0 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "Counter": "0,1,2,3",
        "EventCode": "0x32",
        "EventName": "SW_PREFETCH_ACCESS.T1_T2",
        "PublicDescription": "Counts the number of PREFETCHT1 or PREFETCHT2 instructions executed.",
        "SampleAfterValue": "100003",
        "UMask": "0x4"
    }
]
