[
    {
        "BriefDescription": "Counts the number of page walks completed due to load DTLB misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x08",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to loads (including SW prefetches) whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size. Includes page walks that page fault.",
        "SampleAfterValue": "1000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x12",
        "EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data loads. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to store DTLB misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x49",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to stores whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
        "SampleAfterValue": "1000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Store misses in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x13",
        "EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks  (all page sizes) caused by demand data stores. This implies it missed in the DTLB and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of page walks completed due to instruction fetch misses to any page size.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x85",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts the number of page walks completed due to instruction fetches whose address translations missed in all Translation Lookaside Buffer (TLB) levels and were mapped to any page size.  Includes page walks that page fault.",
        "SampleAfterValue": "1000003",
        "UMask": "0xe",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (All page sizes)",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x11",
        "EventName": "ITLB_MISSES.WALK_COMPLETED",
        "PublicDescription": "Counts completed page walks (all page sizes) caused by a code fetch. This implies it missed in the ITLB (Instruction TLB) and further levels of TLB. The page walk can end with or without a fault.",
        "SampleAfterValue": "100003",
        "UMask": "0xe",
        "Unit": "cpu_core"
    }
]
