[
    {
        "ArchStdEvent": "L1I_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1I_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L1D_CACHE"
    },
    {
        "ArchStdEvent": "L1D_TLB_REFILL"
    },
    {
        "ArchStdEvent": "L1I_CACHE"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L2D_CACHE"
    },
    {
        "ArchStdEvent": "L2D_CACHE_REFILL"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB"
    },
    {
        "ArchStdEvent": "L1D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L1D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_RD"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WR"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_VICTIM"
    },
    {
        "ArchStdEvent": "L2D_CACHE_WB_CLEAN"
    },
    {
        "ArchStdEvent": "L2D_CACHE_INVAL"
    },
    {
        "PublicDescription": "Number of ways read in the instruction cache - Tag RAM",
        "EventCode": "0xC2",
        "EventName": "I_TAG_RAM_RD",
        "BriefDescription": "Number of ways read in the instruction cache - Tag RAM"
    },
    {
        "PublicDescription": "Number of ways read in the instruction cache - Data RAM",
        "EventCode": "0xC3",
        "EventName": "I_DATA_RAM_RD",
        "BriefDescription": "Number of ways read in the instruction cache - Data RAM"
    },
    {
        "PublicDescription": "Number of ways read in the instruction BTAC RAM",
        "EventCode": "0xC4",
        "EventName": "I_BTAC_RAM_RD",
        "BriefDescription": "Number of ways read in the instruction BTAC RAM"
    },
    {
        "PublicDescription": "Level 1 PLD TLB refill",
        "EventCode": "0xE7",
        "EventName": "PLD_UTLB_REFILL",
        "BriefDescription": "Level 1 PLD TLB refill"
    },
    {
        "PublicDescription": "Level 1 CP15 TLB refill",
        "EventCode": "0xE8",
        "EventName": "CP15_UTLB_REFILL",
        "BriefDescription": "Level 1 CP15 TLB refill"
    },
    {
        "PublicDescription": "Level 1 TLB flush",
        "EventCode": "0xE9",
        "EventName": "UTLB_FLUSH",
        "BriefDescription": "Level 1 TLB flush"
    },
    {
        "PublicDescription": "Level 2 TLB access",
        "EventCode": "0xEA",
        "EventName": "TLB_ACCESS",
        "BriefDescription": "Level 2 TLB access"
    },
    {
        "PublicDescription": "Level 2 TLB miss",
        "EventCode": "0xEB",
        "EventName": "TLB_MISS",
        "BriefDescription": "Level 2 TLB miss"
    },
    {
        "PublicDescription": "Data cache hit in itself due to VIPT aliasing",
        "EventCode": "0xEC",
        "EventName": "DCACHE_SELF_HIT_VIPT",
        "BriefDescription": "Data cache hit in itself due to VIPT aliasing"
    }
]
