[
	{
		"Unit": "CPU-M-CF",
		"EventCode": "128",
		"EventName": "L1D_RO_EXCL_WRITES",
		"BriefDescription": "L1D Read-only Exclusive Writes",
		"PublicDescription": "A directory write to the Level-1 Data cache where the line was originally in a Read-Only state in the cache but has been updated to be in the Exclusive state that allows stores to the cache line."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "129",
		"EventName": "DTLB2_WRITES",
		"BriefDescription": "DTLB2 Writes",
		"PublicDescription": "A translation has been written into The Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Data cache. This is a replacement for what was provided for the DTLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "130",
		"EventName": "DTLB2_MISSES",
		"BriefDescription": "DTLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Data cache. Incremented by one for every TLB2 miss in progress for the Level-1 Data cache on this cycle. This is a replacement for what was provided for the DTLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "131",
		"EventName": "CRSTE_1MB_WRITES",
		"BriefDescription": "One Megabyte CRSTE writes",
		"PublicDescription": "A translation entry was written into the Combined Region and Segment Table Entry array in the Level-2 TLB for a one-megabyte page."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "132",
		"EventName": "DTLB2_GPAGE_WRITES",
		"BriefDescription": "DTLB2 Two-Gigabyte Page Writes",
		"PublicDescription": "A translation entry for a two-gigabyte page was written into the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "134",
		"EventName": "ITLB2_WRITES",
		"BriefDescription": "ITLB2 Writes",
		"PublicDescription": "A translation entry has been written into the Translation Lookaside Buffer 2 (TLB2) and the request was made by the Level-1 Instruction cache. This is a replacement for what was provided for the ITLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "135",
		"EventName": "ITLB2_MISSES",
		"BriefDescription": "ITLB2 Misses",
		"PublicDescription": "A TLB2 miss is in progress for a request made by the Level-1 Instruction cache. Incremented by one for every TLB2 miss in progress for the Level-1 Instruction cache in a cycle. This is a replacement for what was provided for the ITLB on z13 and prior machines."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "137",
		"EventName": "TLB2_PTE_WRITES",
		"BriefDescription": "TLB2 Page Table Entry Writes",
		"PublicDescription": "A translation entry was written into the Page Table Entry array in the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "138",
		"EventName": "TLB2_CRSTE_WRITES",
		"BriefDescription": "TLB2 Combined Region and Segment Entry Writes",
		"PublicDescription": "Translation entries were written into the Combined Region and Segment Table Entry array and the Page Table Entry array in the Level-2 TLB."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "139",
		"EventName": "TLB2_ENGINES_BUSY",
		"BriefDescription": "TLB2 Engines Busy",
		"PublicDescription": "The number of Level-2 TLB translation engines busy in a cycle."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "140",
		"EventName": "TX_C_TEND",
		"BriefDescription": "Completed TEND instructions in constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a constrained transactional-execution mode."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "141",
		"EventName": "TX_NC_TEND",
		"BriefDescription": "Completed TEND instructions in non-constrained TX mode",
		"PublicDescription": "A TEND instruction has completed in a non-constrained transactional-execution mode."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "143",
		"EventName": "L1C_TLB2_MISSES",
		"BriefDescription": "L1C TLB2 Misses",
		"PublicDescription": "Increments by one for any cycle where a Level-1 cache or Level-2 TLB miss is in progress."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "145",
		"EventName": "DCW_REQ",
		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "146",
		"EventName": "DCW_REQ_IV",
		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "147",
		"EventName": "DCW_REQ_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Chip HP Hit",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "148",
		"EventName": "DCW_REQ_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Data Cache from L2-Cache with Drawer HP Hit",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "149",
		"EventName": "DCW_ON_CHIP",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "150",
		"EventName": "DCW_ON_CHIP_IV",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "151",
		"EventName": "DCW_ON_CHIP_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Chip HP Hit",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "152",
		"EventName": "DCW_ON_CHIP_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Chip L2-Cache with Drawer HP Hit",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "153",
		"EventName": "DCW_ON_MODULE",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Module L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "154",
		"EventName": "DCW_ON_DRAWER",
		"BriefDescription": "Directory Write Level 1 Data Cache from On-Drawer L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "155",
		"EventName": "DCW_OFF_DRAWER",
		"BriefDescription": "Directory Write Level 1 Data Cache from Off-Drawer L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Data cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "156",
		"EventName": "DCW_ON_CHIP_MEMORY",
		"BriefDescription": "Directory Write Level 1 Cache from On-Chip Memory",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Chip memory."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "157",
		"EventName": "DCW_ON_MODULE_MEMORY",
		"BriefDescription": "Directory Write Level 1 Cache from On-Module Memory",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Module memory."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "158",
		"EventName": "DCW_ON_DRAWER_MEMORY",
		"BriefDescription": "Directory Write Level 1 Cache from On-Drawer Memory",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from On-Drawer memory."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "159",
		"EventName": "DCW_OFF_DRAWER_MEMORY",
		"BriefDescription": "Directory Write Level 1 Cache from Off-Drawer Memory",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from Off-Drawer memory."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "160",
		"EventName": "IDCW_ON_MODULE_IV",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "161",
		"EventName": "IDCW_ON_MODULE_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Chip Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "162",
		"EventName": "IDCW_ON_MODULE_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Module Memory L2-Cache with Drawer Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "163",
		"EventName": "IDCW_ON_DRAWER_IV",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "164",
		"EventName": "IDCW_ON_DRAWER_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Chip Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "165",
		"EventName": "IDCW_ON_DRAWER_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from On-Drawer L2-Cache with Drawer Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "166",
		"EventName": "IDCW_OFF_DRAWER_IV",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "167",
		"EventName": "IDCW_OFF_DRAWER_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Chip Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "168",
		"EventName": "IDCW_OFF_DRAWER_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction and Data Cache from Off-Drawer L2-Cache with Drawer Hit",
		"PublicDescription": "A directory write to the Level-1 Data or Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "169",
		"EventName": "ICW_REQ",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced the requestors Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "170",
		"EventName": "ICW_REQ_IV",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "171",
		"EventName": "ICW_REQ_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Chip HP Hit",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "172",
		"EventName": "ICW_REQ_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from L2-Cache with Drawer HP Hit",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from the requestors Level-2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "173",
		"EventName": "ICW_ON_CHIP",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "174",
		"EventName": "ICW_ON_CHIP_IV",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Intervention",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache with intervention."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "175",
		"EventName": "ICW_ON_CHIP_CHIP_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Chip HP Hit",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip Level-2 cache after using chip level horizontal persistence, Chip-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "176",
		"EventName": "ICW_ON_CHIP_DRAWER_HIT",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Chip L2-Cache with Drawer HP Hit",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Chip level 2 cache after using drawer level horizontal persistence, Drawer-HP hit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "177",
		"EventName": "ICW_ON_MODULE",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Module L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Module Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "178",
		"EventName": "ICW_ON_DRAWER",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from On-Drawer L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an On-Drawer Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "179",
		"EventName": "ICW_OFF_DRAWER",
		"BriefDescription": "Directory Write Level 1 Instruction Cache from Off-Drawer L2-Cache",
		"PublicDescription": "A directory write to the Level-1 Instruction cache directory where the returned cache line was sourced from an Off-Drawer Level-2 cache."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "202",
		"EventName": "CYCLES_SAMETHRD",
		"BriefDescription": "CPU is not in wait state and CPU is running by itself",
		"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running by itself on the Core."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "203",
		"EventName": "CYCLES_DIFFTHRD",
		"BriefDescription": "CPU is not in wait state and CPU is running by another thread",
		"PublicDescription": "The number of cycles the CPU is not in wait state and the CPU is running with another thread on the Core."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "204",
		"EventName": "INST_SAMETHRD",
		"BriefDescription": "Instructions executed on CPU by itself",
		"PublicDescription": "The number of instructions executed on the CPU and the CPU is running by itself on the Core."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "205",
		"EventName": "INST_DIFFTHRD",
		"BriefDescription": "Instructions executed on CPU by another thread",
		"PublicDescription": "The number of instructions executed on the CPU and the CPU is running with another thread on the Core."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "206",
		"EventName": "WRONG_BRANCH_PREDICTION",
		"BriefDescription": "Incorrect branch prediction on core",
		"PublicDescription": "A count of the number of branches that were predicted incorrectly by the branch prediction logic in the Core. This includes incorrectly predicted branches that are executed in Firmware. Examples of instructions implemented in Firmware are complicated instructions like MVCL (Move Character Long) and PC (Program Call)."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "225",
		"EventName": "VX_BCD_EXECUTION_SLOTS",
		"BriefDescription": "Count finished vector arithmetic Binary Coded Decimal instructions",
		"PublicDescription": "Count of floating point execution slots used for finished vector arithmetic Binary Coded Decimal instructions. Instructions: VAP, VSP, VMP, VMSP, VDP, VSDP, VRP, VLIP, VSRP, VPSOP, VCP, VTP, VPKZ, VUPKZ, VCVB, VCVBG, VCVD, VCVDG, VSCHP, VSCSHP, VCSPH, VCLZDP, VPKZR, VSRPR, VUPKZH, VUPKZL, VTZ, VUPH, VUPL, VCVBX, VCVDX."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "226",
		"EventName": "DECIMAL_INSTRUCTIONS",
		"BriefDescription": "Decimal instruction dispatched",
		"PublicDescription": "Decimal instruction dispatched. Instructions: CVB, CVD, AP, CP, DP, ED, EDMK, MP, SRP, SP, ZAP, TP."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "232",
		"EventName": "LAST_HOST_TRANSLATIONS",
		"BriefDescription": "Last host translation done",
		"PublicDescription": "Last Host Translation done."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "244",
		"EventName": "TX_NC_TABORT",
		"BriefDescription": "Aborted transactions in unconstrained TX mode",
		"PublicDescription": "A transaction abort has occurred in a non-constrained transactional-execution mode."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "245",
		"EventName": "TX_C_TABORT_NO_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is not using any special logic to allow the transaction to complete."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "246",
		"EventName": "TX_C_TABORT_SPECIAL",
		"BriefDescription": "Aborted transactions in constrained TX mode using special completion logic",
		"PublicDescription": "A transaction abort has occurred in a constrained transactional-execution mode and the CPU is using special logic to allow the transaction to complete."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "248",
		"EventName": "DFLT_ACCESS",
		"BriefDescription": "Cycles CPU spent obtaining access to Deflate unit",
		"PublicDescription": "Cycles CPU spent obtaining access to Deflate unit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "253",
		"EventName": "DFLT_CYCLES",
		"BriefDescription": "Cycles CPU is using Deflate unit",
		"PublicDescription": "Cycles CPU is using Deflate unit."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "256",
		"EventName": "SORTL",
		"BriefDescription": "Count SORTL instructions",
		"PublicDescription": "Increments by one for every SORT LISTS (SORTL) instruction executed."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "265",
		"EventName": "DFLT_CC",
		"BriefDescription": "Increments DEFLATE CONVERSION CALL",
		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "266",
		"EventName": "DFLT_CCFINISH",
		"BriefDescription": "Increments completed DEFLATE CONVERSION CALL",
		"PublicDescription": "Increments by one for every DEFLATE CONVERSION CALL (DFLTCC) instruction executed that ended in Condition Codes 0, 1 or 2."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "267",
		"EventName": "NNPA_INVOCATIONS",
		"BriefDescription": "NNPA Total invocations",
		"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "268",
		"EventName": "NNPA_COMPLETIONS",
		"BriefDescription": "NNPA Total completions",
		"PublicDescription": "Increments by one for every NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction executed that ended in Condition Code 0."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "269",
		"EventName": "NNPA_WAIT_LOCK",
		"BriefDescription": "Cycles spent obtaining NNPA lock",
		"PublicDescription": "Cycles CPU spent obtaining access to IBM Z Integrated Accelerator for AI."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "270",
		"EventName": "NNPA_HOLD_LOCK",
		"BriefDescription": "Cycles spent holding NNPA lock",
		"PublicDescription": "Cycles CPU is using IBM Z Integrated Accelerator for AI."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "272",
		"EventName": "NNPA_INST_ONCHIP",
		"BriefDescription": "NNPA instructions used on-chip Integrated Accelerator",
		"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used the Local On-Chip IBM Z Integrated Accelerator for AI during its execution"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "273",
		"EventName": "NNPA_INST_OFFCHIP",
		"BriefDescription": "NNPA instructions used off-chip Integrated Accelerator",
		"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used an Off-Chip IBM Z Integrated Accelerator for AI during its execution."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "274",
		"EventName": "NNPA_INST_DIFF",
		"BriefDescription": "NNPA instructions used different Integrated Accelerator",
		"PublicDescription": "A NEURAL NETWORK PROCESSING ASSIST (NNPA) instruction has used a different IBM Z Integrated Accelerator for AI since it was last executed."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "276",
		"EventName": "NNPA_4K_PREFETCH",
		"BriefDescription": "Number of 4K prefetches for Integated Accelerator",
		"PublicDescription": "Number of 4K prefetches done for a remote IBM Z Integated Accelerator for AI."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "277",
		"EventName": "NNPA_COMPL_LOCK",
		"BriefDescription": "A Perform Locked Operation has completed",
		"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has completed."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "278",
		"EventName": "NNPA_RETRY_LOCK",
		"BriefDescription": "A Perform Locked Operation has been retried",
		"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU did not use any special logic to allow the PLO to complete."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "279",
		"EventName": "NNPA_RETRY_LOCK_WITH_PLO",
		"BriefDescription": "A Perform Locked Operation has been retried using special logic",
		"PublicDescription": "A PERFORM LOCKED OPERATION (PLO) has been retried and the CPU is using special logic to allow PLO to complete."
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "448",
		"EventName": "MT_DIAG_CYCLES_ONE_THR_ACTIVE",
		"BriefDescription": "Cycle count with one thread active",
		"PublicDescription": "Cycle count with one thread active"
	},
	{
		"Unit": "CPU-M-CF",
		"EventCode": "449",
		"EventName": "MT_DIAG_CYCLES_TWO_THR_ACTIVE",
		"BriefDescription": "Cycle count with two threads active",
		"PublicDescription": "Cycle count with two threads active"
	}
]
