[
    {
        "BriefDescription": "Counts the total number of branch instructions retired for all branch types.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts the total number of instructions in which the instruction pointer (IP) of the processor is resteered due to a branch instruction and the branch instruction successfully retires.  All branch type instructions are accounted for.",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "All branch instructions retired.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc4",
        "EventName": "BR_INST_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts all branch instructions retired. Available PDIST counters: 0",
        "SampleAfterValue": "400009",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the total number of mispredicted branch instructions retired for all branch types.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts the total number of mispredicted branch instructions retired.  All branch type instructions are accounted for.  Prediction of the branch target address enables the processor to begin executing instructions before the non-speculative execution path is known. The branch prediction unit (BPU) predicts the target address based on the instruction pointer (IP) of the branch and on the execution path through which execution reached this IP.    A branch misprediction occurs when the prediction is wrong, and results in discarding all instructions executed in the speculative path and re-fetching from the correct path.",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "All mispredicted branch instructions retired.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc5",
        "EventName": "BR_MISP_RETIRED.ALL_BRANCHES",
        "PublicDescription": "Counts all the retired branch instructions that were mispredicted by the processor. A branch misprediction occurs when the processor incorrectly predicts the destination of the branch.  When the misprediction is discovered at execution, all the instructions executed in the wrong (speculative) path must be discarded, and the processor must start fetching from the correct path. Available PDIST counters: 0",
        "SampleAfterValue": "400009",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.CORE",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core cycles when the core is not in a halt state.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.CORE",
        "PublicDescription": "Counts the number of core cycles while the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.CORE_P",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.CORE_P",
        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.THREAD_P]",
        "SampleAfterValue": "2000003",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted reference clock cycles.",
        "Counter": "Fixed counter 2",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "SampleAfterValue": "1000003",
        "UMask": "0x3",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "Counter": "Fixed counter 2",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC",
        "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "SampleAfterValue": "2000003",
        "UMask": "0x3",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of unhalted reference clock cycles at TSC frequency.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
        "PublicDescription": "Counts the number of reference cycles that the core is not in a halt state. The core enters the halt state when it is running the HLT instruction. This event is not affected by core frequency changes and increments at a fixed frequency that is also used for the Time Stamp Counter (TSC). This event uses a programmable general purpose performance counter.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Reference cycles when the core is not in halt state.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.REF_TSC_P",
        "PublicDescription": "Counts the number of reference cycles when the core is not in a halt state. The core enters the halt state when it is running the HLT instruction or the MWAIT instruction. This event is not affected by core frequency changes (for example, P states, TM2 transitions) but has the same incrementing frequency as the time stamp counter. This event can approximate elapsed time while the core was not in a halt state. Note: On all current platforms this event stops counting during 'throttling (TM)' states duty off periods the processor is 'halted'.  The counter update is done at a lower clock rate then the core clock the overflow status bit for this counter may appear 'sticky'.  After the counter has overflowed and software clears the overflow status bit and resets the counter to less than MAX. The reset value to the counter is not clocked immediately so the overflow status bit will flip 'high (1)' and generate another PMI (if enabled) after which the reset value gets clocked into the counter. Therefore, software will get the interrupt, read the overflow status bit '1 for bit 34 while the counter value is less than MAX. Software should ignore this case.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of unhalted core clock cycles.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Core cycles when the thread is not in a halt state.",
        "Counter": "Fixed counter 1",
        "EventName": "CPU_CLK_UNHALTED.THREAD",
        "PublicDescription": "Counts the number of core cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. This event is a component in many key event ratios. The core frequency may change from time to time due to transitions associated with Enhanced Intel SpeedStep Technology or TM2. For this reason this event may have a changing ratio with regards to time. When the core frequency is constant, this event can approximate elapsed time while the core was not in the halt state. It is counted on a dedicated fixed counter, leaving the programmable counters available for other events.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of unhalted core clock cycles. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Thread cycles when thread is not in halt state [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x3c",
        "EventName": "CPU_CLK_UNHALTED.THREAD_P",
        "PublicDescription": "This is an architectural event that counts the number of thread cycles while the thread is not in a halt state. The thread enters the halt state when it is running the HLT instruction. The core frequency may change from time to time due to power or thermal throttling. For this reason, this event may have a changing ratio with regards to wall clock time. [This event is alias to CPU_CLK_UNHALTED.CORE_P]",
        "SampleAfterValue": "2000003",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of instructions retired.",
        "Counter": "Fixed counter 0",
        "EventName": "INST_RETIRED.ANY",
        "PublicDescription": "Fixed Counter: Counts the number of instructions retired. Available PDIST counters: 32",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of instructions retired. Fixed Counter - architectural event",
        "Counter": "Fixed counter 0",
        "EventName": "INST_RETIRED.ANY",
        "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 32",
        "SampleAfterValue": "2000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of instructions retired.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.ANY_P",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Number of instructions retired. General Counter - architectural event",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc0",
        "EventName": "INST_RETIRED.ANY_P",
        "PublicDescription": "Counts the number of X86 instructions retired - an Architectural PerfMon event. Counting continues during hardware interrupts, traps, and inside interrupt handlers. Notes: INST_RETIRED.ANY is counted by a designated fixed counter freeing up programmable counters to count other events. INST_RETIRED.ANY_P is counted by a programmable counter. Available PDIST counters: 0",
        "SampleAfterValue": "2000003",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of retired loads that are blocked because its address partially overlapped with an older store.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Loads blocked due to overlapping with a preceding store that cannot be forwarded.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0x03",
        "EventName": "LD_BLOCKS.STORE_FORWARD",
        "PublicDescription": "Counts the number of times where store forwarding was prevented for a load operation. The most common case is a load blocked due to the address of memory access (partially) overlapping with a preceding uncompleted store. Note: See the table of not supported store forwards in the Optimization Guide.",
        "SampleAfterValue": "100003",
        "UMask": "0x82",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Counts the number of LBR entries recorded. Requires LBRs to be enabled in IA32_LBR_CTL.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xe4",
        "EventName": "MISC_RETIRED.LBR_INSERTS",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "LBR record is inserted",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xe4",
        "EventName": "MISC_RETIRED.LBR_INSERTS",
        "PublicDescription": "LBR record is inserted Available PDIST counters: 0",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.BACKEND_BOUND_SLOTS",
        "PublicDescription": "This event counts a subset of the Topdown Slots event that were not consumed by the back-end pipeline due to lack of back-end resources, as a result of memory subsystem delays, execution units limitations, or other conditions. Software can use this event as the numerator for the Backend Bound metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
        "SampleAfterValue": "10000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "TMA slots available for an unhalted logical processor. Fixed counter - architectural event",
        "Counter": "Fixed counter 3",
        "EventName": "TOPDOWN.SLOTS",
        "PublicDescription": "Number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method (TMA). Software can use this event as the denominator for the top-level metrics of the TMA method. This architectural event is counted on a designated fixed counter (Fixed Counter 3).",
        "SampleAfterValue": "10000003",
        "UMask": "0x4",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "TMA slots available for an unhalted logical processor. General counter - architectural event",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN.SLOTS_P",
        "PublicDescription": "Counts the number of available slots for an unhalted logical processor. The event increments by machine-width of the narrowest pipeline as employed by the Top-down Microarchitecture Analysis method.",
        "SampleAfterValue": "10000003",
        "UMask": "0x1",
        "Unit": "cpu_core"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
        "Counter": "36",
        "EventName": "TOPDOWN_BAD_SPECULATION.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x5",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x73",
        "EventName": "TOPDOWN_BAD_SPECULATION.ALL_P",
        "PublicDescription": "Counts the total number of issue slots that were not consumed by the backend because allocation is stalled due to a mispredicted jump or a machine clear. Only issue slots wasted due to fast nukes such as memory ordering nukes are counted. Other nukes are not accounted for. Counts all issue slots blocked during this recovery window, including relevant microcode flows, and while uops are not yet available in the instruction queue (IQ) or until an FE_BOUND event occurs besides OTHER and CISC. Also includes the issue slots that were consumed by the backend but were thrown away because they were younger than the mispredict or machine clear.",
        "SampleAfterValue": "1000003",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL_P]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN_BE_BOUND.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retirement slots not consumed due to backend stalls. [This event is alias to TOPDOWN_BE_BOUND.ALL]",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xa4",
        "EventName": "TOPDOWN_BE_BOUND.ALL_P",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of retirement slots not consumed due to front end stalls.",
        "Counter": "37",
        "EventName": "TOPDOWN_FE_BOUND.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x6",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of retirement slots not consumed due to front end stalls.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x9c",
        "EventName": "TOPDOWN_FE_BOUND.ALL_P",
        "SampleAfterValue": "1000003",
        "UMask": "0x1",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Fixed Counter: Counts the number of consumed retirement slots.",
        "Counter": "38",
        "EventName": "TOPDOWN_RETIRING.ALL",
        "SampleAfterValue": "1000003",
        "UMask": "0x7",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "Counts the number of consumed retirement slots.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc2",
        "EventName": "TOPDOWN_RETIRING.ALL_P",
        "PublicDescription": "Counts the number of consumed retirement slots. Available PDIST counters: 0,1",
        "SampleAfterValue": "1000003",
        "UMask": "0x2",
        "Unit": "cpu_atom"
    },
    {
        "BriefDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric.",
        "Counter": "0,1,2,3,4,5,6,7,8,9",
        "EventCode": "0xc2",
        "EventName": "UOPS_RETIRED.SLOTS",
        "PublicDescription": "This event counts a subset of the Topdown Slots event that are utilized by operations that eventually get retired (committed) by the processor pipeline. Usually, this event positively correlates with higher performance  for example, as measured by the instructions-per-cycle metric. Software can use this event as the numerator for the Retiring metric (or top-level category) of the Top-down Microarchitecture Analysis method.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2",
        "Unit": "cpu_core"
    }
]
