[
    {
        "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "CPL_CYCLES.RING0",
        "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x5C",
        "EventName": "CPL_CYCLES.RING0_TRANS",
        "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
        "Counter": "0,1,2,3",
        "EventCode": "0x5C",
        "EventName": "CPL_CYCLES.RING123",
        "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
        "SampleAfterValue": "2000003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
        "Counter": "0,1,2,3",
        "EventCode": "0x63",
        "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
        "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
        "SampleAfterValue": "2000003",
        "UMask": "0x1"
    }
]
