[
    {
        "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
        "Counter": "0,1,2,3",
        "EventCode": "0xe6",
        "EventName": "BACLEARS.ANY",
        "PublicDescription": "Counts the number of times the front-end is resteered when it finds a branch instruction in a fetch line. This occurs for the first time a branch instruction is fetched or when the branch is not tracked by the BPU (Branch Prediction Unit) anymore.",
        "SampleAfterValue": "100003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Stalls caused by changing prefix length of the instruction. [This event is alias to ILD_STALL.LCP]",
        "Counter": "0,1,2,3",
        "EventCode": "0x87",
        "EventName": "DECODE.LCP",
        "PublicDescription": "Counts cycles that the Instruction Length decoder (ILD) stalls occurred due to dynamically changing prefix length of the decoded instruction (by operand size prefix instruction 0x66, address size prefix instruction 0x67 or REX.W for Intel64). Count is proportional to the number of prefixes in a 16B-line. This may result in a three-cycle penalty for each LCP (Length changing prefix) in a 16-byte chunk. [This event is alias to ILD_STALL.LCP]",
        "SampleAfterValue": "500009",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE transitions count.",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0xab",
        "EventName": "DSB2MITE_SWITCHES.COUNT",
        "PublicDescription": "Counts the number of Decode Stream Buffer (DSB a.k.a. Uop Cache)-to-MITE speculative transitions.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "DSB-to-MITE switch true penalty cycles.",
        "Counter": "0,1,2,3",
        "EventCode": "0xab",
        "EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
        "PublicDescription": "Decode Stream Buffer (DSB) is a Uop-cache that holds translations of previously fetched instructions that were decoded by the legacy x86 decode pipeline (MITE). This event counts fetch penalty cycles when a transition occurs from DSB to MITE.",
        "SampleAfterValue": "100003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Retired Instructions who experienced DSB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.ANY_DSB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x1",
        "PublicDescription": "Counts retired Instructions that experienced DSB (Decode stream buffer i.e. the decoded instruction-cache) miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced a critical DSB miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.DSB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x11",
        "PublicDescription": "Number of retired Instructions that experienced a critical DSB (Decode stream buffer i.e. the decoded instruction-cache) miss. Critical means stalls were exposed to the back-end as a result of the DSB miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced iTLB true miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.ITLB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x14",
        "PublicDescription": "Counts retired Instructions that experienced iTLB (Instruction TLB) true miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced Instruction L1 Cache true miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.L1I_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x12",
        "PublicDescription": "Counts retired Instructions who experienced Instruction L1 Cache true miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced Instruction L2 Cache true miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.L2_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x13",
        "PublicDescription": "Counts retired Instructions who experienced Instruction L2 Cache true miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions after front-end starvation of at least 1 cycle",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_1",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x500106",
        "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 1 cycle which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_128",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x508006",
        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 128 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 16 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_16",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x501006",
        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 16 cycles. During this period the front-end delivered no uops.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions after front-end starvation of at least 2 cycles",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x500206",
        "PublicDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of at least 2 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_256",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x510006",
        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 256 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end had at least 1 bubble-slot for a period of 2 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_2_BUBBLES_GE_1",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x100206",
        "PublicDescription": "Counts retired instructions that are delivered to the back-end after the front-end had at least 1 bubble-slot for a period of 2 cycles. A bubble-slot is an empty issue-pipeline slot while there was no RAT stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 32 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_32",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x502006",
        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 32 cycles. During this period the front-end delivered no uops.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_4",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x500406",
        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 4 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_512",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x520006",
        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 512 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_64",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x504006",
        "PublicDescription": "Counts retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 64 cycles which was not interrupted by a back-end stall.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired instructions that are fetched after an interval where the front-end delivered no uops for a period of 8 cycles which was not interrupted by a back-end stall.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.LATENCY_GE_8",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x500806",
        "PublicDescription": "Counts retired instructions that are delivered to the back-end after a front-end stall of at least 8 cycles. During this period the front-end delivered no uops.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Retired Instructions who experienced STLB (2nd level TLB) true miss.",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0xc6",
        "EventName": "FRONTEND_RETIRED.STLB_MISS",
        "MSRIndex": "0x3F7",
        "MSRValue": "0x15",
        "PublicDescription": "Counts retired Instructions that experienced STLB (2nd level TLB) true miss.",
        "SampleAfterValue": "100007",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_DATA.STALLS]",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE_16B.IFDATA_STALL",
        "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_DATA.STALLS]",
        "SampleAfterValue": "500009",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "ICACHE_64B.IFTAG_HIT",
        "PublicDescription": "Counts instruction fetch tag lookups that hit in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
        "SampleAfterValue": "200003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity.",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "ICACHE_64B.IFTAG_MISS",
        "PublicDescription": "Counts instruction fetch tag lookups that miss in the instruction cache (L1I). Counts at 64-byte cache-line granularity. Accounts for both cacheable and uncacheable accesses.",
        "SampleAfterValue": "200003",
        "UMask": "0x2"
    },
    {
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "ICACHE_64B.IFTAG_STALL",
        "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_TAG.STALLS]",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache miss. [This event is alias to ICACHE_16B.IFDATA_STALL]",
        "Counter": "0,1,2,3",
        "EventCode": "0x80",
        "EventName": "ICACHE_DATA.STALLS",
        "PublicDescription": "Counts cycles where a code line fetch is stalled due to an L1 instruction cache miss. The legacy decode pipeline works at a 16 Byte granularity. [This event is alias to ICACHE_16B.IFDATA_STALL]",
        "SampleAfterValue": "500009",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
        "Counter": "0,1,2,3",
        "EventCode": "0x83",
        "EventName": "ICACHE_TAG.STALLS",
        "PublicDescription": "Counts cycles where a code fetch is stalled due to L1 instruction cache tag miss. [This event is alias to ICACHE_64B.IFTAG_STALL]",
        "SampleAfterValue": "200003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x79",
        "EventName": "IDQ.DSB_CYCLES_ANY",
        "PublicDescription": "Counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles DSB is delivering optimal number of Uops",
        "Counter": "0,1,2,3",
        "CounterMask": "5",
        "EventCode": "0x79",
        "EventName": "IDQ.DSB_CYCLES_OK",
        "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the DSB (Decode Stream Buffer) path. Count includes uops that may 'bypass' the IDQ.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
        "Counter": "0,1,2,3",
        "EventCode": "0x79",
        "EventName": "IDQ.DSB_UOPS",
        "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path.",
        "SampleAfterValue": "2000003",
        "UMask": "0x8"
    },
    {
        "BriefDescription": "Cycles MITE is delivering any Uop",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x79",
        "EventName": "IDQ.MITE_CYCLES_ANY",
        "PublicDescription": "Counts the number of cycles uops were delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles MITE is delivering optimal number of Uops",
        "Counter": "0,1,2,3",
        "CounterMask": "5",
        "EventCode": "0x79",
        "EventName": "IDQ.MITE_CYCLES_OK",
        "PublicDescription": "Counts the number of cycles where optimal number of uops was delivered to the Instruction Decode Queue (IDQ) from the MITE (legacy decode pipeline) path. During these cycles uops are not being delivered from the Decode Stream Buffer (DSB).",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
        "Counter": "0,1,2,3",
        "EventCode": "0x79",
        "EventName": "IDQ.MITE_UOPS",
        "PublicDescription": "Counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
        "SampleAfterValue": "2000003",
        "UMask": "0x4"
    },
    {
        "BriefDescription": "Cycles when uops are being delivered to IDQ while MS is busy",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EventCode": "0x79",
        "EventName": "IDQ.MS_CYCLES_ANY",
        "PublicDescription": "Counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
        "SampleAfterValue": "2000003",
        "UMask": "0x30"
    },
    {
        "BriefDescription": "Number of switches from DSB or MITE to the MS",
        "Counter": "0,1,2,3",
        "CounterMask": "1",
        "EdgeDetect": "1",
        "EventCode": "0x79",
        "EventName": "IDQ.MS_SWITCHES",
        "PublicDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
        "SampleAfterValue": "100003",
        "UMask": "0x30"
    },
    {
        "BriefDescription": "Uops delivered to IDQ while MS is busy",
        "Counter": "0,1,2,3",
        "EventCode": "0x79",
        "EventName": "IDQ.MS_UOPS",
        "PublicDescription": "Counts the total number of uops delivered by the Microcode Sequencer (MS). Any instruction over 4 uops will be delivered by the MS. Some instructions such as transcendentals may additionally generate uops from the MS.",
        "SampleAfterValue": "100003",
        "UMask": "0x30"
    },
    {
        "BriefDescription": "Uops not delivered by IDQ when backend of the machine is not stalled",
        "Counter": "0,1,2,3,4,5,6,7",
        "EventCode": "0x9c",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
        "PublicDescription": "Counts the number of uops not delivered to by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles when no uops are not delivered by the IDQ when backend of the machine is not stalled",
        "Counter": "0,1,2,3,4,5,6,7",
        "CounterMask": "5",
        "EventCode": "0x9c",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
        "PublicDescription": "Counts the number of cycles when no uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    },
    {
        "BriefDescription": "Cycles when optimal number of uops was delivered to the back-end when the back-end is not stalled",
        "Counter": "0,1,2,3,4,5,6,7",
        "CounterMask": "1",
        "EventCode": "0x9c",
        "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
        "Invert": "1",
        "PublicDescription": "Counts the number of cycles when the optimal number of uops were delivered by the Instruction Decode Queue (IDQ) to the back-end of the pipeline when there was no back-end stalls. This event counts for one SMT thread in a given cycle.",
        "SampleAfterValue": "1000003",
        "UMask": "0x1"
    }
]
