Warning: Permanently added '2620:52:3:1:dead:beef:cafe:c1da' (ED25519) to the list of known hosts.

You can reproduce this build on your computer by running:

  sudo dnf install copr-rpmbuild
  /usr/bin/copr-rpmbuild --verbose --drop-resultdir --task-url https://copr.fedorainfracloud.org/backend/get-build-task/8285268-fedora-rawhide-x86_64 --chroot fedora-rawhide-x86_64


Version: 1.1
PID: 7294
Logging PID: 7295
Task:
{'allow_user_ssh': False,
 'appstream': False,
 'background': False,
 'build_id': 8285268,
 'buildroot_pkgs': [],
 'chroot': 'fedora-rawhide-x86_64',
 'enable_net': False,
 'fedora_review': False,
 'git_hash': 'e829c313088597e9b36011e4b8b6b329808ce1a8',
 'git_repo': 'https://copr-dist-git.fedorainfracloud.org/git/thrnciar/python-sphinx/yosys',
 'isolation': 'default',
 'memory_reqs': 2048,
 'package_name': 'yosys',
 'package_version': '0.47-1.20241110gitf20f913',
 'project_dirname': 'python-sphinx',
 'project_name': 'python-sphinx',
 'project_owner': 'thrnciar',
 'repo_priority': None,
 'repos': [{'baseurl': 'https://download.copr.fedorainfracloud.org/results/thrnciar/python-sphinx/fedora-rawhide-x86_64/',
            'id': 'copr_base',
            'name': 'Copr repository',
            'priority': None},
           {'baseurl': 'http://kojipkgs.fedoraproject.org/repos/rawhide/latest/$basearch/',
            'id': 'http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch',
            'name': 'Additional repo http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch'}],
 'sandbox': 'thrnciar/python-sphinx--thrnciar',
 'source_json': {},
 'source_type': None,
 'ssh_public_keys': None,
 'storage': 0,
 'submitter': 'thrnciar',
 'tags': [],
 'task_id': '8285268-fedora-rawhide-x86_64',
 'timeout': 18000,
 'uses_devel_repo': False,
 'with_opts': [],
 'without_opts': []}

Running: git clone https://copr-dist-git.fedorainfracloud.org/git/thrnciar/python-sphinx/yosys /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys --depth 500 --no-single-branch --recursive

cmd: ['git', 'clone', 'https://copr-dist-git.fedorainfracloud.org/git/thrnciar/python-sphinx/yosys', '/var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys', '--depth', '500', '--no-single-branch', '--recursive']
cwd: .
rc: 0
stdout: 
stderr: Cloning into '/var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys'...

Running: git checkout e829c313088597e9b36011e4b8b6b329808ce1a8 --

cmd: ['git', 'checkout', 'e829c313088597e9b36011e4b8b6b329808ce1a8', '--']
cwd: /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys
rc: 0
stdout: 
stderr: Note: switching to 'e829c313088597e9b36011e4b8b6b329808ce1a8'.

You are in 'detached HEAD' state. You can look around, make experimental
changes and commit them, and you can discard any commits you make in this
state without impacting any branches by switching back to a branch.

If you want to create a new branch to retain commits you create, you may
do so (now or later) by using -c with the switch command. Example:

  git switch -c <new-branch-name>

Or undo this operation with:

  git switch -

Turn off this advice by setting config variable advice.detachedHead to false

HEAD is now at e829c31 automatic import of yosys

Running: dist-git-client sources
INFO: Reading stdout from command: md5sum yosys-f20f913.tar.gz
INFO: Downloading yosys_0.33-5.debian.tar.xz
INFO: Calling: curl -H Pragma: -o yosys_0.33-5.debian.tar.xz --location --connect-timeout 60 --retry 3 --retry-delay 10 --remote-time --show-error --fail --retry-all-errors https://copr-dist-git.fedorainfracloud.org/repo/pkgs/thrnciar/python-sphinx/yosys/yosys_0.33-5.debian.tar.xz/md5/ea0e202dc8df4d0df04a98b15aac442d/yosys_0.33-5.debian.tar.xz
  % Total    % Received % Xferd  Average Speed   Time    Time     Time  Current
                                 Dload  Upload   Total   Spent    Left  Speed
100 30100  100 30100    0     0   588k      0 --:--:-- --:--:-- --:--:--  599k
INFO: Reading stdout from command: md5sum yosys_0.33-5.debian.tar.xz

/usr/bin/tail: /var/lib/copr-rpmbuild/main.log: file truncated
Running (timeout=18000): unbuffer mock --spec /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys/yosys.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1732107006.500093 -r /var/lib/copr-rpmbuild/results/configs/child.cfg
INFO: mock.py version 5.9 starting (python version = 3.12.1, NVR = mock-5.9-1.fc39), args: /usr/libexec/mock/mock --spec /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys/yosys.spec --sources /var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys --resultdir /var/lib/copr-rpmbuild/results --uniqueext 1732107006.500093 -r /var/lib/copr-rpmbuild/results/configs/child.cfg
Start(bootstrap): init plugins
INFO: tmpfs initialized
INFO: selinux enabled
INFO: chroot_scan: initialized
INFO: compress_logs: initialized
Finish(bootstrap): init plugins
Start: init plugins
INFO: tmpfs initialized
INFO: selinux enabled
INFO: chroot_scan: initialized
INFO: compress_logs: initialized
Finish: init plugins
INFO: Signal handler active
Start: run
INFO: Start(/var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys/yosys.spec)  Config(fedora-rawhide-x86_64)
Start: clean chroot
Finish: clean chroot
Mock Version: 5.9
INFO: Mock Version: 5.9
Start(bootstrap): chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1732107006.500093/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start(bootstrap): cleaning package manager metadata
Finish(bootstrap): cleaning package manager metadata
INFO: Guessed host environment type: unknown
INFO: Using bootstrap image: registry.fedoraproject.org/fedora:rawhide
INFO: Pulling image: registry.fedoraproject.org/fedora:rawhide
INFO: Copy content of container registry.fedoraproject.org/fedora:rawhide to /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1732107006.500093/root
INFO: Checking that registry.fedoraproject.org/fedora:rawhide image matches host's architecture
INFO: mounting registry.fedoraproject.org/fedora:rawhide with podman image mount
INFO: image registry.fedoraproject.org/fedora:rawhide as /var/lib/containers/storage/overlay/9fdff1dcfb964ab4ba93f385d9633e39d5465107d99dad6585dd15e4b4f3eb5a/merged
INFO: umounting image registry.fedoraproject.org/fedora:rawhide (/var/lib/containers/storage/overlay/9fdff1dcfb964ab4ba93f385d9633e39d5465107d99dad6585dd15e4b4f3eb5a/merged) with podman image umount
INFO: Package manager dnf5 detected and used (fallback)
INFO: Not updating bootstrap chroot, bootstrap_image_ready=True
Start(bootstrap): creating root cache
Finish(bootstrap): creating root cache
Finish(bootstrap): chroot init
Start: chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start: cleaning package manager metadata
Finish: cleaning package manager metadata
INFO: enabled HW Info plugin
INFO: Package manager dnf5 detected and used (direct choice)
INFO: Buildroot is handled by package management downloaded with a bootstrap image:
  rpm-4.20.0-1.fc42.x86_64
  rpm-sequoia-1.7.0-2.fc41.x86_64
  dnf5-5.2.7.0-1.fc42.x86_64
  dnf5-plugins-5.2.7.0-1.fc42.x86_64
Start: installing minimal buildroot with dnf5
Updating and loading repositories:
 fedora                                 100% |  19.3 MiB/s |  21.8 MiB |  00m01s
 Copr repository                        100% |   4.1 MiB/s |   1.5 MiB |  00m00s
 Additional repo http_kojipkgs_fedorapr 100% |  47.4 MiB/s |  14.3 MiB |  00m00s
Repositories loaded.
Package                            Arch   Version                    Repository                                                         Size
Installing group/module packages:
 bash                              x86_64 5.2.37-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   8.2 MiB
 bzip2                             x86_64 1.0.8-19.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  95.7 KiB
 coreutils                         x86_64 9.5-11.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   5.4 MiB
 cpio                              x86_64 2.15-2.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.1 MiB
 diffutils                         x86_64 3.10-8.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.6 MiB
 fedora-release-common             noarch 42-0.8                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  19.7 KiB
 findutils                         x86_64 1:4.10.0-4.fc41            http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.8 MiB
 gawk                              x86_64 5.3.0-4.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 glibc-minimal-langpack            x86_64 2.40.9000-18.fc42          http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   0.0   B
 grep                              x86_64 3.11-9.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.0 MiB
 gzip                              x86_64 1.13-2.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 389.0 KiB
 info                              x86_64 7.1.1-2.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 361.8 KiB
 patch                             x86_64 2.7.6-25.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 266.7 KiB
 redhat-rpm-config                 noarch 296-1.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 186.6 KiB
 rpm-build                         x86_64 4.20.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 194.3 KiB
 sed                               x86_64 4.9-3.fc41                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 861.5 KiB
 shadow-utils                      x86_64 2:4.16.0-7.fc42            http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   4.0 MiB
 tar                               x86_64 2:1.35-4.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.9 MiB
 unzip                             x86_64 6.0-64.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 386.8 KiB
 util-linux                        x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.7 MiB
 which                             x86_64 2.21-42.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  80.2 KiB
 xz                                x86_64 1:5.6.3-2.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.2 MiB
Installing dependencies:
 add-determinism                   x86_64 0.4.3-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.4 MiB
 alternatives                      x86_64 1.30-1.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  66.3 KiB
 ansible-srpm-macros               noarch 1-16.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  35.7 KiB
 audit-libs                        x86_64 4.0.2-1.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 331.3 KiB
 authselect                        x86_64 1.5.0-8.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 157.5 KiB
 authselect-libs                   x86_64 1.5.0-8.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 822.2 KiB
 basesystem                        noarch 11-21.fc41                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   0.0   B
 binutils                          x86_64 2.43.50-8.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  25.4 MiB
 build-reproducibility-srpm-macros noarch 0.4.3-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 735.0   B
 bzip2-libs                        x86_64 1.0.8-19.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  80.7 KiB
 ca-certificates                   noarch 2024.2.69_v8.0.401-2.fc42  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.6 MiB
 coreutils-common                  x86_64 9.5-11.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  11.2 MiB
 cracklib                          x86_64 2.9.11-6.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 238.9 KiB
 crypto-policies                   noarch 20241106-1.git35892de.fc42 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 136.9 KiB
 curl                              x86_64 8.10.1-2.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 453.3 KiB
 cyrus-sasl-lib                    x86_64 2.1.28-27.fc41             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.3 MiB
 debugedit                         x86_64 5.1-1.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 192.7 KiB
 dwz                               x86_64 0.15-8.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 299.2 KiB
 ed                                x86_64 1.20.2-2.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 146.9 KiB
 efi-srpm-macros                   noarch 5-12.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  40.1 KiB
 elfutils                          x86_64 0.192-6.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.6 MiB
 elfutils-debuginfod-client        x86_64 0.192-6.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  80.4 KiB
 elfutils-default-yama-scope       noarch 0.192-6.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.8 KiB
 elfutils-libelf                   x86_64 0.192-6.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.2 MiB
 elfutils-libs                     x86_64 0.192-6.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 672.8 KiB
 fedora-gpg-keys                   noarch 42-0.3                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 126.4 KiB
 fedora-release                    noarch 42-0.8                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   0.0   B
 fedora-release-identity-basic     noarch 42-0.8                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 719.0   B
 fedora-repos                      noarch 42-0.3                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   4.9 KiB
 fedora-repos-rawhide              noarch 42-0.3                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.2 KiB
 file                              x86_64 5.45-7.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 103.5 KiB
 file-libs                         x86_64 5.45-7.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   9.9 MiB
 filesystem                        x86_64 3.18-29.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 106.0   B
 fonts-srpm-macros                 noarch 1:2.0.5-17.fc41            http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  55.8 KiB
 forge-srpm-macros                 noarch 0.4.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  38.9 KiB
 fpc-srpm-macros                   noarch 1.3-13.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 144.0   B
 gdb-minimal                       x86_64 15.2-3.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  13.0 MiB
 gdbm                              x86_64 1:1.23-7.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 460.9 KiB
 gdbm-libs                         x86_64 1:1.23-7.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 121.9 KiB
 ghc-srpm-macros                   noarch 1.9.2-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 779.0   B
 glibc                             x86_64 2.40.9000-18.fc42          http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   6.7 MiB
 glibc-common                      x86_64 2.40.9000-18.fc42          http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.1 MiB
 glibc-gconv-extra                 x86_64 2.40.9000-18.fc42          http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   8.0 MiB
 gmp                               x86_64 1:6.3.0-2.fc41             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 811.4 KiB
 gnat-srpm-macros                  noarch 6-6.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.0 KiB
 go-srpm-macros                    noarch 3.6.0-3.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  60.8 KiB
 jansson                           x86_64 2.14-1.fc42                copr_base                                                      89.3 KiB
 json-c                            x86_64 0.18-1.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  83.3 KiB
 kernel-srpm-macros                noarch 1.0-24.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.9 KiB
 keyutils-libs                     x86_64 1.6.3-4.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  54.4 KiB
 krb5-libs                         x86_64 1.21.3-3.fc42              copr_base                                                       2.3 MiB
 libacl                            x86_64 2.3.2-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  40.0 KiB
 libarchive                        x86_64 3.7.7-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 932.3 KiB
 libattr                           x86_64 2.5.2-4.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  28.5 KiB
 libblkid                          x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 262.5 KiB
 libbrotli                         x86_64 1.1.0-5.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 837.6 KiB
 libcap                            x86_64 2.71-1.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 210.8 KiB
 libcap-ng                         x86_64 0.8.5-3.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  69.2 KiB
 libcom_err                        x86_64 1.47.1-6.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  67.2 KiB
 libcurl                           x86_64 8.10.1-2.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 838.4 KiB
 libeconf                          x86_64 0.7.4-3.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  65.7 KiB
 libevent                          x86_64 2.1.12-14.fc41             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 895.7 KiB
 libfdisk                          x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 362.9 KiB
 libffi                            x86_64 3.4.6-3.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  86.4 KiB
 libgcc                            x86_64 14.2.1-6.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 270.6 KiB
 libgomp                           x86_64 14.2.1-6.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 519.8 KiB
 libidn2                           x86_64 2.3.7-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 329.1 KiB
 libmount                          x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 355.8 KiB
 libnghttp2                        x86_64 1.64.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 174.5 KiB
 libnsl2                           x86_64 2.0.1-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  57.9 KiB
 libpkgconf                        x86_64 2.3.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  78.2 KiB
 libpsl                            x86_64 0.21.5-4.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  80.5 KiB
 libpwquality                      x86_64 1.4.5-11.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 417.8 KiB
 libselinux                        x86_64 3.7-6.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 181.1 KiB
 libsemanage                       x86_64 3.7-3.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 298.0 KiB
 libsepol                          x86_64 3.7-3.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 818.0 KiB
 libsmartcols                      x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 180.4 KiB
 libssh                            x86_64 0.11.1-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 569.6 KiB
 libssh-config                     noarch 0.11.1-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 277.0   B
 libstdc++                         x86_64 14.2.1-6.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.8 MiB
 libtasn1                          x86_64 4.19.0-9.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 175.7 KiB
 libtirpc                          x86_64 1.3.6-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 205.5 KiB
 libtool-ltdl                      x86_64 2.4.7-12.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  66.2 KiB
 libunistring                      x86_64 1.1-8.fc41                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 libuuid                           x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  41.4 KiB
 libverto                          x86_64 0.3.2-9.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  29.5 KiB
 libxcrypt                         x86_64 4.4.36-10.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 267.7 KiB
 libxml2                           x86_64 2.12.8-2.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 libzstd                           x86_64 1.5.6-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 795.9 KiB
 lua-libs                          x86_64 5.4.7-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 285.0 KiB
 lua-srpm-macros                   noarch 1-14.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.3 KiB
 lz4-libs                          x86_64 1.10.0-1.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 145.5 KiB
 mpfr                              x86_64 4.2.1-5.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 832.1 KiB
 ncurses-base                      noarch 6.5-2.20240629.fc41        http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 326.3 KiB
 ncurses-libs                      x86_64 6.5-2.20240629.fc41        http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 975.2 KiB
 ocaml-srpm-macros                 noarch 10-3.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.9 KiB
 openblas-srpm-macros              noarch 2-18.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 112.0   B
 openldap                          x86_64 2.6.8-5.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 644.2 KiB
 openssl-libs                      x86_64 1:3.2.2-8.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   7.8 MiB
 p11-kit                           x86_64 0.25.5-4.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.2 MiB
 p11-kit-trust                     x86_64 0.25.5-4.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 403.8 KiB
 package-notes-srpm-macros         noarch 0.5-12.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.6 KiB
 pam                               x86_64 1.7.0-2.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 pam-libs                          x86_64 1.7.0-2.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 127.7 KiB
 pcre2                             x86_64 10.44-1.fc41.1             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 653.5 KiB
 pcre2-syntax                      noarch 10.44-1.fc41.1             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 251.6 KiB
 perl-srpm-macros                  noarch 1-56.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 861.0   B
 pkgconf                           x86_64 2.3.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  88.6 KiB
 pkgconf-m4                        noarch 2.3.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  14.4 KiB
 pkgconf-pkg-config                x86_64 2.3.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 989.0   B
 popt                              x86_64 1.19-7.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 136.9 KiB
 publicsuffix-list-dafsa           noarch 20240107-4.fc41            http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  67.5 KiB
 pyproject-srpm-macros             noarch 1.16.2-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.9 KiB
 python-srpm-macros                noarch 3.13-3.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  51.0 KiB
 qt5-srpm-macros                   noarch 5.15.15-1.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 500.0   B
 qt6-srpm-macros                   noarch 6.8.0-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 456.0   B
 readline                          x86_64 8.2-11.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 493.1 KiB
 rpm                               x86_64 4.20.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.1 MiB
 rpm-build-libs                    x86_64 4.20.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 206.7 KiB
 rpm-libs                          x86_64 4.20.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 726.1 KiB
 rpm-sequoia                       x86_64 1.7.0-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.4 MiB
 rust-srpm-macros                  noarch 26.3-3.fc42                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   4.8 KiB
 setup                             noarch 2.15.0-5.fc41              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 720.7 KiB
 sqlite-libs                       x86_64 3.47.0-1.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.5 MiB
 systemd-libs                      x86_64 257~rc2-2.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.3 MiB
 util-linux-core                   x86_64 2.40.2-8.fc42              http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.5 MiB
 xxhash-libs                       x86_64 0.8.2-4.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  88.4 KiB
 xz-libs                           x86_64 1:5.6.3-2.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 218.4 KiB
 zig-srpm-macros                   noarch 1-3.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.1 KiB
 zip                               x86_64 3.0-41.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 703.2 KiB
 zlib-ng-compat                    x86_64 2.2.2-1.fc42               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 134.0 KiB
 zstd                              x86_64 1.5.6-2.fc41               http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
Installing groups:
 Buildsystem building group                                                                                                                 

Transaction Summary:
 Installing:       154 packages

Total size of inbound packages is 52 MiB. Need to download 52 MiB.
After this operation, 178 MiB extra will be used (install 178 MiB, remove 0 B).
[  1/154] bzip2-0:1.0.8-19.fc41.x86_64  100% | 700.3 KiB/s |  52.5 KiB |  00m00s
[  2/154] coreutils-0:9.5-11.fc42.x86_6 100% |  10.8 MiB/s |   1.1 MiB |  00m00s
[  3/154] cpio-0:2.15-2.fc41.x86_64     100% |   6.5 MiB/s | 285.2 KiB |  00m00s
[  4/154] bash-0:5.2.37-1.fc42.x86_64   100% |  14.7 MiB/s |   1.8 MiB |  00m00s
[  5/154] diffutils-0:3.10-8.fc41.x86_6 100% |  16.9 MiB/s | 397.2 KiB |  00m00s
[  6/154] fedora-release-common-0:42-0. 100% |   1.2 MiB/s |  23.5 KiB |  00m00s
[  7/154] glibc-minimal-langpack-0:2.40 100% |   5.8 MiB/s | 119.6 KiB |  00m00s
[  8/154] gawk-0:5.3.0-4.fc41.x86_64    100% |  27.2 MiB/s |   1.1 MiB |  00m00s
[  9/154] findutils-1:4.10.0-4.fc41.x86 100% |  11.5 MiB/s | 539.8 KiB |  00m00s
[ 10/154] grep-0:3.11-9.fc41.x86_64     100% |  14.1 MiB/s | 289.7 KiB |  00m00s
[ 11/154] gzip-0:1.13-2.fc41.x86_64     100% |   8.4 MiB/s | 164.1 KiB |  00m00s
[ 12/154] info-0:7.1.1-2.fc42.x86_64    100% |   8.9 MiB/s | 183.2 KiB |  00m00s
[ 13/154] patch-0:2.7.6-25.fc41.x86_64  100% |   7.1 MiB/s | 131.0 KiB |  00m00s
[ 14/154] redhat-rpm-config-0:296-1.fc4 100% |   2.5 MiB/s |  75.7 KiB |  00m00s
[ 15/154] rpm-build-0:4.20.0-1.fc42.x86 100% |   3.1 MiB/s |  75.2 KiB |  00m00s
[ 16/154] sed-0:4.9-3.fc41.x86_64       100% |  13.7 MiB/s | 309.3 KiB |  00m00s
[ 17/154] unzip-0:6.0-64.fc41.x86_64    100% |   9.0 MiB/s | 184.9 KiB |  00m00s
[ 18/154] tar-2:1.35-4.fc41.x86_64      100% |  18.1 MiB/s | 852.1 KiB |  00m00s
[ 19/154] shadow-utils-2:4.16.0-7.fc42. 100% |  24.7 MiB/s |   1.3 MiB |  00m00s
[ 20/154] util-linux-0:2.40.2-8.fc42.x8 100% |  30.2 MiB/s |   1.1 MiB |  00m00s
[ 21/154] which-0:2.21-42.fc41.x86_64   100% |   2.3 MiB/s |  41.6 KiB |  00m00s
[ 22/154] xz-1:5.6.3-2.fc42.x86_64      100% |  16.7 MiB/s | 461.7 KiB |  00m00s
[ 23/154] xz-libs-1:5.6.3-2.fc42.x86_64 100% |   4.8 MiB/s | 111.9 KiB |  00m00s
[ 24/154] audit-libs-0:4.0.2-1.fc41.x86 100% |   6.2 MiB/s | 126.2 KiB |  00m00s
[ 25/154] authselect-libs-0:1.5.0-8.fc4 100% |  10.5 MiB/s | 204.7 KiB |  00m00s
[ 26/154] glibc-0:2.40.9000-18.fc42.x86 100% |  46.4 MiB/s |   2.2 MiB |  00m00s
[ 27/154] libblkid-0:2.40.2-8.fc42.x86_ 100% |   6.4 MiB/s | 125.0 KiB |  00m00s
[ 28/154] libcap-ng-0:0.8.5-3.fc41.x86_ 100% |   1.9 MiB/s |  32.6 KiB |  00m00s
[ 29/154] libfdisk-0:2.40.2-8.fc42.x86_ 100% |   7.4 MiB/s | 159.6 KiB |  00m00s
[ 30/154] libmount-0:2.40.2-8.fc42.x86_ 100% |   8.5 MiB/s | 156.1 KiB |  00m00s
[ 31/154] libselinux-0:3.7-6.fc42.x86_6 100% |   4.8 MiB/s |  88.6 KiB |  00m00s
[ 32/154] libsmartcols-0:2.40.2-8.fc42. 100% |   4.8 MiB/s |  83.9 KiB |  00m00s
[ 33/154] libuuid-0:2.40.2-8.fc42.x86_6 100% |   1.7 MiB/s |  29.0 KiB |  00m00s
[ 34/154] ncurses-libs-0:6.5-2.20240629 100% |  16.3 MiB/s | 334.0 KiB |  00m00s
[ 35/154] pam-libs-0:1.7.0-2.fc42.x86_6 100% |   3.0 MiB/s |  57.9 KiB |  00m00s
[ 36/154] readline-0:8.2-11.fc42.x86_64 100% |  11.0 MiB/s | 213.4 KiB |  00m00s
[ 37/154] pam-0:1.7.0-2.fc42.x86_64     100% |  15.0 MiB/s | 523.5 KiB |  00m00s
[ 38/154] systemd-libs-0:257~rc2-2.fc42 100% |  29.4 MiB/s | 813.0 KiB |  00m00s
[ 39/154] util-linux-core-0:2.40.2-8.fc 100% |  22.1 MiB/s | 521.5 KiB |  00m00s
[ 40/154] zlib-ng-compat-0:2.2.2-1.fc42 100% |   3.6 MiB/s |  76.9 KiB |  00m00s
[ 41/154] bzip2-libs-0:1.0.8-19.fc41.x8 100% |   2.2 MiB/s |  41.1 KiB |  00m00s
[ 42/154] libacl-0:2.3.2-2.fc41.x86_64  100% |   1.4 MiB/s |  24.5 KiB |  00m00s
[ 43/154] libcap-0:2.71-1.fc42.x86_64   100% |   5.0 MiB/s |  86.4 KiB |  00m00s
[ 44/154] libgcc-0:14.2.1-6.fc42.x86_64 100% |   7.0 MiB/s | 135.2 KiB |  00m00s
[ 45/154] libattr-0:2.5.2-4.fc41.x86_64 100% |   1.0 MiB/s |  18.2 KiB |  00m00s
[ 46/154] libeconf-0:0.7.4-3.fc42.x86_6 100% |   2.0 MiB/s |  34.6 KiB |  00m00s
[ 47/154] libsemanage-0:3.7-3.fc42.x86_ 100% |   5.7 MiB/s | 117.2 KiB |  00m00s
[ 48/154] libxcrypt-0:4.4.36-10.fc42.x8 100% |   6.5 MiB/s | 119.0 KiB |  00m00s
[ 49/154] setup-0:2.15.0-5.fc41.noarch  100% |   6.9 MiB/s | 148.3 KiB |  00m00s
[ 50/154] debugedit-0:5.1-1.fc42.x86_64 100% |   3.6 MiB/s |  78.1 KiB |  00m00s
[ 51/154] elfutils-0:0.192-6.fc42.x86_6 100% |  21.3 MiB/s | 545.5 KiB |  00m00s
[ 52/154] elfutils-libelf-0:0.192-6.fc4 100% |   8.4 MiB/s | 207.5 KiB |  00m00s
[ 53/154] file-0:5.45-7.fc41.x86_64     100% |   2.3 MiB/s |  49.1 KiB |  00m00s
[ 54/154] pkgconf-pkg-config-0:2.3.0-1. 100% | 526.9 KiB/s |  10.0 KiB |  00m00s
[ 55/154] libarchive-0:3.7.7-1.fc42.x86 100% |  13.5 MiB/s | 413.9 KiB |  00m00s
[ 56/154] popt-0:1.19-7.fc41.x86_64     100% |   3.2 MiB/s |  59.3 KiB |  00m00s
[ 57/154] binutils-0:2.43.50-8.fc42.x86 100% |  56.4 MiB/s |   5.8 MiB |  00m00s
[ 58/154] rpm-0:4.20.0-1.fc42.x86_64    100% |  20.3 MiB/s | 519.3 KiB |  00m00s
[ 59/154] rpm-build-libs-0:4.20.0-1.fc4 100% |   3.7 MiB/s |  98.7 KiB |  00m00s
[ 60/154] zstd-0:1.5.6-2.fc41.x86_64    100% |  21.4 MiB/s | 481.5 KiB |  00m00s
[ 61/154] rpm-libs-0:4.20.0-1.fc42.x86_ 100% |  11.6 MiB/s | 309.5 KiB |  00m00s
[ 62/154] curl-0:8.10.1-2.fc42.x86_64   100% |  11.4 MiB/s | 221.3 KiB |  00m00s
[ 63/154] ansible-srpm-macros-0:1-16.fc 100% |   1.0 MiB/s |  20.8 KiB |  00m00s
[ 64/154] build-reproducibility-srpm-ma 100% | 588.4 KiB/s |  11.2 KiB |  00m00s
[ 65/154] dwz-0:0.15-8.fc42.x86_64      100% |   7.1 MiB/s | 139.1 KiB |  00m00s
[ 66/154] efi-srpm-macros-0:5-12.fc41.n 100% |   1.3 MiB/s |  22.4 KiB |  00m00s
[ 67/154] fonts-srpm-macros-1:2.0.5-17. 100% |   1.5 MiB/s |  27.0 KiB |  00m00s
[ 68/154] glibc-gconv-extra-0:2.40.9000 100% |  20.8 MiB/s |   1.6 MiB |  00m00s
[ 69/154] fpc-srpm-macros-0:1.3-13.fc41 100% | 398.1 KiB/s |   8.0 KiB |  00m00s
[ 70/154] ghc-srpm-macros-0:1.9.2-1.fc4 100% | 455.9 KiB/s |   9.1 KiB |  00m00s
[ 71/154] gnat-srpm-macros-0:6-6.fc41.n 100% | 526.6 KiB/s |   9.0 KiB |  00m00s
[ 72/154] go-srpm-macros-0:3.6.0-3.fc41 100% |   1.4 MiB/s |  28.0 KiB |  00m00s
[ 73/154] kernel-srpm-macros-0:1.0-24.f 100% | 493.4 KiB/s |   9.9 KiB |  00m00s
[ 74/154] lua-srpm-macros-0:1-14.fc41.n 100% | 493.3 KiB/s |   8.9 KiB |  00m00s
[ 75/154] ocaml-srpm-macros-0:10-3.fc41 100% | 541.1 KiB/s |   9.2 KiB |  00m00s
[ 76/154] openblas-srpm-macros-0:2-18.f 100% | 453.8 KiB/s |   7.7 KiB |  00m00s
[ 77/154] package-notes-srpm-macros-0:0 100% | 614.3 KiB/s |   9.8 KiB |  00m00s
[ 78/154] pyproject-srpm-macros-0:1.16. 100% | 729.9 KiB/s |  13.9 KiB |  00m00s
[ 79/154] perl-srpm-macros-0:1-56.fc41. 100% | 448.0 KiB/s |   8.5 KiB |  00m00s
[ 80/154] qt5-srpm-macros-0:5.15.15-1.f 100% | 523.4 KiB/s |   8.9 KiB |  00m00s
[ 81/154] python-srpm-macros-0:3.13-3.f 100% |   1.3 MiB/s |  23.7 KiB |  00m00s
[ 82/154] rust-srpm-macros-0:26.3-3.fc4 100% | 756.2 KiB/s |  12.1 KiB |  00m00s
[ 83/154] qt6-srpm-macros-0:6.8.0-1.fc4 100% | 532.3 KiB/s |   9.0 KiB |  00m00s
[ 84/154] zig-srpm-macros-0:1-3.fc41.no 100% | 451.3 KiB/s |   8.1 KiB |  00m00s
[ 85/154] zip-0:3.0-41.fc41.x86_64      100% |   9.9 MiB/s | 264.8 KiB |  00m00s
[ 86/154] pkgconf-0:2.3.0-1.fc42.x86_64 100% |   2.5 MiB/s |  45.2 KiB |  00m00s
[ 87/154] pkgconf-m4-0:2.3.0-1.fc42.noa 100% | 842.4 KiB/s |  14.3 KiB |  00m00s
[ 88/154] libpkgconf-0:2.3.0-1.fc42.x86 100% |   2.0 MiB/s |  38.5 KiB |  00m00s
[ 89/154] ed-0:1.20.2-2.fc41.x86_64     100% |   4.4 MiB/s |  81.8 KiB |  00m00s
[ 90/154] authselect-0:1.5.0-8.fc42.x86 100% |   7.3 MiB/s | 141.2 KiB |  00m00s
[ 91/154] gdbm-1:1.23-7.fc41.x86_64     100% |   7.6 MiB/s | 147.2 KiB |  00m00s
[ 92/154] gdbm-libs-1:1.23-7.fc41.x86_6 100% |   3.2 MiB/s |  56.3 KiB |  00m00s
[ 93/154] libnsl2-0:2.0.1-2.fc41.x86_64 100% |   1.7 MiB/s |  29.6 KiB |  00m00s
[ 94/154] libpwquality-0:1.4.5-11.fc41. 100% |   5.9 MiB/s | 108.2 KiB |  00m00s
[ 95/154] libtirpc-0:1.3.6-1.fc42.x86_6 100% |   4.6 MiB/s |  94.9 KiB |  00m00s
[ 96/154] openssl-libs-1:3.2.2-8.fc42.x 100% |  44.4 MiB/s |   2.3 MiB |  00m00s
[ 97/154] ca-certificates-0:2024.2.69_v 100% |  15.1 MiB/s | 944.5 KiB |  00m00s
[ 98/154] crypto-policies-0:20241106-1. 100% |   4.0 MiB/s |  73.3 KiB |  00m00s
[ 99/154] ncurses-base-0:6.5-2.20240629 100% |   3.1 MiB/s |  63.8 KiB |  00m00s
[100/154] libcom_err-0:1.47.1-6.fc42.x8 100% |   1.4 MiB/s |  26.6 KiB |  00m00s
[101/154] libsepol-0:3.7-3.fc42.x86_64  100% |  15.9 MiB/s | 342.2 KiB |  00m00s
[102/154] krb5-libs-0:1.21.3-3.fc42.x86 100% |   9.6 MiB/s | 755.8 KiB |  00m00s
[103/154] pcre2-0:10.44-1.fc41.1.x86_64 100% |  11.9 MiB/s | 243.1 KiB |  00m00s
[104/154] cracklib-0:2.9.11-6.fc41.x86_ 100% |   4.7 MiB/s |  81.7 KiB |  00m00s
[105/154] libzstd-0:1.5.6-2.fc41.x86_64 100% |  13.2 MiB/s | 310.3 KiB |  00m00s
[106/154] libxml2-0:2.12.8-2.fc41.x86_6 100% |  15.3 MiB/s | 687.3 KiB |  00m00s
[107/154] lz4-libs-0:1.10.0-1.fc41.x86_ 100% |   4.1 MiB/s |  70.7 KiB |  00m00s
[108/154] basesystem-0:11-21.fc41.noarc 100% | 460.8 KiB/s |   7.4 KiB |  00m00s
[109/154] glibc-common-0:2.40.9000-18.f 100% |  11.9 MiB/s | 402.6 KiB |  00m00s
[110/154] gmp-1:6.3.0-2.fc41.x86_64     100% |  11.1 MiB/s | 318.0 KiB |  00m00s
[111/154] filesystem-0:3.18-29.fc42.x86 100% |  26.7 MiB/s |   1.1 MiB |  00m00s
[112/154] mpfr-0:4.2.1-5.fc41.x86_64    100% |  15.4 MiB/s | 346.3 KiB |  00m00s
[113/154] fedora-repos-0:42-0.3.noarch  100% | 483.8 KiB/s |   9.2 KiB |  00m00s
[114/154] file-libs-0:5.45-7.fc41.x86_6 100% |  15.2 MiB/s | 762.0 KiB |  00m00s
[115/154] elfutils-debuginfod-client-0: 100% |   2.8 MiB/s |  46.0 KiB |  00m00s
[116/154] elfutils-libs-0:0.192-6.fc42. 100% |  13.5 MiB/s | 263.4 KiB |  00m00s
[117/154] libstdc++-0:14.2.1-6.fc42.x86 100% |  17.4 MiB/s | 890.1 KiB |  00m00s
[118/154] libffi-0:3.4.6-3.fc42.x86_64  100% |   2.2 MiB/s |  40.0 KiB |  00m00s
[119/154] coreutils-common-0:9.5-11.fc4 100% |  37.4 MiB/s |   2.1 MiB |  00m00s
[120/154] p11-kit-trust-0:0.25.5-4.fc42 100% |   7.2 MiB/s | 133.2 KiB |  00m00s
[121/154] p11-kit-0:0.25.5-4.fc42.x86_6 100% |  18.7 MiB/s | 478.3 KiB |  00m00s
[122/154] alternatives-0:1.30-1.fc41.x8 100% |   2.1 MiB/s |  42.5 KiB |  00m00s
[123/154] jansson-0:2.14-1.fc42.x86_64  100% |   4.5 MiB/s |  45.7 KiB |  00m00s
[124/154] add-determinism-0:0.4.3-1.fc4 100% |  24.5 MiB/s | 904.4 KiB |  00m00s
[125/154] keyutils-libs-0:1.6.3-4.fc41. 100% |   1.8 MiB/s |  31.6 KiB |  00m00s
[126/154] libverto-0:0.3.2-9.fc41.x86_6 100% |   1.3 MiB/s |  20.7 KiB |  00m00s
[127/154] lua-libs-0:5.4.7-1.fc42.x86_6 100% |   6.4 MiB/s | 132.1 KiB |  00m00s
[128/154] sqlite-libs-0:3.47.0-1.fc42.x 100% |  25.2 MiB/s | 723.2 KiB |  00m00s
[129/154] rpm-sequoia-0:1.7.0-2.fc41.x8 100% |  16.8 MiB/s | 892.5 KiB |  00m00s
[130/154] libgomp-0:14.2.1-6.fc42.x86_6 100% |  15.8 MiB/s | 356.9 KiB |  00m00s
[131/154] pcre2-syntax-0:10.44-1.fc41.1 100% |   7.3 MiB/s | 149.9 KiB |  00m00s
[132/154] libtasn1-0:4.19.0-9.fc41.x86_ 100% |   4.3 MiB/s |  74.2 KiB |  00m00s
[133/154] fedora-gpg-keys-0:42-0.3.noar 100% |   6.7 MiB/s | 123.4 KiB |  00m00s
[134/154] elfutils-default-yama-scope-0 100% | 725.2 KiB/s |  12.3 KiB |  00m00s
[135/154] fedora-repos-rawhide-0:42-0.3 100% | 461.2 KiB/s |   8.8 KiB |  00m00s
[136/154] json-c-0:0.18-1.fc42.x86_64   100% |   2.6 MiB/s |  44.4 KiB |  00m00s
[137/154] fedora-release-0:42-0.8.noarc 100% | 746.6 KiB/s |  12.7 KiB |  00m00s
[138/154] xxhash-libs-0:0.8.2-4.fc42.x8 100% |   1.7 MiB/s |  36.8 KiB |  00m00s
[139/154] fedora-release-identity-basic 100% | 843.6 KiB/s |  13.5 KiB |  00m00s
[140/154] libcurl-0:8.10.1-2.fc42.x86_6 100% |  13.0 MiB/s | 371.3 KiB |  00m00s
[141/154] libbrotli-0:1.1.0-5.fc41.x86_ 100% |  11.9 MiB/s | 340.5 KiB |  00m00s
[142/154] gdb-minimal-0:15.2-3.fc42.x86 100% |  42.7 MiB/s |   4.3 MiB |  00m00s
[143/154] libidn2-0:2.3.7-2.fc41.x86_64 100% |   6.1 MiB/s | 112.6 KiB |  00m00s
[144/154] libnghttp2-0:1.64.0-1.fc42.x8 100% |   4.4 MiB/s |  77.4 KiB |  00m00s
[145/154] libpsl-0:0.21.5-4.fc41.x86_64 100% |   3.3 MiB/s |  64.1 KiB |  00m00s
[146/154] libssh-0:0.11.1-1.fc42.x86_64 100% |   9.1 MiB/s | 231.9 KiB |  00m00s
[147/154] openldap-0:2.6.8-5.fc41.x86_6 100% |  13.1 MiB/s | 255.6 KiB |  00m00s
[148/154] forge-srpm-macros-0:0.4.0-1.f 100% |  19.3 KiB/s |  19.8 KiB |  00m01s
[149/154] libevent-0:2.1.12-14.fc41.x86 100% |  12.0 MiB/s | 257.5 KiB |  00m00s
[150/154] libtool-ltdl-0:2.4.7-12.fc41. 100% |   1.8 MiB/s |  35.6 KiB |  00m00s
[151/154] cyrus-sasl-lib-0:2.1.28-27.fc 100% |  15.2 MiB/s | 794.9 KiB |  00m00s
[152/154] libssh-config-0:0.11.1-1.fc42 100% | 446.9 KiB/s |   9.4 KiB |  00m00s
[153/154] libunistring-0:1.1-8.fc41.x86 100% |  14.4 MiB/s | 544.8 KiB |  00m00s
[154/154] publicsuffix-list-dafsa-0:202 100% |   3.2 MiB/s |  58.3 KiB |  00m00s
--------------------------------------------------------------------------------
[154/154] Total                         100% |  29.9 MiB/s |  52.1 MiB |  00m02s
Running transaction
[  1/156] Verify package files          100% | 789.0   B/s | 154.0   B |  00m00s
>>> Running pre-transaction scriptlet: filesystem-0:3.18-29.fc42.x86_64
>>> Finished pre-transaction scriptlet: filesystem-0:3.18-29.fc42.x86_64
>>> [RPM] /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root/var/cache/d
[  2/156] Prepare transaction           100% |   1.7 KiB/s | 154.0   B |  00m00s
[  3/156] Installing libgcc-0:14.2.1-6. 100% | 132.9 MiB/s | 272.3 KiB |  00m00s
[  4/156] Installing publicsuffix-list- 100% |  66.7 MiB/s |  68.3 KiB |  00m00s
[  5/156] Installing libssh-config-0:0. 100% |   0.0   B/s | 816.0   B |  00m00s
[  6/156] Installing fedora-release-ide 100% |   0.0   B/s | 976.0   B |  00m00s
[  7/156] Installing fedora-gpg-keys-0: 100% |  18.7 MiB/s | 172.2 KiB |  00m00s
[  8/156] Installing fedora-repos-rawhi 100% |   0.0   B/s |   2.4 KiB |  00m00s
[  9/156] Installing fedora-repos-0:42- 100% |   0.0   B/s |   5.7 KiB |  00m00s
[ 10/156] Installing fedora-release-com 100% |  11.7 MiB/s |  24.0 KiB |  00m00s
[ 11/156] Installing fedora-release-0:4 100% |   0.0   B/s | 124.0   B |  00m00s
[ 12/156] Installing setup-0:2.15.0-5.f 100% |  50.6 MiB/s | 726.1 KiB |  00m00s
>>> [RPM] /etc/hosts created as /etc/hosts.rpmnew
[ 13/156] Installing filesystem-0:3.18- 100% |   1.6 MiB/s | 212.6 KiB |  00m00s
[ 14/156] Installing basesystem-0:11-21 100% |   0.0   B/s | 124.0   B |  00m00s
[ 15/156] Installing pcre2-syntax-0:10. 100% | 124.1 MiB/s | 254.1 KiB |  00m00s
[ 16/156] Installing coreutils-common-0 100% | 233.1 MiB/s |  11.2 MiB |  00m00s
[ 17/156] Installing ncurses-base-0:6.5 100% |  38.2 MiB/s | 351.7 KiB |  00m00s
[ 18/156] Installing glibc-minimal-lang 100% |   0.0   B/s | 124.0   B |  00m00s
[ 19/156] Installing ncurses-libs-0:6.5 100% | 137.0 MiB/s | 981.8 KiB |  00m00s
[ 20/156] Installing glibc-0:2.40.9000- 100% | 216.5 MiB/s |   6.7 MiB |  00m00s
[ 21/156] Installing bash-0:5.2.37-1.fc 100% | 281.7 MiB/s |   8.2 MiB |  00m00s
[ 22/156] Installing glibc-common-0:2.4 100% | 132.4 MiB/s |   1.1 MiB |  00m00s
[ 23/156] Installing glibc-gconv-extra- 100% | 150.7 MiB/s |   8.1 MiB |  00m00s
[ 24/156] Installing zlib-ng-compat-0:2 100% | 131.7 MiB/s | 134.9 KiB |  00m00s
[ 25/156] Installing xz-libs-1:5.6.3-2. 100% | 214.3 MiB/s | 219.5 KiB |  00m00s
[ 26/156] Installing bzip2-libs-0:1.0.8 100% |  79.9 MiB/s |  81.8 KiB |  00m00s
[ 27/156] Installing libuuid-0:2.40.2-8 100% |  41.5 MiB/s |  42.5 KiB |  00m00s
[ 28/156] Installing readline-0:8.2-11. 100% | 241.8 MiB/s | 495.3 KiB |  00m00s
[ 29/156] Installing popt-0:1.19-7.fc41 100% |  35.0 MiB/s | 143.5 KiB |  00m00s
[ 30/156] Installing libblkid-0:2.40.2- 100% | 128.7 MiB/s | 263.6 KiB |  00m00s
[ 31/156] Installing libattr-0:2.5.2-4. 100% |  28.8 MiB/s |  29.5 KiB |  00m00s
[ 32/156] Installing libacl-0:2.3.2-2.f 100% |  39.8 MiB/s |  40.7 KiB |  00m00s
[ 33/156] Installing libxcrypt-0:4.4.36 100% | 132.0 MiB/s | 270.4 KiB |  00m00s
[ 34/156] Installing libzstd-0:1.5.6-2. 100% | 259.5 MiB/s | 797.2 KiB |  00m00s
[ 35/156] Installing elfutils-libelf-0: 100% | 233.3 MiB/s |   1.2 MiB |  00m00s
[ 36/156] Installing gmp-1:6.3.0-2.fc41 100% | 198.6 MiB/s | 813.7 KiB |  00m00s
[ 37/156] Installing libstdc++-0:14.2.1 100% | 250.9 MiB/s |   2.8 MiB |  00m00s
[ 38/156] Installing libeconf-0:0.7.4-3 100% |  65.8 MiB/s |  67.4 KiB |  00m00s
[ 39/156] Installing gdbm-libs-1:1.23-7 100% | 120.7 MiB/s | 123.6 KiB |  00m00s
[ 40/156] Installing mpfr-0:4.2.1-5.fc4 100% | 203.5 MiB/s | 833.7 KiB |  00m00s
[ 41/156] Installing gawk-0:5.3.0-4.fc4 100% | 173.2 MiB/s |   1.7 MiB |  00m00s
[ 42/156] Installing dwz-0:0.15-8.fc42. 100% | 146.8 MiB/s | 300.6 KiB |  00m00s
[ 43/156] Installing unzip-0:6.0-64.fc4 100% | 127.0 MiB/s | 390.3 KiB |  00m00s
[ 44/156] Installing file-libs-0:5.45-7 100% | 496.7 MiB/s |   9.9 MiB |  00m00s
[ 45/156] Installing file-0:5.45-7.fc41 100% |   6.4 MiB/s | 105.0 KiB |  00m00s
[ 46/156] Installing crypto-policies-0: 100% |  14.5 MiB/s | 163.3 KiB |  00m00s
[ 47/156] Installing libcap-ng-0:0.8.5- 100% |  69.4 MiB/s |  71.0 KiB |  00m00s
[ 48/156] Installing audit-libs-0:4.0.2 100% | 108.5 MiB/s | 333.4 KiB |  00m00s
[ 49/156] Installing pam-libs-0:1.7.0-2 100% |  63.4 MiB/s | 129.9 KiB |  00m00s
[ 50/156] Installing libcap-0:2.71-1.fc 100% |  70.3 MiB/s | 215.8 KiB |  00m00s
[ 51/156] Installing systemd-libs-0:257 100% | 227.8 MiB/s |   2.3 MiB |  00m00s
[ 52/156] Installing libsmartcols-0:2.4 100% | 177.1 MiB/s | 181.4 KiB |  00m00s
[ 53/156] Installing libcom_err-0:1.47. 100% |  66.7 MiB/s |  68.3 KiB |  00m00s
[ 54/156] Installing libsepol-0:3.7-3.f 100% | 266.6 MiB/s | 819.0 KiB |  00m00s
[ 55/156] Installing pcre2-0:10.44-1.fc 100% | 213.2 MiB/s | 654.9 KiB |  00m00s
[ 56/156] Installing libselinux-0:3.7-6 100% |  89.0 MiB/s | 182.3 KiB |  00m00s
[ 57/156] Installing sed-0:4.9-3.fc41.x 100% | 121.3 MiB/s | 869.7 KiB |  00m00s
[ 58/156] Installing findutils-1:4.10.0 100% | 185.8 MiB/s |   1.9 MiB |  00m00s
[ 59/156] Installing grep-0:3.11-9.fc41 100% | 111.5 MiB/s |   1.0 MiB |  00m00s
[ 60/156] Installing xz-1:5.6.3-2.fc42. 100% | 123.7 MiB/s |   1.2 MiB |  00m00s
[ 61/156] Installing libmount-0:2.40.2- 100% | 174.3 MiB/s | 356.9 KiB |  00m00s
[ 62/156] Installing lz4-libs-0:1.10.0- 100% | 143.1 MiB/s | 146.6 KiB |  00m00s
[ 63/156] Installing libffi-0:3.4.6-3.f 100% |  85.7 MiB/s |  87.8 KiB |  00m00s
[ 64/156] Installing alternatives-0:1.3 100% |  66.3 MiB/s |  67.9 KiB |  00m00s
[ 65/156] Installing lua-libs-0:5.4.7-1 100% | 139.7 MiB/s | 286.2 KiB |  00m00s
[ 66/156] Installing libtasn1-0:4.19.0- 100% |  86.7 MiB/s | 177.5 KiB |  00m00s
[ 67/156] Installing p11-kit-0:0.25.5-4 100% | 147.7 MiB/s |   2.2 MiB |  00m00s
[ 68/156] Installing libunistring-0:1.1 100% | 247.2 MiB/s |   1.7 MiB |  00m00s
[ 69/156] Installing libidn2-0:2.3.7-2. 100% |  65.4 MiB/s | 335.1 KiB |  00m00s
[ 70/156] Installing libpsl-0:0.21.5-4. 100% |  79.7 MiB/s |  81.7 KiB |  00m00s
[ 71/156] Installing p11-kit-trust-0:0. 100% |  24.8 MiB/s | 405.5 KiB |  00m00s
[ 72/156] Installing openssl-libs-1:3.2 100% | 279.6 MiB/s |   7.8 MiB |  00m00s
[ 73/156] Installing coreutils-0:9.5-11 100% | 142.1 MiB/s |   5.4 MiB |  00m00s
[ 74/156] Installing ca-certificates-0: 100% |   1.2 MiB/s |   2.4 MiB |  00m02s
[ 75/156] Installing gzip-0:1.13-2.fc41 100% |  77.1 MiB/s | 394.6 KiB |  00m00s
[ 76/156] Installing authselect-libs-0: 100% |  68.1 MiB/s | 837.2 KiB |  00m00s
[ 77/156] Installing cracklib-0:2.9.11- 100% |  34.9 MiB/s | 250.3 KiB |  00m00s
[ 78/156] Installing libpwquality-0:1.4 100% |  52.5 MiB/s | 430.1 KiB |  00m00s
[ 79/156] Installing rpm-sequoia-0:1.7. 100% | 263.0 MiB/s |   2.4 MiB |  00m00s
[ 80/156] Installing libevent-0:2.1.12- 100% | 219.6 MiB/s | 899.5 KiB |  00m00s
[ 81/156] Installing zstd-0:1.5.6-2.fc4 100% | 241.6 MiB/s |   1.7 MiB |  00m00s
[ 82/156] Installing util-linux-core-0: 100% | 138.9 MiB/s |   1.5 MiB |  00m00s
[ 83/156] Installing tar-2:1.35-4.fc41. 100% | 227.6 MiB/s |   3.0 MiB |  00m00s
[ 84/156] Installing libsemanage-0:3.7- 100% |  97.6 MiB/s | 299.8 KiB |  00m00s
[ 85/156] Installing shadow-utils-2:4.1 100% | 120.4 MiB/s |   4.1 MiB |  00m00s
[ 86/156] Installing zip-0:3.0-41.fc41. 100% | 172.6 MiB/s | 707.1 KiB |  00m00s
[ 87/156] Installing gdbm-1:1.23-7.fc41 100% | 113.7 MiB/s | 465.8 KiB |  00m00s
[ 88/156] Installing cyrus-sasl-lib-0:2 100% | 256.2 MiB/s |   2.3 MiB |  00m00s
[ 89/156] Installing libfdisk-0:2.40.2- 100% | 177.7 MiB/s | 364.0 KiB |  00m00s
[ 90/156] Installing bzip2-0:1.0.8-19.f 100% |  48.9 MiB/s | 100.2 KiB |  00m00s
[ 91/156] Installing libxml2-0:2.12.8-2 100% | 244.6 MiB/s |   1.7 MiB |  00m00s
[ 92/156] Installing libarchive-0:3.7.7 100% | 228.1 MiB/s | 934.2 KiB |  00m00s
[ 93/156] Installing add-determinism-0: 100% | 270.1 MiB/s |   2.4 MiB |  00m00s
[ 94/156] Installing build-reproducibil 100% |   0.0   B/s |   1.0 KiB |  00m00s
[ 95/156] Installing sqlite-libs-0:3.47 100% | 242.2 MiB/s |   1.5 MiB |  00m00s
[ 96/156] Installing rpm-libs-0:4.20.0- 100% | 236.9 MiB/s | 727.7 KiB |  00m00s
[ 97/156] Installing ed-0:1.20.2-2.fc41 100% |  72.8 MiB/s | 149.2 KiB |  00m00s
[ 98/156] Installing patch-0:2.7.6-25.f 100% | 131.0 MiB/s | 268.2 KiB |  00m00s
[ 99/156] Installing elfutils-default-y 100% | 185.7 KiB/s |   2.0 KiB |  00m00s
[100/156] Installing elfutils-libs-0:0. 100% | 164.7 MiB/s | 674.7 KiB |  00m00s
[101/156] Installing cpio-0:2.15-2.fc41 100% | 137.5 MiB/s |   1.1 MiB |  00m00s
[102/156] Installing diffutils-0:3.10-8 100% | 176.7 MiB/s |   1.6 MiB |  00m00s
[103/156] Installing libpkgconf-0:2.3.0 100% |  77.5 MiB/s |  79.3 KiB |  00m00s
[104/156] Installing pkgconf-0:2.3.0-1. 100% |  44.5 MiB/s |  91.1 KiB |  00m00s
[105/156] Installing jansson-0:2.14-1.f 100% |  88.5 MiB/s |  90.7 KiB |  00m00s
[106/156] Installing keyutils-libs-0:1. 100% |  54.5 MiB/s |  55.8 KiB |  00m00s
[107/156] Installing libverto-0:0.3.2-9 100% |  30.5 MiB/s |  31.3 KiB |  00m00s
[108/156] Installing krb5-libs-0:1.21.3 100% | 192.0 MiB/s |   2.3 MiB |  00m00s
[109/156] Installing libtirpc-0:1.3.6-1 100% | 202.5 MiB/s | 207.3 KiB |  00m00s
[110/156] Installing libnsl2-0:2.0.1-2. 100% |  57.7 MiB/s |  59.1 KiB |  00m00s
[111/156] Installing pam-0:1.7.0-2.fc42 100% |  71.2 MiB/s |   1.7 MiB |  00m00s
[112/156] Installing libssh-0:0.11.1-1. 100% | 186.1 MiB/s | 571.7 KiB |  00m00s
[113/156] Installing libgomp-0:14.2.1-6 100% | 254.5 MiB/s | 521.2 KiB |  00m00s
[114/156] Installing rpm-build-libs-0:4 100% | 202.6 MiB/s | 207.5 KiB |  00m00s
[115/156] Installing json-c-0:0.18-1.fc 100% |  82.6 MiB/s |  84.6 KiB |  00m00s
[116/156] Installing xxhash-libs-0:0.8. 100% |  87.7 MiB/s |  89.8 KiB |  00m00s
[117/156] Installing libbrotli-0:1.1.0- 100% | 205.0 MiB/s | 839.9 KiB |  00m00s
[118/156] Installing libnghttp2-0:1.64. 100% |  85.7 MiB/s | 175.6 KiB |  00m00s
[119/156] Installing libtool-ltdl-0:2.4 100% |  65.7 MiB/s |  67.3 KiB |  00m00s
[120/156] Installing openldap-0:2.6.8-5 100% | 158.2 MiB/s | 648.0 KiB |  00m00s
[121/156] Installing libcurl-0:8.10.1-2 100% | 205.0 MiB/s | 839.5 KiB |  00m00s
[122/156] Installing elfutils-debuginfo 100% |  40.3 MiB/s |  82.6 KiB |  00m00s
[123/156] Installing binutils-0:2.43.50 100% | 262.4 MiB/s |  25.5 MiB |  00m00s
[124/156] Installing elfutils-0:0.192-6 100% | 220.4 MiB/s |   2.6 MiB |  00m00s
[125/156] Installing gdb-minimal-0:15.2 100% | 295.3 MiB/s |  13.0 MiB |  00m00s
[126/156] Installing debugedit-0:5.1-1. 100% |  95.4 MiB/s | 195.4 KiB |  00m00s
[127/156] Installing curl-0:8.10.1-2.fc 100% |  22.3 MiB/s | 455.8 KiB |  00m00s
[128/156] Installing rpm-0:4.20.0-1.fc4 100% |  89.5 MiB/s |   2.5 MiB |  00m00s
[129/156] Installing efi-srpm-macros-0: 100% |  40.2 MiB/s |  41.2 KiB |  00m00s
[130/156] Installing lua-srpm-macros-0: 100% |   1.9 MiB/s |   1.9 KiB |  00m00s
[131/156] Installing zig-srpm-macros-0: 100% |   0.0   B/s |   1.7 KiB |  00m00s
[132/156] Installing pkgconf-m4-0:2.3.0 100% |   0.0   B/s |  14.8 KiB |  00m00s
[133/156] Installing pkgconf-pkg-config 100% |   1.7 MiB/s |   1.8 KiB |  00m00s
[134/156] Installing rust-srpm-macros-0 100% |   0.0   B/s |   5.6 KiB |  00m00s
[135/156] Installing qt6-srpm-macros-0: 100% |   0.0   B/s | 732.0   B |  00m00s
[136/156] Installing qt5-srpm-macros-0: 100% |   0.0   B/s | 776.0   B |  00m00s
[137/156] Installing perl-srpm-macros-0 100% |   0.0   B/s |   1.1 KiB |  00m00s
[138/156] Installing package-notes-srpm 100% |   0.0   B/s |   2.0 KiB |  00m00s
[139/156] Installing openblas-srpm-macr 100% |   0.0   B/s | 392.0   B |  00m00s
[140/156] Installing ocaml-srpm-macros- 100% |   0.0   B/s |   2.2 KiB |  00m00s
[141/156] Installing kernel-srpm-macros 100% |   0.0   B/s |   2.3 KiB |  00m00s
[142/156] Installing gnat-srpm-macros-0 100% |   0.0   B/s |   1.3 KiB |  00m00s
[143/156] Installing ghc-srpm-macros-0: 100% |   0.0   B/s |   1.0 KiB |  00m00s
[144/156] Installing fpc-srpm-macros-0: 100% |   0.0   B/s | 420.0   B |  00m00s
[145/156] Installing ansible-srpm-macro 100% |   0.0   B/s |  36.2 KiB |  00m00s
[146/156] Installing fonts-srpm-macros- 100% |  55.7 MiB/s |  57.0 KiB |  00m00s
[147/156] Installing forge-srpm-macros- 100% |  39.3 MiB/s |  40.3 KiB |  00m00s
[148/156] Installing go-srpm-macros-0:3 100% |  60.5 MiB/s |  62.0 KiB |  00m00s
[149/156] Installing python-srpm-macros 100% |  50.9 MiB/s |  52.2 KiB |  00m00s
[150/156] Installing redhat-rpm-config- 100% |  62.9 MiB/s | 193.2 KiB |  00m00s
[151/156] Installing rpm-build-0:4.20.0 100% |  49.5 MiB/s | 202.9 KiB |  00m00s
[152/156] Installing pyproject-srpm-mac 100% |   1.2 MiB/s |   2.5 KiB |  00m00s
[153/156] Installing util-linux-0:2.40. 100% |  80.8 MiB/s |   3.7 MiB |  00m00s
[154/156] Installing authselect-0:1.5.0 100% |  52.7 MiB/s | 161.9 KiB |  00m00s
[155/156] Installing which-0:2.21-42.fc 100% |  40.2 MiB/s |  82.4 KiB |  00m00s
[156/156] Installing info-0:7.1.1-2.fc4 100% | 137.9 KiB/s | 362.2 KiB |  00m03s
Warning: skipped PGP checks for 154 packages from repositories: copr_base, http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch
Complete!
Finish: installing minimal buildroot with dnf5
Start: creating root cache
Finish: creating root cache
Finish: chroot init
INFO: Installed packages:
INFO: add-determinism-0.4.3-1.fc42.x86_64
alternatives-1.30-1.fc41.x86_64
ansible-srpm-macros-1-16.fc41.noarch
audit-libs-4.0.2-1.fc41.x86_64
authselect-1.5.0-8.fc42.x86_64
authselect-libs-1.5.0-8.fc42.x86_64
basesystem-11-21.fc41.noarch
bash-5.2.37-1.fc42.x86_64
binutils-2.43.50-8.fc42.x86_64
build-reproducibility-srpm-macros-0.4.3-1.fc42.noarch
bzip2-1.0.8-19.fc41.x86_64
bzip2-libs-1.0.8-19.fc41.x86_64
ca-certificates-2024.2.69_v8.0.401-2.fc42.noarch
coreutils-9.5-11.fc42.x86_64
coreutils-common-9.5-11.fc42.x86_64
cpio-2.15-2.fc41.x86_64
cracklib-2.9.11-6.fc41.x86_64
crypto-policies-20241106-1.git35892de.fc42.noarch
curl-8.10.1-2.fc42.x86_64
cyrus-sasl-lib-2.1.28-27.fc41.x86_64
debugedit-5.1-1.fc42.x86_64
diffutils-3.10-8.fc41.x86_64
dwz-0.15-8.fc42.x86_64
ed-1.20.2-2.fc41.x86_64
efi-srpm-macros-5-12.fc41.noarch
elfutils-0.192-6.fc42.x86_64
elfutils-debuginfod-client-0.192-6.fc42.x86_64
elfutils-default-yama-scope-0.192-6.fc42.noarch
elfutils-libelf-0.192-6.fc42.x86_64
elfutils-libs-0.192-6.fc42.x86_64
fedora-gpg-keys-42-0.3.noarch
fedora-release-42-0.8.noarch
fedora-release-common-42-0.8.noarch
fedora-release-identity-basic-42-0.8.noarch
fedora-repos-42-0.3.noarch
fedora-repos-rawhide-42-0.3.noarch
file-5.45-7.fc41.x86_64
file-libs-5.45-7.fc41.x86_64
filesystem-3.18-29.fc42.x86_64
findutils-4.10.0-4.fc41.x86_64
fonts-srpm-macros-2.0.5-17.fc41.noarch
forge-srpm-macros-0.4.0-1.fc42.noarch
fpc-srpm-macros-1.3-13.fc41.noarch
gawk-5.3.0-4.fc41.x86_64
gdb-minimal-15.2-3.fc42.x86_64
gdbm-1.23-7.fc41.x86_64
gdbm-libs-1.23-7.fc41.x86_64
ghc-srpm-macros-1.9.2-1.fc42.noarch
glibc-2.40.9000-18.fc42.x86_64
glibc-common-2.40.9000-18.fc42.x86_64
glibc-gconv-extra-2.40.9000-18.fc42.x86_64
glibc-minimal-langpack-2.40.9000-18.fc42.x86_64
gmp-6.3.0-2.fc41.x86_64
gnat-srpm-macros-6-6.fc41.noarch
go-srpm-macros-3.6.0-3.fc41.noarch
grep-3.11-9.fc41.x86_64
gzip-1.13-2.fc41.x86_64
info-7.1.1-2.fc42.x86_64
jansson-2.14-1.fc42.x86_64
json-c-0.18-1.fc42.x86_64
kernel-srpm-macros-1.0-24.fc41.noarch
keyutils-libs-1.6.3-4.fc41.x86_64
krb5-libs-1.21.3-3.fc42.x86_64
libacl-2.3.2-2.fc41.x86_64
libarchive-3.7.7-1.fc42.x86_64
libattr-2.5.2-4.fc41.x86_64
libblkid-2.40.2-8.fc42.x86_64
libbrotli-1.1.0-5.fc41.x86_64
libcap-2.71-1.fc42.x86_64
libcap-ng-0.8.5-3.fc41.x86_64
libcom_err-1.47.1-6.fc42.x86_64
libcurl-8.10.1-2.fc42.x86_64
libeconf-0.7.4-3.fc42.x86_64
libevent-2.1.12-14.fc41.x86_64
libfdisk-2.40.2-8.fc42.x86_64
libffi-3.4.6-3.fc42.x86_64
libgcc-14.2.1-6.fc42.x86_64
libgomp-14.2.1-6.fc42.x86_64
libidn2-2.3.7-2.fc41.x86_64
libmount-2.40.2-8.fc42.x86_64
libnghttp2-1.64.0-1.fc42.x86_64
libnsl2-2.0.1-2.fc41.x86_64
libpkgconf-2.3.0-1.fc42.x86_64
libpsl-0.21.5-4.fc41.x86_64
libpwquality-1.4.5-11.fc41.x86_64
libselinux-3.7-6.fc42.x86_64
libsemanage-3.7-3.fc42.x86_64
libsepol-3.7-3.fc42.x86_64
libsmartcols-2.40.2-8.fc42.x86_64
libssh-0.11.1-1.fc42.x86_64
libssh-config-0.11.1-1.fc42.noarch
libstdc++-14.2.1-6.fc42.x86_64
libtasn1-4.19.0-9.fc41.x86_64
libtirpc-1.3.6-1.fc42.x86_64
libtool-ltdl-2.4.7-12.fc41.x86_64
libunistring-1.1-8.fc41.x86_64
libuuid-2.40.2-8.fc42.x86_64
libverto-0.3.2-9.fc41.x86_64
libxcrypt-4.4.36-10.fc42.x86_64
libxml2-2.12.8-2.fc41.x86_64
libzstd-1.5.6-2.fc41.x86_64
lua-libs-5.4.7-1.fc42.x86_64
lua-srpm-macros-1-14.fc41.noarch
lz4-libs-1.10.0-1.fc41.x86_64
mpfr-4.2.1-5.fc41.x86_64
ncurses-base-6.5-2.20240629.fc41.noarch
ncurses-libs-6.5-2.20240629.fc41.x86_64
ocaml-srpm-macros-10-3.fc41.noarch
openblas-srpm-macros-2-18.fc41.noarch
openldap-2.6.8-5.fc41.x86_64
openssl-libs-3.2.2-8.fc42.x86_64
p11-kit-0.25.5-4.fc42.x86_64
p11-kit-trust-0.25.5-4.fc42.x86_64
package-notes-srpm-macros-0.5-12.fc41.noarch
pam-1.7.0-2.fc42.x86_64
pam-libs-1.7.0-2.fc42.x86_64
patch-2.7.6-25.fc41.x86_64
pcre2-10.44-1.fc41.1.x86_64
pcre2-syntax-10.44-1.fc41.1.noarch
perl-srpm-macros-1-56.fc41.noarch
pkgconf-2.3.0-1.fc42.x86_64
pkgconf-m4-2.3.0-1.fc42.noarch
pkgconf-pkg-config-2.3.0-1.fc42.x86_64
popt-1.19-7.fc41.x86_64
publicsuffix-list-dafsa-20240107-4.fc41.noarch
pyproject-srpm-macros-1.16.2-1.fc42.noarch
python-srpm-macros-3.13-3.fc41.noarch
qt5-srpm-macros-5.15.15-1.fc42.noarch
qt6-srpm-macros-6.8.0-1.fc42.noarch
readline-8.2-11.fc42.x86_64
redhat-rpm-config-296-1.fc42.noarch
rpm-4.20.0-1.fc42.x86_64
rpm-build-4.20.0-1.fc42.x86_64
rpm-build-libs-4.20.0-1.fc42.x86_64
rpm-libs-4.20.0-1.fc42.x86_64
rpm-sequoia-1.7.0-2.fc41.x86_64
rust-srpm-macros-26.3-3.fc42.noarch
sed-4.9-3.fc41.x86_64
setup-2.15.0-5.fc41.noarch
shadow-utils-4.16.0-7.fc42.x86_64
sqlite-libs-3.47.0-1.fc42.x86_64
systemd-libs-257~rc2-2.fc42.x86_64
tar-1.35-4.fc41.x86_64
unzip-6.0-64.fc41.x86_64
util-linux-2.40.2-8.fc42.x86_64
util-linux-core-2.40.2-8.fc42.x86_64
which-2.21-42.fc41.x86_64
xxhash-libs-0.8.2-4.fc42.x86_64
xz-5.6.3-2.fc42.x86_64
xz-libs-5.6.3-2.fc42.x86_64
zig-srpm-macros-1-3.fc41.noarch
zip-3.0-41.fc41.x86_64
zlib-ng-compat-2.2.2-1.fc42.x86_64
zstd-1.5.6-2.fc41.x86_64
Start: buildsrpm
Start: rpmbuild -bs
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1731196800
Wrote: /builddir/build/SRPMS/yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Finish: rpmbuild -bs
INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan
INFO: /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root/var/log/dnf5.log
INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz
/bin/tar: Removing leading `/' from member names
Finish: buildsrpm
INFO: Done(/var/lib/copr-rpmbuild/workspace/workdir-e2gvuznv/yosys/yosys.spec) Config(child) 0 minutes 37 seconds
INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results
INFO: Cleaning up build root ('cleanup_on_success=True')
Start: clean chroot
INFO: unmounting tmpfs.
Finish: clean chroot
INFO: Start(/var/lib/copr-rpmbuild/results/yosys-0.47-1.20241110gitf20f913.fc42.src.rpm)  Config(fedora-rawhide-x86_64)
Start(bootstrap): chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1732107006.500093/root.
INFO: reusing tmpfs at /var/lib/mock/fedora-rawhide-x86_64-bootstrap-1732107006.500093/root.
INFO: calling preinit hooks
INFO: enabled root cache
INFO: enabled package manager cache
Start(bootstrap): cleaning package manager metadata
Finish(bootstrap): cleaning package manager metadata
Finish(bootstrap): chroot init
Start: chroot init
INFO: mounting tmpfs at /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root.
INFO: calling preinit hooks
INFO: enabled root cache
Start: unpacking root cache
Finish: unpacking root cache
INFO: enabled package manager cache
Start: cleaning package manager metadata
Finish: cleaning package manager metadata
INFO: enabled HW Info plugin
INFO: Buildroot is handled by package management downloaded with a bootstrap image:
  rpm-4.20.0-1.fc42.x86_64
  rpm-sequoia-1.7.0-2.fc41.x86_64
  dnf5-5.2.7.0-1.fc42.x86_64
  dnf5-plugins-5.2.7.0-1.fc42.x86_64
Finish: chroot init
Start: build phase for yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Start: build setup for yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1731196800
Wrote: /builddir/build/SRPMS/yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Updating and loading repositories:
 fedora                                 100% | 810.1 KiB/s |  28.4 KiB |  00m00s
 Copr repository                        100% |  51.2 KiB/s |   1.5 KiB |  00m00s
 Additional repo http_kojipkgs_fedorapr 100% |  73.6 KiB/s |   3.8 KiB |  00m00s
 fedora                                 100% | 543.1 KiB/s | 477.9 KiB |  00m01s
Repositories loaded.
Package "pkgconf-pkg-config-2.3.0-1.fc42.x86_64" is already installed.

Package                               Arch   Version                         Repository                                                         Size
Installing:
 bison                                x86_64 3.8.2-9.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.5 MiB
 cxxopts-devel                        x86_64 3.2.1-2.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  73.6 KiB
 flex                                 x86_64 2.6.4-18.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 805.4 KiB
 gcc-c++                              x86_64 14.2.1-6.fc42                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  38.1 MiB
 graphviz                             x86_64 12.2.0-1.fc42                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  20.8 MiB
 gtkwave                              x86_64 3.3.121-1.fc42                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   4.0 MiB
 iverilog                             x86_64 12.0-8.fc41                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   6.5 MiB
 latexmk                              noarch 4.85-2.fc41                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 991.3 KiB
 libfaketime                          x86_64 0.9.10-10.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 477.0 KiB
 libffi-devel                         x86_64 3.4.6-3.fc42                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  33.1 KiB
 make                                 x86_64 1:4.4.1-9.fc42                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.8 MiB
 pdf2svg                              x86_64 0.2.3-21.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  33.5 KiB
 python3                              x86_64 3.13.0-1.fc42                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  31.8 KiB
 python3-click                        noarch 8.1.7-6.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.1 MiB
 python3-devel                        x86_64 3.13.0-1.fc42                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.8 MiB
 python3-furo                         noarch 2024.08.06-1.fc42               copr_base                                                     358.9 KiB
 python3-sphinx-latex                 noarch 1:8.1.3-1.fc42                  copr_base                                                       0.0   B
 python3-sphinxcontrib-bibtex         noarch 2.6.3-1.fc42                    copr_base                                                     321.3 KiB
 readline-devel                       x86_64 8.2-11.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 553.0 KiB
 rsync                                x86_64 3.3.0-4.fc42                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 776.5 KiB
 tcl-devel                            x86_64 1:8.6.15-2.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 793.3 KiB
 texlive-comment                      noarch 11:svn41927-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  22.3 KiB
 texlive-pgfplots                     noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.4 MiB
 texlive-standalone                   noarch 11:svn64677-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  82.0 KiB
 txt2man                              noarch 1.7.1-7.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  47.1 KiB
 yosyshq-abc                          x86_64 0.46-1.20241011gitcac8f99.fc42  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  28.9 KiB
Installing dependencies:
 Judy                                 x86_64 1.0.5-37.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 368.6 KiB
 abattis-cantarell-vf-fonts           noarch 0.301-13.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 192.7 KiB
 adobe-mappings-cmap                  noarch 20231115-1.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  15.2 MiB
 adobe-mappings-cmap-deprecated       noarch 20231115-1.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 582.1 KiB
 adobe-mappings-pdf                   noarch 20190401-8.fc41                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   4.4 MiB
 adwaita-cursor-theme                 noarch 47.0-1.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  10.0 MiB
 adwaita-icon-theme                   noarch 47.0-1.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.2 MiB
 adwaita-icon-theme-legacy            noarch 46.2-2.fc41                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.1 MiB
 annobin-docs                         noarch 12.77-1.fc42                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  98.4 KiB
 annobin-plugin-gcc                   x86_64 12.77-1.fc42                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 991.3 KiB
 at-spi2-atk                          x86_64 2.54.0-1.fc42                   copr_base                                                     277.0 KiB
 at-spi2-core                         x86_64 2.54.0-1.fc42                   copr_base                                                       1.5 MiB
 atk                                  x86_64 2.54.0-1.fc42                   copr_base                                                     250.0 KiB
 avahi-glib                           x86_64 0.8-30.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  23.6 KiB
 avahi-libs                           x86_64 0.8-30.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 174.2 KiB
 biber                                noarch 2.19-6.fc41                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.3 MiB
 cairo                                x86_64 1.18.0-4.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 cairo-gobject                        x86_64 1.18.0-4.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  35.2 KiB
 cmake-filesystem                     x86_64 3.31.0-1.fc42                   copr_base                                                       0.0   B
 colord-libs                          x86_64 1.4.7-5.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 847.0 KiB
 cpp                                  x86_64 14.2.1-6.fc42                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  35.0 MiB
 cups-filesystem                      noarch 1:2.4.11-3.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   0.0   B
 cups-libs                            x86_64 1:2.4.11-3.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 623.6 KiB
 dbus                                 x86_64 1:1.14.10-4.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   0.0   B
 dbus-broker                          x86_64 36-4.fc41                       http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 382.8 KiB
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 texlive-pst-tree                     noarch 11:svn60421-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  42.6 KiB
 texlive-pstricks                     noarch 11:svn65346-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 468.9 KiB
 texlive-pstricks-add                 noarch 11:svn65067-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 103.4 KiB
 texlive-pxfonts                      noarch 11:svn15878.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 823.0 KiB
 texlive-ragged2e                     noarch 11:svn66152-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 731.9 KiB
 texlive-refcount                     noarch 11:svn53164-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 348.0 KiB
 texlive-rerunfilecheck               noarch 11:svn63869-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 361.8 KiB
 texlive-rsfs                         noarch 11:svn15878.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  97.8 KiB
 texlive-sauerj                       noarch 11:svn15878.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  27.0 KiB
 texlive-setspace                     noarch 11:svn65206-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  22.0 KiB
 texlive-showexpl                     noarch 11:svn57414-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  21.8 KiB
 texlive-stringenc                    noarch 11:svn52982-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.0 MiB
 texlive-subfig                       noarch 11:svn15878.1.3-74.fc42         http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  36.6 KiB
 texlive-svn-prov                     noarch 11:svn64967-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  15.6 KiB
 texlive-symbol                       noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  78.3 KiB
 texlive-tabulary                     noarch 11:svn34368.0.10-74.fc42        http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  22.3 KiB
 texlive-tex                          x86_64 11:svn66186-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 389.4 KiB
 texlive-tex-gyre                     noarch 11:svn65956-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  24.2 MiB
 texlive-tex-gyre-math                noarch 11:svn41264-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.7 MiB
 texlive-tex-ini-files                noarch 11:svn40533-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   8.1 KiB
 texlive-texlive-common-doc           noarch 11:svn54176-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 265.5 KiB
 texlive-texlive-en                   noarch 11:svn66572-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   5.9 MiB
 texlive-texlive-msg-translations     noarch 11:svn66593-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.4 MiB
 texlive-texlive-scripts              noarch 11:svn66584-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 337.2 KiB
 texlive-texlive.infra                noarch 11:svn66512-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.0 MiB
 texlive-times                        noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 992.2 KiB
 texlive-tipa                         noarch 11:svn29349.1.3-74.fc42         http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.7 MiB
 texlive-titlesec                     noarch 11:svn59845-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  97.8 KiB
 texlive-tools                        noarch 11:svn64892-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 403.2 KiB
 texlive-txfonts                      noarch 11:svn15878.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.5 MiB
 texlive-ucharcat                     noarch 11:svn38907-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  10.2 KiB
 texlive-ucs                          noarch 11:svn64114-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.4 MiB
 texlive-underscore                   noarch 11:svn18261.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  19.3 KiB
 texlive-unicode-data                 noarch 11:svn64423-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.1 MiB
 texlive-unicode-math                 noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 517.2 KiB
 texlive-uniquecounter                noarch 11:svn53162-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 312.0 KiB
 texlive-upquote                      noarch 11:svn26059.v1.3-74.fc42        http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  15.1 KiB
 texlive-url                          noarch 11:svn32528.3.4-74.fc42         http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  21.4 KiB
 texlive-utopia                       noarch 11:svn15878.0-74.fc42           http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 540.6 KiB
 texlive-varwidth                     noarch 11:svn24104.0.92-74.fc42        http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  19.5 KiB
 texlive-wasy                         noarch 11:svn53533-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 137.7 KiB
 texlive-wasy-type1                   noarch 11:svn53534-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 332.4 KiB
 texlive-wasysym                      noarch 11:svn54080-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  23.9 KiB
 texlive-wrapfig                      noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  34.5 KiB
 texlive-xcolor                       noarch 11:svn63563-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  79.3 KiB
 texlive-xdvi                         x86_64 11:svn62387-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 743.4 KiB
 texlive-xetex                        x86_64 11:svn66203-86.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.1 MiB
 texlive-xetexconfig                  noarch 11:svn45845-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 305.0   B
 texlive-xifthen                      noarch 11:svn38929-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  14.4 KiB
 texlive-xkeyval                      noarch 11:svn63616-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  69.3 KiB
 texlive-xpatch                       noarch 11:svn54563-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  26.8 KiB
 texlive-xstring                      noarch 11:svn65551-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  56.1 KiB
 texlive-xunicode                     noarch 11:svn30466.0.981-74.fc42       http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 219.6 KiB
 texlive-zapfchan                     noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 178.1 KiB
 texlive-zapfding                     noarch 11:svn61719-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  79.5 KiB
 texlive-zref                         noarch 11:svn62977-74.fc42             http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 816.8 KiB
 tk                                   x86_64 1:8.6.15-1.fc42                 http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   3.6 MiB
 tpm2-tss                             x86_64 4.1.3-3.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.6 MiB
 tzdata                               noarch 2024a-9.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 urw-base35-bookman-fonts             noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.4 MiB
 urw-base35-c059-fonts                noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.4 MiB
 urw-base35-d050000l-fonts            noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  84.3 KiB
 urw-base35-fonts                     noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   5.3 KiB
 urw-base35-fonts-common              noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  37.4 KiB
 urw-base35-gothic-fonts              noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.2 MiB
 urw-base35-nimbus-mono-ps-fonts      noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.0 MiB
 urw-base35-nimbus-roman-fonts        noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.4 MiB
 urw-base35-nimbus-sans-fonts         noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   2.4 MiB
 urw-base35-p052-fonts                noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.5 MiB
 urw-base35-standard-symbols-ps-fonts noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  64.9 KiB
 urw-base35-z003-fonts                noarch 20200910-23.fc41                http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 390.8 KiB
 xdg-utils                            noarch 1.2.1-2.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 346.3 KiB
 xkeyboard-config                     noarch 2.43-1.fc42                     http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   6.6 MiB
 xml-common                           noarch 0.6.3-65.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  78.4 KiB
 xpdf-libs                            x86_64 1:4.05-5.fc41                   http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch   1.7 MiB
 xprop                                x86_64 1.2.7-2.fc41                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  58.8 KiB
 yosyshq-abc-libs                     x86_64 0.46-1.20241011gitcac8f99.fc42  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch  14.4 MiB
 zlib-ng-compat-devel                 x86_64 2.2.2-1.fc42                    http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 106.8 KiB
 zziplib                              x86_64 0.13.74-2.fc41                  http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch 233.7 KiB

Transaction Summary:
 Installing:       736 packages

Total size of inbound packages is 507 MiB. Need to download 507 MiB.
After this operation, 1 GiB extra will be used (install 1 GiB, remove 0 B).
[  1/736] cxxopts-devel-0:3.2.1-2.fc41. 100% | 327.0 KiB/s |  26.8 KiB |  00m00s
[  2/736] flex-0:2.6.4-18.fc41.x86_64   100% |   2.9 MiB/s | 292.5 KiB |  00m00s
[  3/736] bison-0:3.8.2-9.fc41.x86_64   100% |   9.0 MiB/s | 982.3 KiB |  00m00s
[  4/736] graphviz-0:12.2.0-1.fc42.x86_ 100% |  50.7 MiB/s |   4.7 MiB |  00m00s
[  5/736] gtkwave-0:3.3.121-1.fc42.x86_ 100% |  16.5 MiB/s |   2.4 MiB |  00m00s
[  6/736] iverilog-0:12.0-8.fc41.x86_64 100% |  20.0 MiB/s |   2.2 MiB |  00m00s
[  7/736] latexmk-0:4.85-2.fc41.noarch  100% |   7.0 MiB/s | 445.0 KiB |  00m00s
[  8/736] libffi-devel-0:3.4.6-3.fc42.x 100% |   1.7 MiB/s |  28.8 KiB |  00m00s
[  9/736] libfaketime-0:0.9.10-10.fc41. 100% |   2.9 MiB/s | 133.2 KiB |  00m00s
[ 10/736] make-1:4.4.1-9.fc42.x86_64    100% |  16.6 MiB/s | 579.3 KiB |  00m00s
[ 11/736] python3-0:3.13.0-1.fc42.x86_6 100% |   1.6 MiB/s |  27.8 KiB |  00m00s
[ 12/736] pdf2svg-0:0.2.3-21.fc41.x86_6 100% | 523.4 KiB/s |  20.4 KiB |  00m00s
[ 13/736] python3-click-0:8.1.7-6.fc41. 100% |   9.9 MiB/s | 232.2 KiB |  00m00s
[ 14/736] python3-devel-0:3.13.0-1.fc42 100% |  12.0 MiB/s | 357.2 KiB |  00m00s
[ 15/736] python3-furo-0:2024.08.06-1.f 100% |   1.7 MiB/s | 101.3 KiB |  00m00s
[ 16/736] gcc-c++-0:14.2.1-6.fc42.x86_6 100% |  27.2 MiB/s |  14.2 MiB |  00m01s
[ 17/736] readline-devel-0:8.2-11.fc42. 100% |   8.5 MiB/s | 199.2 KiB |  00m00s
[ 18/736] python3-sphinx-latex-1:8.1.3- 100% |  48.4 KiB/s |  11.0 KiB |  00m00s
[ 19/736] rsync-0:3.3.0-4.fc42.x86_64   100% |  14.6 MiB/s | 417.2 KiB |  00m00s
[ 20/736] tcl-devel-1:8.6.15-2.fc42.x86 100% |   7.3 MiB/s | 164.0 KiB |  00m00s
[ 21/736] texlive-comment-11:svn41927-7 100% | 647.9 KiB/s |  17.5 KiB |  00m00s
[ 22/736] texlive-standalone-11:svn6467 100% | 590.7 KiB/s |  27.2 KiB |  00m00s
[ 23/736] texlive-pgfplots-11:svn61719- 100% |   9.3 MiB/s | 578.6 KiB |  00m00s
[ 24/736] python3-sphinxcontrib-bibtex- 100% | 330.7 KiB/s |  92.9 KiB |  00m00s
[ 25/736] yosyshq-abc-0:0.46-1.20241011 100% | 603.3 KiB/s |  19.3 KiB |  00m00s
[ 26/736] txt2man-0:1.7.1-7.fc41.noarch 100% | 721.2 KiB/s |  28.1 KiB |  00m00s
[ 27/736] texlive-adjustbox-11:svn64967 100% | 859.8 KiB/s |  29.2 KiB |  00m00s
[ 28/736] texlive-currfile-11:svn64673- 100% | 988.8 KiB/s |  18.8 KiB |  00m00s
[ 29/736] texlive-filemod-11:svn64967-7 100% | 571.9 KiB/s |  18.9 KiB |  00m00s
[ 30/736] texlive-base-11:20230311-86.f 100% |  25.5 MiB/s |   2.6 MiB |  00m00s
[ 31/736] texlive-gincltex-11:svn64967- 100% | 533.3 KiB/s |  16.5 KiB |  00m00s
[ 32/736] texlive-iftex-11:svn61910-74. 100% | 983.2 KiB/s |  18.7 KiB |  00m00s
[ 33/736] texlive-multido-11:svn18302.1 100% | 872.8 KiB/s |  15.7 KiB |  00m00s
[ 34/736] texlive-kpathsea-11:svn66209- 100% |  29.2 MiB/s |   1.1 MiB |  00m00s
[ 35/736] texlive-pgf-11:svn65553-74.fc 100% |  22.1 MiB/s | 814.3 KiB |  00m00s
[ 36/736] texlive-pstricks-11:svn65346- 100% |   4.4 MiB/s | 109.0 KiB |  00m00s
[ 37/736] texlive-varwidth-11:svn24104. 100% | 827.9 KiB/s |  15.7 KiB |  00m00s
[ 38/736] texlive-xkeyval-11:svn63616-7 100% |   1.2 MiB/s |  24.9 KiB |  00m00s
[ 39/736] yosyshq-abc-libs-0:0.46-1.202 100% |  23.4 MiB/s |   5.5 MiB |  00m00s
[ 40/736] texlive-amsmath-11:svn63514-7 100% |   2.3 MiB/s |  44.3 KiB |  00m00s
[ 41/736] texlive-auto-pst-pdf-11:svn56 100% | 727.3 KiB/s |  14.5 KiB |  00m00s
[ 42/736] texlive-babel-11:svn65823-74. 100% |  10.0 MiB/s | 358.1 KiB |  00m00s
[ 43/736] texlive-bera-11:svn20031.0-74 100% |   3.9 MiB/s | 336.7 KiB |  00m00s
[ 44/736] texlive-amsfonts-11:svn61937- 100% |  27.7 MiB/s |   3.6 MiB |  00m00s
[ 45/736] texlive-biblatex-11:svn66403- 100% |   3.7 MiB/s | 282.5 KiB |  00m00s
[ 46/736] texlive-booktabs-11:svn53402- 100% | 863.0 KiB/s |  15.5 KiB |  00m00s
[ 47/736] texlive-breakurl-11:svn29901. 100% | 708.6 KiB/s |  14.9 KiB |  00m00s
[ 48/736] texlive-caption-11:svn66580-7 100% |   3.5 MiB/s |  79.1 KiB |  00m00s
[ 49/736] texlive-eso-pic-11:svn56658-7 100% | 944.2 KiB/s |  17.0 KiB |  00m00s
[ 50/736] texlive-fancyvrb-11:svn65585- 100% |   1.3 MiB/s |  24.2 KiB |  00m00s
[ 51/736] texlive-filecontents-11:svn52 100% | 789.9 KiB/s |  14.2 KiB |  00m00s
[ 52/736] texlive-footmisc-11:svn62524- 100% |   1.2 MiB/s |  22.5 KiB |  00m00s
[ 53/736] texlive-hyperref-11:svn65758- 100% |   5.4 MiB/s | 111.1 KiB |  00m00s
[ 54/736] texlive-paralist-11:svn43021- 100% | 813.8 KiB/s |  15.5 KiB |  00m00s
[ 55/736] texlive-pst-3d-11:svn17257.1. 100% | 687.2 KiB/s |  15.8 KiB |  00m00s
[ 56/736] texlive-pst-coil-11:svn62977- 100% | 901.7 KiB/s |  16.2 KiB |  00m00s
[ 57/736] texlive-pst-eps-11:svn15878.1 100% | 165.1 KiB/s |  15.0 KiB |  00m00s
[ 58/736] texlive-pst-fill-11:svn60671- 100% | 174.7 KiB/s |  15.9 KiB |  00m00s
[ 59/736] texlive-pst-grad-11:svn15878. 100% | 732.6 KiB/s |  16.1 KiB |  00m00s
[ 60/736] texlive-pst-node-11:svn61838- 100% |   1.6 MiB/s |  38.0 KiB |  00m00s
[ 61/736] texlive-pst-ovl-11:svn54963-7 100% | 594.8 KiB/s |  14.3 KiB |  00m00s
[ 62/736] texlive-pst-plot-11:svn65346- 100% |   1.4 MiB/s |  35.0 KiB |  00m00s
[ 63/736] texlive-koma-script-11:svn646 100% |  30.8 MiB/s |   6.3 MiB |  00m00s
[ 64/736] texlive-pst-tools-11:svn60621 100% | 937.9 KiB/s |  18.8 KiB |  00m00s
[ 65/736] texlive-pst-text-11:svn49542- 100% | 694.0 KiB/s |  16.7 KiB |  00m00s
[ 66/736] texlive-pst-tree-11:svn60421- 100% |   1.0 MiB/s |  18.8 KiB |  00m00s
[ 67/736] texlive-pstricks-add-11:svn65 100% |   1.8 MiB/s |  34.6 KiB |  00m00s
[ 68/736] texlive-setspace-11:svn65206- 100% | 832.5 KiB/s |  15.8 KiB |  00m00s
[ 69/736] texlive-showexpl-11:svn57414- 100% | 884.5 KiB/s |  15.9 KiB |  00m00s
[ 70/736] texlive-ragged2e-11:svn66152- 100% |  17.9 MiB/s | 679.4 KiB |  00m00s
[ 71/736] texlive-subfig-11:svn15878.1. 100% |   1.0 MiB/s |  19.2 KiB |  00m00s
[ 72/736] texlive-tools-11:svn64892-74. 100% |   3.3 MiB/s |  64.1 KiB |  00m00s
[ 73/736] texlive-xcolor-11:svn63563-74 100% |   1.5 MiB/s |  30.1 KiB |  00m00s
[ 74/736] texlive-pst-math-11:svn64732- 100% | 997.6 KiB/s |  18.0 KiB |  00m00s
[ 75/736] texlive-listings-11:svn66222- 100% |   8.0 MiB/s | 164.8 KiB |  00m00s
[ 76/736] texlive-luatexbase-11:svn5266 100% | 693.8 KiB/s |  13.9 KiB |  00m00s
[ 77/736] texlive-atveryend-11:svn53108 100% |  12.5 MiB/s | 382.9 KiB |  00m00s
[ 78/736] texlive-fp-11:svn49719-74.fc4 100% |   1.6 MiB/s |  33.7 KiB |  00m00s
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[ 80/736] texlive-pdftexcmds-11:svn5577 100% |  13.6 MiB/s | 388.6 KiB |  00m00s
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[587/736] liblerc-0:4.0.0-7.fc41.x86_64 100% |   7.6 MiB/s | 210.3 KiB |  00m00s
[588/736] libdatrie-0:0.2.13-10.fc41.x8 100% |   1.9 MiB/s |  32.2 KiB |  00m00s
[589/736] rsvg-pixbuf-loader-0:2.59.2-1 100% |   6.0 MiB/s | 166.1 KiB |  00m00s
[590/736] libusb1-0:1.0.27-4.fc42.x86_6 100% |   4.4 MiB/s |  76.9 KiB |  00m00s
[591/736] adobe-mappings-cmap-0:2023111 100% |   9.4 MiB/s |   2.2 MiB |  00m00s
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[593/736] adobe-mappings-pdf-0:20190401 100% |   8.8 MiB/s | 619.0 KiB |  00m00s
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[595/736] jbig2dec-libs-0:0.20-5.fc41.x 100% |   3.8 MiB/s |  74.0 KiB |  00m00s
[596/736] libXt-0:1.3.1-1.fc42.x86_64   100% |   5.6 MiB/s | 177.4 KiB |  00m00s
[597/736] libicu-0:74.2-2.fc41.x86_64   100% |  12.7 MiB/s |  10.4 MiB |  00m01s
[598/736] libijs-0:0.35-23.fc41.x86_64  100% |   1.3 MiB/s |  29.5 KiB |  00m00s
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[600/736] libglvnd-1:1.7.0-5.fc41.x86_6 100% |   5.9 MiB/s | 114.4 KiB |  00m00s
[601/736] mesa-libGL-0:24.3.0~rc2-1.fc4 100% |   5.5 MiB/s | 163.1 KiB |  00m00s
[602/736] libdav1d-0:1.5.0-1.fc42.x86_6 100% |  10.1 MiB/s | 622.8 KiB |  00m00s
[603/736] libaom-0:3.9.0-3.fc41.x86_64  100% |  13.8 MiB/s |   1.8 MiB |  00m00s
[604/736] rav1e-libs-0:0.7.1-4.fc42.x86 100% |  12.0 MiB/s |   1.0 MiB |  00m00s
[605/736] libvmaf-0:3.0.0-2.fc41.x86_64 100% |   6.3 MiB/s | 193.7 KiB |  00m00s
[606/736] libICE-0:1.1.1-4.fc41.x86_64  100% |   3.8 MiB/s |  74.7 KiB |  00m00s
[607/736] libSM-0:1.2.4-4.fc41.x86_64   100% |   2.5 MiB/s |  43.2 KiB |  00m00s
[608/736] svt-av1-libs-0:2.1.0-2.fc41.x 100% |  14.7 MiB/s |   2.0 MiB |  00m00s
[609/736] libX11-common-0:1.8.10-2.fc42 100% |   5.4 MiB/s | 144.8 KiB |  00m00s
[610/736] graphite2-0:1.3.14-16.fc41.x8 100% |   4.9 MiB/s |  95.1 KiB |  00m00s
[611/736] netpbm-0:11.02.00-7.fc41.x86_ 100% |   6.2 MiB/s | 184.1 KiB |  00m00s
[612/736] gpgme-0:1.24.0-1.fc42.x86_64  100% |   7.1 MiB/s | 217.7 KiB |  00m00s
[613/736] libassuan-0:2.5.7-2.fc41.x86_ 100% |   3.3 MiB/s |  67.1 KiB |  00m00s
[614/736] libgpg-error-0:1.50-2.fc41.x8 100% |   3.8 MiB/s | 232.3 KiB |  00m00s
[615/736] google-noto-fonts-common-0:20 100% | 935.4 KiB/s |  17.8 KiB |  00m00s
[616/736] nettle-0:3.10-3.fc41.x86_64   100% |   8.0 MiB/s | 428.5 KiB |  00m00s
[617/736] mupdf-libs-0:1.24.6-4.fc42.x8 100% |  17.1 MiB/s |  25.8 MiB |  00m02s
[618/736] gnupg2-0:2.4.5-3.fc41.x86_64  100% |  11.9 MiB/s |   2.7 MiB |  00m00s
[619/736] libgcrypt-0:1.11.0-4.fc42.x86 100% |   6.3 MiB/s | 583.2 KiB |  00m00s
[620/736] libksba-0:1.6.7-2.fc41.x86_64 100% |   6.0 MiB/s | 159.7 KiB |  00m00s
[621/736] npth-0:1.7-2.fc41.x86_64      100% |   1.2 MiB/s |  25.2 KiB |  00m00s
[622/736] tpm2-tss-0:4.1.3-3.fc41.x86_6 100% |  10.7 MiB/s | 407.1 KiB |  00m00s
[623/736] libxcrypt-devel-0:4.4.36-10.f 100% |   1.6 MiB/s |  28.9 KiB |  00m00s
[624/736] emacs-filesystem-1:30.0-3.fc4 100% | 420.1 KiB/s |   7.1 KiB |  00m00s
[625/736] libglvnd-opengl-1:1.7.0-5.fc4 100% |   1.7 MiB/s |  37.4 KiB |  00m00s
[626/736] texlive-ifmtarg-11:svn47544-7 100% | 296.2 KiB/s |  12.4 KiB |  00m00s
[627/736] dbus-broker-0:36-4.fc41.x86_6 100% |   3.0 MiB/s | 171.7 KiB |  00m00s
[628/736] kernel-headers-0:6.12.0-65.fc 100% |  13.2 MiB/s |   1.5 MiB |  00m00s
[629/736] libXmu-0:1.2.1-2.fc41.x86_64  100% |   3.6 MiB/s |  78.0 KiB |  00m00s
[630/736] libXaw-0:1.0.16-2.fc41.x86_64 100% |   6.0 MiB/s | 202.6 KiB |  00m00s
[631/736] perl-Text-Unidecode-0:1.30-25 100% |   5.5 MiB/s | 139.6 KiB |  00m00s
[632/736] perl-XML-XPath-0:1.48-7.fc41. 100% |   3.5 MiB/s |  79.3 KiB |  00m00s
[633/736] perl-XML-Parser-0:2.47-5.fc41 100% |   7.2 MiB/s | 228.2 KiB |  00m00s
[634/736] texlive-dehyph-11:svn48599-74 100% |   2.9 MiB/s |  63.4 KiB |  00m00s
[635/736] texlive-index-11:svn24099.4.1 100% | 976.3 KiB/s |  20.5 KiB |  00m00s
[636/736] texlive-parallel-11:svn15878. 100% | 576.9 KiB/s |  15.6 KiB |  00m00s
[637/736] texlive-grffile-11:svn52756-7 100% |   5.6 MiB/s | 358.0 KiB |  00m00s
[638/736] texlive-pdfcol-11:svn64469-74 100% |   9.1 MiB/s | 324.4 KiB |  00m00s
[639/736] texlive-unicode-math-11:svn61 100% |   2.1 MiB/s |  61.1 KiB |  00m00s
[640/736] texlive-beton-11:svn15878.0-7 100% | 714.4 KiB/s |  13.6 KiB |  00m00s
[641/736] texlive-lualibs-11:svn64615-7 100% |   7.0 MiB/s | 150.5 KiB |  00m00s
[642/736] texlive-lua-uni-algos-11:svn6 100% |   3.4 MiB/s |  94.4 KiB |  00m00s
[643/736] texlive-euler-11:svn42428-74. 100% | 806.5 KiB/s |  15.3 KiB |  00m00s
[644/736] texlive-minitoc-11:svn61719-7 100% |   4.1 MiB/s |  83.5 KiB |  00m00s
[645/736] perl-Term-Cap-0:1.18-511.fc41 100% |   1.3 MiB/s |  22.1 KiB |  00m00s
[646/736] perl-mro-0:1.29-512.fc42.x86_ 100% |   1.5 MiB/s |  29.9 KiB |  00m00s
[647/736] perl-B-Hooks-EndOfScope-0:0.2 100% |   1.6 MiB/s |  38.4 KiB |  00m00s
[648/736] perl-namespace-clean-0:0.27-2 100% |   1.2 MiB/s |  29.1 KiB |  00m00s
[649/736] perl-IPC-System-Simple-0:1.30 100% |   1.7 MiB/s |  38.7 KiB |  00m00s
[650/736] perl-Tie-RefHash-0:1.41-1.fc4 100% | 975.8 KiB/s |  23.4 KiB |  00m00s
[651/736] perl-open-0:1.13-512.fc42.noa 100% | 329.6 KiB/s |  16.5 KiB |  00m00s
[652/736] perl-deprecate-0:0.04-512.fc4 100% | 309.1 KiB/s |  14.5 KiB |  00m00s
[653/736] texlive-xetex-11:svn66203-86. 100% |   9.3 MiB/s |   1.2 MiB |  00m00s
[654/736] perl-Sub-Exporter-0:0.991-4.f 100% |   3.3 MiB/s |  71.4 KiB |  00m00s
[655/736] perl-Data-OptList-0:0.114-5.f 100% |   1.3 MiB/s |  26.9 KiB |  00m00s
[656/736] perl-Package-Generator-0:1.10 100% |   1.0 MiB/s |  22.5 KiB |  00m00s
[657/736] perl-Params-Util-0:1.102-16.f 100% |   1.5 MiB/s |  32.8 KiB |  00m00s
[658/736] ncurses-0:6.5-2.20240629.fc41 100% |   6.7 MiB/s | 419.1 KiB |  00m00s
[659/736] perl-Sub-Install-0:0.929-6.fc 100% |   1.2 MiB/s |  22.9 KiB |  00m00s
[660/736] perl-Devel-StackTrace-1:2.05- 100% |   1.5 MiB/s |  30.6 KiB |  00m00s
[661/736] perl-Eval-Closure-0:0.14-24.f 100% |   1.2 MiB/s |  23.8 KiB |  00m00s
[662/736] perl-MRO-Compat-0:0.15-10.fc4 100% |   1.2 MiB/s |  25.4 KiB |  00m00s
[663/736] perl-Ref-Util-0:0.204-21.fc41 100% |   1.1 MiB/s |  23.5 KiB |  00m00s
[664/736] perl-Role-Tiny-0:2.002004-12. 100% |   1.6 MiB/s |  31.9 KiB |  00m00s
[665/736] perl-Opcode-0:1.65-512.fc42.x 100% |   1.9 MiB/s |  35.8 KiB |  00m00s
[666/736] perl-XString-0:0.005-14.fc41. 100% |   1.0 MiB/s |  22.9 KiB |  00m00s
[667/736] perl-Class-Method-Modifiers-0 100% |   1.9 MiB/s |  43.7 KiB |  00m00s
[668/736] perl-Ref-Util-XS-0:0.117-24.f 100% |   1.1 MiB/s |  23.5 KiB |  00m00s
[669/736] perl-Pod-Escapes-1:1.07-511.f 100% |   1.0 MiB/s |  19.8 KiB |  00m00s
[670/736] perl-Exception-Class-0:1.45-1 100% |   2.1 MiB/s |  43.6 KiB |  00m00s
[671/736] perl-Module-Implementation-0: 100% |   1.0 MiB/s |  19.1 KiB |  00m00s
[672/736] perl-Module-CoreList-1:5.2024 100% |   4.2 MiB/s |  90.8 KiB |  00m00s
[673/736] perl-Math-Complex-0:1.62-512. 100% |   2.6 MiB/s |  46.0 KiB |  00m00s
[674/736] perl-Module-Metadata-0:1.0000 100% |   1.8 MiB/s |  35.3 KiB |  00m00s
[675/736] perl-Net-SMTP-SSL-0:1.04-25.f 100% | 649.4 KiB/s |  11.7 KiB |  00m00s
[676/736] perl-Email-Date-Format-0:1.00 100% | 943.5 KiB/s |  18.9 KiB |  00m00s
[677/736] perl-MIME-Types-0:2.26-2.fc41 100% |   3.4 MiB/s |  70.5 KiB |  00m00s
[678/736] perl-Locale-Maketext-0:1.33-5 100% |   4.8 MiB/s |  93.8 KiB |  00m00s
[679/736] perl-I18N-LangTags-0:0.45-512 100% |   2.8 MiB/s |  52.4 KiB |  00m00s
[680/736] perl-Number-Compare-0:0.03-39 100% | 624.1 KiB/s |  11.9 KiB |  00m00s
[681/736] perl-Text-Glob-0:0.11-24.fc41 100% | 746.4 KiB/s |  13.4 KiB |  00m00s
[682/736] perl-Devel-LexAlias-0:0.05-38 100% | 821.9 KiB/s |  16.4 KiB |  00m00s
[683/736] perl-Class-Data-Inheritable-0 100% | 556.2 KiB/s |  12.8 KiB |  00m00s
[684/736] perl-PadWalker-0:2.5-15.fc41. 100% |   1.3 MiB/s |  27.2 KiB |  00m00s
[685/736] perl-Devel-Caller-0:2.07-7.fc 100% | 912.0 KiB/s |  19.2 KiB |  00m00s
[686/736] perltidy-0:20240903-1.fc42.no 100% |  14.8 MiB/s | 789.7 KiB |  00m00s
[687/736] perl-Date-ISO8601-0:0.005-21. 100% |   1.0 MiB/s |  19.2 KiB |  00m00s
[688/736] perl-DateTime-TimeZone-System 100% |   1.2 MiB/s |  22.5 KiB |  00m00s
[689/736] perl-Hash-Util-FieldHash-0:1. 100% |   2.0 MiB/s |  38.8 KiB |  00m00s
[690/736] perl-Params-Classify-0:0.015- 100% |   1.1 MiB/s |  30.7 KiB |  00m00s
[691/736] perl-File-ShareDir-0:1.118-12 100% |   1.4 MiB/s |  29.8 KiB |  00m00s
[692/736] perl-Variable-Magic-0:0.64-3. 100% |   2.6 MiB/s |  55.3 KiB |  00m00s
[693/736] gumbo-parser-1:0.12.1-2.fc41. 100% |   5.0 MiB/s | 132.3 KiB |  00m00s
[694/736] nss-softokn-freebl-0:3.105.0- 100% |  11.8 MiB/s | 325.2 KiB |  00m00s
[695/736] libX11-xcb-0:1.8.10-2.fc42.x8 100% | 659.6 KiB/s |  11.9 KiB |  00m00s
[696/736] libXxf86vm-0:1.1.5-7.fc41.x86 100% | 941.8 KiB/s |  17.9 KiB |  00m00s
[697/736] libdrm-0:2.4.123-1.fc42.x86_6 100% |   7.7 MiB/s | 158.5 KiB |  00m00s
[698/736] tesseract-libs-0:5.5.0-1.fc42 100% |  18.6 MiB/s |   1.3 MiB |  00m00s
[699/736] leptonica-0:1.85.0-1.fc42.x86 100% |  11.9 MiB/s |   1.2 MiB |  00m00s
[700/736] mesa-libglapi-0:24.3.0~rc2-1. 100% |   2.5 MiB/s |  51.3 KiB |  00m00s
[701/736] libxshmfence-0:1.3.2-5.fc42.x 100% | 638.4 KiB/s |  13.4 KiB |  00m00s
[702/736] lm_sensors-libs-0:3.6.0-20.fc 100% |   2.1 MiB/s |  40.7 KiB |  00m00s
[703/736] mesa-filesystem-0:24.3.0~rc2- 100% |   1.0 MiB/s |  21.2 KiB |  00m00s
[704/736] mesa-libgbm-0:24.3.0~rc2-1.fc 100% |   2.5 MiB/s |  50.2 KiB |  00m00s
[705/736] spirv-tools-libs-0:2024.3-4.f 100% |  12.6 MiB/s |   1.5 MiB |  00m00s
[706/736] libedit-0:3.1-53.20240808cvs. 100% |   4.3 MiB/s | 105.6 KiB |  00m00s
[707/736] libpciaccess-0:0.16-13.fc41.x 100% |   1.4 MiB/s |  26.5 KiB |  00m00s
[708/736] giflib-0:5.2.2-2.fc41.x86_64  100% |   2.7 MiB/s |  51.9 KiB |  00m00s
[709/736] dbus-common-1:1.14.10-4.fc41. 100% | 814.5 KiB/s |  14.7 KiB |  00m00s
[710/736] teckit-0:2.5.12-3.fc41.x86_64 100% |   5.4 MiB/s | 355.4 KiB |  00m00s
[711/736] texlive-everyshi-11:svn57001- 100% |   3.9 MiB/s | 144.8 KiB |  00m00s
[712/736] texlive-xetexconfig-11:svn458 100% | 320.0 KiB/s |   9.0 KiB |  00m00s
[713/736] texlive-lualatex-math-11:svn6 100% | 568.5 KiB/s |  18.2 KiB |  00m00s
[714/736] texlive-ucharcat-11:svn38907- 100% | 362.5 KiB/s |  13.0 KiB |  00m00s
[715/736] texlive-notoccite-11:svn18129 100% | 299.8 KiB/s |  10.5 KiB |  00m00s
[716/736] perl-English-0:1.11-512.fc42. 100% | 451.4 KiB/s |  13.5 KiB |  00m00s
[717/736] perl-Pod-Html-0:1.35-512.fc42 100% |   1.3 MiB/s |  29.4 KiB |  00m00s
[718/736] perl-encoding-4:3.00-511.fc41 100% |   3.1 MiB/s |  63.2 KiB |  00m00s
[719/736] perl-Package-Stash-0:0.40-8.f 100% | 904.4 KiB/s |  32.6 KiB |  00m00s
[720/736] perl-Filter-2:1.64-512.fc41.x 100% |   3.6 MiB/s |  80.1 KiB |  00m00s
[721/736] perl-Devel-CallChecker-0:0.00 100% |   1.1 MiB/s |  23.9 KiB |  00m00s
[722/736] perl-Package-Stash-XS-0:0.30- 100% |   1.9 MiB/s |  36.1 KiB |  00m00s
[723/736] perl-Class-Inspector-0:1.36-1 100% |   1.4 MiB/s |  30.4 KiB |  00m00s
[724/736] perl-DynaLoader-Functions-0:0 100% | 998.7 KiB/s |  19.0 KiB |  00m00s
[725/736] libwayland-server-0:1.23.0-2. 100% |   2.4 MiB/s |  41.1 KiB |  00m00s
[726/736] hwdata-0:0.389-1.fc42.noarch  100% |   7.4 MiB/s |   1.6 MiB |  00m00s
[727/736] xpdf-libs-1:4.05-5.fc41.x86_6 100% |   7.2 MiB/s | 594.2 KiB |  00m00s
[728/736] pyproject-rpm-macros-0:1.16.2 100% |   2.3 MiB/s |  44.7 KiB |  00m00s
[729/736] python-rpm-macros-0:3.13-3.fc 100% | 803.1 KiB/s |  17.7 KiB |  00m00s
[730/736] python3-rpm-generators-0:14-1 100% |   1.6 MiB/s |  29.3 KiB |  00m00s
[731/736] python3-rpm-macros-0:3.13-3.f 100% | 777.7 KiB/s |  12.4 KiB |  00m00s
[732/736] annobin-plugin-gcc-0:12.77-1. 100% |  10.5 MiB/s | 977.2 KiB |  00m00s
[733/736] gcc-plugin-annobin-0:14.2.1-6 100% |   2.9 MiB/s |  57.1 KiB |  00m00s
[734/736] annobin-docs-0:12.77-1.fc42.n 100% |   4.7 MiB/s |  92.4 KiB |  00m00s
[735/736] llvm-libs-0:19.1.3-3.fc42.x86 100% |  17.4 MiB/s |  31.5 MiB |  00m02s
[736/736] mesa-dri-drivers-0:24.3.0~rc2 100% |  15.6 MiB/s |  29.3 MiB |  00m02s
--------------------------------------------------------------------------------
[736/736] Total                         100% |  33.7 MiB/s | 506.8 MiB |  00m15s
Running transaction
[  1/738] Verify package files          100% | 364.0   B/s | 736.0   B |  00m02s
>>> Running pre-transaction scriptlet: texlive-base-11:20230311-86.fc42.x86_64
>>> Finished pre-transaction scriptlet: texlive-base-11:20230311-86.fc42.x86_64
>>> [RPM] /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root/var/cache/d
[  2/738] Prepare transaction           100% |   1.5 KiB/s | 736.0   B |  00m00s
[  3/738] Installing texlive-base-11:20 100% | 181.1 MiB/s |  19.0 MiB |  00m00s
[  4/738] Installing texlive-lib-11:202 100% | 181.2 MiB/s |   1.1 MiB |  00m00s
[  5/738] Installing libpng-2:1.6.44-1. 100% | 120.6 MiB/s | 247.0 KiB |  00m00s
[  6/738] Installing expat-0:2.6.4-1.fc 100% | 140.4 MiB/s | 287.6 KiB |  00m00s
[  7/738] Installing libjpeg-turbo-0:3. 100% | 257.4 MiB/s | 790.8 KiB |  00m00s
[  8/738] Installing nspr-0:4.35.0-30.f 100% | 154.9 MiB/s | 317.2 KiB |  00m00s
[  9/738] Installing libgpg-error-0:1.5 100% | 145.7 MiB/s | 895.4 KiB |  00m00s
[ 10/738] Installing fonts-filesystem-1 100% |   0.0   B/s | 788.0   B |  00m00s
[ 11/738] Installing urw-base35-fonts-c 100% |  37.5 MiB/s |  38.4 KiB |  00m00s
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[195/738] Installing perl-Symbol-0:1.09 100% |   0.0   B/s |   7.2 KiB |  00m00s
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[202/738] Installing perl-base-0:2.27-5 100% |  12.6 MiB/s |  12.9 KiB |  00m00s
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[206/738] Installing perl-mro-0:1.29-51 100% |  45.6 MiB/s |  46.7 KiB |  00m00s
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[213/738] Installing perl-MIME-Base64-0 100% |  23.6 MiB/s |  48.4 KiB |  00m00s
[214/738] Installing perl-Errno-0:1.38- 100% |   0.0   B/s |   8.8 KiB |  00m00s
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[219/738] Installing perl-Carp-0:1.54-5 100% |  46.6 MiB/s |  47.7 KiB |  00m00s
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[221/738] Installing perl-DynaLoader-0: 100% |  31.7 MiB/s |  32.5 KiB |  00m00s
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[248/738] Installing perl-Encode-Locale 100% |  19.6 MiB/s |  20.1 KiB |  00m00s
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[256/738] Installing perl-Parse-RecDesc 100% |  65.4 MiB/s | 535.4 KiB |  00m00s
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[271/738] Installing perl-Digest-HMAC-0 100% |  30.7 MiB/s |  31.5 KiB |  00m00s
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[306/738] Installing perl-libwww-perl-0 100% |  86.3 MiB/s | 530.3 KiB |  00m00s
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[314/738] Installing perl-Tie-Cycle-0:1 100% |  24.0 MiB/s |  24.6 KiB |  00m00s
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[332/738] Installing perl-XString-0:0.0 100% |  19.0 MiB/s |  38.9 KiB |  00m00s
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[334/738] Installing perl-Role-Tiny-0:2 100% |  62.0 MiB/s |  63.5 KiB |  00m00s
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[346/738] Installing perl-MIME-Lite-0:3 100% |  81.0 MiB/s | 248.9 KiB |  00m00s
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[351/738] Installing perl-Module-Load-C 100% |  29.2 MiB/s |  29.9 KiB |  00m00s
[352/738] Installing perl-IPC-Cmd-2:1.0 100% |  83.9 MiB/s |  85.9 KiB |  00m00s
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[364/738] Installing perl-B-Hooks-EndOf 100% |  24.4 MiB/s |  75.1 KiB |  00m00s
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[369/738] Installing perl-Specio-0:0.48 100% |  48.1 MiB/s | 344.7 KiB |  00m00s
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[373/738] Installing perl-XML-XPath-0:1 100% |  51.3 MiB/s | 210.1 KiB |  00m00s
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[378/738] Installing texlive-hyph-utf8- 100% |  74.8 MiB/s |  76.6 KiB |  00m00s
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[380/738] Installing texlive-knuth-lib- 100% |  34.6 MiB/s | 106.3 KiB |  00m00s
[381/738] Installing texlive-plain-11:s 100% |  22.2 MiB/s | 113.8 KiB |  00m00s
[382/738] Installing texlive-tex-ini-fi 100% |   9.9 MiB/s |  10.1 KiB |  00m00s
[383/738] Installing texlive-unicode-da 100% | 219.3 MiB/s |   3.1 MiB |  00m00s
[384/738] Installing texlive-graphics-d 100% |  97.5 MiB/s |  99.9 KiB |  00m00s
[385/738] Installing texlive-luatex-11: 100% |  50.3 MiB/s |   9.2 MiB |  00m00s
[386/738] Installing texlive-gsftopk-11 100% |  23.7 MiB/s |  48.6 KiB |  00m00s
[387/738] Installing texlive-texlive.in 100% | 143.9 MiB/s |   1.0 MiB |  00m00s
[388/738] Installing texlive-texlive-sc 100% |  42.6 MiB/s | 349.1 KiB |  00m00s
[389/738] Installing texlive-kpathsea-1 100% | 129.8 MiB/s |   2.1 MiB |  00m00s
[390/738] Installing texlive-iftex-11:s 100% |  29.6 MiB/s |  30.3 KiB |  00m00s
[391/738] Installing texlive-amsmath-11 100% | 131.2 MiB/s | 268.7 KiB |  00m00s
[392/738] Installing texlive-kvoptions- 100% | 134.7 MiB/s | 551.6 KiB |  00m00s
[393/738] Installing texlive-url-11:svn 100% |  21.6 MiB/s |  22.1 KiB |  00m00s
[394/738] Installing texlive-pdftexcmds 100% | 138.5 MiB/s | 425.6 KiB |  00m00s
[395/738] Installing texlive-ltxcmds-11 100% |  34.6 MiB/s | 425.5 KiB |  00m00s
[396/738] Installing texlive-babel-11:s 100% |  26.1 MiB/s |   2.2 MiB |  00m00s
[397/738] Installing texlive-atveryend- 100% | 200.8 MiB/s | 411.2 KiB |  00m00s
[398/738] Installing texlive-etex-pkg-1 100% |  18.6 MiB/s |  19.0 KiB |  00m00s
[399/738] Installing texlive-etoolbox-1 100% |  66.1 MiB/s |  67.7 KiB |  00m00s
[400/738] Installing texlive-atbegshi-1 100% | 217.3 MiB/s | 445.1 KiB |  00m00s
[401/738] Installing texlive-multido-11 100% |   9.6 MiB/s |  19.6 KiB |  00m00s
[402/738] Installing texlive-amsfonts-1 100% |  88.9 MiB/s |   6.0 MiB |  00m00s
[403/738] Installing texlive-auxhook-11 100% | 148.0 MiB/s | 303.2 KiB |  00m00s
[404/738] Installing texlive-etexcmds-1 100% | 157.4 MiB/s | 322.3 KiB |  00m00s
[405/738] Installing texlive-latex-font 100% |  24.3 MiB/s | 124.2 KiB |  00m00s
[406/738] Installing texlive-lm-11:svn6 100% |  96.7 MiB/s |  39.5 MiB |  00m00s
[407/738] Installing texlive-varwidth-1 100% |  19.8 MiB/s |  20.3 KiB |  00m00s
[408/738] Installing texlive-booktabs-1 100% |  18.6 MiB/s |  19.0 KiB |  00m00s
[409/738] Installing texlive-footmisc-1 100% |  64.1 MiB/s |  65.6 KiB |  00m00s
[410/738] Installing texlive-fp-11:svn4 100% |  62.4 MiB/s | 127.9 KiB |  00m00s
[411/738] Installing texlive-marvosym-1 100% |  91.9 MiB/s | 188.3 KiB |  00m00s
[412/738] Installing texlive-infwarerr- 100% | 150.2 MiB/s | 307.5 KiB |  00m00s
[413/738] Installing texlive-intcalc-11 100% |  38.5 MiB/s | 472.8 KiB |  00m00s
[414/738] Installing texlive-kvsetkeys- 100% | 209.4 MiB/s | 428.8 KiB |  00m00s
[415/738] Installing texlive-letltxmacr 100% | 152.7 MiB/s | 312.6 KiB |  00m00s
[416/738] Installing texlive-pdfescape- 100% | 184.2 MiB/s | 377.2 KiB |  00m00s
[417/738] Installing texlive-zapfding-1 100% |  26.9 MiB/s |  82.7 KiB |  00m00s
[418/738] Installing texlive-bigintcalc 100% | 252.4 MiB/s | 516.8 KiB |  00m00s
[419/738] Installing texlive-fancyhdr-1 100% |  31.9 MiB/s |  32.7 KiB |  00m00s
[420/738] Installing texlive-graphics-c 100% | 563.1 KiB/s |   3.9 KiB |  00m00s
[421/738] Installing texlive-graphics-1 100% |  62.8 MiB/s | 128.7 KiB |  00m00s
[422/738] Installing texlive-tools-11:s 100% |  80.4 MiB/s | 411.7 KiB |  00m00s
[423/738] Installing texlive-xkeyval-11 100% |  69.9 MiB/s |  71.6 KiB |  00m00s
[424/738] Installing texlive-geometry-1 100% |  49.1 MiB/s |  50.2 KiB |  00m00s
[425/738] Installing texlive-colortbl-1 100% |  21.3 MiB/s |  21.8 KiB |  00m00s
[426/738] Installing texlive-uniquecoun 100% | 153.1 MiB/s | 313.5 KiB |  00m00s
[427/738] Installing texlive-hypdoc-11: 100% | 175.5 MiB/s | 359.5 KiB |  00m00s
[428/738] Installing texlive-l3backend- 100% | 158.1 MiB/s |   1.1 MiB |  00m00s
[429/738] Installing texlive-natbib-11: 100% |  65.5 MiB/s | 134.2 KiB |  00m00s
[430/738] Installing texlive-palatino-1 100% |  62.3 MiB/s |   1.1 MiB |  00m00s
[431/738] Installing texlive-rerunfilec 100% | 177.4 MiB/s | 363.3 KiB |  00m00s
[432/738] Installing texlive-caption-11 100% | 222.8 MiB/s | 912.6 KiB |  00m00s
[433/738] Installing texlive-carlisle-1 100% |  32.0 MiB/s |  32.8 KiB |  00m00s
[434/738] Installing texlive-csquotes-1 100% | 110.6 MiB/s | 113.3 KiB |  00m00s
[435/738] Installing texlive-sauerj-11: 100% |  27.9 MiB/s |  28.6 KiB |  00m00s
[436/738] Installing texlive-bitset-11: 100% | 129.6 MiB/s | 663.5 KiB |  00m00s
[437/738] Installing texlive-catchfile- 100% | 156.3 MiB/s | 320.0 KiB |  00m00s
[438/738] Installing texlive-ifplatform 100% |  13.1 MiB/s |  13.5 KiB |  00m00s
[439/738] Installing texlive-babelbib-1 100% | 153.8 MiB/s | 787.2 KiB |  00m00s
[440/738] Installing texlive-paralist-1 100% |  23.6 MiB/s |  24.1 KiB |  00m00s
[441/738] Installing texlive-ragged2e-1 100% | 119.4 MiB/s | 733.3 KiB |  00m00s
[442/738] Installing texlive-setspace-1 100% |   0.0   B/s |  22.4 KiB |  00m00s
[443/738] Installing texlive-ctablestac 100% |  20.4 MiB/s |  20.9 KiB |  00m00s
[444/738] Installing texlive-luatexbase 100% |  14.7 MiB/s |  15.1 KiB |  00m00s
[445/738] Installing texlive-bookmark-1 100% | 186.3 MiB/s | 572.2 KiB |  00m00s
[446/738] Installing texlive-gettitlest 100% | 166.1 MiB/s | 340.1 KiB |  00m00s
[447/738] Installing texlive-hycolor-11 100% | 201.7 MiB/s | 413.1 KiB |  00m00s
[448/738] Installing texlive-kvdefineke 100% |  77.0 MiB/s | 315.5 KiB |  00m00s
[449/738] Installing texlive-refcount-1 100% | 170.5 MiB/s | 349.2 KiB |  00m00s
[450/738] Installing texlive-stringenc- 100% | 175.7 MiB/s |   1.1 MiB |  00m00s
[451/738] Installing texlive-titlesec-1 100% |  96.6 MiB/s |  98.9 KiB |  00m00s
[452/738] Installing texlive-latexconfi 100% |   9.6 MiB/s |   9.8 KiB |  00m00s
[453/738] Installing texlive-hologo-11: 100% |  54.2 MiB/s | 666.1 KiB |  00m00s
[454/738] Installing texlive-firstaid-1 100% | 145.9 MiB/s | 298.8 KiB |  00m00s
[455/738] Installing texlive-grfext-11: 100% | 160.7 MiB/s | 329.1 KiB |  00m00s
[456/738] Installing texlive-avantgar-1 100% |  77.6 MiB/s |   1.2 MiB |  00m00s
[457/738] Installing texlive-bookman-11 100% |  72.6 MiB/s |   1.2 MiB |  00m00s
[458/738] Installing texlive-charter-11 100% |  81.1 MiB/s | 415.0 KiB |  00m00s
[459/738] Installing texlive-courier-11 100% |  83.2 MiB/s | 937.1 KiB |  00m00s
[460/738] Installing texlive-fpl-11:svn 100% | 106.0 MiB/s | 651.2 KiB |  00m00s
[461/738] Installing texlive-mathpazo-1 100% |  38.0 MiB/s | 116.7 KiB |  00m00s
[462/738] Installing texlive-helvetic-1 100% |  30.5 MiB/s |   1.8 MiB |  00m00s
[463/738] Installing texlive-lm-math-11 100% | 143.9 MiB/s | 736.9 KiB |  00m00s
[464/738] Installing texlive-symbol-11: 100% |  26.7 MiB/s |  82.0 KiB |  00m00s
[465/738] Installing texlive-times-11:s 100% |  55.5 MiB/s |   1.0 MiB |  00m00s
[466/738] Installing texlive-utopia-11: 100% |  67.3 MiB/s | 551.4 KiB |  00m00s
[467/738] Installing texlive-psnfss-11: 100% |  11.7 MiB/s | 119.5 KiB |  00m00s
[468/738] Installing texlive-wasy-11:sv 100% |  69.4 MiB/s | 142.1 KiB |  00m00s
[469/738] Installing texlive-glyphlist- 100% |  89.0 MiB/s |  91.1 KiB |  00m00s
[470/738] Installing texlive-lua-alt-ge 100% |   0.0   B/s |   4.3 KiB |  00m00s
[471/738] Installing texlive-modes-11:s 100% | 191.4 MiB/s | 391.9 KiB |  00m00s
[472/738] Installing texlive-placeins-1 100% |   5.2 MiB/s |   5.4 KiB |  00m00s
[473/738] Installing texlive-zref-11:sv 100% | 160.6 MiB/s | 822.0 KiB |  00m00s
[474/738] Installing texlive-metafont-1 100% |  88.0 MiB/s | 810.7 KiB |  00m00s
[475/738] Installing texlive-wasy-type1 100% | 109.6 MiB/s | 336.7 KiB |  00m00s
[476/738] Installing texlive-auto-pst-p 100% |  15.2 MiB/s |  15.6 KiB |  00m00s
[477/738] Installing texlive-subfig-11: 100% |  36.6 MiB/s |  37.5 KiB |  00m00s
[478/738] Installing texlive-breakurl-1 100% |  17.5 MiB/s |  17.9 KiB |  00m00s
[479/738] Installing texlive-tabulary-1 100% |  22.5 MiB/s |  23.1 KiB |  00m00s
[480/738] Installing texlive-logreq-11: 100% |  26.6 MiB/s |  27.2 KiB |  00m00s
[481/738] Installing texlive-fncychap-1 100% |  37.5 MiB/s |  38.4 KiB |  00m00s
[482/738] Installing texlive-euro-11:sv 100% |  15.5 MiB/s |  15.9 KiB |  00m00s
[483/738] Installing texlive-dvips-11:s 100% | 105.7 MiB/s |   1.6 MiB |  00m00s
[484/738] Installing texlive-memoir-11: 100% | 157.4 MiB/s | 483.6 KiB |  00m00s
[485/738] Installing texlive-hopatch-11 100% | 169.5 MiB/s | 347.2 KiB |  00m00s
[486/738] Installing texlive-filemod-11 100% |  21.6 MiB/s |  44.1 KiB |  00m00s
[487/738] Installing texlive-tex-gyre-1 100% |  79.7 MiB/s |  24.4 MiB |  00m00s
[488/738] Installing texlive-fileconten 100% |  12.7 MiB/s |  13.0 KiB |  00m00s
[489/738] Installing texlive-pst-math-1 100% |  23.1 MiB/s |  23.7 KiB |  00m00s
[490/738] Installing texlive-marginnote 100% |  22.8 MiB/s |  23.3 KiB |  00m00s
[491/738] Installing texlive-mparhack-1 100% |  20.6 MiB/s |  21.1 KiB |  00m00s
[492/738] Installing texlive-picture-11 100% | 158.6 MiB/s | 324.8 KiB |  00m00s
[493/738] Installing texlive-hobsub-11: 100% |  80.0 MiB/s |  81.9 KiB |  00m00s
[494/738] Installing texlive-hyperref-1 100% | 150.3 MiB/s | 769.4 KiB |  00m00s
[495/738] Installing texlive-attachfile 100% |  32.4 MiB/s |  33.2 KiB |  00m00s
[496/738] Installing texlive-svn-prov-1 100% |   0.0   B/s |  16.3 KiB |  00m00s
[497/738] Installing texlive-xstring-11 100% |  55.7 MiB/s |  57.0 KiB |  00m00s
[498/738] Installing texlive-float-11:s 100% |  15.8 MiB/s |  16.2 KiB |  00m00s
[499/738] Installing texlive-collectbox 100% |  27.7 MiB/s |  28.3 KiB |  00m00s
[500/738] Installing texlive-ifoddpage- 100% |  21.0 MiB/s |  21.5 KiB |  00m00s
[501/738] Installing texlive-anyfontsiz 100% |  13.1 MiB/s |  13.4 KiB |  00m00s
[502/738] Installing texlive-capt-of-11 100% |  10.6 MiB/s |  10.9 KiB |  00m00s
[503/738] Installing texlive-cmap-11:sv 100% |  37.9 MiB/s |  38.8 KiB |  00m00s
[504/738] Installing texlive-framed-11: 100% |   0.0   B/s |  22.4 KiB |  00m00s
[505/738] Installing texlive-gnu-freefo 100% | 104.8 MiB/s |  17.0 MiB |  00m00s
[506/738] Installing texlive-luatex85-1 100% |  24.6 MiB/s |  25.1 KiB |  00m00s
[507/738] Installing texlive-needspace- 100% |  10.2 MiB/s |  10.5 KiB |  00m00s
[508/738] Installing texlive-parskip-11 100% |  16.3 MiB/s |  16.7 KiB |  00m00s
[509/738] Installing texlive-wrapfig-11 100% |  34.4 MiB/s |  35.2 KiB |  00m00s
[510/738] Installing texlive-pdfcolmk-1 100% |  20.2 MiB/s |  20.7 KiB |  00m00s
[511/738] Installing texlive-xcolor-11: 100% |  78.8 MiB/s |  80.7 KiB |  00m00s
[512/738] Installing texlive-eso-pic-11 100% |  27.9 MiB/s |  28.6 KiB |  00m00s
[513/738] Installing texlive-luabidi-11 100% |  26.1 MiB/s |  26.8 KiB |  00m00s
[514/738] Installing texlive-makecmds-1 100% |  11.6 MiB/s |  11.9 KiB |  00m00s
[515/738] Installing texlive-alphalph-1 100% | 184.1 MiB/s | 377.1 KiB |  00m00s
[516/738] Installing texlive-enumitem-1 100% |  58.7 MiB/s |  60.1 KiB |  00m00s
[517/738] Installing texlive-underscore 100% |  19.6 MiB/s |  20.1 KiB |  00m00s
[518/738] Installing texlive-euenc-11:s 100% |  41.2 MiB/s |  42.2 KiB |  00m00s
[519/738] Installing texlive-kastrup-11 100% |   4.1 MiB/s |   4.2 KiB |  00m00s
[520/738] Installing texlive-babel-engl 100% |  45.4 MiB/s |  46.5 KiB |  00m00s
[521/738] Installing texlive-fix2col-11 100% |  17.0 MiB/s |  17.4 KiB |  00m00s
[522/738] Installing texlive-latex-lab- 100% | 144.4 MiB/s |   2.3 MiB |  00m00s
[523/738] Installing texlive-mfnfss-11: 100% |  24.2 MiB/s |  24.7 KiB |  00m00s
[524/738] Installing texlive-mptopdf-11 100% |  75.0 MiB/s | 153.5 KiB |  00m00s
[525/738] Installing texlive-pagesel-11 100% | 173.9 MiB/s | 356.1 KiB |  00m00s
[526/738] Installing texlive-pslatex-11 100% |  14.3 MiB/s |  29.2 KiB |  00m00s
[527/738] Installing texlive-pspicture- 100% |  14.4 MiB/s |  14.7 KiB |  00m00s
[528/738] Installing texlive-cmextra-11 100% |  34.6 MiB/s | 141.8 KiB |  00m00s
[529/738] Installing texlive-euro-ce-11 100% |  23.0 MiB/s |  47.1 KiB |  00m00s
[530/738] Installing texlive-eurosym-11 100% |  73.1 MiB/s | 224.7 KiB |  00m00s
[531/738] Installing texlive-manfnt-fon 100% |  42.1 MiB/s |  43.1 KiB |  00m00s
[532/738] Installing texlive-mflogo-fon 100% |  20.5 MiB/s |  42.0 KiB |  00m00s
[533/738] Installing texlive-ncntrsbk-1 100% |  40.7 MiB/s | 958.2 KiB |  00m00s
[534/738] Installing texlive-pxfonts-11 100% |  69.5 MiB/s | 853.5 KiB |  00m00s
[535/738] Installing texlive-rsfs-11:sv 100% |  49.9 MiB/s | 102.2 KiB |  00m00s
[536/738] Installing texlive-tex-gyre-m 100% | 140.8 MiB/s |   2.7 MiB |  00m00s
[537/738] Installing texlive-txfonts-11 100% |  66.6 MiB/s |   1.5 MiB |  00m00s
[538/738] Installing texlive-wasysym-11 100% |  24.4 MiB/s |  25.0 KiB |  00m00s
[539/738] Installing texlive-zapfchan-1 100% |  36.1 MiB/s | 185.0 KiB |  00m00s
[540/738] Installing texlive-bibtex-11: 100% |  16.7 MiB/s | 787.0 KiB |  00m00s
[541/738] Installing texlive-colorprofi 100% |  66.9 MiB/s | 274.1 KiB |  00m00s
[542/738] Installing texlive-ec-11:svn2 100% |  37.0 MiB/s |   2.7 MiB |  00m00s
[543/738] Installing texlive-enctex-11: 100% |  61.0 MiB/s | 187.3 KiB |  00m00s
[544/738] Installing texlive-hyphenex-1 100% |   0.0   B/s |  26.1 KiB |  00m00s
[545/738] Installing texlive-knuth-loca 100% |  18.4 MiB/s | 113.1 KiB |  00m00s
[546/738] Installing texlive-luahbtex-1 100% | 129.7 MiB/s |   6.4 MiB |  00m00s
[547/738] Installing texlive-makeindex- 100% | 100.0 MiB/s | 512.1 KiB |  00m00s
[548/738] Installing texlive-mflogo-11: 100% |  13.3 MiB/s |  13.6 KiB |  00m00s
[549/738] Installing texlive-mfware-11: 100% |  57.0 MiB/s | 233.5 KiB |  00m00s
[550/738] Installing texlive-tex-11:svn 100% | 127.3 MiB/s | 390.9 KiB |  00m00s
[551/738] Installing texlive-texlive-en 100% |  58.2 MiB/s |   5.9 MiB |  00m00s
[552/738] Installing texlive-texlive-ms 100% | 175.8 MiB/s |   1.4 MiB |  00m00s
[553/738] Installing texlive-xdvi-11:sv 100% | 145.6 MiB/s | 745.5 KiB |  00m00s
[554/738] Installing texlive-changepage 100% |  27.6 MiB/s |  28.2 KiB |  00m00s
[555/738] Installing texlive-ifmtarg-11 100% |   9.7 MiB/s |   9.9 KiB |  00m00s
[556/738] Installing texlive-dehyph-11: 100% | 117.8 MiB/s | 241.2 KiB |  00m00s
[557/738] Installing texlive-grffile-11 100% |  92.9 MiB/s | 380.7 KiB |  00m00s
[558/738] Installing texlive-index-11:s 100% |  60.7 MiB/s |  62.1 KiB |  00m00s
[559/738] Installing texlive-parallel-1 100% |  22.8 MiB/s |  23.3 KiB |  00m00s
[560/738] Installing texlive-pdfcol-11: 100% | 169.3 MiB/s | 346.8 KiB |  00m00s
[561/738] Installing texlive-lua-uni-al 100% | 128.2 MiB/s | 131.3 KiB |  00m00s
[562/738] Installing texlive-lualibs-11 100% | 150.7 MiB/s | 771.6 KiB |  00m00s
[563/738] Installing texlive-luaotfload 100% | 158.0 MiB/s |   8.2 MiB |  00m00s
[564/738] Installing texlive-beton-11:s 100% |  12.2 MiB/s |  12.5 KiB |  00m00s
[565/738] Installing texlive-euler-11:s 100% |  20.9 MiB/s |  21.4 KiB |  00m00s
[566/738] Installing texlive-everyshi-1 100% | 155.2 MiB/s | 158.9 KiB |  00m00s
[567/738] Installing texlive-xetexconfi 100% |   0.0   B/s | 776.0   B |  00m00s
[568/738] Installing texlive-ucharcat-1 100% |  10.7 MiB/s |  10.9 KiB |  00m00s
[569/738] Installing texlive-notoccite- 100% |   2.9 MiB/s |   3.0 KiB |  00m00s
[570/738] Installing perl-Package-Stash 100% |  34.7 MiB/s |  71.0 KiB |  00m00s
[571/738] Installing perl-Package-Stash 100% |  28.4 MiB/s |  58.1 KiB |  00m00s
[572/738] Installing perl-namespace-cle 100% |  14.5 MiB/s |  44.6 KiB |  00m00s
[573/738] Installing perl-namespace-aut 100% |  44.0 MiB/s |  45.0 KiB |  00m00s
[574/738] Installing perl-Log-Dispatch- 100% |  36.6 MiB/s | 150.0 KiB |  00m00s
[575/738] Installing perl-Log-Dispatch- 100% |  53.2 MiB/s |  54.5 KiB |  00m00s
[576/738] Installing perl-Log-Log4perl- 100% |  73.1 MiB/s | 897.8 KiB |  00m00s
[577/738] Installing perl-Class-Inspect 100% |  57.9 MiB/s |  59.3 KiB |  00m00s
[578/738] Installing perl-File-ShareDir 100% |   8.3 MiB/s |  59.2 KiB |  00m00s
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Warning: skipped PGP checks for 736 packages from repositories: copr_base, http_kojipkgs_fedoraproject_org_repos_rawhide_latest_basearch
Complete!
Finish: build setup for yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Start: rpmbuild yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Building target platforms: x86_64
Building for target x86_64
setting SOURCE_DATE_EPOCH=1731196800
Executing(%mkbuilddir): /bin/sh -e /var/tmp/rpm-tmp.gPP1F1
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ test -d /builddir/build/BUILD/yosys-0.47-build
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w /builddir/build/BUILD/yosys-0.47-build
+ /usr/bin/rm -rf /builddir/build/BUILD/yosys-0.47-build
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-0.47-build
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-0.47-build/SPECPARTS
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%prep): /bin/sh -e /var/tmp/rpm-tmp.iFjJz7
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ cd /builddir/build/BUILD/yosys-0.47-build
+ rm -rf yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ /usr/lib/rpm/rpmuncompress -x /builddir/build/SOURCES/yosys-f20f913.tar.gz
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0001-fedora-yosys-cfginc-patch.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0002-fedora-yosys-mancfginc-patch.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0003-fedora-yosys-doc-offline-patch.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0004-fedora-yosys-cxxopts-patch.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0005-Respect-SOURCE_DATE_EPOCH-in-generate_bram_types_sim.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ /usr/lib/rpm/rpmuncompress /builddir/build/SOURCES/0006-fedora-yosys-furo-patch.patch
+ /usr/bin/patch -p1 -s --fuzz=0 --no-backup-if-mismatch -f
+ cp /builddir/build/SOURCES/viz.js .
+ cd /builddir/build/BUILD/yosys-0.47-build
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ /usr/lib/rpm/rpmuncompress -x /builddir/build/SOURCES/yosys_0.33-5.debian.tar.xz
+ STATUS=0
+ '[' 0 -ne 0 ']'
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w .
++ find . -name '*.py'
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./.github/workflows/wheels/_run_cibw_linux.py
+ touch -r ./.github/workflows/wheels/_run_cibw_linux.py ./.github/workflows/wheels/_run_cibw_linux.py.new
+ mv ./.github/workflows/wheels/_run_cibw_linux.py.new ./.github/workflows/wheels/_run_cibw_linux.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/edif/runtest.py
+ touch -r ./backends/edif/runtest.py ./backends/edif/runtest.py.new
+ mv ./backends/edif/runtest.py.new ./backends/edif/runtest.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtbmc.py
+ touch -r ./backends/smt2/smtbmc.py ./backends/smt2/smtbmc.py.new
+ mv ./backends/smt2/smtbmc.py.new ./backends/smt2/smtbmc.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtbmc_incremental.py
+ touch -r ./backends/smt2/smtbmc_incremental.py ./backends/smt2/smtbmc_incremental.py.new
+ mv ./backends/smt2/smtbmc_incremental.py.new ./backends/smt2/smtbmc_incremental.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/smtio.py
+ touch -r ./backends/smt2/smtio.py ./backends/smt2/smtio.py.new
+ mv ./backends/smt2/smtio.py.new ./backends/smt2/smtio.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/witness.py
+ touch -r ./backends/smt2/witness.py ./backends/smt2/witness.py.new
+ mv ./backends/smt2/witness.py.new ./backends/smt2/witness.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./backends/smt2/ywio.py
+ touch -r ./backends/smt2/ywio.py ./backends/smt2/ywio.py.new
+ mv ./backends/smt2/ywio.py.new ./backends/smt2/ywio.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/source/conf.py
+ touch -r ./docs/source/conf.py ./docs/source/conf.py.new
+ mv ./docs/source/conf.py.new ./docs/source/conf.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/tests/macro_commands.py
+ touch -r ./docs/tests/macro_commands.py ./docs/tests/macro_commands.py.new
+ mv ./docs/tests/macro_commands.py.new ./docs/tests/macro_commands.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/RtlilLexer.py
+ touch -r ./docs/util/RtlilLexer.py ./docs/util/RtlilLexer.py.new
+ mv ./docs/util/RtlilLexer.py.new ./docs/util/RtlilLexer.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/__init__.py
+ touch -r ./docs/util/__init__.py ./docs/util/__init__.py.new
+ mv ./docs/util/__init__.py.new ./docs/util/__init__.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/cellref.py
+ touch -r ./docs/util/cellref.py ./docs/util/cellref.py.new
+ mv ./docs/util/cellref.py.new ./docs/util/cellref.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./docs/util/cmdref.py
+ touch -r ./docs/util/cmdref.py ./docs/util/cmdref.py.new
+ mv ./docs/util/cmdref.py.new ./docs/util/cmdref.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./examples/python-api/pass.py
+ touch -r ./examples/python-api/pass.py ./examples/python-api/pass.py.new
+ mv ./examples/python-api/pass.py.new ./examples/python-api/pass.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./examples/python-api/script.py
+ touch -r ./examples/python-api/script.py ./examples/python-api/script.py.new
+ mv ./examples/python-api/script.py.new ./examples/python-api/script.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./misc/__init__.py
+ touch -r ./misc/__init__.py ./misc/__init__.py.new
+ mv ./misc/__init__.py.new ./misc/__init__.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./misc/py_wrap_generator.py
+ touch -r ./misc/py_wrap_generator.py ./misc/py_wrap_generator.py.new
+ mv ./misc/py_wrap_generator.py.new ./misc/py_wrap_generator.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./passes/pmgen/pmgen.py
+ touch -r ./passes/pmgen/pmgen.py ./passes/pmgen/pmgen.py.new
+ mv ./passes/pmgen/pmgen.py.new ./passes/pmgen/pmgen.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./setup.py
+ touch -r ./setup.py ./setup.py.new
+ mv ./setup.py.new ./setup.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/common/cellhelp.py
+ touch -r ./techlibs/common/cellhelp.py ./techlibs/common/cellhelp.py.new
+ mv ./techlibs/common/cellhelp.py.new ./techlibs/common/cellhelp.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/common/gen_fine_ffs.py
+ touch -r ./techlibs/common/gen_fine_ffs.py ./techlibs/common/gen_fine_ffs.py.new
+ mv ./techlibs/common/gen_fine_ffs.py.new ./techlibs/common/gen_fine_ffs.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/ecp5/tests/test_diamond_ffs.py
+ touch -r ./techlibs/ecp5/tests/test_diamond_ffs.py ./techlibs/ecp5/tests/test_diamond_ffs.py.new
+ mv ./techlibs/ecp5/tests/test_diamond_ffs.py.new ./techlibs/ecp5/tests/test_diamond_ffs.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/gatemate/make_lut_tree_lib.py
+ touch -r ./techlibs/gatemate/make_lut_tree_lib.py ./techlibs/gatemate/make_lut_tree_lib.py.new
+ mv ./techlibs/gatemate/make_lut_tree_lib.py.new ./techlibs/gatemate/make_lut_tree_lib.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/gowin/cells_xtra.py
+ touch -r ./techlibs/gowin/cells_xtra.py ./techlibs/gowin/cells_xtra.py.new
+ mv ./techlibs/gowin/cells_xtra.py.new ./techlibs/gowin/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/lattice/cells_xtra.py
+ touch -r ./techlibs/lattice/cells_xtra.py ./techlibs/lattice/cells_xtra.py.new
+ mv ./techlibs/lattice/cells_xtra.py.new ./techlibs/lattice/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/nexus/cells_xtra.py
+ touch -r ./techlibs/nexus/cells_xtra.py ./techlibs/nexus/cells_xtra.py.new
+ mv ./techlibs/nexus/cells_xtra.py.new ./techlibs/nexus/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
+ touch -r ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py.new
+ mv ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py.new ./techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./techlibs/xilinx/cells_xtra.py
+ touch -r ./techlibs/xilinx/cells_xtra.py ./techlibs/xilinx/cells_xtra.py.new
+ mv ./techlibs/xilinx/cells_xtra.py.new ./techlibs/xilinx/cells_xtra.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/arch/ecp5/add_sub.py
+ touch -r ./tests/arch/ecp5/add_sub.py ./tests/arch/ecp5/add_sub.py.new
+ mv ./tests/arch/ecp5/add_sub.py.new ./tests/arch/ecp5/add_sub.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/arch/gatemate/gen_luttrees.py
+ touch -r ./tests/arch/gatemate/gen_luttrees.py ./tests/arch/gatemate/gen_luttrees.py.new
+ mv ./tests/arch/gatemate/gen_luttrees.py.new ./tests/arch/gatemate/gen_luttrees.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
+ touch -r ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py.new
+ mv ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py.new ./tests/arch/quicklogic/qlf_k6n10f/mem_gen.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/bram/generate.py
+ touch -r ./tests/bram/generate.py ./tests/bram/generate.py.new
+ mv ./tests/bram/generate.py.new ./tests/bram/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/fsm/generate.py
+ touch -r ./tests/fsm/generate.py ./tests/fsm/generate.py.new
+ mv ./tests/fsm/generate.py.new ./tests/fsm/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/conftest.py
+ touch -r ./tests/functional/conftest.py ./tests/functional/conftest.py.new
+ mv ./tests/functional/conftest.py.new ./tests/functional/conftest.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/rkt_vcd.py
+ touch -r ./tests/functional/rkt_vcd.py ./tests/functional/rkt_vcd.py.new
+ mv ./tests/functional/rkt_vcd.py.new ./tests/functional/rkt_vcd.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/rtlil_cells.py
+ touch -r ./tests/functional/rtlil_cells.py ./tests/functional/rtlil_cells.py.new
+ mv ./tests/functional/rtlil_cells.py.new ./tests/functional/rtlil_cells.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/smt_vcd.py
+ touch -r ./tests/functional/smt_vcd.py ./tests/functional/smt_vcd.py.new
+ mv ./tests/functional/smt_vcd.py.new ./tests/functional/smt_vcd.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/smtio.py
+ touch -r ./tests/functional/smtio.py ./tests/functional/smtio.py.new
+ mv ./tests/functional/smtio.py.new ./tests/functional/smtio.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/functional/test_functional.py
+ touch -r ./tests/functional/test_functional.py ./tests/functional/test_functional.py.new
+ mv ./tests/functional/test_functional.py.new ./tests/functional/test_functional.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/memlib/generate.py
+ touch -r ./tests/memlib/generate.py ./tests/memlib/generate.py.new
+ mv ./tests/memlib/generate.py.new ./tests/memlib/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/opt_share/generate.py
+ touch -r ./tests/opt_share/generate.py ./tests/opt_share/generate.py.new
+ mv ./tests/opt_share/generate.py.new ./tests/opt_share/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/realmath/generate.py
+ touch -r ./tests/realmath/generate.py ./tests/realmath/generate.py.new
+ mv ./tests/realmath/generate.py.new ./tests/realmath/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/rpc/frontend.py
+ touch -r ./tests/rpc/frontend.py ./tests/rpc/frontend.py.new
+ mv ./tests/rpc/frontend.py.new ./tests/rpc/frontend.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/share/generate.py
+ touch -r ./tests/share/generate.py ./tests/share/generate.py.new
+ mv ./tests/share/generate.py.new ./tests/share/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/tools/txt2tikztiming.py
+ touch -r ./tests/tools/txt2tikztiming.py ./tests/tools/txt2tikztiming.py.new
+ mv ./tests/tools/txt2tikztiming.py.new ./tests/tools/txt2tikztiming.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/xprop/generate.py
+ touch -r ./tests/xprop/generate.py ./tests/xprop/generate.py.new
+ mv ./tests/xprop/generate.py.new ./tests/xprop/generate.py
+ for f in `find . -name \*.py`
+ sed 's|/usr/bin/env python3|/usr/bin/python3|' ./tests/xprop/test.py
+ touch -r ./tests/xprop/test.py ./tests/xprop/test.py.new
+ mv ./tests/xprop/test.py.new ./tests/xprop/test.py
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%build): /bin/sh -e /var/tmp/rpm-tmp.8FTJrr
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ make config-gcc
rm -rf share
rm -rf kernel/*.pyh
rm -f kernel/version_f20f913223c42fce6ecc4382b281cf67952e0a72.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o kernel/drivertools.o kernel/functional.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o libs/subcircuit/subcircuit.o frontends/aiger/aigerparse.o frontends/aiger2/xaiger.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/internal_stats.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/cmds/box_derive.o passes/cmds/example_dt.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/hierarchy/keep_hierarchy.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o 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techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/microchip/synth_microchip.o techlibs/microchip/microchip_dffopt.o techlibs/nanoxplore/synth_nanoxplore.o techlibs/nanoxplore/nx_carry.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o frontends/rtlil/rtlil_parser.tab.cc frontends/rtlil/rtlil_parser.tab.hh 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make -C source/code_examples/scrambler clean
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make -C source/code_examples/selections clean
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rm -rf *.dot
rm -f sumprod.out
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make -C source/code_examples/show clean
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make -C source/code_examples/stubnets clean
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rm -f stubnets.so stubnets.d
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make -C source/code_examples/synth_flow clean
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make -C source/code_examples/techmap clean
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rm -rf build/*
rm -rf source/cmd util/__pycache__
rm -rf source/generated
make -C source/_images clean
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echo 'CONFIG := gcc' > Makefile.conf
+ /usr/bin/make -O -j2 V=1 VERBOSE=1 PREFIX=/usr ABCEXTERNAL=/usr/bin/abc PRETTY=0 all
[Makefile.conf] CONFIG := gcc
rm -f kernel/version_*.o kernel/version_*.d kernel/version_*.cc
mkdir -p kernel && echo "namespace Yosys { extern const char *yosys_version_str; const char *yosys_version_str=\"Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)\"; }" > kernel/version_f20f913223c42fce6ecc4382b281cf67952e0a72.cc
mkdir -p techlibs/common
python3 techlibs/common/cellhelp.py techlibs/common/simlib.v > techlibs/common/simlib_help.inc.new
mv techlibs/common/simlib_help.inc.new techlibs/common/simlib_help.inc
mkdir -p techlibs/common
python3 techlibs/common/cellhelp.py techlibs/common/simcells.v > techlibs/common/simcells_help.inc.new
mv techlibs/common/simcells_help.inc.new techlibs/common/simcells_help.inc
mkdir -p kernel/
g++ -o kernel/driver.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/driver.cc
mkdir -p kernel/
g++ -o kernel/log.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_SRC='"./"' kernel/log.cc
mkdir -p kernel/
g++ -o kernel/calc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/calc.cc
kernel/calc.cc: In function ‘Yosys::RTLIL::Const Yosys::RTLIL::const_not(const Const&, const Const&, bool, bool, int)’:
kernel/calc.cc:142:23: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  142 |                 if (i >= arg1_ext.size())
      |                     ~~^~~~~~~~~~~~~~~~~~
kernel/calc.cc: In function ‘Yosys::RTLIL::Const Yosys::logic_wrapper(RTLIL::State (*)(RTLIL::State, RTLIL::State), RTLIL::Const, RTLIL::Const, bool, bool, int)’:
kernel/calc.cc:164:36: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  164 |                 RTLIL::State a = i < arg1.size() ? arg1.bits()[i] : RTLIL::State::S0;
      |                                  ~~^~~~~~~~~~~~~
kernel/calc.cc:165:36: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  165 |                 RTLIL::State b = i < arg2.size() ? arg2.bits()[i] : RTLIL::State::S0;
      |                                  ~~^~~~~~~~~~~~~
kernel/calc.cc: In function ‘Yosys::RTLIL::Const Yosys::logic_reduce_wrapper(RTLIL::State, RTLIL::State (*)(RTLIL::State, RTLIL::State), const RTLIL::Const&, int)’:
kernel/calc.cc:196:30: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  196 |         for (size_t i = 0; i < arg1.size(); i++)
      |                            ~~^~~~~~~~~~~~~
kernel/calc.cc: In function ‘Yosys::RTLIL::Const Yosys::RTLIL::const_eq(const Const&, const Const&, bool, bool, int)’:
kernel/calc.cc:377:30: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  377 |         for (size_t i = 0; i < arg1_ext.size(); i++) {
      |                            ~~^~~~~~~~~~~~~~~~~
kernel/calc.cc: In function ‘Yosys::RTLIL::Const Yosys::RTLIL::const_eqx(const Const&, const Const&, bool, bool, int)’:
kernel/calc.cc:410:30: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  410 |         for (size_t i = 0; i < arg1_ext.size(); i++) {
      |                            ~~^~~~~~~~~~~~~~~~~
mkdir -p kernel/
g++ -o kernel/rtlil.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/rtlil.cc
kernel/rtlil.cc: In member function ‘size_t Yosys::RTLIL::Const::get_min_size(bool) const’:
kernel/rtlil.cc:400:30: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  400 |         if (is_signed && idx < size()) {
      |                          ~~~~^~~~~~~~
mkdir -p kernel/
g++ -o kernel/binding.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/binding.cc
mkdir -p kernel/
g++ -o kernel/yosys.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYOSYS_DATDIR='"/usr/share/yosys"' -DYOSYS_PROGRAM_PREFIX='""' -DABCEXTERNAL='"/usr/bin/abc"' kernel/yosys.cc
mkdir -p kernel/
g++ -o kernel/celledges.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/celledges.cc
mkdir -p kernel/
g++ -o kernel/cellaigs.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cellaigs.cc
mkdir -p kernel/
g++ -o kernel/cost.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/cost.cc
mkdir -p kernel/
g++ -o kernel/scopeinfo.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/scopeinfo.cc
mkdir -p kernel/
g++ -o kernel/qcsat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/qcsat.cc
mkdir -p kernel/
g++ -o kernel/satgen.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/satgen.cc
mkdir -p kernel/
g++ -o kernel/mem.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/mem.cc
mkdir -p kernel/
g++ -o kernel/ffmerge.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ffmerge.cc
mkdir -p kernel/
g++ -o kernel/ff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/ff.cc
mkdir -p kernel/
g++ -o kernel/json.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/json.cc
mkdir -p kernel/
g++ -o kernel/yw.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/yw.cc
mkdir -p kernel/
g++ -o kernel/sexpr.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/sexpr.cc
mkdir -p kernel/
g++ -o kernel/fmt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fmt.cc
mkdir -p kernel/
g++ -o kernel/drivertools.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/drivertools.cc
In file included from ./kernel/yosys_common.h:163,
                 from ./kernel/rtlil.h:23,
                 from ./kernel/drivertools.h:25,
                 from kernel/drivertools.cc:20:
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveChunk::hash() const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
mkdir -p kernel/
g++ -o kernel/fstdata.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/fstdata.cc
mkdir -p libs/bigint/
g++ -o libs/bigint/BigIntegerAlgorithms.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerAlgorithms.cc
mkdir -p libs/bigint/
g++ -o libs/bigint/BigInteger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigInteger.cc
mkdir -p libs/bigint/
g++ -o libs/bigint/BigIntegerUtils.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigIntegerUtils.cc
mkdir -p libs/bigint/
g++ -o libs/bigint/BigUnsigned.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsigned.cc
mkdir -p libs/bigint/
g++ -o libs/bigint/BigUnsignedInABase.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/bigint/BigUnsignedInABase.cc
mkdir -p libs/sha1/
g++ -o libs/sha1/sha1.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/sha1/sha1.cpp
mkdir -p libs/json11/
g++ -o libs/json11/json11.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/json11/json11.cpp
mkdir -p libs/ezsat/
g++ -o libs/ezsat/ezsat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezsat.cc
mkdir -p libs/ezsat/
g++ -o libs/ezsat/ezminisat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/ezsat/ezminisat.cc
mkdir -p libs/minisat/
g++ -o libs/minisat/Options.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Options.cc
mkdir -p kernel/
g++ -o kernel/functional.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/functional.cc
In file included from ./kernel/yosys_common.h:163,
                 from ./kernel/yosys.h:42,
                 from ./kernel/functional.h:24,
                 from kernel/functional.cc:21:
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
In file included from ./kernel/functional.h:26:
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveChunk::hash() const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::do_hash(Yosys::DriveBit const&) const’ at ./kernel/hashlib.h:741:19,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::do_rehash()’ at ./kernel/hashlib.h:752:22,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::pool(Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> > const&)’ at ./kernel/hashlib.h:902:12,
    inlined from ‘Yosys::DriveBitMultiple::DriveBitMultiple(Yosys::DriveBitMultiple const&)’ at ./kernel/drivertools.h:143:8,
    inlined from ‘Yosys::DriveBit::operator=(Yosys::DriveBitMultiple const&)’ at ./kernel/drivertools.h:350:45,
    inlined from ‘Yosys::DriveBit::operator=(Yosys::DriveBit const&) [clone .isra.0]’ at ./kernel/drivertools.h:257:19:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::operator=(Yosys::DriveBit const&) [clone .isra.0]’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveSpec::hash() const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::hash(Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_hash(Yosys::DriveSpec const&) const’ at ./kernel/hashlib.h:284:19,
    inlined from ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_rehash()’ at ./kernel/hashlib.h:295:22:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_rehash()’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::DriveSpec::operator==(Yosys::DriveSpec const&) const’ at ./kernel/drivertools.h:1151:37,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::cmp(Yosys::DriveSpec const&, Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:58:12,
    inlined from ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’ at ./kernel/hashlib.h:362:32:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::DriveSpec::operator==(Yosys::DriveSpec const&) const’ at ./kernel/drivertools.h:1151:53,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::cmp(Yosys::DriveSpec const&, Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:58:12,
    inlined from ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’ at ./kernel/hashlib.h:362:32:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::hashlib::dict<Yosys::DriveSpec, Yosys::Functional::Node, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
mkdir -p libs/minisat/
g++ -o libs/minisat/SimpSolver.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/SimpSolver.cc
mkdir -p libs/minisat/
g++ -o libs/minisat/System.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/System.cc
mkdir -p libs/minisat/
g++ -o libs/minisat/Solver.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/minisat/Solver.cc
mkdir -p libs/fst/
g++ -o libs/fst/fastlz.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fastlz.cc
mkdir -p libs/fst/
g++ -o libs/fst/fstapi.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/fstapi.cc
In function ‘fstWritex(fstReaderContext*, void*, unsigned int)’,
    inlined from ‘fstReaderIterBlocks2’ at libs/fst/fstapi.cc:5812:66:
libs/fst/fstapi.cc:3473:26: warning: ‘write’ reading between 65536 and 4294967295 bytes from a region of size 16 [-Wstringop-overread]
 3473 |                 if (write(xc->writex_fd, s, len)) { };
      |                     ~~~~~^~~~~~~~~~~~~~~~~~~~~~~
libs/fst/fstapi.cc: In function ‘fstReaderIterBlocks2’:
libs/fst/fstapi.cc:5807:62: note: source object ‘vcd_id’ of size 16
 5807 |                                                         char vcd_id[16];
      |                                                              ^~~~~~
In file included from /usr/include/zconf.h:164,
                 from /usr/include/zlib.h:41,
                 from libs/fst/fstapi.h:41,
                 from libs/fst/fstapi.cc:46:
/usr/include/unistd.h:378:16: note: in a call to function ‘write’ declared with attribute ‘access (read_only, 2, 3)’
  378 | extern ssize_t write (int __fd, const void *__buf, size_t __n) __wur
      |                ^~~~~
In function ‘fstWritex(fstReaderContext*, void*, unsigned int)’,
    inlined from ‘fstReaderIterBlocks2’ at libs/fst/fstapi.cc:6073:66:
libs/fst/fstapi.cc:3473:26: warning: ‘write’ reading between 65536 and 4294967295 bytes from a region of size 32 [-Wstringop-overread]
 3473 |                 if (write(xc->writex_fd, s, len)) { };
      |                     ~~~~~^~~~~~~~~~~~~~~~~~~~~~~
libs/fst/fstapi.cc: In function ‘fstReaderIterBlocks2’:
libs/fst/fstapi.cc:6054:62: note: source object ‘wx_buf’ of size 32
 6054 |                                                         char wx_buf[32];
      |                                                              ^~~~~~
/usr/include/unistd.h:378:16: note: in a call to function ‘write’ declared with attribute ‘access (read_only, 2, 3)’
  378 | extern ssize_t write (int __fd, const void *__buf, size_t __n) __wur
      |                ^~~~~
In function ‘fstWritex(fstReaderContext*, void*, unsigned int)’,
    inlined from ‘fstReaderIterBlocks2’ at libs/fst/fstapi.cc:6084:50:
libs/fst/fstapi.cc:3473:26: warning: ‘write’ reading between 65536 and 4294967295 bytes from a region of size 16 [-Wstringop-overread]
 3473 |                 if (write(xc->writex_fd, s, len)) { };
      |                     ~~~~~^~~~~~~~~~~~~~~~~~~~~~~
libs/fst/fstapi.cc: In function ‘fstReaderIterBlocks2’:
libs/fst/fstapi.cc:6080:46: note: source object ‘vcd_id’ of size 16
 6080 |                                         char vcd_id[16];
      |                                              ^~~~~~
/usr/include/unistd.h:378:16: note: in a call to function ‘write’ declared with attribute ‘access (read_only, 2, 3)’
  378 | extern ssize_t write (int __fd, const void *__buf, size_t __n) __wur
      |                ^~~~~
mkdir -p libs/fst/
g++ -o libs/fst/lz4.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/fst/lz4.cc
mkdir -p libs/subcircuit/
g++ -o libs/subcircuit/subcircuit.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER libs/subcircuit/subcircuit.cc
mkdir -p frontends/aiger/
g++ -o frontends/aiger/aigerparse.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger/aigerparse.cc
mkdir -p frontends/aiger2/
g++ -o frontends/aiger2/xaiger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/aiger2/xaiger.cc
frontends/aiger2/xaiger.cc: In member function ‘void {anonymous}::Xaiger2Frontend::read_sc_mapping(std::istream*&, std::string, std::vector<std::__cxx11::basic_string<char> >, Yosys::RTLIL::Design*)’:
frontends/aiger2/xaiger.cc:201:50: warning: variable ‘box_inputs’ set but not used [-Wunused-but-set-variable]
  201 |                                         uint32_t box_inputs, box_outputs, box_id, box_seq;
      |                                                  ^~~~~~~~~~
frontends/aiger2/xaiger.cc:201:75: warning: variable ‘box_id’ set but not used [-Wunused-but-set-variable]
  201 |                                         uint32_t box_inputs, box_outputs, box_id, box_seq;
      |                                                                           ^~~~~~
frontends/aiger2/xaiger.cc:340:62: warning: variable ‘box_outputs’ set but not used [-Wunused-but-set-variable]
  340 |                                         uint32_t box_inputs, box_outputs, box_id, box_seq;
      |                                                              ^~~~~~~~~~~
frontends/aiger2/xaiger.cc:340:75: warning: variable ‘box_id’ set but not used [-Wunused-but-set-variable]
  340 |                                         uint32_t box_inputs, box_outputs, box_id, box_seq;
      |                                                                           ^~~~~~
mkdir -p frontends/ast/
g++ -o frontends/ast/ast.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast.cc
frontends/ast/ast.cc: In member function ‘double Yosys::AST::AstNode::asReal(bool)’:
frontends/ast/ast.cc:1032:38: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
 1032 |                 for (size_t i = 0; i < val.size(); i++)
      |                                    ~~^~~~~~~~~~~~
mkdir -p frontends/ast/
g++ -o frontends/ast/genrtlil.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/genrtlil.cc
mkdir -p frontends/ast/
g++ -o frontends/ast/dpicall.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/dpicall.cc
mkdir -p frontends/ast/
g++ -o frontends/ast/simplify.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/simplify.cc
frontends/ast/simplify.cc: In member function ‘bool Yosys::AST::AstNode::simplify(bool, int, int, bool)’:
frontends/ast/simplify.cc:3496:54: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
 3496 |                                 for (size_t i = 0; i < arg_value.size(); i++)
      |                                                    ~~^~~~~~~~~~~~~~~~~~
frontends/ast/simplify.cc:4342:62: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
 4342 |                                         for (size_t i = 0; i < a.size(); i++)
      |                                                            ~~^~~~~~~~~~
mkdir -p frontends/ast/
g++ -o frontends/ast/ast_binding.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/ast/ast_binding.cc
mkdir -p frontends/blif/
g++ -o frontends/blif/blifparse.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/blif/blifparse.cc
mkdir -p frontends/json/
g++ -o frontends/json/jsonparse.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/json/jsonparse.cc
mkdir -p frontends/rpc/
g++ -o frontends/rpc/rpc_frontend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rpc/rpc_frontend.cc
mkdir -p frontends/rtlil/
bison -o frontends/rtlil/rtlil_parser.tab.cc -d -r all -b frontends/rtlil/rtlil_parser frontends/rtlil/rtlil_parser.y
mkdir -p frontends/rtlil/
flex -o frontends/rtlil/rtlil_lexer.cc frontends/rtlil/rtlil_lexer.l
mkdir -p frontends/liberty/
g++ -o frontends/liberty/liberty.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/liberty/liberty.cc
mkdir -p frontends/rtlil/
g++ -o frontends/rtlil/rtlil_frontend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_frontend.cc
mkdir -p frontends/verilog/
bison -Wall -Werror -o frontends/verilog/verilog_parser.tab.cc -d -r all -b frontends/verilog/verilog_parser frontends/verilog/verilog_parser.y
mkdir -p frontends/verific/
g++ -o frontends/verific/verific.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verific/verific.cc
mkdir -p frontends/verilog/
g++ -o frontends/verilog/verilog_frontend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_frontend.cc
mkdir -p frontends/verilog/
g++ -o frontends/verilog/preproc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/preproc.cc
mkdir -p frontends/verilog/
g++ -o frontends/verilog/const2ast.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/const2ast.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/add.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/add.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/exec.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/exec.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/delete.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/delete.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/design.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/design.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/select.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/select.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/show.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/show.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/rename.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/rename.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/viz.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/viz.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/autoname.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/autoname.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/connect.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connect.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/scatter.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scatter.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/setundef.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setundef.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/splitnets.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitnets.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/splitcells.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splitcells.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/stat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/stat.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/internal_stats.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/internal_stats.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/copy.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/copy.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/setattr.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/setattr.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/splice.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/splice.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/scc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scc.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/glift.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/glift.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/logcmd.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logcmd.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/torder.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/torder.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/write_file.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/write_file.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/tee.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/tee.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/cover.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/cover.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/trace.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/trace.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/connwrappers.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/connwrappers.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/plugin.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/plugin.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/edgetypes.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/edgetypes.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/check.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/check.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/portlist.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/portlist.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/chtype.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chtype.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/chformal.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/chformal.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/blackbox.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/blackbox.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/bugpoint.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/bugpoint.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/scratchpad.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/scratchpad.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/ltp.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/ltp.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/printattrs.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/printattrs.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/logger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/logger.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/sta.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/sta.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/clean_zerowidth.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/clean_zerowidth.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/xprop.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/xprop.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/dft_tag.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/dft_tag.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/box_derive.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/box_derive.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/future.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/future.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_make.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_make.cc
mkdir -p passes/cmds/
g++ -o passes/cmds/example_dt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/cmds/example_dt.cc
In file included from ./kernel/yosys_common.h:163,
                 from ./kernel/yosys.h:42,
                 from passes/cmds/example_dt.cc:1:
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
In file included from passes/cmds/example_dt.cc:2:
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::hash() const’ at ./kernel/hashlib.h:1057:23,
    inlined from ‘Yosys::DriveBitMultiple::hash() const’ at ./kernel/drivertools.h:176:26,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:386:27:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::hash() const’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveChunk::hash() const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveChunk, Yosys::hashlib::hash_ops<Yosys::DriveChunk> >::do_hash(Yosys::DriveChunk const&) const’ at ./kernel/hashlib.h:741:19,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveChunk, Yosys::hashlib::hash_ops<Yosys::DriveChunk> >::do_rehash()’ at ./kernel/hashlib.h:752:22:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::hashlib::pool<Yosys::DriveChunk, Yosys::hashlib::hash_ops<Yosys::DriveChunk> >::do_rehash()’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveSpec::hash() const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveBit::hash() const’ at ./kernel/drivertools.h:389:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveBit>::hash(Yosys::DriveBit const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::do_hash(Yosys::DriveBit const&) const’ at ./kernel/hashlib.h:741:19,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::do_rehash()’ at ./kernel/hashlib.h:752:22,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> >::pool(Yosys::hashlib::pool<Yosys::DriveBit, Yosys::hashlib::hash_ops<Yosys::DriveBit> > const&)’ at ./kernel/hashlib.h:902:12,
    inlined from ‘Yosys::DriveBitMultiple::DriveBitMultiple(Yosys::DriveBitMultiple const&)’ at ./kernel/drivertools.h:143:8,
    inlined from ‘Yosys::DriveBit::operator=(Yosys::DriveBitMultiple const&)’ at ./kernel/drivertools.h:350:45,
    inlined from ‘Yosys::DriveBit::operator=(Yosys::DriveBit const&) [clone .isra.0]’ at ./kernel/drivertools.h:257:19:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::DriveBit::operator=(Yosys::DriveBit const&) [clone .isra.0]’:
./kernel/drivertools.h:367:30: note: ‘inner’ was declared here
  367 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::hash(Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveSpec, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_hash(Yosys::DriveSpec const&) const’ at ./kernel/hashlib.h:741:19,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveSpec, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_rehash()’ at ./kernel/hashlib.h:752:22:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘Yosys::hashlib::pool<Yosys::DriveSpec, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_rehash()’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::DriveSpec::operator==(Yosys::DriveSpec const&) const’ at ./kernel/drivertools.h:1151:37,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::cmp(Yosys::DriveSpec const&, Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:58:12,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveSpec, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’ at ./kernel/hashlib.h:815:32,
    inlined from ‘Yosys::hashlib::idict<Yosys::DriveSpec, 0, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::operator()(Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:1109:29,
    inlined from ‘(anonymous namespace)::ExampleDtPass::execute(std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >, Yosys::RTLIL::Design*)::{lambda(Yosys::DriveSpec const&)#1}::operator()(Yosys::DriveSpec const&) const’ at passes/cmds/example_dt.cc:74:22:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘(anonymous namespace)::ExampleDtPass::execute(std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >, Yosys::RTLIL::Design*)::{lambda(Yosys::DriveSpec const&)#1}::operator()(Yosys::DriveSpec const&) const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
In function ‘Yosys::hashlib::mkhash(unsigned int, unsigned int)’,
    inlined from ‘Yosys::DriveChunk::hash() const’ at ./kernel/drivertools.h:937:16,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveChunk>::hash(Yosys::DriveChunk const&)’ at ./kernel/hashlib.h:61:16,
    inlined from ‘Yosys::hashlib::hash_ops<std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> > >::hash(std::vector<Yosys::DriveChunk, std::allocator<Yosys::DriveChunk> >)’ at ./kernel/hashlib.h:146:14,
    inlined from ‘Yosys::DriveSpec::hash() const’ at ./kernel/drivertools.h:1145:51,
    inlined from ‘Yosys::DriveSpec::operator==(Yosys::DriveSpec const&) const’ at ./kernel/drivertools.h:1151:53,
    inlined from ‘Yosys::hashlib::hash_ops<Yosys::DriveSpec>::cmp(Yosys::DriveSpec const&, Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:58:12,
    inlined from ‘Yosys::hashlib::pool<Yosys::DriveSpec, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::do_lookup(Yosys::DriveSpec const&, int&) const’ at ./kernel/hashlib.h:815:32,
    inlined from ‘Yosys::hashlib::idict<Yosys::DriveSpec, 0, Yosys::hashlib::hash_ops<Yosys::DriveSpec> >::operator()(Yosys::DriveSpec const&)’ at ./kernel/hashlib.h:1109:29,
    inlined from ‘(anonymous namespace)::ExampleDtPass::execute(std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >, Yosys::RTLIL::Design*)::{lambda(Yosys::DriveSpec const&)#1}::operator()(Yosys::DriveSpec const&) const’ at passes/cmds/example_dt.cc:74:22:
./kernel/hashlib.h:30:33: warning: ‘inner’ may be used uninitialized [-Wmaybe-uninitialized]
   30 |         return ((a << 5) + a) ^ b;
      |                                 ^
./kernel/drivertools.h: In member function ‘(anonymous namespace)::ExampleDtPass::execute(std::vector<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> >, std::allocator<std::__cxx11::basic_string<char, std::char_traits<char>, std::allocator<char> > > >, Yosys::RTLIL::Design*)::{lambda(Yosys::DriveSpec const&)#1}::operator()(Yosys::DriveSpec const&) const’:
./kernel/drivertools.h:915:30: note: ‘inner’ was declared here
  915 |                 unsigned int inner;
      |                              ^~~~~
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_miter.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_miter.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_simple.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_simple.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_status.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_status.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_add.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_add.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_remove.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_remove.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_induct.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_induct.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_struct.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_struct.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_purge.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_purge.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_opt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_opt.cc
mkdir -p passes/equiv/
g++ -o passes/equiv/equiv_mark.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/equiv/equiv_mark.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_detect.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_detect.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_extract.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_extract.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_opt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_opt.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_recode.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_recode.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_expand.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_expand.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_info.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_info.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_export.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_export.cc
mkdir -p passes/fsm/
g++ -o passes/fsm/fsm_map.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/fsm/fsm_map.cc
passes/fsm/fsm_map.cc: In function ‘void {anonymous}::implement_pattern_cache(Yosys::RTLIL::Module*, std::map<Yosys::RTLIL::Const, std::set<int> >&, std::set<int>&, int, Yosys::RTLIL::Wire*, Yosys::RTLIL::SigSpec&, Yosys::RTLIL::SigSpec)’:
passes/fsm/fsm_map.cc:57:38: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
   57 |                 for (size_t j = 0; j < pattern.size(); j++)
      |                                    ~~^~~~~~~~~~~~~~~~
passes/fsm/fsm_map.cc: In function ‘void {anonymous}::map_fsm(Yosys::RTLIL::Cell*, Yosys::RTLIL::Module*)’:
passes/fsm/fsm_map.cc:201:38: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  201 |                 for (size_t j = 0; j < state.size(); j++)
      |                                    ~~^~~~~~~~~~~~~~
passes/fsm/fsm_map.cc:264:54: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  264 |                                 for (size_t j = 0; j < state.size(); j++)
      |                                                    ~~^~~~~~~~~~~~~~
mkdir -p passes/hierarchy/
g++ -o passes/hierarchy/uniquify.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/uniquify.cc
mkdir -p passes/hierarchy/
g++ -o passes/hierarchy/hierarchy.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/hierarchy.cc
mkdir -p passes/hierarchy/
g++ -o passes/hierarchy/keep_hierarchy.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/keep_hierarchy.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory.cc
mkdir -p passes/hierarchy/
g++ -o passes/hierarchy/submod.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/hierarchy/submod.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_share.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_share.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_dff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_dff.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_collect.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_collect.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_unpack.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_unpack.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_map.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_map.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_memx.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_memx.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_bram.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bram.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_narrow.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_narrow.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_nordff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_nordff.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_bmux2rom.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_bmux2rom.cc
mkdir -p passes/memory/
g++ -o passes/memory/memlib.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memlib.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt.cc
mkdir -p passes/memory/
g++ -o passes/memory/memory_libmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/memory/memory_libmap.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_mem.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_merge.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_merge.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_mem_feedback.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_feedback.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_mem_widen.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_widen.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_muxtree.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_muxtree.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_mem_priority.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_mem_priority.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_reduce.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_reduce.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_share.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_share.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_dff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_dff.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_clean.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_clean.cc
mkdir -p passes/opt/
g++ -o passes/opt/share.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/share.cc
mkdir -p passes/opt/
g++ -o passes/opt/wreduce.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/wreduce.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_demorgan.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_demorgan.cc
mkdir -p passes/opt/
g++ -o passes/opt/rmports.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/rmports.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_lut.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_lut_ins.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_lut_ins.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_expr.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_expr.cc
mkdir -p passes/opt/
g++ -o passes/opt/opt_ffinv.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/opt_ffinv.cc
mkdir -p passes/opt/
g++ -o passes/opt/muxpack.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/muxpack.cc
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/test_pmgen_pm.h -p test_pmgen passes/pmgen/test_pmgen.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_dsp_pm.h -p ice40_dsp passes/pmgen/ice40_dsp.pmg
mkdir -p passes/pmgen && python3 passes/pmgen/pmgen.py -o passes/pmgen/peepopt_pm.h -p peepopt passes/pmgen/peepopt_shiftmul_right.pmg passes/pmgen/peepopt_shiftmul_left.pmg passes/pmgen/peepopt_shiftadd.pmg passes/pmgen/peepopt_muldiv.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_srl_pm.h -p xilinx_srl passes/pmgen/xilinx_srl.pmg
mkdir -p passes/opt/
g++ -o passes/opt/pmux2shiftx.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/opt/pmux2shiftx.cc
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/ice40_wrapcarry_pm.h -p ice40_wrapcarry passes/pmgen/ice40_wrapcarry.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_pm.h -p xilinx_dsp passes/pmgen/xilinx_dsp.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp48a_pm.h -p xilinx_dsp48a passes/pmgen/xilinx_dsp48a.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_CREG_pm.h -p xilinx_dsp_CREG passes/pmgen/xilinx_dsp_CREG.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/xilinx_dsp_cascade_pm.h -p xilinx_dsp_cascade passes/pmgen/xilinx_dsp_cascade.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/microchip_dsp_pm.h -p microchip_dsp passes/pmgen/microchip_dsp.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/microchip_dsp_CREG_pm.h -p microchip_dsp_CREG passes/pmgen/microchip_dsp_CREG.pmg
mkdir -p passes/pmgen/ && python3 passes/pmgen/pmgen.py -o passes/pmgen/microchip_dsp_cascade_pm.h -p microchip_dsp_cascade passes/pmgen/microchip_dsp_cascade.pmg
mkdir -p passes/pmgen/
g++ -o passes/pmgen/peepopt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/peepopt.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/ice40_dsp.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_dsp.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_prune.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_prune.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_clean.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_clean.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/xilinx_srl.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_srl.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_rmdead.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rmdead.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_init.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_init.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_arst.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_arst.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_rom.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_rom.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_mux.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_mux.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_dlatch.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dlatch.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_memwr.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_memwr.cc
mkdir -p passes/proc/
g++ -o passes/proc/proc_dff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/proc/proc_dff.cc
mkdir -p passes/sat/
g++ -o passes/sat/freduce.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/freduce.cc
mkdir -p passes/sat/
g++ -o passes/sat/sat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sat.cc
mkdir -p passes/sat/
g++ -o passes/sat/eval.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/eval.cc
mkdir -p passes/sat/
g++ -o passes/sat/miter.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/miter.cc
mkdir -p passes/sat/
g++ -o passes/sat/sim.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/sim.cc
mkdir -p passes/sat/
g++ -o passes/sat/assertpmux.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/assertpmux.cc
mkdir -p passes/sat/
g++ -o passes/sat/expose.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/expose.cc
mkdir -p passes/sat/
g++ -o passes/sat/clk2fflogic.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/clk2fflogic.cc
mkdir -p passes/sat/
g++ -o passes/sat/async2sync.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/async2sync.cc
mkdir -p passes/sat/
g++ -o passes/sat/supercover.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/supercover.cc
mkdir -p passes/sat/
g++ -o passes/sat/formalff.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/formalff.cc
mkdir -p passes/sat/
g++ -o passes/sat/fmcombine.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fmcombine.cc
mkdir -p passes/sat/
g++ -o passes/sat/cutpoint.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/cutpoint.cc
mkdir -p passes/sat/
g++ -o passes/sat/fminit.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/fminit.cc
mkdir -p passes/sat/
g++ -o passes/sat/mutate.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/mutate.cc
mkdir -p passes/sat/
g++ -o passes/sat/recover_names.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/recover_names.cc
mkdir -p passes/sat/
g++ -o passes/sat/synthprop.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/synthprop.cc
mkdir -p passes/sat/
g++ -o passes/sat/qbfsat.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/sat/qbfsat.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/flatten.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flatten.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/simplemap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/simplemap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/techmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/techmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/dfflibmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflibmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/maccmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/maccmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/libparse.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/libparse.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/booth.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/booth.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/abc9.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc9.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/abc9_exe.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc9_exe.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/abc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/abc9_ops.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/abc9_ops.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/abc_new.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DABCEXTERNAL='"/usr/bin/abc"' passes/techmap/abc_new.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/clkbufmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/clkbufmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/iopadmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/iopadmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/hilomap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/hilomap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/extract.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/extract_fa.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_fa.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/extract_counter.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_counter.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/extract_reduce.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extract_reduce.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/alumacc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/alumacc.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/dffinit.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffinit.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/pmuxtree.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/pmuxtree.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/bmuxmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bmuxmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/demuxmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/demuxmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/bwmuxmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bwmuxmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/aigmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/aigmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/muxcover.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/muxcover.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/lut2mux.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/lut2mux.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/tribuf.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/tribuf.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/nlutmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/nlutmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/shregmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/shregmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/deminout.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/deminout.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/insbuf.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/insbuf.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/bufnorm.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/bufnorm.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/attrmvcp.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmvcp.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/attrmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/attrmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/zinit.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/zinit.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/dffunmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dffunmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/dfflegalize.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/dfflegalize.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/extractinv.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/extractinv.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/flowmap.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/flowmap.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/cellmatch.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/cellmatch.cc
mkdir -p passes/techmap/
g++ -o passes/techmap/clockgate.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/clockgate.cc
mkdir -p passes/tests/
g++ -o passes/tests/test_autotb.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_autotb.cc
mkdir -p passes/tests/
g++ -o passes/tests/test_abcloop.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_abcloop.cc
mkdir -p passes/tests/
g++ -o passes/tests/test_cell.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/tests/test_cell.cc
mkdir -p backends/aiger/
g++ -o backends/aiger/aiger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/aiger.cc
mkdir -p backends/aiger/
g++ -o backends/aiger/xaiger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger/xaiger.cc
mkdir -p backends/aiger2/
g++ -o backends/aiger2/aiger.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/aiger2/aiger.cc
backends/aiger2/aiger.cc: In member function ‘(anonymous namespace)::Index<(anonymous namespace)::XAigerAnalysis, int, 0, 0>::impl_op((anonymous namespace)::Index<(anonymous namespace)::XAigerAnalysis, int, 0, 0>::HierCursor&, Yosys::RTLIL::Cell*, Yosys::RTLIL::IdString, int)’:
backends/aiger2/aiger.cc:273:43: warning: ‘a’ may be used uninitialized [-Wmaybe-uninitialized]
  273 |                                 return XOR(carry, XNOR(a, b));
      |                                        ~~~^~~~~~~~~~~~~~~~~~~
backends/aiger2/aiger.cc:265:37: note: ‘a’ was declared here
  265 |                                 Lit a, b;
      |                                     ^
backends/aiger2/aiger.cc:273:43: warning: ‘b’ may be used uninitialized [-Wmaybe-uninitialized]
  273 |                                 return XOR(carry, XNOR(a, b));
      |                                        ~~~^~~~~~~~~~~~~~~~~~~
backends/aiger2/aiger.cc:265:40: note: ‘b’ was declared here
  265 |                                 Lit a, b;
      |                                        ^
In function ‘(anonymous namespace)::AigerWriter::negate(unsigned int)’,
    inlined from ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::NOT(unsigned int)’ at backends/aiger2/aiger.cc:173:24,
    inlined from ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::XNOR(unsigned int, unsigned int)’ at backends/aiger2/aiger.cc:202:13,
    inlined from ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::impl_op((anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::HierCursor&, Yosys::RTLIL::Cell*, Yosys::RTLIL::IdString, int)’ at backends/aiger2/aiger.cc:273:15:
backends/aiger2/aiger.cc:672:30: warning: ‘a’ may be used uninitialized [-Wmaybe-uninitialized]
  672 |                 return lit ^ 1;
      |                              ^
backends/aiger2/aiger.cc: In member function ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::impl_op((anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::HierCursor&, Yosys::RTLIL::Cell*, Yosys::RTLIL::IdString, int)’:
backends/aiger2/aiger.cc:265:37: note: ‘a’ was declared here
  265 |                                 Lit a, b;
      |                                     ^
In member function ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::XNOR(unsigned int, unsigned int)’,
    inlined from ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::impl_op((anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::HierCursor&, Yosys::RTLIL::Cell*, Yosys::RTLIL::IdString, int)’ at backends/aiger2/aiger.cc:273:15:
backends/aiger2/aiger.cc:202:27: warning: ‘b’ may be used uninitialized [-Wmaybe-uninitialized]
  202 |                 return NOT(OR(AND(a, NOT(b)), AND(NOT(a), b)));
      |                        ~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
backends/aiger2/aiger.cc: In member function ‘(anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::impl_op((anonymous namespace)::Index<(anonymous namespace)::AigerWriter, unsigned int, 0u, 1u>::HierCursor&, Yosys::RTLIL::Cell*, Yosys::RTLIL::IdString, int)’:
backends/aiger2/aiger.cc:265:40: note: ‘b’ was declared here
  265 |                                 Lit a, b;
      |                                        ^
mkdir -p backends/blif/
g++ -o backends/blif/blif.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/blif/blif.cc
mkdir -p backends/btor/
g++ -o backends/btor/btor.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/btor/btor.cc
mkdir -p backends/cxxrtl/
g++ -o backends/cxxrtl/cxxrtl_backend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/cxxrtl/cxxrtl_backend.cc
mkdir -p backends/edif/
g++ -o backends/edif/edif.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/edif/edif.cc
backends/edif/edif.cc: In lambda function:
backends/edif/edif.cc:341:54: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  341 |                                 for (size_t i = 0; i < val.size(); i += 4) {
      |                                                    ~~^~~~~~~~~~~~
backends/edif/edif.cc:343:49: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  343 |                                         if (i+0 < val.size() && val.at(i+0) == RTLIL::State::S1) digit_value |= 1;
      |                                             ~~~~^~~~~~~~~~~~
backends/edif/edif.cc:344:49: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  344 |                                         if (i+1 < val.size() && val.at(i+1) == RTLIL::State::S1) digit_value |= 2;
      |                                             ~~~~^~~~~~~~~~~~
backends/edif/edif.cc:345:49: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  345 |                                         if (i+2 < val.size() && val.at(i+2) == RTLIL::State::S1) digit_value |= 4;
      |                                             ~~~~^~~~~~~~~~~~
backends/edif/edif.cc:346:49: warning: comparison of integer expressions of different signedness: ‘size_t’ {aka ‘long unsigned int’} and ‘int’ [-Wsign-compare]
  346 |                                         if (i+3 < val.size() && val.at(i+3) == RTLIL::State::S1) digit_value |= 8;
      |                                             ~~~~^~~~~~~~~~~~
mkdir -p backends/functional/
g++ -o backends/functional/cxx.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/functional/cxx.cc
mkdir -p backends/firrtl/
g++ -o backends/firrtl/firrtl.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/firrtl/firrtl.cc
mkdir -p backends/functional/
g++ -o backends/functional/smtlib_rosette.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/functional/smtlib_rosette.cc
mkdir -p backends/functional/
g++ -o backends/functional/smtlib.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/functional/smtlib.cc
mkdir -p backends/functional/
g++ -o backends/functional/test_generic.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/functional/test_generic.cc
mkdir -p backends/jny/
g++ -o backends/jny/jny.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/jny/jny.cc
mkdir -p backends/intersynth/
g++ -o backends/intersynth/intersynth.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/intersynth/intersynth.cc
mkdir -p backends/rtlil/
g++ -o backends/rtlil/rtlil_backend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/rtlil/rtlil_backend.cc
mkdir -p backends/json/
g++ -o backends/json/json.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/json/json.cc
mkdir -p backends/simplec/
g++ -o backends/simplec/simplec.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/simplec/simplec.cc
mkdir -p backends/smt2/
g++ -o backends/smt2/smt2.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smt2/smt2.cc
mkdir -p backends/smv/
g++ -o backends/smv/smv.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/smv/smv.cc
mkdir -p backends/spice/
g++ -o backends/spice/spice.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/spice/spice.cc
mkdir -p backends/table/
g++ -o backends/table/table.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/table/table.cc
mkdir -p techlibs/achronix/
g++ -o techlibs/achronix/synth_achronix.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/achronix/synth_achronix.cc
mkdir -p techlibs/anlogic/
g++ -o techlibs/anlogic/synth_anlogic.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/synth_anlogic.cc
mkdir -p techlibs/anlogic/
g++ -o techlibs/anlogic/anlogic_eqn.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_eqn.cc
mkdir -p techlibs/anlogic/
g++ -o techlibs/anlogic/anlogic_fixcarry.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/anlogic/anlogic_fixcarry.cc
mkdir -p techlibs/common/
g++ -o techlibs/common/synth.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/synth.cc
mkdir -p backends/verilog/
g++ -o backends/verilog/verilog_backend.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER backends/verilog/verilog_backend.cc
mkdir -p techlibs/common/
g++ -o techlibs/common/prep.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/common/prep.cc
mkdir -p techlibs/coolrunner2/
g++ -o techlibs/coolrunner2/synth_coolrunner2.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/synth_coolrunner2.cc
mkdir -p techlibs/coolrunner2/
g++ -o techlibs/coolrunner2/coolrunner2_sop.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_sop.cc
mkdir -p techlibs/coolrunner2/
g++ -o techlibs/coolrunner2/coolrunner2_fixup.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/coolrunner2/coolrunner2_fixup.cc
mkdir -p techlibs/easic/
g++ -o techlibs/easic/synth_easic.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/easic/synth_easic.cc
mkdir -p techlibs/efinix/
g++ -o techlibs/efinix/synth_efinix.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/synth_efinix.cc
mkdir -p techlibs/ecp5/
g++ -o techlibs/ecp5/synth_ecp5.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ecp5/synth_ecp5.cc
mkdir -p techlibs/fabulous/
g++ -o techlibs/fabulous/synth_fabulous.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/fabulous/synth_fabulous.cc
mkdir -p techlibs/efinix/
g++ -o techlibs/efinix/efinix_fixcarry.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/efinix/efinix_fixcarry.cc
mkdir -p techlibs/gatemate/
g++ -o techlibs/gatemate/synth_gatemate.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/synth_gatemate.cc
mkdir -p techlibs/gowin/
g++ -o techlibs/gowin/synth_gowin.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gowin/synth_gowin.cc
mkdir -p techlibs/gatemate/
g++ -o techlibs/gatemate/gatemate_foldinv.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/gatemate/gatemate_foldinv.cc
mkdir -p techlibs/greenpak4/
g++ -o techlibs/greenpak4/synth_greenpak4.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/synth_greenpak4.cc
mkdir -p techlibs/greenpak4/
g++ -o techlibs/greenpak4/greenpak4_dffinv.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/greenpak4/greenpak4_dffinv.cc
mkdir -p techlibs/ice40/
g++ -o techlibs/ice40/synth_ice40.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/synth_ice40.cc
mkdir -p techlibs/ice40/
g++ -o techlibs/ice40/ice40_braminit.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_braminit.cc
mkdir -p techlibs/intel/
g++ -o techlibs/intel/synth_intel.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel/synth_intel.cc
mkdir -p techlibs/ice40/
g++ -o techlibs/ice40/ice40_opt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/ice40/ice40_opt.cc
mkdir -p techlibs/intel_alm/
g++ -o techlibs/intel_alm/synth_intel_alm.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/intel_alm/synth_intel_alm.cc
mkdir -p techlibs/lattice/
g++ -o techlibs/lattice/synth_lattice.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/lattice/synth_lattice.cc
mkdir -p techlibs/lattice/
g++ -o techlibs/lattice/lattice_gsr.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/lattice/lattice_gsr.cc
mkdir -p techlibs/microchip/
g++ -o techlibs/microchip/synth_microchip.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/microchip/synth_microchip.cc
mkdir -p techlibs/nanoxplore/
g++ -o techlibs/nanoxplore/synth_nanoxplore.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nanoxplore/synth_nanoxplore.cc
mkdir -p techlibs/microchip/
g++ -o techlibs/microchip/microchip_dffopt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/microchip/microchip_dffopt.cc
mkdir -p techlibs/nanoxplore/
g++ -o techlibs/nanoxplore/nx_carry.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nanoxplore/nx_carry.cc
mkdir -p techlibs/nexus/
g++ -o techlibs/nexus/synth_nexus.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/nexus/synth_nexus.cc
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/synth_quicklogic.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/synth_quicklogic.cc
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/ql_bram_merge.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_bram_merge.cc
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/ql_bram_types.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_bram_types.cc
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/ql_dsp_io_regs.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_io_regs.cc
mkdir -p techlibs/quicklogic/ && python3 passes/pmgen/pmgen.py -o techlibs/quicklogic/ql_dsp_macc_pm.h -p ql_dsp_macc techlibs/quicklogic/ql_dsp_macc.pmg
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/ql_dsp_simd.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_simd.cc
In file included from techlibs/quicklogic/ql_dsp_simd.cc:19:
techlibs/quicklogic/ql_dsp_simd.cc: In member function ‘virtual void {anonymous}::QlDspSimdPass::execute(std::vector<std::__cxx11::basic_string<char> >, Yosys::RTLIL::Design*)’:
techlibs/quicklogic/ql_dsp_simd.cc:213:69: warning: comparison of integer expressions of different signedness: ‘int’ and ‘const size_t’ {aka ‘const long unsigned int’} [-Wsign-compare]
  213 |                                         log_assert(mode_bits.size() == m_ModeBitsSize);
      |                                                    ~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~
./kernel/log.h:226:78: note: in definition of macro ‘log_assert’
  226 | #  define log_assert(_assert_expr_) YOSYS_NAMESPACE_PREFIX log_assert_worker(_assert_expr_, #_assert_expr_, __FILE__, __LINE__)
      |                                                                              ^~~~~~~~~~~~~
mkdir -p techlibs/sf2/
g++ -o techlibs/sf2/synth_sf2.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/sf2/synth_sf2.cc
mkdir -p techlibs/xilinx/
g++ -o techlibs/xilinx/synth_xilinx.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/synth_xilinx.cc
sed -e 's#@CXXFLAGS@#-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -Wall -Wextra -ggdb -I"/usr/include/yosys" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER#;' \
		-e 's#@CXX@#g++#;' -e 's#@LINKFLAGS@#-rdynamic#;' -e 's#@LIBS@#-lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64 -lffi -ldl -lz -ltcl8.6 -ltclstub8.6#;' \
		-e 's#@BINDIR@#/usr/bin#;' -e 's#@DATDIR@#/usr/share/yosys#;' < misc/yosys-config.in > yosys-config
chmod +x yosys-config
mkdir -p passes/techmap/
g++ -o passes/techmap/filterlib.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/techmap/filterlib.cc
sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < backends/smt2/smtbmc.py > yosys-smtbmc.new
chmod +x yosys-smtbmc.new
mv yosys-smtbmc.new yosys-smtbmc
sed 's|##yosys-sys-path##|sys.path += [os.path.dirname(os.path.realpath(__file__)) + p for p in ["/share/python3", "/../share/yosys/python3"]]|;' < backends/smt2/witness.py > yosys-witness.new
chmod +x yosys-witness.new
mv yosys-witness.new yosys-witness
mkdir -p share/include/kernel/
cp "./"/kernel/binding.h share/include/kernel/binding.h
mkdir -p share/include/kernel/
cp "./"/kernel/bitpattern.h share/include/kernel/bitpattern.h
mkdir -p share/include/kernel/
cp "./"/kernel/cellaigs.h share/include/kernel/cellaigs.h
mkdir -p share/include/kernel/
cp "./"/kernel/celledges.h share/include/kernel/celledges.h
mkdir -p share/include/kernel/
cp "./"/kernel/celltypes.h share/include/kernel/celltypes.h
mkdir -p share/include/kernel/
cp "./"/kernel/consteval.h share/include/kernel/consteval.h
mkdir -p share/include/kernel/
cp "./"/kernel/constids.inc share/include/kernel/constids.inc
mkdir -p share/include/kernel/
cp "./"/kernel/cost.h share/include/kernel/cost.h
mkdir -p share/include/kernel/
cp "./"/kernel/drivertools.h share/include/kernel/drivertools.h
mkdir -p share/include/kernel/
cp "./"/kernel/ff.h share/include/kernel/ff.h
mkdir -p share/include/kernel/
cp "./"/kernel/ffinit.h share/include/kernel/ffinit.h
mkdir -p share/include/kernel/
cp "./"/kernel/ffmerge.h share/include/kernel/ffmerge.h
mkdir -p share/include/kernel/
cp "./"/kernel/fmt.h share/include/kernel/fmt.h
mkdir -p share/include/kernel/
cp "./"/kernel/fstdata.h share/include/kernel/fstdata.h
mkdir -p share/include/kernel/
cp "./"/kernel/hashlib.h share/include/kernel/hashlib.h
mkdir -p share/include/kernel/
cp "./"/kernel/json.h share/include/kernel/json.h
mkdir -p share/include/kernel/
cp "./"/kernel/log.h share/include/kernel/log.h
mkdir -p share/include/kernel/
cp "./"/kernel/macc.h share/include/kernel/macc.h
mkdir -p share/include/kernel/
cp "./"/kernel/modtools.h share/include/kernel/modtools.h
mkdir -p share/include/kernel/
cp "./"/kernel/mem.h share/include/kernel/mem.h
mkdir -p share/include/kernel/
cp "./"/kernel/qcsat.h share/include/kernel/qcsat.h
mkdir -p share/include/kernel/
cp "./"/kernel/register.h share/include/kernel/register.h
mkdir -p share/include/kernel/
cp "./"/kernel/rtlil.h share/include/kernel/rtlil.h
mkdir -p share/include/kernel/
cp "./"/kernel/satgen.h share/include/kernel/satgen.h
mkdir -p share/include/kernel/
cp "./"/kernel/scopeinfo.h share/include/kernel/scopeinfo.h
mkdir -p share/include/kernel/
cp "./"/kernel/sexpr.h share/include/kernel/sexpr.h
mkdir -p share/include/kernel/
cp "./"/kernel/sigtools.h share/include/kernel/sigtools.h
mkdir -p share/include/kernel/
cp "./"/kernel/timinginfo.h share/include/kernel/timinginfo.h
mkdir -p share/include/kernel/
cp "./"/kernel/utils.h share/include/kernel/utils.h
mkdir -p share/include/kernel/
cp "./"/kernel/yosys.h share/include/kernel/yosys.h
mkdir -p share/include/kernel/
cp "./"/kernel/yosys_common.h share/include/kernel/yosys_common.h
mkdir -p share/include/kernel/
cp "./"/kernel/yw.h share/include/kernel/yw.h
mkdir -p share/include/libs/ezsat/
cp "./"/libs/ezsat/ezsat.h share/include/libs/ezsat/ezsat.h
mkdir -p share/include/libs/ezsat/
cp "./"/libs/ezsat/ezminisat.h share/include/libs/ezsat/ezminisat.h
mkdir -p share/include/libs/fst/
cp "./"/libs/fst/fstapi.h share/include/libs/fst/fstapi.h
mkdir -p share/include/libs/sha1/
cp "./"/libs/sha1/sha1.h share/include/libs/sha1/sha1.h
mkdir -p share/include/libs/json11/
cp "./"/libs/json11/json11.hpp share/include/libs/json11/json11.hpp
mkdir -p share/include/passes/fsm/
cp "./"/passes/fsm/fsmdata.h share/include/passes/fsm/fsmdata.h
mkdir -p share/include/frontends/ast/
cp "./"/frontends/ast/ast.h share/include/frontends/ast/ast.h
mkdir -p share/include/frontends/ast/
cp "./"/frontends/ast/ast_binding.h share/include/frontends/ast/ast_binding.h
mkdir -p share/include/frontends/blif/
cp "./"/frontends/blif/blifparse.h share/include/frontends/blif/blifparse.h
mkdir -p share/include/backends/rtlil/
cp "./"/backends/rtlil/rtlil_backend.h share/include/backends/rtlil/rtlil_backend.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_vcd.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_time.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/
cp "./"/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h share/include/backends/cxxrtl/runtime/cxxrtl/cxxrtl_replay.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.cc
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi.h
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.cc
mkdir -p share/include/backends/cxxrtl/runtime/cxxrtl/capi/
cp "./"/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h share/include/backends/cxxrtl/runtime/cxxrtl/capi/cxxrtl_capi_vcd.h
mkdir -p share/python3
cp "./"/backends/smt2/smtio.py share/python3/smtio.py
mkdir -p share/python3
cp "./"/backends/smt2/ywio.py share/python3/ywio.py
mkdir -p share/achronix/speedster22i/
cp "./"/techlibs/achronix/speedster22i/cells_sim.v share/achronix/speedster22i/cells_sim.v
mkdir -p share/achronix/speedster22i/
cp "./"/techlibs/achronix/speedster22i/cells_map.v share/achronix/speedster22i/cells_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/cells_map.v share/anlogic/cells_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/arith_map.v share/anlogic/arith_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/cells_sim.v share/anlogic/cells_sim.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/eagle_bb.v share/anlogic/eagle_bb.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/lutrams.txt share/anlogic/lutrams.txt
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/lutrams_map.v share/anlogic/lutrams_map.v
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/brams.txt share/anlogic/brams.txt
mkdir -p share/anlogic
cp "./"/techlibs/anlogic/brams_map.v share/anlogic/brams_map.v
mkdir -p share
cp "./"/techlibs/common/simlib.v share/simlib.v
mkdir -p share
cp "./"/techlibs/common/simcells.v share/simcells.v
mkdir -p share
cp "./"/techlibs/common/techmap.v share/techmap.v
mkdir -p share
cp "./"/techlibs/common/smtmap.v share/smtmap.v
mkdir -p share
cp "./"/techlibs/common/pmux2mux.v share/pmux2mux.v
mkdir -p share
cp "./"/techlibs/common/adff2dff.v share/adff2dff.v
mkdir -p share
cp "./"/techlibs/common/dff2ff.v share/dff2ff.v
mkdir -p share
cp "./"/techlibs/common/gate2lut.v share/gate2lut.v
mkdir -p share
cp "./"/techlibs/common/cmp2lut.v share/cmp2lut.v
mkdir -p share
cp "./"/techlibs/common/cells.lib share/cells.lib
mkdir -p share
cp "./"/techlibs/common/mul2dsp.v share/mul2dsp.v
mkdir -p share
cp "./"/techlibs/common/abc9_model.v share/abc9_model.v
mkdir -p share
cp "./"/techlibs/common/abc9_map.v share/abc9_map.v
mkdir -p share
cp "./"/techlibs/common/abc9_unmap.v share/abc9_unmap.v
mkdir -p share
cp "./"/techlibs/common/cmp2lcu.v share/cmp2lcu.v
mkdir -p share
cp "./"/techlibs/common/cmp2softlogic.v share/cmp2softlogic.v
mkdir -p share/choices
cp "./"/techlibs/common/choices/kogge-stone.v share/choices/kogge-stone.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_latch.v share/coolrunner2/cells_latch.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_sim.v share/coolrunner2/cells_sim.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/cells_counter_map.v share/coolrunner2/cells_counter_map.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/tff_extract.v share/coolrunner2/tff_extract.v
mkdir -p share/coolrunner2
cp "./"/techlibs/coolrunner2/xc2_dff.lib share/coolrunner2/xc2_dff.lib
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_ff.vh share/ecp5/cells_ff.vh
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_io.vh share/ecp5/cells_io.vh
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_map.v share/ecp5/cells_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_sim.v share/ecp5/cells_sim.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/cells_bb.v share/ecp5/cells_bb.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/lutrams_map.v share/ecp5/lutrams_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/lutrams.txt share/ecp5/lutrams.txt
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/brams_map.v share/ecp5/brams_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/brams.txt share/ecp5/brams.txt
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/arith_map.v share/ecp5/arith_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/latches_map.v share/ecp5/latches_map.v
mkdir -p share/ecp5
cp "./"/techlibs/ecp5/dsp_map.v share/ecp5/dsp_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/cells_map.v share/efinix/cells_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/arith_map.v share/efinix/arith_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/cells_sim.v share/efinix/cells_sim.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/brams_map.v share/efinix/brams_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/gbuf_map.v share/efinix/gbuf_map.v
mkdir -p share/efinix
cp "./"/techlibs/efinix/brams.txt share/efinix/brams.txt
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/cells_map.v share/fabulous/cells_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/prims.v share/fabulous/prims.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/latches_map.v share/fabulous/latches_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/ff_map.v share/fabulous/ff_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/ram_regfile.txt share/fabulous/ram_regfile.txt
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/regfile_map.v share/fabulous/regfile_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/io_map.v share/fabulous/io_map.v
mkdir -p share/fabulous
cp "./"/techlibs/fabulous/arith_map.v share/fabulous/arith_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/reg_map.v share/gatemate/reg_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/mux_map.v share/gatemate/mux_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/lut_map.v share/gatemate/lut_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/mul_map.v share/gatemate/mul_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/arith_map.v share/gatemate/arith_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/cells_sim.v share/gatemate/cells_sim.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/cells_bb.v share/gatemate/cells_bb.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_map.v share/gatemate/brams_map.v
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams.txt share/gatemate/brams.txt
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_init_20.vh share/gatemate/brams_init_20.vh
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/brams_init_40.vh share/gatemate/brams_init_40.vh
mkdir -p share/gatemate
cp "./"/techlibs/gatemate/inv_map.v share/gatemate/inv_map.v
mkdir -p techlibs/gatemate
python3 techlibs/gatemate/make_lut_tree_lib.py
touch techlibs/gatemate/lut_tree_lib.mk
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_map.v share/gowin/cells_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_sim.v share/gowin/cells_sim.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/cells_xtra.v share/gowin/cells_xtra.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/arith_map.v share/gowin/arith_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/brams_map.v share/gowin/brams_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/brams.txt share/gowin/brams.txt
mkdir -p share/gowin
cp "./"/techlibs/gowin/lutrams_map.v share/gowin/lutrams_map.v
mkdir -p share/gowin
cp "./"/techlibs/gowin/lutrams.txt share/gowin/lutrams.txt
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_blackbox.v share/greenpak4/cells_blackbox.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_latch.v share/greenpak4/cells_latch.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_map.v share/greenpak4/cells_map.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim.v share/greenpak4/cells_sim.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_ams.v share/greenpak4/cells_sim_ams.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_digital.v share/greenpak4/cells_sim_digital.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/cells_sim_wip.v share/greenpak4/cells_sim_wip.v
mkdir -p share/greenpak4
cp "./"/techlibs/greenpak4/gp_dff.lib share/greenpak4/gp_dff.lib
mkdir -p share/ice40
cp "./"/techlibs/ice40/arith_map.v share/ice40/arith_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/cells_map.v share/ice40/cells_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/ff_map.v share/ice40/ff_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/cells_sim.v share/ice40/cells_sim.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/latches_map.v share/ice40/latches_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/brams.txt share/ice40/brams.txt
mkdir -p share/ice40
cp "./"/techlibs/ice40/brams_map.v share/ice40/brams_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/spram.txt share/ice40/spram.txt
mkdir -p share/ice40
cp "./"/techlibs/ice40/spram_map.v share/ice40/spram_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/dsp_map.v share/ice40/dsp_map.v
mkdir -p share/ice40
cp "./"/techlibs/ice40/abc9_model.v share/ice40/abc9_model.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/m9k_bb.v share/intel/common/m9k_bb.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/altpll_bb.v share/intel/common/altpll_bb.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/brams_m9k.txt share/intel/common/brams_m9k.txt
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/brams_map_m9k.v share/intel/common/brams_map_m9k.v
mkdir -p share/intel/common
cp "./"/techlibs/intel/common/ff_map.v share/intel/common/ff_map.v
mkdir -p share/intel/max10
cp "./"/techlibs/intel/max10/cells_sim.v share/intel/max10/cells_sim.v
mkdir -p share/intel/cyclone10lp
cp "./"/techlibs/intel/cyclone10lp/cells_sim.v share/intel/cyclone10lp/cells_sim.v
mkdir -p share/intel/cycloneiv
cp "./"/techlibs/intel/cycloneiv/cells_sim.v share/intel/cycloneiv/cells_sim.v
mkdir -p share/intel/cycloneive
cp "./"/techlibs/intel/cycloneive/cells_sim.v share/intel/cycloneive/cells_sim.v
mkdir -p share/intel/max10
cp "./"/techlibs/intel/max10/cells_map.v share/intel/max10/cells_map.v
mkdir -p share/intel/cyclone10lp
cp "./"/techlibs/intel/cyclone10lp/cells_map.v share/intel/cyclone10lp/cells_map.v
mkdir -p share/intel/cycloneiv
cp "./"/techlibs/intel/cycloneiv/cells_map.v share/intel/cycloneiv/cells_map.v
mkdir -p share/intel/cycloneive
cp "./"/techlibs/intel/cycloneive/cells_map.v share/intel/cycloneive/cells_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_map.v share/intel_alm/common/abc9_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_unmap.v share/intel_alm/common/abc9_unmap.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/abc9_model.v share/intel_alm/common/abc9_model.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/alm_map.v share/intel_alm/common/alm_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/alm_sim.v share/intel_alm/common/alm_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/arith_alm_map.v share/intel_alm/common/arith_alm_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dff_map.v share/intel_alm/common/dff_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dff_sim.v share/intel_alm/common/dff_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dsp_sim.v share/intel_alm/common/dsp_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/dsp_map.v share/intel_alm/common/dsp_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/mem_sim.v share/intel_alm/common/mem_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/misc_sim.v share/intel_alm/common/misc_sim.v
mkdir -p share/intel_alm/cyclonev
cp "./"/techlibs/intel_alm/cyclonev/cells_sim.v share/intel_alm/cyclonev/cells_sim.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m10k.txt share/intel_alm/common/bram_m10k.txt
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/bram_m10k_map.v share/intel_alm/common/bram_m10k_map.v
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/lutram_mlab.txt share/intel_alm/common/lutram_mlab.txt
mkdir -p share/intel_alm/common
cp "./"/techlibs/intel_alm/common/megafunction_bb.v share/intel_alm/common/megafunction_bb.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_ff.vh share/lattice/cells_ff.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_io.vh share/lattice/cells_io.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_map.v share/lattice/cells_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/common_sim.vh share/lattice/common_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/ccu2d_sim.vh share/lattice/ccu2d_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/ccu2c_sim.vh share/lattice/ccu2c_sim.vh
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_ecp5.v share/lattice/cells_sim_ecp5.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo2.v share/lattice/cells_sim_xo2.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo3.v share/lattice/cells_sim_xo3.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_sim_xo3d.v share/lattice/cells_sim_xo3d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_ecp5.v share/lattice/cells_bb_ecp5.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo2.v share/lattice/cells_bb_xo2.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo3.v share/lattice/cells_bb_xo3.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/cells_bb_xo3d.v share/lattice/cells_bb_xo3d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/lutrams_map.v share/lattice/lutrams_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/lutrams.txt share/lattice/lutrams.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_map_16kd.v share/lattice/brams_map_16kd.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_16kd.txt share/lattice/brams_16kd.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_map_8kc.v share/lattice/brams_map_8kc.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/brams_8kc.txt share/lattice/brams_8kc.txt
mkdir -p share/lattice
cp "./"/techlibs/lattice/arith_map_ccu2c.v share/lattice/arith_map_ccu2c.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/arith_map_ccu2d.v share/lattice/arith_map_ccu2d.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/latches_map.v share/lattice/latches_map.v
mkdir -p share/lattice
cp "./"/techlibs/lattice/dsp_map_18x18.v share/lattice/dsp_map_18x18.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/arith_map.v share/microchip/arith_map.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/cells_map.v share/microchip/cells_map.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/cells_sim.v share/microchip/cells_sim.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/polarfire_dsp_map.v share/microchip/polarfire_dsp_map.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/brams_defs.vh share/microchip/brams_defs.vh
mkdir -p share/microchip
cp "./"/techlibs/microchip/LSRAM_map.v share/microchip/LSRAM_map.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/LSRAM.txt share/microchip/LSRAM.txt
mkdir -p share/microchip
cp "./"/techlibs/microchip/uSRAM_map.v share/microchip/uSRAM_map.v
mkdir -p share/microchip
cp "./"/techlibs/microchip/uSRAM.txt share/microchip/uSRAM.txt
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/arith_map.v share/nanoxplore/arith_map.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/brams_init.vh share/nanoxplore/brams_init.vh
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/brams_map.v share/nanoxplore/brams_map.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/brams.txt share/nanoxplore/brams.txt
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_bb.v share/nanoxplore/cells_bb.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_bb_l.v share/nanoxplore/cells_bb_l.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_bb_m.v share/nanoxplore/cells_bb_m.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_bb_u.v share/nanoxplore/cells_bb_u.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_map.v share/nanoxplore/cells_map.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_sim.v share/nanoxplore/cells_sim.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_sim_l.v share/nanoxplore/cells_sim_l.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_sim_m.v share/nanoxplore/cells_sim_m.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_sim_u.v share/nanoxplore/cells_sim_u.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_wrap.v share/nanoxplore/cells_wrap.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_wrap_l.v share/nanoxplore/cells_wrap_l.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_wrap_m.v share/nanoxplore/cells_wrap_m.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/cells_wrap_u.v share/nanoxplore/cells_wrap_u.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/io_map.v share/nanoxplore/io_map.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/latches_map.v share/nanoxplore/latches_map.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_init.vh share/nanoxplore/rf_init.vh
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_l.txt share/nanoxplore/rf_rams_l.txt
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_m.txt share/nanoxplore/rf_rams_m.txt
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_u.txt share/nanoxplore/rf_rams_u.txt
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_map_l.v share/nanoxplore/rf_rams_map_l.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_map_m.v share/nanoxplore/rf_rams_map_m.v
mkdir -p share/nanoxplore
cp "./"/techlibs/nanoxplore/rf_rams_map_u.v share/nanoxplore/rf_rams_map_u.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_map.v share/nexus/cells_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_sim.v share/nexus/cells_sim.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/parse_init.vh share/nexus/parse_init.vh
mkdir -p share/nexus
cp "./"/techlibs/nexus/cells_xtra.v share/nexus/cells_xtra.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lutrams_map.v share/nexus/lutrams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lutrams.txt share/nexus/lutrams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/brams_map.v share/nexus/brams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/brams.txt share/nexus/brams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/lrams_map.v share/nexus/lrams_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/lrams.txt share/nexus/lrams.txt
mkdir -p share/nexus
cp "./"/techlibs/nexus/arith_map.v share/nexus/arith_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/latches_map.v share/nexus/latches_map.v
mkdir -p share/nexus
cp "./"/techlibs/nexus/dsp_map.v share/nexus/dsp_map.v
mkdir -p share/quicklogic/common
cp "./"/techlibs/quicklogic/common/cells_sim.v share/quicklogic/common/cells_sim.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/ffs_map.v share/quicklogic/pp3/ffs_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/lut_map.v share/quicklogic/pp3/lut_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/latches_map.v share/quicklogic/pp3/latches_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/cells_map.v share/quicklogic/pp3/cells_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/cells_sim.v share/quicklogic/pp3/cells_sim.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_model.v share/quicklogic/pp3/abc9_model.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_map.v share/quicklogic/pp3/abc9_map.v
mkdir -p share/quicklogic/pp3
cp "./"/techlibs/quicklogic/pp3/abc9_unmap.v share/quicklogic/pp3/abc9_unmap.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/arith_map.v share/quicklogic/qlf_k6n10f/arith_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/libmap_brams.txt share/quicklogic/qlf_k6n10f/libmap_brams.txt
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/libmap_brams_map.v share/quicklogic/qlf_k6n10f/libmap_brams_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/brams_map.v share/quicklogic/qlf_k6n10f/brams_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/brams_sim.v share/quicklogic/qlf_k6n10f/brams_sim.v
mkdir -p techlibs/quicklogic/qlf_k6n10f/ && python3 techlibs/quicklogic/qlf_k6n10f/generate_bram_types_sim.py techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/cells_sim.v share/quicklogic/qlf_k6n10f/cells_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/ffs_map.v share/quicklogic/qlf_k6n10f/ffs_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_sim.v share/quicklogic/qlf_k6n10f/dsp_sim.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_map.v share/quicklogic/qlf_k6n10f/dsp_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/dsp_final_map.v share/quicklogic/qlf_k6n10f/dsp_final_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/TDP18K_FIFO.v share/quicklogic/qlf_k6n10f/TDP18K_FIFO.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/ufifo_ctl.v share/quicklogic/qlf_k6n10f/ufifo_ctl.v
mkdir -p share/quicklogic/qlf_k6n10f
cp "./"/techlibs/quicklogic/qlf_k6n10f/sram1024x18_mem.v share/quicklogic/qlf_k6n10f/sram1024x18_mem.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/arith_map.v share/sf2/arith_map.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/cells_map.v share/sf2/cells_map.v
mkdir -p share/sf2
cp "./"/techlibs/sf2/cells_sim.v share/sf2/cells_sim.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_map.v share/xilinx/cells_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_sim.v share/xilinx/cells_sim.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/cells_xtra.v share/xilinx/cells_xtra.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcv.txt share/xilinx/lutrams_xcv.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcv_map.v share/xilinx/lutrams_xcv_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xc5v.txt share/xilinx/lutrams_xc5v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xcu.txt share/xilinx/lutrams_xcu.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lutrams_xc5v_map.v share/xilinx/lutrams_xc5v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcv.txt share/xilinx/brams_xcv.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcv_map.v share/xilinx/brams_xcv_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_defs.vh share/xilinx/brams_defs.vh
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc2v.txt share/xilinx/brams_xc2v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc2v_map.v share/xilinx/brams_xc2v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc3sda.txt share/xilinx/brams_xc3sda.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc3sda_map.v share/xilinx/brams_xc3sda_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc4v.txt share/xilinx/brams_xc4v.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc4v_map.v share/xilinx/brams_xc4v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc5v_map.v share/xilinx/brams_xc5v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xc6v_map.v share/xilinx/brams_xc6v_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/brams_xcu_map.v share/xilinx/brams_xcu_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/urams.txt share/xilinx/urams.txt
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/urams_map.v share/xilinx/urams_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/arith_map.v share/xilinx/arith_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/ff_map.v share/xilinx/ff_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/lut_map.v share/xilinx/lut_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/mux_map.v share/xilinx/mux_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc3s_mult_map.v share/xilinx/xc3s_mult_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc3sda_dsp_map.v share/xilinx/xc3sda_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc6s_dsp_map.v share/xilinx/xc6s_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc4v_dsp_map.v share/xilinx/xc4v_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc5v_dsp_map.v share/xilinx/xc5v_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xc7_dsp_map.v share/xilinx/xc7_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/xcu_dsp_map.v share/xilinx/xcu_dsp_map.v
mkdir -p share/xilinx
cp "./"/techlibs/xilinx/abc9_model.v share/xilinx/abc9_model.v
mkdir -p kernel/
g++ -o kernel/version_f20f913223c42fce6ecc4382b281cf67952e0a72.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/version_f20f913223c42fce6ecc4382b281cf67952e0a72.cc
mkdir -p techlibs/xilinx/
g++ -o techlibs/xilinx/xilinx_dffopt.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/xilinx/xilinx_dffopt.cc
mkdir -p frontends/rtlil/
g++ -o frontends/rtlil/rtlil_parser.tab.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_parser.tab.cc
mkdir -p frontends/rtlil/
g++ -o frontends/rtlil/rtlil_lexer.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/rtlil/rtlil_lexer.cc
mkdir -p frontends/verilog/
g++ -o frontends/verilog/verilog_parser.tab.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -DYYMAXDEPTH=10000000 frontends/verilog/verilog_parser.tab.cc
mkdir -p frontends/verilog/
flex -o frontends/verilog/verilog_lexer.cc frontends/verilog/verilog_lexer.l
mkdir -p kernel/
g++ -o kernel/register.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER kernel/register.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/ice40_wrapcarry.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/ice40_wrapcarry.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/test_pmgen.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/test_pmgen.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/microchip_dsp.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/microchip_dsp.cc
mkdir -p passes/pmgen/
g++ -o passes/pmgen/xilinx_dsp.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER passes/pmgen/xilinx_dsp.cc
mkdir -p ./
g++ -o yosys-filterlib -rdynamic passes/techmap/filterlib.o  -lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64 -lffi -ldl -lz -ltcl8.6 -ltclstub8.6
mkdir -p share/gatemate
cp techlibs/gatemate/lut_tree_cells.genlib share/gatemate/lut_tree_cells.genlib
mkdir -p share/gatemate
cp techlibs/gatemate/lut_tree_map.v share/gatemate/lut_tree_map.v
mkdir -p share/quicklogic/qlf_k6n10f
cp techlibs/quicklogic/qlf_k6n10f/bram_types_sim.v share/quicklogic/qlf_k6n10f/bram_types_sim.v
mkdir -p techlibs/quicklogic/
g++ -o techlibs/quicklogic/ql_dsp_macc.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER techlibs/quicklogic/ql_dsp_macc.cc
mkdir -p frontends/verilog/
g++ -o frontends/verilog/verilog_lexer.o -c  -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer  -Wall -Wextra -ggdb -I. -I"./" -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE  -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER frontends/verilog/verilog_lexer.cc
g++ -o yosys  -rdynamic kernel/version_f20f913223c42fce6ecc4382b281cf67952e0a72.o kernel/driver.o kernel/register.o kernel/rtlil.o kernel/log.o kernel/calc.o kernel/yosys.o kernel/binding.o kernel/cellaigs.o kernel/celledges.o kernel/cost.o kernel/satgen.o kernel/scopeinfo.o kernel/qcsat.o kernel/mem.o kernel/ffmerge.o kernel/ff.o kernel/yw.o kernel/json.o kernel/fmt.o kernel/sexpr.o kernel/drivertools.o kernel/functional.o kernel/fstdata.o libs/bigint/BigIntegerAlgorithms.o libs/bigint/BigInteger.o libs/bigint/BigIntegerUtils.o libs/bigint/BigUnsigned.o libs/bigint/BigUnsignedInABase.o libs/sha1/sha1.o libs/json11/json11.o libs/ezsat/ezsat.o libs/ezsat/ezminisat.o libs/minisat/Options.o libs/minisat/SimpSolver.o libs/minisat/Solver.o libs/minisat/System.o libs/fst/fstapi.o libs/fst/fastlz.o libs/fst/lz4.o libs/subcircuit/subcircuit.o frontends/aiger/aigerparse.o frontends/aiger2/xaiger.o frontends/ast/ast.o frontends/ast/simplify.o frontends/ast/genrtlil.o frontends/ast/dpicall.o frontends/ast/ast_binding.o frontends/blif/blifparse.o frontends/json/jsonparse.o frontends/liberty/liberty.o frontends/rpc/rpc_frontend.o frontends/rtlil/rtlil_parser.tab.o frontends/rtlil/rtlil_lexer.o frontends/rtlil/rtlil_frontend.o frontends/verific/verific.o frontends/verilog/verilog_parser.tab.o frontends/verilog/verilog_lexer.o frontends/verilog/preproc.o frontends/verilog/verilog_frontend.o frontends/verilog/const2ast.o passes/cmds/exec.o passes/cmds/add.o passes/cmds/delete.o passes/cmds/design.o passes/cmds/select.o passes/cmds/show.o passes/cmds/viz.o passes/cmds/rename.o passes/cmds/autoname.o passes/cmds/connect.o passes/cmds/scatter.o passes/cmds/setundef.o passes/cmds/splitnets.o passes/cmds/splitcells.o passes/cmds/stat.o passes/cmds/internal_stats.o passes/cmds/setattr.o passes/cmds/copy.o passes/cmds/splice.o passes/cmds/scc.o passes/cmds/glift.o passes/cmds/torder.o passes/cmds/logcmd.o passes/cmds/tee.o passes/cmds/write_file.o passes/cmds/connwrappers.o passes/cmds/cover.o passes/cmds/trace.o passes/cmds/plugin.o passes/cmds/check.o passes/cmds/edgetypes.o passes/cmds/portlist.o passes/cmds/chformal.o passes/cmds/chtype.o passes/cmds/blackbox.o passes/cmds/ltp.o passes/cmds/bugpoint.o passes/cmds/scratchpad.o passes/cmds/logger.o passes/cmds/printattrs.o passes/cmds/sta.o passes/cmds/clean_zerowidth.o passes/cmds/xprop.o passes/cmds/dft_tag.o passes/cmds/future.o passes/cmds/box_derive.o passes/cmds/example_dt.o passes/equiv/equiv_make.o passes/equiv/equiv_miter.o passes/equiv/equiv_simple.o passes/equiv/equiv_status.o passes/equiv/equiv_add.o passes/equiv/equiv_remove.o passes/equiv/equiv_induct.o passes/equiv/equiv_struct.o passes/equiv/equiv_purge.o passes/equiv/equiv_mark.o passes/equiv/equiv_opt.o passes/fsm/fsm.o passes/fsm/fsm_detect.o passes/fsm/fsm_extract.o passes/fsm/fsm_opt.o passes/fsm/fsm_expand.o passes/fsm/fsm_recode.o passes/fsm/fsm_info.o passes/fsm/fsm_export.o passes/fsm/fsm_map.o passes/hierarchy/hierarchy.o passes/hierarchy/uniquify.o passes/hierarchy/submod.o passes/hierarchy/keep_hierarchy.o passes/memory/memory.o passes/memory/memory_dff.o passes/memory/memory_share.o passes/memory/memory_collect.o passes/memory/memory_unpack.o passes/memory/memory_bram.o passes/memory/memory_map.o passes/memory/memory_memx.o passes/memory/memory_nordff.o passes/memory/memory_narrow.o passes/memory/memory_libmap.o passes/memory/memory_bmux2rom.o passes/memory/memlib.o passes/opt/opt.o passes/opt/opt_merge.o passes/opt/opt_mem.o passes/opt/opt_mem_feedback.o passes/opt/opt_mem_priority.o passes/opt/opt_mem_widen.o passes/opt/opt_muxtree.o passes/opt/opt_reduce.o passes/opt/opt_dff.o passes/opt/opt_share.o passes/opt/opt_clean.o passes/opt/opt_expr.o passes/opt/share.o passes/opt/wreduce.o passes/opt/opt_demorgan.o passes/opt/rmports.o passes/opt/opt_lut.o passes/opt/opt_lut_ins.o passes/opt/opt_ffinv.o passes/opt/pmux2shiftx.o passes/opt/muxpack.o passes/pmgen/test_pmgen.o passes/pmgen/ice40_dsp.o passes/pmgen/ice40_wrapcarry.o passes/pmgen/xilinx_dsp.o passes/pmgen/microchip_dsp.o passes/pmgen/peepopt.o passes/pmgen/xilinx_srl.o passes/proc/proc.o passes/proc/proc_prune.o passes/proc/proc_clean.o passes/proc/proc_rmdead.o passes/proc/proc_init.o passes/proc/proc_arst.o passes/proc/proc_rom.o passes/proc/proc_mux.o passes/proc/proc_dlatch.o passes/proc/proc_dff.o passes/proc/proc_memwr.o passes/sat/sat.o passes/sat/freduce.o passes/sat/eval.o passes/sat/sim.o passes/sat/miter.o passes/sat/expose.o passes/sat/assertpmux.o passes/sat/clk2fflogic.o passes/sat/async2sync.o passes/sat/formalff.o passes/sat/supercover.o passes/sat/fmcombine.o passes/sat/mutate.o passes/sat/cutpoint.o passes/sat/fminit.o passes/sat/recover_names.o passes/sat/qbfsat.o passes/sat/synthprop.o passes/techmap/flatten.o passes/techmap/techmap.o passes/techmap/simplemap.o passes/techmap/dfflibmap.o passes/techmap/maccmap.o passes/techmap/booth.o passes/techmap/libparse.o passes/techmap/abc.o passes/techmap/abc9.o passes/techmap/abc9_exe.o passes/techmap/abc9_ops.o passes/techmap/abc_new.o passes/techmap/iopadmap.o passes/techmap/clkbufmap.o passes/techmap/hilomap.o passes/techmap/extract.o passes/techmap/extract_fa.o passes/techmap/extract_counter.o passes/techmap/extract_reduce.o passes/techmap/alumacc.o passes/techmap/dffinit.o passes/techmap/pmuxtree.o passes/techmap/bmuxmap.o passes/techmap/demuxmap.o passes/techmap/bwmuxmap.o passes/techmap/muxcover.o passes/techmap/aigmap.o passes/techmap/tribuf.o passes/techmap/lut2mux.o passes/techmap/nlutmap.o passes/techmap/shregmap.o passes/techmap/deminout.o passes/techmap/insbuf.o passes/techmap/bufnorm.o passes/techmap/attrmvcp.o passes/techmap/attrmap.o passes/techmap/zinit.o passes/techmap/dfflegalize.o passes/techmap/dffunmap.o passes/techmap/flowmap.o passes/techmap/extractinv.o passes/techmap/cellmatch.o passes/techmap/clockgate.o passes/tests/test_autotb.o passes/tests/test_cell.o passes/tests/test_abcloop.o backends/aiger/aiger.o backends/aiger/xaiger.o backends/aiger2/aiger.o backends/blif/blif.o backends/btor/btor.o backends/cxxrtl/cxxrtl_backend.o backends/edif/edif.o backends/firrtl/firrtl.o backends/functional/cxx.o backends/functional/smtlib.o backends/functional/smtlib_rosette.o backends/functional/test_generic.o backends/intersynth/intersynth.o backends/jny/jny.o backends/json/json.o backends/rtlil/rtlil_backend.o backends/simplec/simplec.o backends/smt2/smt2.o backends/smv/smv.o backends/spice/spice.o backends/table/table.o backends/verilog/verilog_backend.o techlibs/achronix/synth_achronix.o techlibs/anlogic/synth_anlogic.o techlibs/anlogic/anlogic_eqn.o techlibs/anlogic/anlogic_fixcarry.o techlibs/common/synth.o techlibs/common/prep.o techlibs/coolrunner2/synth_coolrunner2.o techlibs/coolrunner2/coolrunner2_sop.o techlibs/coolrunner2/coolrunner2_fixup.o techlibs/easic/synth_easic.o techlibs/ecp5/synth_ecp5.o techlibs/efinix/synth_efinix.o techlibs/efinix/efinix_fixcarry.o techlibs/fabulous/synth_fabulous.o techlibs/gatemate/synth_gatemate.o techlibs/gatemate/gatemate_foldinv.o techlibs/gowin/synth_gowin.o techlibs/greenpak4/synth_greenpak4.o techlibs/greenpak4/greenpak4_dffinv.o techlibs/ice40/synth_ice40.o techlibs/ice40/ice40_braminit.o techlibs/ice40/ice40_opt.o techlibs/intel/synth_intel.o techlibs/intel_alm/synth_intel_alm.o techlibs/lattice/synth_lattice.o techlibs/lattice/lattice_gsr.o techlibs/microchip/synth_microchip.o techlibs/microchip/microchip_dffopt.o techlibs/nanoxplore/synth_nanoxplore.o techlibs/nanoxplore/nx_carry.o techlibs/nexus/synth_nexus.o techlibs/quicklogic/synth_quicklogic.o techlibs/quicklogic/ql_bram_merge.o techlibs/quicklogic/ql_bram_types.o techlibs/quicklogic/ql_dsp_simd.o techlibs/quicklogic/ql_dsp_io_regs.o techlibs/quicklogic/ql_dsp_macc.o techlibs/sf2/synth_sf2.o techlibs/xilinx/synth_xilinx.o techlibs/xilinx/xilinx_dffopt.o  -lstdc++ -lm -lrt -lreadline -L/usr/lib64/../lib64 -lffi -ldl -lz -ltcl8.6 -ltclstub8.6 
frontends/rtlil/rtlil_parser.tab.cc:492:7: warning: type ‘union yyalloc’ violates the C++ One Definition Rule [-Wodr]
  492 | union yyalloc
      |       ^
frontends/verilog/verilog_parser.tab.cc:1164:7: note: a different type is defined in another translation unit
 1164 | union yyalloc
      |       ^
frontends/rtlil/rtlil_parser.tab.cc:494:14: note: the first difference of corresponding definitions is field ‘yyss_alloc’
  494 |   yy_state_t yyss_alloc;
      |              ^
frontends/verilog/verilog_parser.tab.cc:1166:14: note: a field of same name but different type is defined in another translation unit
 1166 |   yy_state_t yyss_alloc;
      |              ^
frontends/rtlil/rtlil_parser.tab.cc:126: warning: type ‘yysymbol_kind_t’ violates the C++ One Definition Rule [-Wodr]
  126 | enum yysymbol_kind_t
frontends/verilog/verilog_parser.tab.cc:431: note: an enum with different value name is defined in another translation unit
  431 | enum yysymbol_kind_t
frontends/rtlil/rtlil_parser.tab.cc:132: note: name ‘YYSYMBOL_TOK_ID’ differs from name ‘YYSYMBOL_TOK_STRING’ defined in another translation unit
  132 |   YYSYMBOL_TOK_ID = 3,                     /* TOK_ID  */
frontends/verilog/verilog_parser.tab.cc:437: note: mismatching definition
  437 |   YYSYMBOL_TOK_STRING = 3,                 /* TOK_STRING  */
kernel/register.cc: In function ‘__ct_base .constprop’:
kernel/register.cc:782:9: note: variable tracking size limit exceeded with ‘-fvar-tracking-assignments’, retrying without
  782 |         CellHelpMessages() {
      |         ^

  Build successful.

+ make ABCEXTERNAL=/usr/bin/abc DOC_TARGET=latexpdf docs
[Makefile.conf] CONFIG := gcc

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `help -write-rst-command-reference-manual' --

    abc [options] [selection]

This pass uses the ABC tool [1] for technology mapping of yosys's internal gate
library to a target architecture.

    -exe <command>
        use the specified command instead of "/usr/bin/abc" to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script <file>
        use the specified ABC script file instead of the default script.

        if <file> starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:

        for -liberty/-genlib without -constr:
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               &get -n; &dch -f; &nf {D}; &put

        for -liberty/-genlib with -constr:
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               &get -n; &dch -f; &nf {D}; &put; buffer; upsize {D};
               dnsize {D}; stime -p

        for -lut/-luts (only one LUT size):
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               dch -f; if; mfs2; lutpack {S}

        for -lut/-luts (different LUT sizes):
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               dch -f; if; mfs2

        for -sop:
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               dch -f; cover {I} {P}

        otherwise:
          strash; &get -n; &fraig -x; &put; scorr; dc2; dretime; strash;
               &get -n; &dch -f; &nf {D}; &put

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):

        for -liberty/-genlib without -constr:
          strash; dretime; map {D}

        for -liberty/-genlib with -constr:
          strash; dretime; map {D}; buffer; upsize {D}; dnsize {D};
               stime -p

        for -lut/-luts:
          strash; dretime; if

        for -sop:
          strash; dretime; cover {I} {P}

        otherwise:
          strash; dretime; map

    -liberty <file>
        generate netlists for the specified cell library (using the liberty
        file format).

    -dont_use <cell_name>
        generate netlists for the specified cell library (using the liberty
        file format).

    -genlib <file>
        generate netlists for the specified cell library (using the SIS Genlib
        file format).

    -constr <file>
        pass this file with timing constraints to ABC.
        use with -liberty/-genlib.

        a constr file contains two lines:
            set_driving_cell <cell_name>
            set_load <floating_point_number>

        the set_driving_cell statement defines which cell type is assumed to
        drive the primary inputs and the set_load statement sets the load in
        femtofarads for each primary output.

    -D <picoseconds>
        set delay target. the string {D} in the default scripts above is
        replaced by this option when used, and an empty string otherwise.
        this also replaces 'dretime' with 'dretime; retime -o {D}' in the
        default scripts above.

    -I <num>
        maximum number of SOP inputs.
        (replaces {I} in the default scripts above)

    -P <num>
        maximum number of SOP products.
        (replaces {P} in the default scripts above)

    -S <num>
        maximum number of LUT inputs shared.
        (replaces {S} in the default scripts above, default: -S 1)

    -lut <width>
        generate netlist using luts of (max) the specified width.

    -lut <w1>:<w2>
        generate netlist using luts of (max) the specified width <w2>. All
        luts with width <= <w1> have constant cost. for luts larger than <w1>
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -sop
        map to sum-of-product cells and inverters

    -g type1,type2,...
        Map to the specified list of gate types. Supported gates types are:
           AND, NAND, OR, NOR, XOR, XNOR, ANDNOT, ORNOT, MUX,
           NMUX, AOI3, OAI3, AOI4, OAI4.
        (The NOT gate is always added to this list automatically.)

        The following aliases can be used to reference common sets of gate
        types:
          simple: AND OR XOR MUX
          cmos2:  NAND NOR
          cmos3:  NAND NOR AOI3 OAI3
          cmos4:  NAND NOR AOI3 OAI3 AOI4 OAI4
          cmos:   NAND NOR AOI3 OAI3 AOI4 OAI4 NMUX MUX XOR XNOR
          gates:  AND NAND OR NOR XOR XNOR ANDNOT ORNOT
          aig:    AND NAND OR NOR ANDNOT ORNOT

        The alias 'all' represent the full set of all gate types.

        Prefix a gate type with a '-' to remove it from the list. For example
        the arguments 'AND,OR,XOR' and 'simple,-MUX' are equivalent.

        The default is 'all,-NMUX,-AOI3,-OAI3,-AOI4,-OAI4'.

    -dff
        also pass $_DFF_?_ and $_DFFE_??_ cells through ABC. modules with many
        clock domains are automatically partitioned in clock domains and each
        domain is passed through ABC independently.

    -clk [!]<clock-signal-name>[,[!]<enable-signal-name>]
        use only the specified clock domain. this is like -dff, but only FF
        cells that belong to the specified clock domain are used.

    -keepff
        set the "keep" attribute on flip-flop output wires. (and thus preserve
        them, for example for equivalence checking.)

    -nocleanup
        when this option is used, the temporary files created by this pass
        are not removed. this is useful for debugging.

    -showtmp
        print the temp dir name in log. usually this is suppressed so that the
        command output is identical across runs.

    -markgroups
        set a 'abcgroup' attribute on all objects created by ABC. The value of
        this attribute is a unique integer for each ABC process started. This
        is useful for debugging the partitioning of clock domains.

    -dress
        run the 'dress' command after all other ABC commands. This aims to
        preserve naming by an equivalence check between the original and
        post-ABC netlists (experimental).

When no target cell library is specified the Yosys standard cell library is
loaded into ABC before the ABC script is executed.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/


    abc9 [options] [selection]

This script pass performs a sequence of commands to facilitate the use of the
ABC tool [1] for technology mapping of the current design to a target FPGA
architecture. Only fully-selected modules are supported.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -exe <command>
        use the specified command instead of "/usr/bin/abc" to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script <file>
        use the specified ABC script file instead of the default script.

        if <file> starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:
          &scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):
          &if {C} {W} {D} {R} -v

    -D <picoseconds>
        set delay target. the string {D} in the default scripts above is
        replaced by this option when used, and an empty string otherwise
        (indicating best possible delay).

    -lut <width>
        generate netlist using luts of (max) the specified width.

    -lut <w1>:<w2>
        generate netlist using luts of (max) the specified width <w2>. All
        luts with width <= <w1> have constant cost. for luts larger than <w1>
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -lut <file>
        pass this file with lut library to ABC.

    -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -maxlut <width>
        when auto-generating the lut library, discard all luts equal to or
        greater than this size (applicable when neither -lut nor -luts is
        specified).

    -dff
        also pass $_DFF_[NP]_ cells through to ABC. modules with many clock
        domains are supported and automatically partitioned by ABC.

    -nocleanup
        when this option is used, the temporary files created by this pass
        are not removed. this is useful for debugging.

    -showtmp
        print the temp dir name in log. usually this is suppressed so that the
        command output is identical across runs.

    -box <file>
        pass this file with box library to ABC.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as an XAIGER file with `write_xaiger' and then load that into ABC
externally if you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/


    check:
        abc9_ops -check [-dff]    (option if -dff)

    map:
        abc9_ops -prep_hier [-dff]    (option if -dff)
        scc -specify -set_attr abc9_scc_id {}
        abc9_ops -prep_bypass [-prep_dff]    (option if -dff)
        design -stash $abc9
        design -load $abc9_map
        proc
        wbflip
        techmap -wb -map %$abc9 -map +/techmap.v A:abc9_flop
        opt -nodffe -nosdff
        abc9_ops -prep_dff_submod                                                     (only if -dff)
        setattr -set submod "$abc9_flop" t:$_DFF_?_ %ci* %co* t:$_DFF_?_ %d           (only if -dff)
        submod                                                                        (only if -dff)
        setattr -mod -set whitebox 1 -set abc9_flop 1 -set abc9_box 1 *_$abc9_flop    (only if -dff)
        foreach module in design
            rename <module-name>_$abc9_flop _TECHMAP_REPLACE_                         (only if -dff)
        abc9_ops -prep_dff_unmap                                                      (only if -dff)
        design -copy-to $abc9 =*_$abc9_flop                                           (only if -dff)
        delete =*_$abc9_flop                                                          (only if -dff)
        design -stash $abc9_map
        design -load $abc9
        design -delete $abc9
        techmap -wb -max_iter 1 -map %$abc9_map -map +/abc9_map.v [-D DFF]    (option if -dff)
        design -delete $abc9_map

    pre:
        read_verilog -icells -lib -specify +/abc9_model.v
        abc9_ops -break_scc -prep_delays -prep_xaiger [-dff]    (option for -dff)
        abc9_ops -prep_lut <maxlut>    (skip if -lut or -luts)
        abc9_ops -prep_box    (skip if -box)
        design -stash $abc9
        design -load $abc9_holes
        techmap -wb -map %$abc9 -map +/techmap.v
        opt -purge
        aigmap
        design -stash $abc9_holes
        design -load $abc9
        design -delete $abc9

    exe:
        aigmap
        foreach module in selection
            abc9_ops -write_lut <abc-temp-dir>/input.lut    (skip if '-lut' or '-luts')
            abc9_ops -write_box <abc-temp-dir>/input.box    (skip if '-box')
            write_xaiger -map <abc-temp-dir>/input.sym [-dff] <abc-temp-dir>/input.xaig
            abc9_exe [options] -cwd <abc-temp-dir> -lut [<abc-temp-dir>/input.lut] -box [<abc-temp-dir>/input.box]
            read_aiger -xaiger -wideports -module_name <module-name>$abc9 -map <abc-temp-dir>/input.sym <abc-temp-dir>/output.aig
            abc9_ops -reintegrate [-dff]

    unmap:
        techmap -wb -map %$abc9_unmap -map +/abc9_unmap.v
        design -delete $abc9_unmap
        design -delete $abc9_holes
        delete =*_$abc9_byp
        setattr -mod -unset abc9_box_id


    abc9_exe [options]

 
This pass uses the ABC tool [1] for technology mapping of the top module
(according to the (* top *) attribute or if only one module is currently
selected) to a target FPGA architecture.

    -exe <command>
        use the specified command instead of "/usr/bin/abc" to execute ABC.
        This can e.g. be used to call a specific version of ABC or a wrapper.

    -script <file>
        use the specified ABC script file instead of the default script.

        if <file> starts with a plus sign (+), then the rest of the filename
        string is interpreted as the command string to be passed to ABC. The
        leading plus sign is removed and all commas (,) in the string are
        replaced with blanks before the string is passed to ABC.

        if no -script parameter is given, the following scripts are used:
          &scorr; &sweep; &dc2; &dch -f; &ps; &if {C} {W} {D} {R} -v; &mfs

    -fast
        use different default scripts that are slightly faster (at the cost
        of output quality):
          &if {C} {W} {D} {R} -v

    -constr <file>
        pass this file with timing constraints to ABC.
        use with -liberty.

        a constr file contains two lines:
            set_driving_cell <cell_name>
            set_load <floating_point_number>

        the set_driving_cell statement defines which cell type is assumed to
        drive the primary inputs and the set_load statement sets the load in
        femtofarads for each primary output.

    -liberty <file>
        read the given Liberty file as a description of the target cell library.
        this option can be used multiple times.

    -dont_use <cell_name>
        avoid usage of the technology cell <cell_name> when mapping the design.
        this option can be used multiple times.

    -D <picoseconds>
        set delay target. the string {D} in the default scripts above is
        replaced by this option when used, and an empty string otherwise
        (indicating best possible delay).

    -lut <width>
        generate netlist using luts of (max) the specified width.

    -lut <w1>:<w2>
        generate netlist using luts of (max) the specified width <w2>. All
        luts with width <= <w1> have constant cost. for luts larger than <w1>
        the area cost doubles with each additional input bit. the delay cost
        is still constant for all lut widths.

    -lut <file>
        pass this file with lut library to ABC.

    -luts <cost1>,<cost2>,<cost3>,<sizeN>:<cost4-N>,..
        generate netlist using luts. Use the specified costs for luts with 1,
        2, 3, .. inputs.

    -showtmp
        print the temp dir name in log. usually this is suppressed so that the
        command output is identical across runs.

    -box <file>
        pass this file with box library to ABC.

    -cwd <dir>
        use this as the current working directory, inside which the 'input.xaig'
        file is expected. temporary files will be created in this directory, and
        the mapped result will be written to 'output.aig'.

Note that this is a logic optimization pass within Yosys that is calling ABC
internally. This is not going to "run ABC on your design". It will instead run
ABC on logic snippets extracted from your design. You will not get any useful
output when passing an ABC script that writes a file. Instead write your full
design as BLIF file with write_blif and then load that into ABC externally if
you want to use ABC to convert your design into another format.

[1] http://www.eecs.berkeley.edu/~alanmi/abc/


    abc9_ops [options] [selection]

This pass contains a set of supporting operations for use during ABC technology
mapping, and is expected to be called in conjunction with other operations from
the `abc9' script pass. Only fully-selected modules are supported.

    -check
        check that the design is valid, e.g. (* abc9_box_id *) values are
        unique, (* abc9_carry *) is only given for one input/output port, etc.

    -prep_hier
        derive all used (* abc9_box *) or (* abc9_flop *) (if -dff option)
        whitebox modules. with (* abc9_flop *) modules, only those containing
        $dff/$_DFF_[NP]_ cells with zero initial state -- due to an ABC
        limitation -- will be derived.

    -prep_bypass
        create techmap rules in the '$abc9_map' and '$abc9_unmap' designs for
        bypassing sequential (* abc9_box *) modules using a combinatorial box
        (named *_$abc9_byp). bypassing is necessary if sequential elements (e.g.
        $dff, $mem, etc.) are discovered inside so that any combinatorial paths
        will be correctly captured. this bypass box will only contain ports that
        are referenced by a simple path declaration ($specify2 cell) inside a
        specify block.

    -prep_dff
        select all (* abc9_flop *) modules instantiated in the design and store
        in the named selection '$abc9_flops'.

    -prep_dff_submod
        within (* abc9_flop *) modules, rewrite all edge-sensitive path
        declarations and $setup() timing checks ($specify3 and $specrule cells)
        that share a 'DST' port with the $_DFF_[NP]_.Q port from this 'Q' port
        to the DFF's 'D' port. this is to prepare such specify cells to be moved
        into the flop box.

    -prep_dff_unmap
        populate the '$abc9_unmap' design with techmap rules for mapping
        *_$abc9_flop cells back into their derived cell types (where the rules
        created by -prep_hier will then map back to the original cell with
        parameters).

    -prep_delays
        insert `$__ABC9_DELAY' blackbox cells into the design to account for
        certain required times.

    -break_scc
        for an arbitrarily chosen cell in each unique SCC of each selected
        module (tagged with an (* abc9_scc_id = <int> *) attribute) interrupt
        all wires driven by this cell's outputs with a temporary
        $__ABC9_SCC_BREAKER cell to break the SCC.

    -prep_xaiger
        prepare the design for XAIGER output. this includes computing the
        topological ordering of ABC9 boxes, as well as preparing the 
        '$abc9_holes' design that contains the logic behaviour of ABC9
        whiteboxes.

    -dff
        consider flop cells (those instantiating modules marked with
        (* abc9_flop *)) during -prep_{delays,xaiger,box}.

    -prep_lut <maxlut>
        pre-compute the lut library by analysing all modules marked with
        (* abc9_lut=<area> *).

    -write_lut <dst>
        write the pre-computed lut library to <dst>.

    -prep_box
        pre-compute the box library by analysing all modules marked with
        (* abc9_box *).

    -write_box <dst>
        write the pre-computed box library to <dst>.

    -reintegrate
        for each selected module, re-intergrate the module '<module-name>$abc9'
        by first recovering ABC9 boxes, and then stitching in the remaining
        primary inputs and outputs.


    abc_new [options] [selection]

This command uses the ABC tool [1] to optimize the current design and map it to
the target standard cell library.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -exe <command>
    -script <file>
    -D <picoseconds>
    -constr <file>
    -dont_use <cell_name>
    -liberty <file>
        these options are passed on to the 'abc9_exe' command which invokes
        the ABC tool on individual modules of the design. please see
        'help abc9_exe' for more details

[1] http://www.eecs.berkeley.edu/~alanmi/abc/


    check:
        abc9_ops -check

    prep_boxes:
        box_derive
        abc9_ops -prep_box

    map:
        foreach module in selection
          abc9_ops -write_box <abc-temp-dir>/input.box
          write_xaiger2 -mapping_prep -map2 <abc-temp-dir>/input.map2 <abc-temp-dir>/input.xaig
          abc9_exe [options] -cwd <abc-temp-dir> -box <abc-temp-dir>/input.box
          read_xaiger2 -sc_mapping -module_name <module> -map2 <abc-temp-dir>/input.map2 <abc-temp-dir>/output.aig


WARNING: THE 'abc_new' COMMAND IS EXPERIMENTAL.


    add <command> [selection]

This command adds objects to the design. It operates on all fully selected
modules. So e.g. 'add -wire foo' will add a wire foo to all selected modules.


    add {-wire|-input|-inout|-output} <name> <width> [selection]

Add a wire (input, inout, output port) with the given name and width. The
command will fail if the object exists already and has different properties
than the object to be created.


    add -global_input <name> <width> [selection]

Like 'add -input', but also connect the signal between instances of the
selected modules.


    add {-assert|-assume|-live|-fair|-cover} <name1> [-if <name2>]

Add an $assert, $assume, etc. cell connected to a wire named name1, with its
enable signal optionally connected to a wire named name2 (default: 1'b1).


    add -mod <name[s]>

Add module[s] with the specified name[s].


    aigmap [options] [selection]

Replace all logic cells with circuits made of only $_AND_ and
$_NOT_ cells.

    -nand
        Enable creation of $_NAND_ cells

    -select
        Overwrite replaced cells in the current selection with new $_AND_,
        $_NOT_, and $_NAND_, cells


    alumacc [selection]

This pass translates arithmetic operations like $add, $mul, $lt, etc. to $alu
and $macc cells.


    anlogic_eqn [selection]

Calculate equations for luts since bitstream generator depends on it.


    anlogic_fixcarry [options] [selection]

Add Anlogic adders to fix carry chain if needed.


    assertpmux [options] [selection]

This command adds asserts to the design that assert that all parallel muxes
($pmux cells) have a maximum of one of their inputs enable at any time.

    -noinit
        do not enforce the pmux condition during the init state

    -always
        usually the $pmux condition is only checked when the $pmux output
        is used by the mux tree it drives. this option will deactivate this
        additional constraint and check the $pmux condition always.


    async2sync [options] [selection]

This command replaces async FF inputs with sync circuits emulating the same
behavior for when the async signals are actually synchronized to the clock.

This pass assumes negative hold time for the async FF inputs. For example when
a reset deasserts with the clock edge, then the FF output will still drive the
reset value in the next cycle regardless of the data-in value at the time of
the clock edge.

    -nolower
        Do not automatically run 'chformal -lower' to lower $check cells.


    attrmap [options] [selection]

This command renames attributes and/or maps key/value pairs to
other key/value pairs.

    -tocase <name>
        Match attribute names case-insensitively and set it to the specified
        name.

    -rename <old_name> <new_name>
        Rename attributes as specified

    -map <old_name>=<old_value> <new_name>=<new_value>
        Map key/value pairs as indicated.

    -imap <old_name>=<old_value> <new_name>=<new_value>
        Like -map, but use case-insensitive match for <old_value> when
        it is a string value.

    -remove <name>=<value>
        Remove attributes matching this pattern.

    -modattr
        Operate on module attributes instead of attributes on wires and cells.

For example, mapping Xilinx-style "keep" attributes to Yosys-style:

    attrmap -tocase keep -imap keep="true" keep=1 \
            -imap keep="false" keep=0 -remove keep=0


    attrmvcp [options] [selection]

Move or copy attributes on wires to the cells driving them.

    -copy
        By default, attributes are moved. This will only add
        the attribute to the cell, without removing it from
        the wire.

    -purge
        If no selected cell consumes the attribute, then it is
        left on the wire by default. This option will cause the
        attribute to be removed from the wire, even if no selected
        cell takes it.

    -driven
        By default, attriburtes are moved to the cell driving the
        wire. With this option set it will be moved to the cell
        driven by the wire instead.

    -attr <attrname>
        Move or copy this attribute. This option can be used
        multiple times.


    autoname [selection]

Assign auto-generated public names to objects with private names (the ones
with $-prefix).


    blackbox [options] [selection]

Convert modules into blackbox modules (remove contents and set the blackbox
module attribute).


    bmuxmap [selection]

This pass transforms $bmux cells to trees of $mux cells.

    -pmux
        transform to $pmux instead of $mux cells.


    booth [selection]

This pass replaces multiplier cells with a radix-4 Booth-encoded implementation.
It operates on $mul cells whose width of operands is at least 4x4 and whose
width of result is at least 8.

    -lowpower
        use an alternative low-power architecture for the generated multiplier
        (signed multipliers only)


    box_derive [-base <base_module>] [-naming_attr <attr>] [selection]

As part of the assembly of the design hierarchy done by the 'hierarchy' command,
specializations of parametric modules are derived on demand: for each choice of
parameter values appearing in the design, a copy of the parametric module is
derived which is specialized to that choice.

This derivation process ignores blackboxes and whiteboxes (boxes). To supplement,
this 'box_derive' command can be used to request the derivation of modules based
on box instances appearing in the design, which is desirable in certain use
cases. Only the selected cells are considered as the instances that steer the
derivation process.

    -base <base_module>
        instead of deriving the module that directly corresponds to each box
        instance, derive a specialization of <base_module> (this option applies
        to all selected box cells)

    -naming_attr <attr>
        once a specialization is derived, use the value of the module attribute
        <attr> for a name which should be used for the derived module (this
        replaces the internal Yosys naming scheme in which the names of derived
        modules start with '$paramod$')


    bufnorm [options] [selection]

Insert buffer cells into the design as needed, to make sure that each wire
has exactly one driving cell port, and aliasing wires are buffered using
buffer cells, than can be chained in a canonical order.

Running 'bufnorm' on the whole design enters 'buffered-normalized mode'.

    -buf
        Create $buf cells for all buffers. The default is to use $_BUF_ cells
        for sigle-bit buffers and $buf cells only for multi-bit buffers.

    -chain
        Chain all alias wires. By default only wires with positive-valued
        'chain' or 'keep' attribute on them are chained.

    -output
        Enable chaining of ouput ports wires.

    -public
        Enable chaining of wires wth public names.

    -nochain
        Disable chaining of wires with 'chain' attribute.

    -nokeep
        Disable chaining of wires with 'keep' attribute.

    -flat
        Alias for -nokeep and -nochain.

    -nosticky
        Disable 'sticky' behavior of output ports already driving whole
        wires, and always enforce canonical sort order instead.

    -alphasort
        Strictly use alphanumeric sort for chain-order. (Default is
        to chain 'keep' wires first, then ports in declaration order,
        and then the other wires in alphanumeric sort order.)

Run 'bufnorm' with -pos, -bits, or -conn on the whole design to remove all
$buf buffer cells and exit 'buffered-normalized mode' again.

    -pos
        Create (multi- and single-bit) $pos cells instead $buf and $_BUF_.

    -bits
        Create arrays of $_BUF_ cells instead of multi-bit $buf cells.

    -conn
        Create 'direct connections' instead of buffer cells.

    -nomode
        Do not automatically enter or leave 'buffered-normalized mode'.

The 'bufnorm' command can also be used to just switch in and out of
'buffered-normalized mode' and run the low-level re-normalizer.

    -update
        Enter 'buffered-normalized mode' and (re-)normalize.

    -reset
        Leave 'buffered-normalized mode' without changing the netlist.


WARNING: THE 'bufnorm' COMMAND IS EXPERIMENTAL.


    bugpoint [options] [-script <filename> | -command "<command>"]

This command minimizes the current design that is known to crash Yosys with the
given script into a smaller testcase. It does this by removing an arbitrary part
of the design and recursively invokes a new Yosys process with this modified
design and the same script, repeating these steps while it can find a smaller
design that still causes a crash. Once this command finishes, it replaces the
current design with the smallest testcase it was able to produce.
In order to save the reduced testcase you must write this out to a file with
another command after `bugpoint` like `write_rtlil` or `write_verilog`.

    -script <filename> | -command "<command>"
        use this script file or command to crash Yosys. required.

    -yosys <filename>
        use this Yosys binary. if not specified, `yosys` is used.

    -grep "<string>"
        only consider crashes that place this string in the log file.

    -fast
        run `proc_clean; clean -purge` after each minimization step. converges
        faster, but produces larger testcases, and may fail to produce any
        testcase at all if the crash is related to dangling wires.

    -clean
        run `proc_clean; clean -purge` before checking testcase and after
        finishing. produces smaller and more useful testcases, but may fail to
        produce any testcase at all if the crash is related to dangling wires.

It is possible to constrain which parts of the design will be considered for
removal. Unless one or more of the following options are specified, all parts
will be considered.

    -modules
        try to remove modules. modules with a (* bugpoint_keep *) attribute
        will be skipped.

    -ports
        try to remove module ports. ports with a (* bugpoint_keep *) attribute
        will be skipped (useful for clocks, resets, etc.)

    -cells
        try to remove cells. cells with a (* bugpoint_keep *) attribute will
        be skipped.

    -connections
        try to reconnect ports to 'x.

    -processes
        try to remove processes. processes with a (* bugpoint_keep *) attribute
        will be skipped.

    -assigns
        try to remove process assigns from cases.

    -updates
        try to remove process updates from syncs.

    -runner "<prefix>"
        child process wrapping command, e.g., "timeout 30", or valgrind.


    bwmxumap [options] [selection]

This pass replaces $bwmux cells with equivalent logic


    cd <modname>

This is just a shortcut for 'select -module <modname>'.


    cd <cellname>

When no module with the specified name is found, but there is a cell
with the specified name in the current module, then this is equivalent
to 'cd <celltype>'.


    cd ..

Remove trailing substrings that start with '.' in current module name until
the name of a module in the current design is generated, then switch to that
module. Otherwise clear the current selection.


    cd

This is just a shortcut for 'select -clear'.


    cellmatch -lib <design> [module selection]

This pass identifies functionally equivalent counterparts between each of the
selected modules and a module from the secondary design <design>. For every such
correspondence found, a techmap rule is generated for mapping instances of the
former to instances of the latter. This techmap rule is saved in yet another
design called '$cellmatch', which is created if non-existent.

This pass restricts itself to combinational modules. Modules are functionally
equivalent as long as their truth tables are identical upto a permutation of
inputs and outputs. The supported number of inputs is limited to 6.

    cellmatch -derive_luts [module selection]

For every port in each selected module, characterize its combinational
function with a 'lut' attribute if possible.


    check [options] [selection]

This pass identifies the following problems in the current design:

  - combinatorial loops
  - two or more conflicting drivers for one wire
  - used wires that do not have a driver

Options:

    -noinit
        also check for wires which have the 'init' attribute set

    -initdrv
        also check for wires that have the 'init' attribute set and are not
        driven by an FF cell type

    -mapped
        also check for internal cells that have not been mapped to cells of the
        target architecture

    -allow-tbuf
        modify the -mapped behavior to still allow $_TBUF_ cells

    -assert
        produce a runtime error if any problems are found in the current design

    -force-detailed-loop-check
        for the detection of combinatorial loops, use a detailed connectivity
        model for all internal cells for which it is available. This disables
        falling back to a simpler overapproximating model for those cells for
        which the detailed model is expected costly.


    chformal [types] [mode] [options] [selection]

Make changes to the formal constraints of the design. The [types] options
the type of constraint to operate on. If none of the following options are
given, the command will operate on all constraint types:

    -assert       $assert cells, representing assert(...) constraints
    -assume       $assume cells, representing assume(...) constraints
    -live         $live cells, representing assert(s_eventually ...)
    -fair         $fair cells, representing assume(s_eventually ...)
    -cover        $cover cells, representing cover() statements

    Additionally chformal will operate on $check cells corresponding to the
    selected constraint types.

Exactly one of the following modes must be specified:

    -remove
        remove the cells and thus constraints from the design

    -early
        bypass FFs that only delay the activation of a constraint. When inputs
        of the bypassed FFs do not remain stable between clock edges, this may
        result in unexpected behavior.

    -delay <N>
        delay activation of the constraint by <N> clock cycles

    -skip <N>
        ignore activation of the constraint in the first <N> clock cycles

    -coverenable
        add cover statements for the enable signals of the constraints

    -assert2assume
    -assume2assert
    -live2fair
    -fair2live
        change the roles of cells as indicated. these options can be combined

    -lower
        convert each $check cell into an $assert, $assume, $live, $fair or
        $cover cell. If the $check cell contains a message, also produce a
        $print cell.


    chparam [ -set name value ]... [selection]

Re-evaluate the selected modules with new parameters. String values must be
passed in double quotes (").


    chparam -list [selection]

List the available parameters of the selected modules.


    chtype [options] [selection]

Change the types of cells in the design.

    -set <type>
        set the cell type to the given type

    -map <old_type> <new_type>
        change cells types that match <old_type> to <new_type>



    clean [options] [selection]

This is identical to 'opt_clean', but less verbose.

When commands are separated using the ';;' token, this command will be executed
between the commands.

When commands are separated using the ';;;' token, this command will be executed
in -purge mode between the commands.


    clean_zerowidth [selection]

Fixes the selected cells and processes to contain no zero-width connections.
Depending on the cell type, this may be implemented by removing the connection,
widening it to 1-bit, or removing the cell altogether.


    clk2fflogic [options] [selection]

This command replaces clocked flip-flops with generic $ff cells that use the
implicit global clock. This is useful for formal verification of designs with
multiple clocks.

This pass assumes negative hold time for the async FF inputs. For example when
a reset deasserts with the clock edge, then the FF output will still drive the
reset value in the next cycle regardless of the data-in value at the time of
the clock edge.

    -nolower
        Do not automatically run 'chformal -lower' to lower $check cells.


    clkbufmap [options] [selection]

Inserts clock buffers between nets connected to clock inputs and their drivers.

In the absence of any selection, all wires without the 'clkbuf_inhibit'
attribute will be considered for clock buffer insertion.
Alternatively, to consider all wires without the 'buffer_type' attribute set to
'none' or 'bufr' one would specify:
  'w:* a:buffer_type=none a:buffer_type=bufr %u %d'
as the selection.

    -buf <celltype> <portname_out>:<portname_in>
        Specifies the cell type to use for the clock buffers
        and its port names.  The first port will be connected to
        the clock network sinks, and the second will be connected
        to the actual clock source.

    -inpad <celltype> <portname_out>:<portname_in>
        If specified, a PAD cell of the given type is inserted on
        clock nets that are also top module's inputs (in addition
        to the clock buffer, if any).

At least one of -buf or -inpad should be specified.

    clockgate [options] [selection]

This pass transforms each set of FFs sharing the same clock and
enable signal into a clock-gating cell and a set of enable-less FFs.
Primarily a power-saving transformation on ASIC designs.

    -pos <celltype> <ce>:<clk>:<gclk>
        If specified, rising-edge FFs will have CE inputs
        removed and a gated clock will be created by the
        user-specified <celltype> ICG (integrated clock gating)
        cell with ports named <ce>, <clk>, <gclk>.
        The ICG's clock enable pin must be active high.
    -neg <celltype> <ce>:<clk>:<gclk>
        If specified, falling-edge FFs will have CE inputs
        removed and a gated clock will be created by the
        user-specified <celltype> ICG (integrated clock gating)
        cell with ports named <ce>, <clk>, <gclk>.
        The ICG's clock enable pin must be active high.
    -tie_lo <port_name>
        Port <port_name> of the ICG will be tied to zero.
        Intended for DFT scan-enable pins.
    -min_net_size <n>
        Only transform sets of at least <n> eligible FFs.

    connect [-nomap] [-nounset] -set <lhs-expr> <rhs-expr> [selection]

Create a connection. This is equivalent to adding the statement 'assign
<lhs-expr> = <rhs-expr>;' to the Verilog input. Per default, all existing
drivers for <lhs-expr> are unconnected. This can be overwritten by using
the -nounset option.


    connect [-nomap] -unset <expr> [selection]

Unconnect all existing drivers for the specified expression.


    connect [-nomap] [-assert] -port <cell> <port> <expr> [selection]

Connect the specified cell port to the specified cell port.


Per default signal alias names are resolved and all signal names are mapped
the the signal name of the primary driver. Using the -nomap option deactivates
this behavior.

The connect command operates in one module only. Either only one module must
be selected or an active module must be set using the 'cd' command.

The -assert option verifies that the connection already exists, instead of
making it.

This command does not operate on module with processes.


    connect_rpc -exec <command> [args...]
    connect_rpc -path <path>

Load modules using an out-of-process frontend.

    -exec <command> [args...]
        run <command> with arguments [args...]. send requests on stdin, read
        responses from stdout.

    -path <path>
        connect to Unix domain socket at <path>. (Unix)
        connect to bidirectional byte-type named pipe at <path>. (Windows)

A simple JSON-based, newline-delimited protocol is used for communicating with
the frontend. Yosys requests data from the frontend by sending exactly 1 line
of JSON. Frontend responds with data or error message by replying with exactly
1 line of JSON as well.

    -> {"method": "modules"}
    <- {"modules": ["<module-name>", ...]}
    <- {"error": "<error-message>"}
        request for the list of modules that can be derived by this frontend.
        the 'hierarchy' command will call back into this frontend if a cell
        with type <module-name> is instantiated in the design.

    -> {"method": "derive", "module": "<module-name">, "parameters": {
        "<param-name>": {"type": "[unsigned|signed|string|real]",
                           "value": "<param-value>"}, ...}}
    <- {"frontend": "[rtlil|verilog|...]","source": "<source>"}}
    <- {"error": "<error-message>"}
        request for the module <module-name> to be derived for a specific set of
        parameters. <param-name> starts with \ for named parameters, and with $
        for unnamed parameters, which are numbered starting at 1.<param-value>
        for integer parameters is always specified as a binary string of
        unlimited precision. the <source> returned by the frontend is
        hygienically parsedby a built-in Yosys <frontend>, allowing the RPC
        frontend to return anyconvenient representation of the module. the
        derived module is cached,so the response should be the same whenever the
        same set of parameters is provided.

    connwrappers [options] [selection]

Wrappers are used in coarse-grain synthesis to wrap cells with smaller ports
in wrapper cells with a (larger) constant port size. I.e. the upper bits
of the wrapper output are signed/unsigned bit extended. This command uses this
knowledge to rewire the inputs of the driven cells to match the output of
the driving cell.

    -signed <cell_type> <port_name> <width_param>
    -unsigned <cell_type> <port_name> <width_param>
        consider the specified signed/unsigned wrapper output

    -port <cell_type> <port_name> <width_param> <sign_param>
        use the specified parameter to decide if signed or unsigned

The options -signed, -unsigned, and -port can be specified multiple times.


    coolrunner2_fixup [options] [selection]

Insert necessary buffer cells for CoolRunner-II architecture.


    coolrunner2_sop [options] [selection]

Break $sop cells into ANDTERM/ORTERM cells.


    copy old_name new_name

Copy the specified module. Note that selection patterns are not supported
by this command.


    cover [options] [pattern]

Print the code coverage counters collected using the cover() macro in the Yosys
C++ code. This is useful to figure out what parts of Yosys are utilized by a
test bench.

    -q
        Do not print output to the normal destination (console and/or log file)

    -o file
        Write output to this file, truncate if exists.

    -a file
        Write output to this file, append if exists.

    -d dir
        Write output to a newly created file in the specified directory.

When one or more pattern (shell wildcards) are specified, then only counters
matching at least one pattern are printed.


It is also possible to instruct Yosys to print the coverage counters on program
exit to a file using environment variables:

    YOSYS_COVER_DIR="{dir-name}" yosys {args}

        This will create a file (with an auto-generated name) in this
        directory and write the coverage counters to it.

    YOSYS_COVER_FILE="{file-name}" yosys {args}

        This will append the coverage counters to the specified file.


Hint: Use the following AWK command to consolidate Yosys coverage files:

    gawk '{ p[$3] = $1; c[$3] += $2; } END { for (i in p)
      printf "%-60s %10d %s\n", p[i], c[i], i; }' {files} | sort -k3


Coverage counters are only available in Yosys for Linux.


    cutpoint [options] [selection]

This command adds formal cut points to the design.

    -undef
        set cupoint nets to undef (x). the default behavior is to create a
        $anyseq cell and drive the cutpoint net from that


    debug cmd

Execute the specified command with debug log messages enabled


    delete [selection]

Deletes the selected objects. This will also remove entire modules, if the
whole module is selected.


    delete {-input|-output|-port} [selection]

Does not delete any object but removes the input and/or output flag on the
selected wires, thus 'deleting' module ports.


    deminout [options] [selection]

"Demote" inout ports to input or output ports, if possible.


    demuxmap [selection]

This pass transforms $demux cells to a bunch of equality comparisons.


    design -reset

Clear the current design.


    design -save <name>

Save the current design under the given name.


    design -stash <name>

Save the current design under the given name and then clear the current design.


    design -push

Push the current design to the stack and then clear the current design.


    design -push-copy

Push the current design to the stack without clearing the current design.


    design -pop

Reset the current design and pop the last design from the stack.


    design -load <name>

Reset the current design and load the design previously saved under the given
name.


    design -copy-from <name> [-as <new_mod_name>] <selection>

Copy modules from the specified design into the current one. The selection is
evaluated in the other design.


    design -copy-to <name> [-as <new_mod_name>] [selection]

Copy modules from the current design into the specified one.


    design -import <name> [-as <new_top_name>] [selection]

Import the specified design into the current design. The source design must
either have a selected top module or the selection must contain exactly one
module that is then used as top module for this command.


    design -reset-vlog

The Verilog front-end remembers defined macros and top-level declarations
between calls to 'read_verilog'. This command resets this memory.

    design -delete <name>

Delete the design previously saved under the given name.


    dffinit [options] [selection]

This pass sets an FF cell parameter to the the initial value of the net it
drives. (This is primarily used in FPGA flows.)

    -ff <cell_name> <output_port> <init_param>
        operate on the specified cell type. this option can be used
        multiple times.

    -highlow
        use the string values "high" and "low" to represent a single-bit
        initial value of 1 or 0. (multi-bit values are not supported in this
        mode.)

    -strinit <string for high> <string for low> 
        use string values in the command line to represent a single-bit
        initial value of 1 or 0. (multi-bit values are not supported in this
        mode.)

    -noreinit
        fail if the FF cell has already a defined initial value set in other
        passes and the initial value of the net it drives is not equal to
        the already defined initial value.


    dfflegalize [options] [selection]

Converts FFs to types supported by the target.

    -cell <cell_type_pattern> <init_values>
        specifies a supported group of FF cells.  <cell_type_pattern>
        is a yosys internal fine cell name, where ? characters can be
        as a wildcard matching any character.  <init_values> specifies
        which initialization values these FF cells can support, and can
        be one of:

        - x (no init value supported)
        - 0
        - 1
        - r (init value has to match reset value, only for some FF types)
        - 01 (both 0 and 1 supported).

    -mince <num>
        specifies a minimum number of FFs that should be using any given
        clock enable signal.  If a clock enable signal doesn't meet this
        threshold, it is unmapped into soft logic.

    -minsrst <num>
        specifies a minimum number of FFs that should be using any given
        sync set/reset signal.  If a sync set/reset signal doesn't meet this
        threshold, it is unmapped into soft logic.

The following cells are supported by this pass (ie. will be ingested,
and can be specified as allowed targets):

- $_DFF_[NP]_
- $_DFFE_[NP][NP]_
- $_DFF_[NP][NP][01]_
- $_DFFE_[NP][NP][01][NP]_
- $_ALDFF_[NP][NP]_
- $_ALDFFE_[NP][NP][NP]_
- $_DFFSR_[NP][NP][NP]_
- $_DFFSRE_[NP][NP][NP][NP]_
- $_SDFF_[NP][NP][01]_
- $_SDFFE_[NP][NP][01][NP]_
- $_SDFFCE_[NP][NP][01][NP]_
- $_SR_[NP][NP]_
- $_DLATCH_[NP]_
- $_DLATCH_[NP][NP][01]_
- $_DLATCHSR_[NP][NP][NP]_

The following transformations are performed by this pass:

- upconversion from a less capable cell to a more capable cell, if the less
  capable cell is not supported (eg. dff -> dffe, or adff -> dffsr)
- unmapping FFs with clock enable (due to unsupported cell type or -mince)
- unmapping FFs with sync reset (due to unsupported cell type or -minsrst)
- adding inverters on the control pins (due to unsupported polarity)
- adding inverters on the D and Q pins and inverting the init/reset values
  (due to unsupported init or reset value)
- converting sr into adlatch (by tying D to 1 and using E as set input)
- emulating unsupported dffsr cell by adff + adff + sr + mux
- emulating unsupported dlatchsr cell by adlatch + adlatch + sr + mux
- emulating adff when the (reset, init) value combination is unsupported by
  dff + adff + dlatch + mux
- emulating adlatch when the (reset, init) value combination is unsupported by
- dlatch + adlatch + dlatch + mux
If the pass is unable to realize a given cell type (eg. adff when only plain dff
is available), an error is raised.

    dfflibmap [-prepare] [-map-only] [-info] [-dont_use <cell_name>] -liberty <file> [selection]

Map internal flip-flop cells to the flip-flop cells in the technology
library specified in the given liberty file.

This pass may add inverters as needed. Therefore it is recommended to
first run this pass and then map the logic paths to the target technology.

When called with -prepare, this command will convert the internal FF cells
to the internal cell types that best match the cells found in the given
liberty file, but won't actually map them to the target cells.

When called with -map-only, this command will only map internal cell
types that are already of exactly the right type to match the target
cells, leaving remaining internal cells untouched.

When called with -info, this command will only print the target cell
list, along with their associated internal cell types, and the arguments
that would be passed to the dfflegalize pass.  The design will not be
changed.

When called with -dont_use, this command will not map to the specified cell
name as an alternative to setting the dont_use property in the Liberty file.
This argument can be called multiple times with different cell names. This
argument also supports simple glob patterns in the cell name.


    dffunmap [options] [selection]

This pass transforms FF types with clock enable and/or synchronous reset into
their base type (with neither clock enable nor sync reset) by emulating the
clock enable and synchronous reset with multiplexers on the cell input.

    -ce-only
        unmap only clock enables, leave synchronous resets alone.

    -srst-only
        unmap only synchronous resets, leave clock enables alone.


    dft_tag [options] [selection]

This pass... TODO

    -overwrite-only
        Only process $overwrite_tag and $original_tag cells.
    -tag-public
        For each public wire that may carry tagged data, create a new public
        wire (named <wirename>:<tagname>) that carries the tag bits. Note
        that without this, tagging logic will only be emitted as required
        for uses of $get_tag.


    dump [options] [selection]

Write the selected parts of the design to the console or specified file in
RTLIL format.

    -m
        also dump the module headers, even if only parts of a single
        module is selected

    -n
        only dump the module headers if the entire module is selected

    -o <filename>
        write to the specified file.

    -a <filename>
        like -outfile but append instead of overwrite


    echo on

Print all commands to log before executing them.


    echo off

Do not print all commands to log before executing them. (default)


    edgetypes [options] [selection]

This command lists all unique types of 'edges' found in the selection. An 'edge'
is a 4-tuple of source and sink cell type and port name.


    efinix_fixcarry [options] [selection]

Add Efinix adders to fix carry chain if needed.


    equiv_add [-try] gold_sig gate_sig

This command adds an $equiv cell for the specified signals.


    equiv_add [-try] -cell gold_cell gate_cell

This command adds $equiv cells for the ports of the specified cells.


    equiv_induct [options] [selection]

Uses a version of temporal induction to prove $equiv cells.

Only selected $equiv cells are proven and only selected cells are used to
perform the proof.

    -undef
        enable modelling of undef states

    -seq <N>
        the max. number of time steps to be considered (default = 4)

This command is very effective in proving complex sequential circuits, when
the internal state of the circuit quickly propagates to $equiv cells.

However, this command uses a weak definition of 'equivalence': This command
proves that the two circuits will not diverge after they produce equal
outputs (observable points via $equiv) for at least <N> cycles (the <N>
specified via -seq).

Combined with simulation this is very powerful because simulation can give
you confidence that the circuits start out synced for at least <N> cycles
after reset.


    equiv_make [options] gold_module gate_module equiv_module

This creates a module annotated with $equiv cells from two presumably
equivalent modules. Use commands such as 'equiv_simple' and 'equiv_status'
to work with the created equivalent checking module.

    -inames
        Also match cells and wires with $... names.

    -blacklist <file>
        Do not match cells or signals that match the names in the file.

    -encfile <file>
        Match FSM encodings using the description from the file.
        See 'help fsm_recode' for details.

    -make_assert
        Check equivalence with $assert cells instead of $equiv.
        $eqx (===) is used to compare signals.
Note: The circuit created by this command is not a miter (with something like
a trigger output), but instead uses $equiv cells to encode the equivalence
checking problem. Use 'miter -equiv' if you want to create a miter circuit.


    equiv_mark [options] [selection]

This command marks the regions in an equivalence checking module. Region 0 is
the proven part of the circuit. Regions with higher numbers are connected
unproven subcricuits. The integer attribute 'equiv_region' is set on all
wires and cells.


    equiv_miter [options] miter_module [selection]

This creates a miter module for further analysis of the selected $equiv cells.

    -trigger
        Create a trigger output

    -cmp
        Create cmp_* outputs for individual unproven $equiv cells

    -assert
        Create a $assert cell for each unproven $equiv cell

    -undef
        Create compare logic that handles undefs correctly


    equiv_opt [options] [command]

This command uses temporal induction to check circuit equivalence before and
after an optimization pass.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to the start of the command list, and empty to
        label is synonymous to the end of the command list.

    -map <filename>
        expand the modules in this file before proving equivalence. this is
        useful for handling architecture-specific primitives.

    -blacklist <file>
        Do not match cells or signals that match the names in the file
        (passed to equiv_make).

    -assert
        produce an error if the circuits are not equivalent.

    -multiclock
        run clk2fflogic before equivalence checking.

    -async2sync
        run async2sync before equivalence checking.

    -undef
        enable modelling of undef states during equiv_induct.

    -nocheck
        disable running check before and after the command under test.

The following commands are executed by this verification command:

    run_pass:
        hierarchy -auto-top
        design -save preopt
        check -assert    (unless -nocheck)
        [command]
        check -assert    (unless -nocheck)
        design -stash postopt

    prepare:
        design -copy-from preopt  -as gold A:top
        design -copy-from postopt -as gate A:top

    techmap:    (only with -map)
        techmap -wb -D EQUIV -autoproc -map <filename> ...

    prove:
        clk2fflogic    (only with -multiclock)
        async2sync     (only with -async2sync)
        equiv_make -blacklist <filename> ... gold gate equiv
        equiv_induct [-undef] equiv
        equiv_status [-assert] equiv

    restore:
        design -load preopt


    equiv_purge [options] [selection]

This command removes the proven part of an equivalence checking module, leaving
only the unproven segments in the design. This will also remove and add module
ports as needed.


    equiv_remove [options] [selection]

This command removes the selected $equiv cells. If neither -gold nor -gate is
used then only proven cells are removed.

    -gold
        keep gold circuit

    -gate
        keep gate circuit


    equiv_simple [options] [selection]

This command tries to prove $equiv cells using a simple direct SAT approach.

    -v
        verbose output

    -undef
        enable modelling of undef states

    -short
        create shorter input cones that stop at shared nodes. This yields
        simpler SAT problems but sometimes fails to prove equivalence.

    -nogroup
        disabling grouping of $equiv cells by output wire

    -seq <N>
        the max. number of time steps to be considered (default = 1)


    equiv_status [options] [selection]

This command prints status information for all selected $equiv cells.

    -assert
        produce an error if any unproven $equiv cell is found


    equiv_struct [options] [selection]

This command adds additional $equiv cells based on the assumption that the
gold and gate circuit are structurally equivalent. Note that this can introduce
bad $equiv cells in cases where the netlists are not structurally equivalent,
for example when analyzing circuits with cells with commutative inputs. This
command will also de-duplicate gates.

    -fwd
        by default this command performans forward sweeps until nothing can
        be merged by forwards sweeps, then backward sweeps until forward
        sweeps are effective again. with this option set only forward sweeps
        are performed.

    -fwonly <cell_type>
        add the specified cell type to the list of cell types that are only
        merged in forward sweeps and never in backward sweeps. $equiv is in
        this list automatically.

    -icells
        by default, the internal RTL and gate cell types are ignored. add
        this option to also process those cell types with this command.

    -maxiter <N>
        maximum number of iterations to run before aborting


    eval [options] [selection]

This command evaluates the value of a signal given the value of all required
inputs.

    -set <signal> <value>
        set the specified signal to the specified value.

    -set-undef
        set all unspecified source signals to undef (x)

    -table <signal>
        create a truth table using the specified input signals

    -show <signal>
        show the value for the specified signal. if no -show option is passed
        then all output ports of the current module are used.


TODO: add help message


    exec [options] -- [command]

Execute a command in the operating system shell.  All supplied arguments are
concatenated and passed as a command to popen(3).  Whitespace is not guaranteed
to be preserved, even if quoted.  stdin and stderr are not connected, while
stdout is logged unless the "-q" option is specified.


    -q
        Suppress stdout and stderr from subprocess

    -expect-return <int>
        Generate an error if popen() does not return specified value.
        May only be specified once; the final specified value is controlling
        if specified multiple times.

    -expect-stdout <regex>
        Generate an error if the specified regex does not match any line
        in subprocess's stdout.  May be specified multiple times.

    -not-expect-stdout <regex>
        Generate an error if the specified regex matches any line
        in subprocess's stdout.  May be specified multiple times.


    Example: exec -q -expect-return 0 -- echo "bananapie" | grep "nana"



    expose [options] [selection]

This command exposes all selected internal signals of a module as additional
outputs.

    -dff
        only consider wires that are directly driven by register cell.

    -cut
        when exposing a wire, create an input/output pair and cut the internal
        signal path at that wire.

    -input
        when exposing a wire, create an input port and disconnect the internal
        driver.

    -shared
        only expose those signals that are shared among the selected modules.
        this is useful for preparing modules for equivalence checking.

    -evert
        also turn connections to instances of other modules to additional
        inputs and outputs and remove the module instances.

    -evert-dff
        turn flip-flops to sets of inputs and outputs.

    -sep <separator>
        when creating new wire/port names, the original object name is suffixed
        with this separator (default: '.') and the port name or a type
        designator for the exposed signal.


    extract -map <map_file> [options] [selection]
    extract -mine <out_file> [options] [selection]

This pass looks for subcircuits that are isomorphic to any of the modules
in the given map file and replaces them with instances of this modules. The
map file can be a Verilog source file (*.v) or an RTLIL source file (*.il).

    -map <map_file>
        use the modules in this file as reference. This option can be used
        multiple times.

    -map %<design-name>
        use the modules in this in-memory design as reference. This option can
        be used multiple times.

    -verbose
        print debug output while analyzing

    -constports
        also find instances with constant drivers. this may be much
        slower than the normal operation.

    -nodefaultswaps
        normally builtin port swapping rules for internal cells are used per
        default. This turns that off, so e.g. 'a^b' does not match 'b^a'
        when this option is used.

    -compat <needle_type> <haystack_type>
        Per default, the cells in the map file (needle) must have the
        type as the cells in the active design (haystack). This option
        can be used to register additional pairs of types that should
        match. This option can be used multiple times.

    -swap <needle_type> <port1>,<port2>[,...]
        Register a set of swappable ports for a needle cell type.
        This option can be used multiple times.

    -perm <needle_type> <port1>,<port2>[,...] <portA>,<portB>[,...]
        Register a valid permutation of swappable ports for a needle
        cell type. This option can be used multiple times.

    -cell_attr <attribute_name>
        Attributes on cells with the given name must match.

    -wire_attr <attribute_name>
        Attributes on wires with the given name must match.

    -ignore_parameters
        Do not use parameters when matching cells.

    -ignore_param <cell_type> <parameter_name>
        Do not use this parameter when matching cells.

This pass does not operate on modules with unprocessed processes in it.
(I.e. the 'proc' pass should be used first to convert processes to netlists.)

This pass can also be used for mining for frequent subcircuits. In this mode
the following options are to be used instead of the -map option.

    -mine <out_file>
        mine for frequent subcircuits and write them to the given RTLIL file

    -mine_cells_span <min> <max>
        only mine for subcircuits with the specified number of cells
        default value: 3 5

    -mine_min_freq <num>
        only mine for subcircuits with at least the specified number of matches
        default value: 10

    -mine_limit_matches_per_module <num>
        when calculating the number of matches for a subcircuit, don't count
        more than the specified number of matches per module

    -mine_max_fanout <num>
        don't consider internal signals with more than <num> connections

The modules in the map file may have the attribute 'extract_order' set to an
integer value. Then this value is used to determine the order in which the pass
tries to map the modules to the design (ascending, default value is 0).

See 'help techmap' for a pass that does the opposite thing.


    extract_counter [options] [selection]

This pass converts non-resettable or async resettable counters to counter cells.
Use a target-specific 'techmap' map file to convert those cells to the actual
target cells.

    -maxwidth N
        Only extract counters up to N bits wide (default 64)

    -minwidth N
        Only extract counters at least N bits wide (default 2)

    -allow_arst yes|no
        Allow counters to have async reset (default yes)

    -dir up|down|both
        Look for up-counters, down-counters, or both (default down)

    -pout X,Y,...
        Only allow parallel output from the counter to the listed cell types
        (if not specified, parallel outputs are not restricted)



    extract_fa [options] [selection]

This pass extracts full/half adders from a gate-level design.

    -fa, -ha
        Enable cell types (fa=full adder, ha=half adder)
        All types are enabled if none of this options is used

    -d <int>
        Set maximum depth for extracted logic cones (default=20)

    -b <int>
        Set maximum breadth for extracted logic cones (default=6)

    -v
        Verbose output


    extract_reduce [options] [selection]

converts gate chains into $reduce_* cells

This command finds chains of $_AND_, $_OR_, and $_XOR_ cells and replaces them
with their corresponding $reduce_* cells. Because this command only operates on
these cell types, it is recommended to map the design to only these cell types
using the `abc -g` command. Note that, in some cases, it may be more effective
to map the design to only $_AND_ cells, run extract_reduce, map the remaining
parts of the design to AND/OR/XOR cells, and run extract_reduce a second time.

    -allow-off-chain
        Allows matching of cells that have loads outside the chain. These cells
        will be replicated and folded into the $reduce_* cell, but the original
        cell will remain, driving its original loads.


    extractinv [options] [selection]

Searches the design for all cells with invertible pins controlled by a cell
parameter (eg. IS_CLK_INVERTED on many Xilinx cells) and removes the parameter.
If the parameter was set to 1, inserts an explicit inverter cell in front of
the pin instead.  Normally used for output to ISE, which does not support the
inversion parameters.

To mark a cell port as invertible, use (* invertible_pin = "param_name" *)
on the wire in the blackbox module.  The parameter value should have
the same width as the port, and will be effectively XORed with it.

    -inv <celltype> <portname_out>:<portname_in>
        Specifies the cell type to use for the inverters and its port names.
        This option is required.


    flatten [options] [selection]

This pass flattens the design by replacing cells by their implementation. This
pass is very similar to the 'techmap' pass. The only difference is that this
pass is using the current design as mapping library.

Cells and/or modules with the 'keep_hierarchy' attribute set will not be
flattened by this command.

    -wb
        Ignore the 'whitebox' attribute on cell implementations.

    -noscopeinfo
        Do not create '$scopeinfo' cells that preserve attributes of cells and
        modules that were removed during flattening. With this option, the
        'src' attribute of a given cell is merged into all objects replacing
        that cell, with multiple distinct 'src' locations separated by '|'.
        Without this option these 'src' locations can be found via the
        cell_src' and 'module_src' attribute of '$scopeinfo' cells.

    -scopename
        Create 'scopename' attributes for objects with a private name. This
        attribute records the 'hdlname' of the enclosing scope. For objects
        with a public name the enclosing scope can be found via their
        'hdlname' attribute.


    flowmap [options] [selection]

This pass uses the FlowMap technology mapping algorithm to pack logic gates
into k-LUTs with optimal depth. It allows mapping any circuit elements that can
be evaluated with the `eval` pass, including cells with multiple output ports
and multi-bit input and output ports.

    -maxlut k
        perform technology mapping for a k-LUT architecture. if not specified,
        defaults to 3.

    -minlut n
        only produce n-input or larger LUTs. if not specified, defaults to 1.

    -cells <cell>[,<cell>,...]
        map specified cells. if not specified, maps $_NOT_, $_AND_, $_OR_,
        $_XOR_ and $_MUX_, which are the outputs of the `simplemap` pass.

    -relax
        perform depth relaxation and area minimization.

    -r-alpha n, -r-beta n, -r-gamma n
        parameters of depth relaxation heuristic potential function.
        if not specified, alpha=8, beta=2, gamma=1.

    -optarea n
        optimize for area by trading off at most n logic levels for fewer LUTs.
        n may be zero, to optimize for area without increasing depth.
        implies -relax.

    -debug
        dump intermediate graphs.

    -debug-relax
        explain decisions performed during depth relaxation.


    fmcombine [options] module_name gold_cell gate_cell

This pass takes two cells, which are instances of the same module, and replaces
them with one instance of a special 'combined' module, that effectively
contains two copies of the original module, plus some formal properties.

This is useful for formal test benches that check what differences in behavior
a slight difference in input causes in a module.

    -initeq
        Insert assumptions that initially all FFs in both circuits have the
        same initial values.

    -anyeq
        Do not duplicate $anyseq/$anyconst cells.

    -fwd
        Insert forward hint assumptions into the combined module.

    -bwd
        Insert backward hint assumptions into the combined module.
        (Backward hints are logically equivalend to fordward hits, but
        some solvers are faster with bwd hints, or even both -bwd and -fwd.)

    -nop
        Don't insert hint assumptions into the combined module.
        (This should not provide any speedup over the original design, but
        strangely sometimes it does.)

If none of -fwd, -bwd, and -nop is given, then -fwd is used as default.


    fminit [options] <selection>

This pass creates init constraints (for example for reset sequences) in a formal
model.

    -seq <signal> <sequence>
        Set sequence using comma-separated list of values, use 'z for
        unconstrained bits. The last value is used for the remainder of the
        trace.

    -set <signal> <value>
        Add constant value constraint

    -posedge <signal>
    -negedge <signal>
        Set clock for init sequences


    formalff [options] [selection]

This pass transforms clocked flip-flops to prepare a design for formal
verification. If a design contains latches and/or multiple different clocks run
the async2sync or clk2fflogic passes before using this pass.

    -clk2ff
        Replace all clocked flip-flops with $ff cells that use the implicit
        global clock. This assumes, without checking, that the design uses a
        single global clock. If that is not the case, the clk2fflogic pass
        should be used instead.

    -ff2anyinit
        Replace uninitialized bits of $ff cells with $anyinit cells. An
        $anyinit cell behaves exactly like an $ff cell with an undefined
        initialization value. The difference is that $anyinit inhibits
        don't-care optimizations and is used to track solver-provided values
        in witness traces.

        If combined with -clk2ff this also affects newly created $ff cells.

    -anyinit2ff
        Replaces $anyinit cells with uninitialized $ff cells. This performs the
        reverse of -ff2anyinit and can be used, before running a backend pass
        (or similar) that is not yet aware of $anyinit cells.

        Note that after running -anyinit2ff, in general, performing don't-care
        optimizations is not sound in a formal verification setting.

    -fine
        Emit fine-grained $_FF_ cells instead of coarse-grained $ff cells for
        -anyinit2ff. Cannot be combined with -clk2ff or -ff2anyinit.

    -setundef
        Find FFs with undefined initialization values for which changing the
        initialization does not change the observable behavior and initialize
        them. For -ff2anyinit, this reduces the number of generated $anyinit
        cells that drive wires with private names.

    -hierarchy
        Propagates the 'replaced_by_gclk' attribute set by clk2ff upwards
        through the design hierarchy towards the toplevel inputs. This option
        works on the whole design and ignores the selection.

    -assume
        Add assumptions that constrain wires with the 'replaced_by_gclk'
        attribute to the value they would have before an active clock edge.


    freduce [options] [selection]

This pass performs functional reduction in the circuit. I.e. if two nodes are
equivalent, they are merged to one node and one of the redundant drivers is
disconnected. A subsequent call to 'clean' will remove the redundant drivers.

    -v, -vv
        enable verbose or very verbose output

    -inv
        enable explicit handling of inverted signals

    -stop <n>
        stop after <n> reduction operations. this is mostly used for
        debugging the freduce command itself.

    -dump <prefix>
        dump the design to <prefix>_<module>_<num>.il after each reduction
        operation. this is mostly used for debugging the freduce command.

This pass is undef-aware, i.e. it considers don't-care values for detecting
equivalent nodes.

All selected wires are considered for rewiring. The selected cells cover the
circuit that is analyzed.


    fsm [options] [selection]

This pass calls all the other fsm_* passes in a useful order. This performs
FSM extraction and optimization. It also calls opt_clean as needed:

    fsm_detect          unless got option -nodetect
    fsm_extract

    fsm_opt
    opt_clean
    fsm_opt

    fsm_expand          if got option -expand
    opt_clean           if got option -expand
    fsm_opt             if got option -expand

    fsm_recode          unless got option -norecode

    fsm_info

    fsm_export          if got option -export
    fsm_map             unless got option -nomap

Options:

    -expand, -norecode, -export, -nomap
        enable or disable passes as indicated above

    -fullexpand
        call expand with -full option

    -encoding type
    -fm_set_fsm_file file
    -encfile file
        passed through to fsm_recode pass

This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe'
before this pass to prepare the design.


    fsm_detect [options] [selection]

This pass detects finite state machines by identifying the state signal.
The state signal is then marked by setting the attribute 'fsm_encoding'
on the state signal to "auto".

    -ignore-self-reset
        Mark FSMs even if they are self-resetting

Existing 'fsm_encoding' attributes are not changed by this pass.

Signals can be protected from being detected by this pass by setting the
'fsm_encoding' attribute to "none".

This pass uses a subset of FF types to detect FSMs. Run 'opt -nosdff -nodffe'
before this pass to prepare the design for fsm_detect.


    fsm_expand [-full] [selection]

The fsm_extract pass is conservative about the cells that belong to a finite
state machine. This pass can be used to merge additional auxiliary gates into
the finite state machine.

By default, fsm_expand is still a bit conservative regarding merging larger
word-wide cells. Call with -full to consider all cells for merging.


    fsm_export [-noauto] [-o filename] [-origenc] [selection]

This pass creates a KISS2 file for every selected FSM. For FSMs with the
'fsm_export' attribute set, the attribute value is used as filename, otherwise
the module and cell name is used as filename. If the parameter '-o' is given,
the first exported FSM is written to the specified filename. This overwrites
the setting as specified with the 'fsm_export' attribute. All other FSMs are
exported to the default name as mentioned above.

    -noauto
        only export FSMs that have the 'fsm_export' attribute set

    -o filename
        filename of the first exported FSM

    -origenc
        use binary state encoding as state names instead of s0, s1, ...


    fsm_extract [selection]

This pass operates on all signals marked as FSM state signals using the
'fsm_encoding' attribute. It consumes the logic that creates the state signal
and uses the state signal to generate control signal and replaces it with an
FSM cell.

The generated FSM cell still generates the original state signal with its
original encoding. The 'fsm_opt' pass can be used in combination with the
'opt_clean' pass to eliminate this signal.


    fsm_info [selection]

This pass dumps all internal information on FSM cells. It can be useful for
analyzing the synthesis process and is called automatically by the 'fsm'
pass so that this information is included in the synthesis log file.


    fsm_map [selection]

This pass translates FSM cells to flip-flops and logic.


    fsm_opt [selection]

This pass optimizes FSM cells. It detects which output signals are actually
not used and removes them from the FSM. This pass is usually used in
combination with the 'opt_clean' pass (see also 'help fsm').


    fsm_recode [options] [selection]

This pass reassign the state encodings for FSM cells. At the moment only
one-hot encoding and binary encoding is supported.
    -encoding <type>
        specify the encoding scheme used for FSMs without the
        'fsm_encoding' attribute or with the attribute set to `auto'.

    -fm_set_fsm_file <file>
        generate a file containing the mapping from old to new FSM encoding
        in form of Synopsys Formality set_fsm_* commands.

    -encfile <file>
        write the mappings from old to new FSM encoding to a file in the
        following format:

            .fsm <module_name> <state_signal>
            .map <old_bitpattern> <new_bitpattern>


    fst2tb [options] [top-level]

This command generates testbench for the circuit using the given top-level
module and simulus signal from FST file

    -tb <name>
        generated testbench name.
        files <name>.v and <name>.txt are created as result.

    -r <filename>
        read simulation FST file

    -clock <portname>
        name of top-level clock input

    -clockn <portname>
        name of top-level clock input (inverse polarity)

    -scope <name>
        scope of simulation top model

    -start <time>
        start co-simulation in arbitary time (default 0)

    -stop <time>
        stop co-simulation in arbitary time (default END)

    -n <integer>
        number of clock cycles to simulate (default: 20)


    future [options] [selection]


    gatemate_foldinv [selection]


This pass searches for $__CC_NOT cells and folds them into CC_LUT2, CC_L2T4
and CC_L2T5 cells as created by LUT tree mapping.


    glift <command> [options] [selection]

Augments the current or specified module with gate-level information flow 
tracking (GLIFT) logic using the "constructive mapping" approach. Also can set
up QBF-SAT optimization problems in order to optimize GLIFT models or trade off
precision and complexity.


Commands:

  -create-precise-model
    Replaces the current or specified module with one that has corresponding
    "taint" inputs, outputs, and internal nets along with precise taint
    tracking logic. For example, precise taint tracking logic for an AND gate
    is:

      y_t = a & b_t | b & a_t | a_t & b_t


  -create-imprecise-model
    Replaces the current or specified module with one that has corresponding
    "taint" inputs, outputs, and internal nets along with imprecise "All OR"
    taint tracking logic:

      y_t = a_t | b_t


  -create-instrumented-model
    Replaces the current or specified module with one that has corresponding
    "taint" inputs, outputs, and internal nets along with 4 varying-precision
    versions of taint tracking logic. Which version of taint tracking logic is
    used for a given gate is determined by a MUX selected by an $anyconst cell.
     By default, unless the `-no-cost-model` option is provided, an additional
    wire named `__glift_weight` with the `keep` and `minimize` attributes is
    added to the module along with pmuxes and adders to calculate a rough
    estimate of the number of logic gates in the GLIFT model given an assignment
    for the $anyconst cells. The four versions of taint tracking logic for an
    AND gate are:
      y_t = a & b_t | b & a_t | a_t & b_t       (like `-create-precise-model`)
      y_t = a_t | a & b_t
      y_t = b_t | b & a_t
      y_t = a_t | b_t                           (like `-create-imprecise-model`)


Options:

  -taint-constants
    Constant values in the design are labeled as tainted.
    (default: label constants as un-tainted)

  -keep-outputs
    Do not remove module outputs. Taint tracking outputs will appear in the
    module ports alongside the orignal outputs.
    (default: original module outputs are removed)

  -simple-cost-model
    Do not model logic area. Instead model the number of non-zero assignments to
    $anyconsts. Taint tracking logic versions vary in their size, but all
    reduced-precision versions are significantly smaller than the fully-precise
    version. A non-zero $anyconst assignment means that reduced-precision taint
    tracking logic was chosen for some gate. Only applicable in combination with
    `-create-instrumented-model`. (default: use a complex model and give that
     wire the "keep" and "minimize" attributes)

  -no-cost-model
    Do not model taint tracking logic area and do not create a `__glift_weight`
    wire. Only applicable in combination with `-create-instrumented-model`.
    (default: model area and give that wire the "keep" and "minimize"
    attributes)

  -instrument-more
    Allow choice from more versions of (even simpler) taint tracking logic. A
    total of 8 versions of taint tracking logic will be added per gate,
    including the 4 versions from `-create-instrumented-model` and these
    additional versions:

      y_t = a_t
      y_t = b_t
      y_t = 1
      y_t = 0

    Only applicable in combination with `-create-instrumented-model`.
    (default: do not add more versions of taint tracking logic.


    greenpak4_dffinv [options] [selection]

Merge GP_INV cells with GP_DFF* and GP_DLATCH* cells.


    help  ................  list all commands
    help <command>  ......  print help message for given command
    help -all  ...........  print complete command reference

    help -cells ..........  list all cell types
    help <celltype>  .....  print help message for given cell type
    help <celltype>+  ....  print verilog code for given cell type


    hierarchy [-check] [-top <module>]
    hierarchy -generate <cell-types> <port-decls>

In parametric designs, a module might exists in several variations with
different parameter values. This pass looks at all modules in the current
design and re-runs the language frontends for the parametric modules as
needed. It also resolves assignments to wired logic data types (wand/wor),
resolves positional module parameters, unrolls array instances, and more.

    -check
        also check the design hierarchy. this generates an error when
        an unknown module is used as cell type.

    -simcheck
        like -check, but also throw an error if blackbox modules are
        instantiated, and throw an error if the design has no top module.

    -smtcheck
        like -simcheck, but allow smtlib2_module modules.

    -purge_lib
        by default the hierarchy command will not remove library (blackbox)
        modules. use this option to also remove unused blackbox modules.

    -libdir <directory>
        search for files named <module_name>.v in the specified directory
        for unknown modules and automatically run read_verilog for each
        unknown module.

    -keep_positionals
        per default this pass also converts positional arguments in cells
        to arguments using port names. This option disables this behavior.

    -keep_portwidths
        per default this pass adjusts the port width on cells that are
        module instances when the width does not match the module port. This
        option disables this behavior.

    -nodefaults
        do not resolve input port default values

    -nokeep_prints
        per default this pass sets the "keep" attribute on all modules
        that directly or indirectly display text on the terminal.
        This option disables this behavior.

    -nokeep_asserts
        per default this pass sets the "keep" attribute on all modules
        that directly or indirectly contain one or more formal properties.
        This option disables this behavior.

    -top <module>
        use the specified top module to build the design hierarchy. Modules
        outside this tree (unused modules) are removed.

        when the -top option is used, the 'top' attribute will be set on the
        specified top module. otherwise a module with the 'top' attribute set
        will implicitly be used as top module, if such a module exists.

    -auto-top
        automatically determine the top of the design hierarchy and mark it.

    -chparam name value 
       elaborate the top module using this parameter value. Modules on which
       this parameter does not exist may cause a warning message to be output.
       This option can be specified multiple times to override multiple
       parameters. String values must be passed in double quotes (").

In -generate mode this pass generates blackbox modules for the given cell
types (wildcards supported). For this the design is searched for cells that
match the given types and then the given port declarations are used to
determine the direction of the ports. The syntax for a port declaration is:

    {i|o|io}[@<num>]:<portname>

Input ports are specified with the 'i' prefix, output ports with the 'o'
prefix and inout ports with the 'io' prefix. The optional <num> specifies
the position of the port in the parameter list (needed when instantiated
using positional arguments). When <num> is not specified, the <portname> can
also contain wildcard characters.

This pass ignores the current selection and always operates on all modules
in the current design.


    hilomap [options] [selection]

Map constants to 'tielo' and 'tiehi' driver cells.

    -hicell <celltype> <portname>
        Replace constant hi bits with this cell.

    -locell <celltype> <portname>
        Replace constant lo bits with this cell.

    -singleton
        Create only one hi/lo cell and connect all constant bits
        to that cell. Per default a separate cell is created for
        each constant bit.


    history

This command prints all commands in the shell history buffer. This are
all commands executed in an interactive session, but not the commands
from executed scripts.


    ice40_braminit

This command processes all SB_RAM40_4K blocks with a non-empty INIT_FILE
parameter and converts it into the required INIT_x attributes


    ice40_dsp [options] [selection]

Map multipliers ($mul/SB_MAC16) and multiply-accumulate ($mul/SB_MAC16 + $add)
cells into iCE40 DSP resources.
Currently, only the 16x16 multiply mode is supported and not the 2 x 8x8 mode.

Pack input registers (A, B, {C,D}; with optional hold), pipeline registers
({F,J,K,G}, H), output registers (O -- full 32-bits or lower 16-bits only; with
optional hold), and post-adder into the SB_MAC16 resource.

Multiply-accumulate operations using the post-adder with feedback on the {C,D}
input will be folded into the DSP. In this scenario only, resetting the
the accumulator to an arbitrary value can be inferred to use the {C,D} input.


    ice40_opt [options] [selection]

This command executes the following script:

    do
        <ice40 specific optimizations>
        opt_expr -mux_undef -undriven [-full]
        opt_merge
        opt_dff
        opt_clean
    while <changed design>


    ice40_wrapcarry [selection]

Wrap manually instantiated SB_CARRY cells, along with their associated SB_LUT4s,
into an internal $__ICE40_CARRY_WRAPPER cell for preservation across technology
mapping.

Attributes on both cells will have their names prefixed with 'SB_CARRY.' or
'SB_LUT4.' and attached to the wrapping cell.
A (* keep *) attribute on either cell will be logically OR-ed together.

    -unwrap
        unwrap $__ICE40_CARRY_WRAPPER cells back into SB_CARRYs and SB_LUT4s,
        including restoring their attributes.


    insbuf [options] [selection]

Insert buffer cells into the design for directly connected wires.

    -buf <celltype> <in-portname> <out-portname>
        Use the given cell type instead of $_BUF_. (Notice that the next
        call to "clean" will remove all $_BUF_ in the design.)

    -chain
        Chain buffer cells

Print internal statistics for developers (experimental)

    iopadmap [options] [selection]

Map module inputs/outputs to PAD cells from a library. This pass
can only map to very simple PAD cells. Use 'techmap' to further map
the resulting cells to more sophisticated PAD cells.

    -inpad <celltype> <in_port>[:<ext_port>]
        Map module input ports to the given cell type with the
        given output port name. if a 2nd portname is given, the
        signal is passed through the pad cell, using the 2nd
        portname as the port facing the module port.

    -outpad <celltype> <out_port>[:<ext_port>]
    -inoutpad <celltype> <io_port>[:<ext_port>]
        Similar to -inpad, but for output and inout ports.

    -toutpad <celltype> <oe_port>:<out_port>[:<ext_port>]
        Merges $_TBUF_ cells into the output pad cell. This takes precedence
        over the other -outpad cell. The first portname is the enable input
        of the tristate driver, which can be prefixed with `~` for negative
        polarity enable.

    -tinoutpad <celltype> <oe_port>:<in_port>:<out_port>[:<ext_port>]
        Merges $_TBUF_ cells into the inout pad cell. This takes precedence
        over the other -inoutpad cell. The first portname is the enable input
        of the tristate driver and the 2nd portname is the internal output
        buffering the external signal.  Like with `-toutpad`, the enable can
        be marked as negative polarity by prefixing the name with `~`.

    -ignore <celltype> <portname>[:<portname>]*
        Skips mapping inputs/outputs that are already connected to given
        ports of the given cell.  Can be used multiple times.  This is in
        addition to the cells specified as mapping targets.

    -widthparam <param_name>
        Use the specified parameter name to set the port width.

    -nameparam <param_name>
        Use the specified parameter to set the port name.

    -bits
        create individual bit-wide buffers even for ports that
        are wider. (the default behavior is to create word-wide
        buffers using -widthparam to set the word size on the cell.)

Tristate PADS (-toutpad, -tinoutpad) always operate in -bits mode.


    jny [options] [selection]

Write JSON netlist metadata for the current design

    -o <filename>
        write to the specified file.

    -no-connections
        Don't include connection information in the netlist output.

    -no-attributes
        Don't include attributed information in the netlist output.

    -no-properties
        Don't include property information in the netlist output.

See 'help write_jny' for a description of the JSON format used.


    json [options] [selection]

Write a JSON netlist of all selected objects.

    -o <filename>
        write to the specified file.

    -aig
        also include AIG models for the different gate types

    -compat-int
        emit 32-bit or smaller fully-defined parameter values directly
        as JSON numbers (for compatibility with old parsers)

See 'help write_json' for a description of the JSON format used.


    keep_hierarchy [options]

Add the keep_hierarchy attribute.

    -min_cost <min_cost>
        only add the attribute to modules estimated to have more
        than <min_cost> gates after simple techmapping. Intended
        for tuning trade-offs between quality and yosys runtime.

    lattice_gsr [options] [selection]

Trim active low async resets connected to GSR and resolve GSR parameter,
if a GSR or SGSR primitive is used in the design.

If any cell has the GSR parameter set to "AUTO", this will be resolved
to "ENABLED" if a GSR primitive is present and the (* nogsr *) attribute
is not set, otherwise it will be resolved to "DISABLED".


    license

This command produces the following notice.

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/


    log [options] string
    log [ -push | -pop ]

Print the given string to the screen and/or the log file. This is useful for TCL
scripts, because the TCL command "puts" only goes to stdout but not to
logfiles.

    -stdout
        Print the output to stdout too. This is useful when all Yosys is
        executed with a script and the -q (quiet operation) argument to notify
        the user.

    -stderr
        Print the output to stderr too.

    -nolog
        Don't use the internal log() command. Use either -stdout or -stderr,
        otherwise no output will be generated at all.

    -n
        do not append a newline

    -header
        log a pass header

    -push
        push a new level on the pass counter

    -pop
        pop from the pass counter


    logger [options]

This command sets global logger properties, also available using command line
options.

    -[no]time
        enable/disable display of timestamp in log output.

    -[no]stderr
        enable/disable logging errors to stderr.

    -warn regex
        print a warning for all log messages matching the regex.

    -nowarn regex
        if a warning message matches the regex, it is printed as regular
        message instead.

    -werror regex
        if a warning message matches the regex, it is printed as error
        message instead and the tool terminates with a nonzero return code.

    -[no]debug
        globally enable/disable debug log messages.

    -experimental <feature>
        do not print warnings for the specified experimental feature

    -expect <type> <regex> <expected_count>
        expect log, warning or error to appear. matched errors will terminate
        with exit code 0.

    -expect-no-warnings
        gives error in case there is at least one warning that is not expected.

    -check-expected
        verifies that the patterns previously set up by -expect have actually
        been met, then clears the expected log list.  If this is not called
        manually, the check will happen at yosys exist time instead.


    ls [selection]

When no active module is selected, this prints a list of modules.

When an active module is selected, this prints a list of objects in the module.


    ltp [options] [selection]

This command prints the longest topological path in the design. (Only considers
paths within a single module, so the design must be flattened.)

    -noff
        automatically exclude FF cell types


    lut2mux [options] [selection]

This pass converts $lut cells to $_MUX_ gates.


    maccmap [-unmap] [selection]

This pass maps $macc cells to yosys $fa and $alu cells. When the -unmap option
is used then the $macc cell is mapped to $add, $sub, etc. cells instead.


    memory [-norom] [-nomap] [-nordff] [-nowiden] [-nosat] [-memx] [-no-rw-check] [-bram <bram_rules>] [selection]

This pass calls all the other memory_* passes in a useful order:

    opt_mem
    opt_mem_priority
    opt_mem_feedback
    memory_bmux2rom                     (skipped if called with -norom)
    memory_dff [-no-rw-check]           (skipped if called with -nordff or -memx)
    opt_clean
    memory_share [-nowiden] [-nosat]
    opt_mem_widen
    memory_memx                         (when called with -memx)
    opt_clean
    memory_collect
    memory_bram -rules <bram_rules>     (when called with -bram)
    memory_map                          (skipped if called with -nomap)

This converts memories to word-wide DFFs and address decoders
or multiport memory blocks if called with the -nomap option.


    memory_bmux2rom [options] [selection]

This pass converts $bmux cells with constant A input to ROMs.


    memory_bram -rules <rule_file> [selection]

This pass converts the multi-port $mem memory cells into block ram instances.
The given rules file describes the available resources and how they should be
used.

The rules file contains configuration options, a set of block ram description
and a sequence of match rules.

The option 'attr_icase' configures how attribute values are matched. The value 0
means case-sensitive, 1 means case-insensitive.

A block ram description looks like this:

    bram RAMB1024X32     # name of BRAM cell
      init 1             # set to '1' if BRAM can be initialized
      abits 10           # number of address bits
      dbits 32           # number of data bits
      groups 2           # number of port groups
      ports  1 1         # number of ports in each group
      wrmode 1 0         # set to '1' if this groups is write ports
      enable 4 1         # number of enable bits
      transp 0 2         # transparent (for read ports)
      clocks 1 2         # clock configuration
      clkpol 2 2         # clock polarity configuration
    endbram

For the option 'transp' the value 0 means non-transparent, 1 means transparent
and a value greater than 1 means configurable. All groups with the same
value greater than 1 share the same configuration bit.

For the option 'clocks' the value 0 means non-clocked, and a value greater
than 0 means clocked. All groups with the same value share the same clock
signal.

For the option 'clkpol' the value 0 means negative edge, 1 means positive edge
and a value greater than 1 means configurable. All groups with the same value
greater than 1 share the same configuration bit.

Using the same bram name in different bram blocks will create different variants
of the bram. Verilog configuration parameters for the bram are created as
needed.

It is also possible to create variants by repeating statements in the bram block
and appending '@<label>' to the individual statements.

A match rule looks like this:

    match RAMB1024X32
      max waste 16384    # only use this bram if <= 16k ram bits are unused
      min efficiency 80  # only use this bram if efficiency is at least 80%
    endmatch

It is possible to match against the following values with min/max rules:

    words  ........  number of words in memory in design
    abits  ........  number of address bits on memory in design
    dbits  ........  number of data bits on memory in design
    wports  .......  number of write ports on memory in design
    rports  .......  number of read ports on memory in design
    ports  ........  number of ports on memory in design
    bits  .........  number of bits in memory in design
    dups ..........  number of duplications for more read ports

    awaste  .......  number of unused address slots for this match
    dwaste  .......  number of unused data bits for this match
    bwaste  .......  number of unused bram bits for this match
    waste  ........  total number of unused bram bits (bwaste*dups)
    efficiency  ...  total percentage of used and non-duplicated bits

    acells  .......  number of cells in 'address-direction'
    dcells  .......  number of cells in 'data-direction'
    cells  ........  total number of cells (acells*dcells*dups)

A match containing the command 'attribute' followed by a list of space
separated 'name[=string_value]' values requires that the memory contains any
one of the given attribute name and string values (where specified), or name
and integer 1 value (if no string_value given, since Verilog will interpret
'(* attr *)' as '(* attr=1 *)').
A name prefixed with '!' indicates that the attribute must not exist.

The interface for the created bram instances is derived from the bram
description. Use 'techmap' to convert the created bram instances into
instances of the actual bram cells of your target architecture.

A match containing the command 'or_next_if_better' is only used if it
has a higher efficiency than the next match (and the one after that if
the next also has 'or_next_if_better' set, and so forth).

A match containing the command 'make_transp' will add external circuitry
to simulate 'transparent read', if necessary.

A match containing the command 'make_outreg' will add external flip-flops
to implement synchronous read ports, if necessary.

A match containing the command 'shuffle_enable A' will re-organize
the data bits to accommodate the enable pattern of port A.


    memory_collect [selection]

This pass collects memories and memory ports and creates generic multiport
memory cells.


    memory_dff [-no-rw-check] [selection]

This pass detects DFFs at memory read ports and merges them into the memory
port. I.e. it consumes an asynchronous memory port and the flip-flops at its
interface and yields a synchronous memory port.

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


    memory_libmap -lib <library_file> [-D <condition>] [selection]

This pass takes a description of available RAM cell types and maps
all selected memories to one of them, or leaves them to be mapped to FFs.

  -lib <library_file>
    Selects a library file containing RAM cell definitions. This option
    can be passed more than once to select multiple libraries.
    See passes/memory/memlib.md for description of the library format.

  -D <condition>
    Enables a condition that can be checked within the library file
    to eg. select between slightly different hardware variants.
    This option can be passed any number of times.

  -logic-cost-rom <num>
  -logic-cost-ram <num>
    Sets the cost of a single bit for memory lowered to soft logic.

  -no-auto-distributed
  -no-auto-block
  -no-auto-huge
    Disables automatic mapping of given kind of RAMs.  Manual mapping
    (using ram_style or other attributes) is still supported.


    memory_map [options] [selection]

This pass converts multiport memory cells as generated by the memory_collect
pass to word-wide DFFs and address decoders.

    -attr !<name>
        do not map memories that have attribute <name> set.

    -attr <name>[=<value>]
        for memories that have attribute <name> set, only map them if its value
        is a string <value> (if specified), or an integer 1 (otherwise). if this
        option is specified multiple times, map the memory if the attribute is
        to any of the values.

    -iattr
        for -attr, suppress case sensitivity in matching of <value>.

    -rom-only
        only perform conversion for ROMs (memories with no write ports).

    -keepdc
        when mapping ROMs, keep x-bits shared across read ports.

    -formal
        map memories for a global clock based formal verification flow.
        This implies -keepdc, uses $ff cells for ROMs and sets hdlname
        attributes. It also has limited support for async write ports
        as generated by clk2fflogic.


    memory_memx [selection]

This pass adds additional circuitry that emulates the Verilog simulation
behavior for out-of-bounds memory reads and writes.


    memory_narrow [options] [selection]

This pass splits up wide memory ports into several narrow ports.


    memory_nordff [options] [selection]

This pass extracts FFs from memory read ports. This results in a netlist
similar to what one would get from not calling memory_dff.


    memory_share [-nosat] [-nowiden] [selection]

This pass merges share-able memory ports into single memory ports.

The following methods are used to consolidate the number of memory ports:

  - When multiple write ports access the same address then this is converted
    to a single write port with a more complex data and/or enable logic path.

  - When multiple read or write ports access adjacent aligned addresses, they
    are merged to a single wide read or write port.  This transformation can be
    disabled with the "-nowiden" option.

  - When multiple write ports are never accessed at the same time (a SAT
    solver is used to determine this), then the ports are merged into a single
    write port.  This transformation can be disabled with the "-nosat" option.

Note that in addition to the algorithms implemented in this pass, the $memrd
and $memwr cells are also subject to generic resource sharing passes (and other
optimizations) such as "share" and "opt_merge".


    memory_unpack [selection]

This pass converts the multi-port $mem memory cells into individual $memrd and
$memwr cells. It is the counterpart to the memory_collect pass.


    microchip_dffopt [options] [selection]

Converts hardware clock enable and set/reset signals on FFs to emulation
using LUTs, if doing so would improve area. Operates on post-techmap LUT, DFF
cells. 


    microchip_dsp [options] [selection]

Pack input registers 'A', 'B', 'C', and 'D' (with optional enable/reset),
output register 'P' (with optional enable/reset), pre-adder and/or post-adder into
Microchip DSP resources.

Multiply-accumulate operations using the post-adder with feedback on the 'C'
input will be folded into the DSP. In this scenario only, the 'C' input can be
used to override the current accumulation result with a new value. This will
be added to the multiplier result to form the next accumulation result.

Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'
connections (optionally, where 'P' is right-shifted by 17-bits and used as an
input to the post-adder. This pattern is common for summing partial products to
implement wide multipliers). Cascade chains are limited to a mazimum length 
of 24 cells, corresponding to PolarFire (pf) devices.

This pass is a no-op if the scratchpad variable 'microchip_dsp.multonly' is set
to 1.


    -family {polarfire}
        select the family to target
        default: polarfire


    miter -equiv [options] gold_name gate_name miter_name

Creates a miter circuit for equivalence checking. The gold- and gate- modules
must have the same interfaces. The miter circuit will have all inputs of the
two source modules, prefixed with 'in_'. The miter circuit has a 'trigger'
output that goes high if an output mismatch between the two source modules is
detected.

    -ignore_gold_x
        a undef (x) bit in the gold module output will match any value in
        the gate module output.

    -make_outputs
        also route the gold- and gate-outputs to 'gold_*' and 'gate_*' outputs
        on the miter circuit.

    -make_outcmp
        also create a cmp_* output for each gold/gate output pair.

    -make_assert
        also create an 'assert' cell that checks if trigger is always low.

    -make_cover
        also create a 'cover' cell for each gold/gate output pair.

    -flatten
        call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.


    -cross
        allow output ports on the gold module to match input ports on the
        gate module. This is useful when the gold module contains additional
        logic to drive some of the gate module inputs.


    miter -assert [options] module [miter_name]

Creates a miter circuit for property checking. All input ports are kept,
output ports are discarded. An additional output 'trigger' is created that
goes high when an assert is violated. Without a miter_name, the existing
module is modified.

    -make_outputs
        keep module output ports.

    -flatten
        call 'flatten -wb; opt_expr -keepdc -undriven;;' on the miter circuit.


    mutate -list N [options] [selection]

Create a list of N mutations using an even sampling.

    -o filename
        Write list to this file instead of console output

    -s filename
        Write a list of all src tags found in the design to the specified file

    -seed N
        RNG seed for selecting mutations

    -none
        Include a "none" mutation in the output

    -ctrl name width value
        Add -ctrl options to the output. Use 'value' for first mutation, then
        simply count up from there.

    -mode name
    -module name
    -cell name
    -port name
    -portbit int
    -ctrlbit int
    -wire name
    -wirebit int
    -src string
        Filter list of mutation candidates to those matching
        the given parameters.

    -cfg option int
        Set a configuration option. Options available:
          weight_pq_w weight_pq_b weight_pq_c weight_pq_s
          weight_pq_mw weight_pq_mb weight_pq_mc weight_pq_ms
          weight_cover pick_cover_prcnt


    mutate -mode MODE [options]

Apply the given mutation.

    -ctrl name width value
        Add a control signal with the given name and width. The mutation is
        activated if the control signal equals the given value.

    -module name
    -cell name
    -port name
    -portbit int
    -ctrlbit int
        Mutation parameters, as generated by 'mutate -list N'.

    -wire name
    -wirebit int
    -src string
        Ignored. (They are generated by -list for documentation purposes.)


    muxcover [options] [selection]

Cover trees of $_MUX_ cells with $_MUX{4,8,16}_ cells

    -mux4[=cost], -mux8[=cost], -mux16[=cost]
        Cover $_MUX_ trees using the specified types of MUXes (with optional
        integer costs). If none of these options are given, the effect is the
        same as if all of them are.
        Default costs: $_MUX4_ = 220, $_MUX8_ = 460, 
                       $_MUX16_ = 940

    -mux2=cost
        Use the specified cost for $_MUX_ cells when making covering decisions.
        Default cost: $_MUX_ = 100

    -dmux=cost
        Use the specified cost for $_MUX_ cells used in decoders.
        Default cost: 90

    -nodecode
        Do not insert decoder logic. This reduces the number of possible
        substitutions, but guarantees that the resulting circuit is not
        less efficient than the original circuit.

    -nopartial
        Do not consider mappings that use $_MUX<N>_ to select from less
        than <N> different signals.


    muxpack [selection]

This pass converts cascaded chains of $pmux cells (e.g. those create from case
constructs) and $mux cells (e.g. those created by if-else constructs) into
$pmux cells.

This optimisation is conservative --- it will only pack $mux or $pmux cells
whose select lines are driven by '$eq' cells with other such cells if it can be
certain that their select inputs are mutually exclusive.


    nlutmap [options] [selection]

This pass uses successive calls to 'abc' to map to an architecture. That
provides a small number of differently sized LUTs.

    -luts N_1,N_2,N_3,...
        The number of LUTs with 1, 2, 3, ... inputs that are
        available in the target architecture.

    -assert
        Create an error if not all logic can be mapped

Excess logic that does not fit into the specified LUTs is mapped back
to generic logic gates ($_AND_, etc.).


    nx_carry [options] [selection]

Fixes carry chain if needed, break it on 24 elements and group by 4 into NX_CY.


    onehot [options] [selection]

This pass optimizes $eq cells that compare one-hot signals against constants

    -v, -vv
        verbose output


    opt [options] [selection]

This pass calls all the other opt_* passes in a useful order. This performs
a series of trivial optimizations and cleanups. This pass executes the other
passes in the following order:

    opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]
    opt_merge [-share_all] -nomux

    do
        opt_muxtree
        opt_reduce [-fine] [-full]
        opt_merge [-share_all]
        opt_share  (-full only)
        opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat]  (except when called with -noff)
        opt_clean [-purge]
        opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]
    while <changed design>

When called with -fast the following script is used instead:

    do
        opt_expr [-mux_undef] [-mux_bool] [-undriven] [-noclkinv] [-fine] [-full] [-keepdc]
        opt_merge [-share_all]
        opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat]  (except when called with -noff)
        opt_clean [-purge]
    while <changed design in opt_dff>

Note: Options in square brackets (such as [-keepdc]) are passed through to
the opt_* commands when given to 'opt'.



    opt_clean [options] [selection]

This pass identifies wires and cells that are unused and removes them. Other
passes often remove cells but leave the wires in the design or reconnect the
wires but leave the old cells in the design. This pass can be used to clean up
after the passes that do the actual work.

This pass only operates on completely selected modules without processes.

    -purge
        also remove internal nets if they have a public name


    opt_demorgan [selection]

This pass pushes inverters through $reduce_* cells if this will reduce the
overall gate count of the circuit


    opt_dff [-nodffe] [-nosdff] [-keepdc] [-sat] [selection]

This pass converts flip-flops to a more suitable type by merging clock enables
and synchronous reset multiplexers, removing unused control inputs, or
potentially removes the flip-flop altogether, converting it to a constant
driver.

    -nodffe
        disables dff -> dffe conversion, and other transforms recognizing clock
        enable

    -nosdff
        disables dff -> sdff conversion, and other transforms recognizing sync
        resets

    -simple-dffe
        only enables clock enable recognition transform for obvious cases

    -sat
        additionally invoke SAT solver to detect and remove flip-flops (with
        non-constant inputs) that can also be replaced with a constant driver

    -keepdc
        some optimizations change the behavior of the circuit with respect to
        don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
        all result bits to be set to x. this behavior changes when 'a+0' is
        replaced by 'a'. the -keepdc option disables all such optimizations.


    opt_expr [options] [selection]

This pass performs const folding on internal cell types with constant inputs.
It also performs some simple expression rewriting.

    -mux_undef
        remove 'undef' inputs from $mux, $pmux and $_MUX_ cells

    -mux_bool
        replace $mux cells with inverters or buffers when possible

    -undriven
        replace undriven nets with undef (x) constants

    -noclkinv
        do not optimize clock inverters by changing FF types

    -fine
        perform fine-grain optimizations

    -full
        alias for -mux_undef -mux_bool -undriven -fine

    -keepdc
        some optimizations change the behavior of the circuit with respect to
        don't-care bits. for example in 'a+0' a single x-bit in 'a' will cause
        all result bits to be set to x. this behavior changes when 'a+0' is
        replaced by 'a'. the -keepdc option disables all such optimizations.


    opt_ffinv [selection]

This pass pushes inverters to the other side of a FF when they can be merged
into LUTs on the other side.


    opt_lut [options] [selection]

This pass combines cascaded $lut cells with unused inputs.

	-tech ice40
        treat the design as a LUT-mapped circuit for the iCE40 architecture
        and preserve connections to SB_CARRY as appropriate

    -limit N
        only perform the first N combines, then stop. useful for debugging.


    opt_lut_ins [options] [selection]

This pass removes unused inputs from LUT cells (that is, inputs that can not
influence the output signal given this LUT's value).  While such LUTs cannot
be directly emitted by ABC, they can be a result of various post-ABC
transformations, such as mapping wide LUTs (not all sub-LUTs will use the
full set of inputs) or optimizations such as xilinx_dffopt.

    -tech <technology>
        Instead of generic $lut cells, operate on LUT cells specific
        to the given technology.  Valid values are: xilinx, lattice, gowin.


    opt_mem [options] [selection]

This pass performs various optimizations on memories in the design.


    opt_mem_feedback [selection]

This pass detects cases where an asynchronous read port is only connected via
a mux tree to a write port with the same address.  When such a connection is
found, it is replaced with a new condition on an enable signal, allowing
for removal of the read port.


    opt_mem_priority [selection]

This pass detects cases where one memory write port has priority over another
even though they can never collide with each other -- ie. there can never be
a situation where a given memory bit is written by both ports at the same
time, for example because of always-different addresses, or mutually exclusive
enable signals. In such cases, the priority relation is removed.


    opt_mem_widen [options] [selection]

This pass looks for memories where all ports are wide and adjusts the base
memory width up until that stops being the case.


    opt_merge [options] [selection]

This pass identifies cells with identical type and input signals. Such cells
are then merged to one cell.

    -nomux
        Do not merge MUX cells.

    -share_all
        Operate on all cell types, not just built-in types.

    -keepdc
        Do not merge flipflops with don't-care bits in their initial value.


    opt_muxtree [selection]

This pass analyzes the control signals for the multiplexer trees in the design
and identifies inputs that can never be active. It then removes this dead
branches from the multiplexer trees.

This pass only operates on completely selected modules without processes.


    opt_reduce [options] [selection]

This pass performs two interlinked optimizations:

1. it consolidates trees of large AND gates or OR gates and eliminates
duplicated inputs.

2. it identifies duplicated inputs to MUXes and replaces them with a single
input with the original control signals OR'ed together.

    -fine
      perform fine-grain optimizations

    -full
      alias for -fine


    opt_share [selection]

This pass identifies mutually exclusive cells of the same type that:
    (a) share an input signal,
    (b) drive the same $mux, $_MUX_, or $pmux multiplexing cell,

allowing the cell to be merged and the multiplexer to be moved from
multiplexing its output to multiplexing the non-shared input signals.


    paramap [options] [selection]

This command renames cell parameters and/or maps key/value pairs to
other key/value pairs.

    -tocase <name>
        Match attribute names case-insensitively and set it to the specified
        name.

    -rename <old_name> <new_name>
        Rename attributes as specified

    -map <old_name>=<old_value> <new_name>=<new_value>
        Map key/value pairs as indicated.

    -imap <old_name>=<old_value> <new_name>=<new_value>
        Like -map, but use case-insensitive match for <old_value> when
        it is a string value.

    -remove <name>=<value>
        Remove attributes matching this pattern.

For example, mapping Diamond-style ECP5 "init" attributes to Yosys-style:

    paramap -tocase INIT t:LUT4


    peepopt [options] [selection]

This pass applies a collection of peephole optimizers to the current design.

This pass employs the following rules:

   * muldiv - Replace (A*B)/B with A

   * shiftmul - Replace A>>(B*C) with A'>>(B<<K) where C and K are constants
                and A' is derived from A by appropriately inserting padding
                into the signal. (right variant)

                Analogously, replace A<<(B*C) with appropriate selection of
                output bits from A<<(B<<K). (left variant)

   * shiftadd - Replace A>>(B+D) with (A'>>D)>>(B) where D is constant and
                A' is derived from A by padding or cutting inaccessible bits.
                Scratchpad: 'peepopt.shiftadd.max_data_multiple' (default: 2)
                limits the amount of padding to a multiple of the data, 
                to avoid high resource usage from large temporary MUX trees.


    plugin [options]

Load and list loaded plugins.

    -i <plugin_filename>
        Load (install) the specified plugin.

    -a <alias_name>
        Register the specified alias name for the loaded plugin

    -l
        List loaded plugins


    pmux2shiftx [options] [selection]

This pass transforms $pmux cells to $shiftx cells.

    -v, -vv
        verbose output

    -min_density <percentage>
        specifies the minimum density for the shifter
        default: 50

    -min_choices <int>
        specified the minimum number of choices for a control signal
        default: 3

    -onehot ignore|pmux|shiftx
        select strategy for one-hot encoded control signals
        default: pmux

    -norange
        disable $sub inference for "range decoders"


    pmuxtree [selection]

This pass transforms $pmux cells to trees of $mux cells.


    portlist [options] [selection]

This command lists all module ports found in the selected modules.

If no selection is provided then it lists the ports on the top module.

  -m
    print verilog blackbox module definitions instead of port lists


    prep [options]

This command runs a conservative RTL synthesis. A typical application for this
is the preparation stage of a verification flow. This command does not operate
on partly selected designs.

    -top <module>
        use the specified module as top module (default='top')

    -auto-top
        automatically determine the top of the design hierarchy

    -flatten
        flatten the design before synthesis. this will pass '-auto-top' to
        'hierarchy' if no top module is specified.

    -ifx
        passed to 'proc'. uses verilog simulation behavior for verilog if/case
        undef handling. this also prevents 'wreduce' from being run.

    -memx
        simulate verilog simulation behavior for out-of-bounds memory accesses
        using the 'memory_memx' pass.

    -nomem
        do not run any of the memory_* passes

    -rdff
        call 'memory_dff'. This enables merging of FFs into
        memory read ports.

    -nokeepdc
        do not call opt_* with -keepdc

    -run <from_label>[:<to_label>]
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.


The following commands are executed by this synthesis command:

    begin:
        hierarchy -check [-top <top> | -auto-top]

    coarse:
        proc [-ifx]
        flatten    (if -flatten)
        future
        opt_expr -keepdc
        opt_clean
        check
        opt -noff -keepdc
        wreduce -keepdc [-memx]
        memory_dff    (if -rdff)
        memory_memx    (if -memx)
        opt_clean
        memory_collect
        opt -noff -keepdc -fast

    check:
        stat
        check


    printattrs [selection]

Print all attributes of the selected objects.



    proc [options] [selection]

This pass calls all the other proc_* passes in the most common order.

    proc_clean
    proc_rmdead
    proc_prune
    proc_init
    proc_arst
    proc_rom
    proc_mux
    proc_dlatch
    proc_dff
    proc_memwr
    proc_clean
    opt_expr -keepdc

This replaces the processes in the design with multiplexers,
flip-flops and latches.

The following options are supported:

    -nomux
        Will omit the proc_mux pass.

    -norom
        Will omit the proc_rom pass.

    -global_arst [!]<netname>
        This option is passed through to proc_arst.

    -ifx
        This option is passed through to proc_mux. proc_rmdead is not
        executed in -ifx mode.

    -noopt
        Will omit the opt_expr pass.


    proc_arst [-global_arst [!]<netname>] [selection]

This pass identifies asynchronous resets in the processes and converts them
to a different internal representation that is suitable for generating
flip-flop cells with asynchronous resets.

    -global_arst [!]<netname>
        In modules that have a net with the given name, use this net as async
        reset for registers that have been assign initial values in their
        declaration ('reg foobar = constant_value;'). Use the '!' modifier for
        active low reset signals. Note: the frontend stores the default value
        in the 'init' attribute on the net.


    proc_clean [options] [selection]

    -quiet
        do not print any messages.

This pass removes empty parts of processes and ultimately removes a process
if it contains only empty structures.


    proc_dff [selection]

This pass identifies flip-flops in the processes and converts them to
d-type flip-flop cells.


    proc_dlatch [selection]

This pass identifies latches in the processes and converts them to
d-type latches.


    proc_init [selection]

This pass extracts the 'init' actions from processes (generated from Verilog
'initial' blocks) and sets the initial value to the 'init' attribute on the
respective wire.


    proc_memwr [selection]

This pass converts memory writes in processes into $memwr cells.


    proc_mux [options] [selection]

This pass converts the decision trees in processes (originating from if-else
and case statements) to trees of multiplexer cells.

    -ifx
        Use Verilog simulation behavior with respect to undef values in
        'case' expressions and 'if' conditions.


    proc_prune [selection]

This pass identifies assignments in processes that are always overwritten by
a later assignment to the same signal and removes them.


    proc_rmdead [selection]

This pass identifies unreachable branches in decision trees and removes them.


    proc_rom [selection]

This pass converts switches into read-only memories when appropriate.


    qbfsat [options] [selection]

This command solves an "exists-forall" 2QBF-SAT problem defined over the
currently selected module. Existentially-quantified variables are declared by
assigning a wire "$anyconst". Universally-quantified variables may be
explicitly declared by assigning a wire "$allconst", but module inputs will be
treated as universally-quantified variables by default.

    -nocleanup
        Do not delete temporary files and directories. Useful for debugging.

    -dump-final-smt2 <file>
        Pass the --dump-smt2 option to yosys-smtbmc.

    -assume-outputs
        Add an "$assume" cell for the conjunction of all one-bit module output
        wires.

    -assume-negative-polarity
        When adding $assume cells for one-bit module output wires, assume they
        are negative polarity signals and should always be low, for example like
        the miters created with the `miter` command.

    -nooptimize
        Ignore "\minimize" and "\maximize" attributes, do not emit
        "(maximize)" or "(minimize)" in the SMT-LIBv2, and generally make no
        attempt to optimize anything.

    -nobisection
        If a wire is marked with the "\minimize" or "\maximize" attribute,
        do not attempt to optimize that value with the default iterated solving
        and threshold bisection approach. Instead, have yosys-smtbmc emit a
        "(minimize)" or "(maximize)" command in the SMT-LIBv2 output and
        hope that the solver supports optimizing quantified bitvector problems.

    -solver <solver>
        Use a particular solver. Choose one of: "z3", "yices", "cvc4"
        and "cvc5". (default: yices)

    -solver-option <name> <value>
        Set the specified solver option in the SMT-LIBv2 problem file.

    -timeout <value>
        Set the per-iteration timeout in seconds.
        (default: no timeout)

    -O0, -O1, -O2
        Control the use of ABC to simplify the QBF-SAT problem before solving.

    -sat
        Generate an error if the solver does not return "sat".

    -unsat
        Generate an error if the solver does not return "unsat".

    -show-smtbmc
        Print the output from yosys-smtbmc.

    -specialize
        If the problem is satisfiable, replace each "$anyconst" cell with its
        corresponding constant value from the model produced by the solver.

    -specialize-from-file <solution file>
        Do not run the solver, but instead only attempt to replace each
        "$anyconst" cell in the current module with a constant value provided
        by the specified file.

    -write-solution <solution file>
        If the problem is satisfiable, write the corresponding constant value
        for each "$anyconst" cell from the model produced by the solver to the
        specified file.


    ql_bram_merge [selection]

    This pass identifies k6n10f 18K BRAM cells and packs pairs of them together
    into a TDP36K cell operating in split mode


    ql_bram_types [selection]

    This pass changes the type of TDP36K cells to different types based on the
    configuration of the cell.


    ql_dsp_io_regs [options] [selection]

This pass looks for QL_DSP2 cells and changes their cell type depending on their
configuration.

    ql_dsp_macc [selection]

This pass looks for a multiply-accumulate pattern based on which it infers a
QuickLogic DSP cell.


    ql_dsp_simd [selection]

This pass identifies K6N10f DSP cells with identical configuration and pack pairs
of them together into other DSP cells that can perform SIMD operation.

    read {-vlog95|-vlog2k|-sv2005|-sv2009|-sv2012|-sv|-formal} <verilog-file>..

Load the specified Verilog/SystemVerilog files. (Full SystemVerilog support
is only available via Verific.)

Additional -D<macro>[=<value>] options may be added after the option indicating
the language version (and before file names) to set additional verilog defines.


    read {-liberty} <liberty-file>..

Load the specified Liberty files.

    -lib
        only create empty blackbox modules


    read {-f|-F} <command-file>

Load and execute the specified command file. (Requires Verific.)
Check verific command for more information about supported commands in file.


    read -define <macro>[=<value>]..

Set global Verilog/SystemVerilog defines.


    read -undef <macro>..

Unset global Verilog/SystemVerilog defines.


    read -incdir <directory>

Add directory to global Verilog/SystemVerilog include directories.


    read -verific
    read -noverific

Subsequent calls to 'read' will either use or not use Verific. Calling 'read'
with -verific will result in an error on Yosys binaries that are built without
Verific support. The default is to use Verific if it is available.


    read_aiger [options] [filename]

Load module from an AIGER file into the current design.

    -module_name <module_name>
        name of module to be created (default: <filename>)

    -clk_name <wire_name>
        if specified, AIGER latches to be transformed into $_DFF_P_ cells
        clocked by wire of this name. otherwise, $_FF_ cells will be used

    -map <filename>
        read file with port and latch symbols

    -wideports
        merge ports that match the pattern 'name[int]' into a single
        multi-bit port 'name'

    -xaiger
        read XAIGER extensions


    read_blif [options] [filename]

Load modules from a BLIF file into the current design.

    -sop
        Create $sop cells instead of $lut cells

    -wideports
        Merge ports that match the pattern 'name[int]' into a single
        multi-bit port 'name'.


    read_json [filename]

Load modules from a JSON file into the current design See "help write_json"
for a description of the file format.


    read_liberty [filename]

Read cells from liberty file as modules into current design.

    -lib
        only create empty blackbox modules

    -wb
        mark imported cells as whiteboxes

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a blackbox
        module, and overwrite the existing module if it is  a blackbox module.)

    -overwrite
        overwrite existing modules with the same name

    -ignore_miss_func
        ignore cells with missing function specification of outputs

    -ignore_miss_dir
        ignore cells with a missing or invalid direction
        specification on a pin

    -ignore_miss_data_latch
        ignore latches with missing data and/or enable pins

    -setattr <attribute_name>
        set the specified attribute (to the value 1) on all loaded modules

    -unit_delay
        import combinational timing arcs under the unit delay model


    read_rtlil [filename]

Load modules from an RTLIL file to the current design. (RTLIL is a text
representation of a design in yosys's internal format.)

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a blackbox
        module, and overwrite the existing module if it is a blackbox module.)

    -overwrite
        overwrite existing modules with the same name

    -lib
        only create empty blackbox modules


    read_verilog [options] [filename]

Load modules from a Verilog file to the current design. A large subset of
Verilog-2005 is supported.

    -sv
        enable support for SystemVerilog features. (only a small subset
        of SystemVerilog is supported)

    -formal
        enable support for SystemVerilog assertions and some Yosys extensions
        replace the implicit -D SYNTHESIS with -D FORMAL

    -nosynthesis
        don't add implicit -D SYNTHESIS

    -noassert
        ignore assert() statements

    -noassume
        ignore assume() statements

    -norestrict
        ignore restrict() statements

    -assume-asserts
        treat all assert() statements like assume() statements

    -assert-assumes
        treat all assume() statements like assert() statements

    -nodisplay
        suppress output from display system tasks ($display et. al).
        This does not affect the output from a later 'sim' command.

    -debug
        alias for -dump_ast1 -dump_ast2 -dump_vlog1 -dump_vlog2 -yydebug

    -dump_ast1
        dump abstract syntax tree (before simplification)

    -dump_ast2
        dump abstract syntax tree (after simplification)

    -no_dump_ptr
        do not include hex memory addresses in dump (easier to diff dumps)

    -dump_vlog1
        dump ast as Verilog code (before simplification)

    -dump_vlog2
        dump ast as Verilog code (after simplification)

    -dump_rtlil
        dump generated RTLIL netlist

    -yydebug
        enable parser debug output

    -nolatches
        usually latches are synthesized into logic loops
        this option prohibits this and sets the output to 'x'
        in what would be the latches hold condition

        this behavior can also be achieved by setting the
        'nolatches' attribute on the respective module or
        always block.

    -nomem2reg
        under certain conditions memories are converted to registers
        early during simplification to ensure correct handling of
        complex corner cases. this option disables this behavior.

        this can also be achieved by setting the 'nomem2reg'
        attribute on the respective module or register.

        This is potentially dangerous. Usually the front-end has good
        reasons for converting an array to a list of registers.
        Prohibiting this step will likely result in incorrect synthesis
        results.

    -mem2reg
        always convert memories to registers. this can also be
        achieved by setting the 'mem2reg' attribute on the respective
        module or register.

    -nomeminit
        do not infer $meminit cells and instead convert initialized
        memories to registers directly in the front-end.

    -ppdump
        dump Verilog code after pre-processor

    -nopp
        do not run the pre-processor

    -nodpi
        disable DPI-C support

    -noblackbox
        do not automatically add a (* blackbox *) attribute to an
        empty module.

    -lib
        only create empty blackbox modules. This implies -DBLACKBOX.
        modules with the (* whitebox *) attribute will be preserved.
        (* lib_whitebox *) will be treated like (* whitebox *).

    -nowb
        delete (* whitebox *) and (* lib_whitebox *) attributes from
        all modules.

    -specify
        parse and import specify blocks

    -noopt
        don't perform basic optimizations (such as const folding) in the
        high-level front-end.

    -icells
        interpret cell types starting with '$' as internal cell types

    -pwires
        add a wire for each module parameter

    -nooverwrite
        ignore re-definitions of modules. (the default behavior is to
        create an error message if the existing module is not a black box
        module, and overwrite the existing module otherwise.)

    -overwrite
        overwrite existing modules with the same name

    -defer
        only read the abstract syntax tree and defer actual compilation
        to a later 'hierarchy' command. Useful in cases where the default
        parameters of modules yield invalid or not synthesizable code.

    -noautowire
        make the default of `default_nettype be "none" instead of "wire".

    -setattr <attribute_name>
        set the specified attribute (to the value 1) on all loaded modules

    -Dname[=definition]
        define the preprocessor symbol 'name' and set its optional value
        'definition'

    -Idir
        add 'dir' to the directories which are used when searching include
        files

The command 'verilog_defaults' can be used to register default options for
subsequent calls to 'read_verilog'.

Note that the Verilog frontend does a pretty good job of processing valid
verilog input, but has not very good error reporting. It generally is
recommended to use a simulator (for example Icarus Verilog) for checking
the syntax of the code, rather than to rely on read_verilog for that.

Depending on if read_verilog is run in -formal mode, either the macro
SYNTHESIS or FORMAL is defined automatically, unless -nosynthesis is used.
In addition, read_verilog always defines the macro YOSYS.

See the Yosys README file for a list of non-standard Verilog features
supported by the Yosys Verilog front-end.


    read_xaiger2 -sc_mapping [options] <filename>

Read a standard cell mapping from a XAIGER file into an existing module.

    -module_name <name>
        name of the target module

    -map2 <filename>
        read file with symbol information


WARNING: THE 'read_xaiger2' COMMAND IS EXPERIMENTAL.


    recover_names [command]

This pass executes a lossy mapping command and uses a combination of simulation
 to find candidate equivalences and SAT to recover exact original net names.


    rename old_name new_name

Rename the specified object. Note that selection patterns are not supported
by this command.



    rename -output old_name new_name

Like above, but also make the wire an output. This will fail if the object is
not a wire.


    rename -src [selection]

Assign names auto-generated from the src attribute to all selected wires and
cells with private names.


    rename -wire [selection] [-suffix <suffix>]

Assign auto-generated names based on the wires they drive to all selected
cells with private names. Ignores cells driving privatly named wires.
By default, the cell is named after the wire with the cell type as suffix.
The -suffix option can be used to set the suffix to the given string instead.


    rename -enumerate [-pattern <pattern>] [selection]

Assign short auto-generated names to all selected wires and cells with private
names. The -pattern option can be used to set the pattern for the new names.
The character % in the pattern is replaced with a integer number. The default
pattern is '_%_'.


    rename -witness

Assigns auto-generated names to all $any*/$all* output wires and containing
cells that do not have a public name. This ensures that, during formal
verification, a solver-found trace can be fully specified using a public
hierarchical names.


    rename -hide [selection]

Assign private names (the ones with $-prefix) to all selected wires and cells
with public names. This ignores all selected ports.


    rename -top new_name

Rename top module.


    rename -scramble-name [-seed <seed>] [selection]

Assign randomly-generated names to all selected wires and cells. The seed option
can be used to change the random number generator seed from the default, but it
must be non-zero.


    rmports [selection]

This pass identifies ports in the selected modules which are not used or
driven and removes them.


    sat [options] [selection]

This command solves a SAT problem defined over the currently selected circuit
and additional constraints passed as parameters.

    -all
        show all solutions to the problem (this can grow exponentially, use
        -max <N> instead to get <N> solutions)

    -max <N>
        like -all, but limit number of solutions to <N>

    -enable_undef
        enable modeling of undef value (aka 'x-bits')
        this option is implied by -set-def, -set-undef et. cetera

    -max_undef
        maximize the number of undef bits in solutions, giving a better
        picture of which input bits are actually vital to the solution.

    -set <signal> <value>
        set the specified signal to the specified value.

    -set-def <signal>
        add a constraint that all bits of the given signal must be defined

    -set-any-undef <signal>
        add a constraint that at least one bit of the given signal is undefined

    -set-all-undef <signal>
        add a constraint that all bits of the given signal are undefined

    -set-def-inputs
        add -set-def constraints for all module inputs

    -set-def-formal
        add -set-def constraints for formal $anyinit, $anyconst, $anyseq cells

    -show <signal>
        show the model for the specified signal. if no -show option is
        passed then a set of signals to be shown is automatically selected.

    -show-inputs, -show-outputs, -show-ports
        add all module (input/output) ports to the list of shown signals

    -show-regs, -show-public, -show-all
        show all registers, show signals with 'public' names, show all signals

    -ignore_div_by_zero
        ignore all solutions that involve a division by zero

    -ignore_unknown_cells
        ignore all cells that can not be matched to a SAT model

The following options can be used to set up a sequential problem:

    -seq <N>
        set up a sequential problem with <N> time steps. The steps will
        be numbered from 1 to N.

        note: for large <N> it can be significantly faster to use
        -tempinduct-baseonly -maxsteps <N> instead of -seq <N>.

    -set-at <N> <signal> <value>
    -unset-at <N> <signal>
        set or unset the specified signal to the specified value in the
        given timestep. this has priority over a -set for the same signal.

    -set-assumes
        set all assumptions provided via $assume cells

    -set-def-at <N> <signal>
    -set-any-undef-at <N> <signal>
    -set-all-undef-at <N> <signal>
        add undef constraints in the given timestep.

    -set-init <signal> <value>
        set the initial value for the register driving the signal to the value

    -set-init-undef
        set all initial states (not set using -set-init) to undef

    -set-init-def
        do not force a value for the initial state but do not allow undef

    -set-init-zero
        set all initial states (not set using -set-init) to zero

    -dump_vcd <vcd-file-name>
        dump SAT model (counter example in proof) to VCD file

    -dump_json <json-file-name>
        dump SAT model (counter example in proof) to a WaveJSON file.

    -dump_cnf <cnf-file-name>
        dump CNF of SAT problem (in DIMACS format). in temporal induction
        proofs this is the CNF of the first induction step.

The following additional options can be used to set up a proof. If also -seq
is passed, a temporal induction proof is performed.

    -tempinduct
        Perform a temporal induction proof. In a temporal induction proof it is
        proven that the condition holds forever after the number of time steps
        specified using -seq.

    -tempinduct-def
        Perform a temporal induction proof. Assume an initial state with all
        registers set to defined values for the induction step.

    -tempinduct-baseonly
        Run only the basecase half of temporal induction (requires -maxsteps)

    -tempinduct-inductonly
        Run only the induction half of temporal induction

    -tempinduct-skip <N>
        Skip the first <N> steps of the induction proof.

        note: this will assume that the base case holds for <N> steps.
        this must be proven independently with "-tempinduct-baseonly
        -maxsteps <N>". Use -initsteps if you just want to set a
        minimal induction length.

    -prove <signal> <value>
        Attempt to proof that <signal> is always <value>.

    -prove-x <signal> <value>
        Like -prove, but an undef (x) bit in the lhs matches any value on
        the right hand side. Useful for equivalence checking.

    -prove-asserts
        Prove that all asserts in the design hold.

    -prove-skip <N>
        Do not enforce the prove-condition for the first <N> time steps.

    -maxsteps <N>
        Set a maximum length for the induction.

    -initsteps <N>
        Set initial length for the induction.
        This will speed up the search of the right induction length
        for deep induction proofs.

    -stepsize <N>
        Increase the size of the induction proof in steps of <N>.
        This will speed up the search of the right induction length
        for deep induction proofs.

    -timeout <N>
        Maximum number of seconds a single SAT instance may take.

    -verify
        Return an error and stop the synthesis script if the proof fails.

    -verify-no-timeout
        Like -verify but do not return an error for timeouts.

    -falsify
        Return an error and stop the synthesis script if the proof succeeds.

    -falsify-no-timeout
        Like -falsify but do not return an error for timeouts.


    scatter [selection]

This command adds additional intermediate nets on all cell ports. This is used
for testing the correct use of the SigMap helper in passes. If you don't know
what this means: don't worry -- you only need this pass when testing your own
extensions to Yosys.

Use the opt_clean command to get rid of the additional nets.


    scc [options] [selection]

This command identifies strongly connected components (aka logic loops) in the
design.

    -expect <num>
        expect to find exactly <num> SCCs. A different number of SCCs will
        produce an error.

    -max_depth <num>
        limit to loops not longer than the specified number of cells. This
        can e.g. be useful in identifying small local loops in a module that
        implements one large SCC.

    -nofeedback
        do not count cells that have their output fed back into one of their
        inputs as single-cell scc.

    -all_cell_types
        Usually this command only considers internal non-memory cells. With
        this option set, all cells are considered. For unknown cells all ports
        are assumed to be bidirectional 'inout' ports.

    -set_attr <name> <value>
        set the specified attribute on all cells that are part of a logic
        loop. the special token {} in the value is replaced with a unique
        identifier for the logic loop.

    -select
        replace the current selection with a selection of all cells and wires
        that are part of a found logic loop

    -specify
        examine specify rules to detect logic loops in whitebox/blackbox cells


    scratchpad [options]

This pass allows to read and modify values from the scratchpad of the current
design. Options:

    -get <identifier>
        print the value saved in the scratchpad under the given identifier.

    -set <identifier> <value>
        save the given value in the scratchpad under the given identifier.

    -unset <identifier>
        remove the entry for the given identifier from the scratchpad.

    -copy <identifier_from> <identifier_to>
        copy the value of the first identifier to the second identifier.

    -assert <identifier> <value>
        assert that the entry for the given identifier is set to the given
        value.

    -assert-set <identifier>
        assert that the entry for the given identifier exists.

    -assert-unset <identifier>
        assert that the entry for the given identifier does not exist.

The identifier may not contain whitespace. By convention, it is usually prefixed
by the name of the pass that uses it, e.g. 'opt.did_something'. If the value
contains whitespace, it must be enclosed in double quotes.


    script <filename> [<from_label>:<to_label>]
    script -scriptwire [selection]

This command executes the yosys commands in the specified file (default
behaviour), or commands embedded in the constant text value connected to the
selected wires.

In the default (file) case, the 2nd argument can be used to only execute the
section of the file between the specified labels. An empty from label is
synonymous with the beginning of the file and an empty to label is synonymous
with the end of the file.

If only one label is specified (without ':') then only the block
marked with that label (until the next label) is executed.

In "-scriptwire" mode, the commands on the selected wire(s) will be executed
in the scope of (and thus, relative to) the wires' owning module(s). This
'-module' mode can be exited by using the 'cd' command.


    select [ -add | -del | -set <name> ] {-read <filename> | <selection>}
    select [ -unset <name> ]
    select [ <assert_option> ] {-read <filename> | <selection>}
    select [ -list | -list-mod | -write <filename> | -count | -clear ]
    select -module <modname>

Most commands use the list of currently selected objects to determine which part
of the design to operate on. This command can be used to modify and view this
list of selected objects.

Note that many commands support an optional [selection] argument that can be
used to override the global selection for the command. The syntax of this
optional argument is identical to the syntax of the <selection> argument
described here.

    -add, -del
        add or remove the given objects to the current selection.
        without this options the current selection is replaced.

    -set <name>
        do not modify the current selection. instead save the new selection
        under the given name (see @<name> below). to save the current selection,
        use "select -set <name> %"

    -unset <name>
        do not modify the current selection. instead remove a previously saved
        selection under the given name (see @<name> below).

    -assert-none
        do not modify the current selection. instead assert that the given
        selection is empty. i.e. produce an error if any object or module
        matching the selection is found.

    -assert-any
        do not modify the current selection. instead assert that the given
        selection is non-empty. i.e. produce an error if no object or module
        matching the selection is found.

    -assert-mod-count N
        do not modify the current selection. instead assert that the given
        selection contains exactly N modules (partially or fully selected).

    -assert-count N
        do not modify the current selection. instead assert that the given
        selection contains exactly N objects.

    -assert-max N
        do not modify the current selection. instead assert that the given
        selection contains less than or exactly N objects.

    -assert-min N
        do not modify the current selection. instead assert that the given
        selection contains at least N objects.

    -list
        list all objects in the current selection

    -write <filename>
        like -list but write the output to the specified file

    -read <filename>
        read the specified file (written by -write)

    -count
        count all objects in the current selection

    -clear
        clear the current selection. this effectively selects the whole
        design. it also resets the selected module (see -module). use the
        command 'select *' to select everything but stay in the current module.

    -none
        create an empty selection. the current module is unchanged.

    -module <modname>
        limit the current scope to the specified module.
        the difference between this and simply selecting the module
        is that all object names are interpreted relative to this
        module after this command until the selection is cleared again.

When this command is called without an argument, the current selection
is displayed in a compact form (i.e. only the module name when a whole module
is selected).

The <selection> argument itself is a series of commands for a simple stack
machine. Each element on the stack represents a set of selected objects.
After this commands have been executed, the union of all remaining sets
on the stack is computed and used as selection for the command.

Pushing (selecting) object when not in -module mode:

    <mod_pattern>
        select the specified module(s)

    <mod_pattern>/<obj_pattern>
        select the specified object(s) from the module(s)

Pushing (selecting) object when in -module mode:

    <obj_pattern>
        select the specified object(s) from the current module

By default, patterns will not match black/white-box modules or their
contents. To include such objects, prefix the pattern with '='.

A <mod_pattern> can be a module name, wildcard expression (*, ?, [..])
matching module names, or one of the following:

    A:<pattern>, A:<pattern>=<pattern>
        all modules with an attribute matching the given pattern
        in addition to = also <, <=, >=, and > are supported

    N:<pattern>
        all modules with a name matching the given pattern
        (i.e. 'N:' is optional as it is the default matching rule)

An <obj_pattern> can be an object name, wildcard expression, or one of
the following:

    w:<pattern>
        all wires with a name matching the given wildcard pattern

    i:<pattern>, o:<pattern>, x:<pattern>
        all inputs (i:), outputs (o:) or any ports (x:) with matching names

    s:<size>, s:<min>:<max>
        all wires with a matching width

    m:<pattern>
        all memories with a name matching the given pattern

    c:<pattern>
        all cells with a name matching the given pattern

    t:<pattern>
        all cells with a type matching the given pattern

    t:@<name>
        all cells with a type matching a module in the saved selection <name>

    p:<pattern>
        all processes with a name matching the given pattern

    a:<pattern>
        all objects with an attribute name matching the given pattern

    a:<pattern>=<pattern>
        all objects with a matching attribute name-value-pair.
        in addition to = also <, <=, >=, and > are supported

    r:<pattern>, r:<pattern>=<pattern>
        cells with matching parameters. also with <, <=, >= and >.

    n:<pattern>
        all objects with a name matching the given pattern
        (i.e. 'n:' is optional as it is the default matching rule)

    @<name>
        push the selection saved prior with 'select -set <name> ...'

The following actions can be performed on the top sets on the stack:

    %
        push a copy of the current selection to the stack

    %%
        replace the stack with a union of all elements on it

    %n
        replace top set with its invert

    %u
        replace the two top sets on the stack with their union

    %i
        replace the two top sets on the stack with their intersection

    %d
        pop the top set from the stack and subtract it from the new top

    %D
        like %d but swap the roles of two top sets on the stack

    %c
        create a copy of the top set from the stack and push it

    %x[<num1>|*][.<num2>][:<rule>[:<rule>..]]
        expand top set <num1> num times according to the specified rules.
        (i.e. select all cells connected to selected wires and select all
        wires connected to selected cells) The rules specify which cell
        ports to use for this. the syntax for a rule is a '-' for exclusion
        and a '+' for inclusion, followed by an optional comma separated
        list of cell types followed by an optional comma separated list of
        cell ports in square brackets. a rule can also be just a cell or wire
        name that limits the expansion (is included but does not go beyond).
        select at most <num2> objects. a warning message is printed when this
        limit is reached. When '*' is used instead of <num1> then the process
        is repeated until no further object are selected.

    %ci[<num1>|*][.<num2>][:<rule>[:<rule>..]]
    %co[<num1>|*][.<num2>][:<rule>[:<rule>..]]
        similar to %x, but only select input (%ci) or output cones (%co)

    %xe[...] %cie[...] %coe
        like %x, %ci, and %co but only consider combinatorial cells

    %a
        expand top set by selecting all wires that are (at least in part)
        aliases for selected wires.

    %s
        expand top set by adding all modules that implement cells in selected
        modules

    %m
        expand top set by selecting all modules that contain selected objects

    %M
        select modules that implement selected cells

    %C
        select cells that implement selected modules

    %R[<num>]
        select <num> random objects from top selection (default 1)

Example: the following command selects all wires that are connected to a
'GATE' input of a 'SWITCH' cell:

    select */t:SWITCH %x:+[GATE] */t:SWITCH %d


    setattr [ -mod ] [ -set name value | -unset name ]... [selection]

Set/unset the given attributes on the selected objects. String values must be
passed in double quotes (").

When called with -mod, this command will set and unset attributes on modules
instead of objects within modules.


    setparam [ -type cell_type ] [ -set name value | -unset name ]... [selection]

Set/unset the given parameters on the selected cells. String values must be
passed in double quotes (").

The -type option can be used to change the cell type of the selected cells.


    setundef [options] [selection]

This command replaces undef (x) constants with defined (0/1) constants.

    -undriven
        also set undriven nets to constant values

    -expose
        also expose undriven nets as inputs (use with -undriven)

    -zero
        replace with bits cleared (0)

    -one
        replace with bits set (1)

    -undef
        replace with undef (x) bits, may be used with -undriven

    -anyseq
        replace with $anyseq drivers (for formal)

    -anyconst
        replace with $anyconst drivers (for formal)

    -random <seed>
        replace with random bits using the specified integer as seed
        value for the random number generator.

    -init
        also create/update init values for flip-flops

    -params
        replace undef in cell parameters


    share [options] [selection]

This pass merges shareable resources into a single resource. A SAT solver
is used to determine if two resources are share-able.

  -force
    Per default the selection of cells that is considered for sharing is
    narrowed using a list of cell types. With this option all selected
    cells are considered for resource sharing.

    IMPORTANT NOTE: If the -all option is used then no cells with internal
    state must be selected!

  -aggressive
    Per default some heuristics are used to reduce the number of cells
    considered for resource sharing to only large resources. This options
    turns this heuristics off, resulting in much more cells being considered
    for resource sharing.

  -fast
    Only consider the simple part of the control logic in SAT solving, resulting
    in much easier SAT problems at the cost of maybe missing some opportunities
    for resource sharing.

  -limit N
    Only perform the first N merges, then stop. This is useful for debugging.


    shell

This command enters the interactive command mode. This can be useful
in a script to interrupt the script at a certain point and allow for
interactive inspection or manual synthesis of the design at this point.

The command prompt of the interactive shell indicates the current
selection (see 'help select'):

    yosys>
        the entire design is selected

    yosys*>
        only part of the design is selected

    yosys [modname]>
        the entire module 'modname' is selected using 'select -module modname'

    yosys [modname]*>
        only part of current module 'modname' is selected

When in interactive shell, some errors (e.g. invalid command arguments)
do not terminate yosys but return to the command prompt.

This command is the default action if nothing else has been specified
on the command line.

Press Ctrl-D or type 'exit' to leave the interactive shell.


    show [options] [selection]

Create a graphviz DOT file for the selected part of the design and compile it
to a graphics file (usually SVG or PostScript).

    -viewer <viewer>
        Run the specified command with the graphics file as parameter.
        On Windows, this pauses yosys until the viewer exits.
        Use "-viewer none" to not run any command.

    -format <format>
        Generate a graphics file in the specified format. Use 'dot' to just
        generate a .dot file, or other <format> strings such as 'svg' or 'ps'
        to generate files in other formats (this calls the 'dot' command).

    -lib <verilog_or_rtlil_file>
        Use the specified library file for determining whether cell ports are
        inputs or outputs. This option can be used multiple times to specify
        more than one library.

        note: in most cases it is better to load the library before calling
        show with 'read_verilog -lib <filename>'. it is also possible to
        load liberty files with 'read_liberty -lib <filename>'.

    -prefix <prefix>
        generate <prefix>.* instead of ~/.yosys_show.*

    -color <color> <object>
        assign the specified color to the specified object. The object can be
        a single selection wildcard expressions or a saved set of objects in
        the @<name> syntax (see "help select" for details).

    -label <text> <object>
        assign the specified label text to the specified object. The object can
        be a single selection wildcard expressions or a saved set of objects in
        the @<name> syntax (see "help select" for details).

    -colors <seed>
        Randomly assign colors to the wires. The integer argument is the seed
        for the random number generator. Change the seed value if the colored
        graph still is ambiguous. A seed of zero deactivates the coloring.

    -colorattr <attribute_name>
        Use the specified attribute to assign colors. A unique color is
        assigned to each unique value of this attribute.

    -width
        annotate buses with a label indicating the width of the bus.

    -signed
        mark ports (A, B) that are declared as signed (using the [AB]_SIGNED
        cell parameter) with an asterisk next to the port name.

    -stretch
        stretch the graph so all inputs are on the left side and all outputs
        (including inout ports) are on the right side.

    -pause
        wait for the user to press enter to before returning

    -enum
        enumerate objects with internal ($-prefixed) names

    -long
        do not abbreviate objects with internal ($-prefixed) names

    -notitle
        do not add the module name as graph title to the dot file

    -nobg
        don't run viewer in the background, IE wait for the viewer tool to
        exit before returning

    -href
        adds href attribute to all items representing cells and wires, using
        src attribute of origin

When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
specified, 'xdot' is used to display the schematic (POSIX systems only).

The generated output files are '~/.yosys_show.dot' and '~/.yosys_show.<format>',
unless another prefix is specified using -prefix <prefix>.

Yosys on Windows and YosysJS use different defaults: The output is written
to 'show.dot' in the current directory and new viewer is launched each time
the 'show' command is executed.


    shregmap [options] [selection]

This pass converts chains of $_DFF_[NP]_ gates to target specific shift register
primitives. The generated shift register will be of type $__SHREG_DFF_[NP]_ and
will use the same interface as the original $_DFF_*_ cells. The cell parameter
'DEPTH' will contain the depth of the shift register. Use a target-specific
'techmap' map file to convert those cells to the actual target cells.

    -minlen N
        minimum length of shift register (default = 2)
        (this is the length after -keep_before and -keep_after)

    -maxlen N
        maximum length of shift register (default = no limit)
        larger chains will be mapped to multiple shift register instances

    -keep_before N
        number of DFFs to keep before the shift register (default = 0)

    -keep_after N
        number of DFFs to keep after the shift register (default = 0)

    -clkpol pos|neg|any
        limit match to only positive or negative edge clocks. (default = any)

    -enpol pos|neg|none|any_or_none|any
        limit match to FFs with the specified enable polarity. (default = none)

    -match <cell_type>[:<d_port_name>:<q_port_name>]
        match the specified cells instead of $_DFF_N_ and $_DFF_P_. If
        ':<d_port_name>:<q_port_name>' is omitted then 'D' and 'Q' is used
        by default. E.g. the option '-clkpol pos' is just an alias for
        '-match $_DFF_P_', which is an alias for '-match $_DFF_P_:D:Q'.

    -params
        instead of encoding the clock and enable polarity in the cell name by
        deriving from the original cell name, simply name all generated cells
        $__SHREG_ and use CLKPOL and ENPOL parameters. An ENPOL value of 2 is
        used to denote cells without enable input. The ENPOL parameter is
        omitted when '-enpol none' (or no -enpol option) is passed.

    -zinit
        assume the shift register is automatically zero-initialized, so it
        becomes legal to merge zero initialized FFs into the shift register.

    -init
        map initialized registers to the shift reg, add an INIT parameter to
        generated cells with the initialization value. (first bit to shift out
        in LSB position)

    -tech greenpak4
        map to greenpak4 shift registers.


    sim [options] [top-level]

This command simulates the circuit using the given top-level module.

    -vcd <filename>
        write the simulation results to the given VCD file

    -fst <filename>
        write the simulation results to the given FST file

    -aiw <filename>
        write the simulation results to an AIGER witness file
        (requires a *.aim file via -map)

    -hdlname
        use the hdlname attribute when writing simulation results
        (preserves hierarchy in a flattened design)

    -x
        ignore constant x outputs in simulation file.

    -date
        include date and full version info in output.

    -clock <portname>
        name of top-level clock input

    -clockn <portname>
        name of top-level clock input (inverse polarity)

    -multiclock
        mark that witness file is multiclock.

    -reset <portname>
        name of top-level reset input (active high)

    -resetn <portname>
        name of top-level inverted reset input (active low)

    -rstlen <integer>
        number of cycles reset should stay active (default: 1)

    -zinit
        zero-initialize all uninitialized regs and memories

    -timescale <string>
        include the specified timescale declaration in the vcd

    -n <integer>
        number of clock cycles to simulate (default: 20)

    -noinitstate
        do not activate $initstate cells during the first cycle

    -a
        use all nets in VCD/FST operations, not just those with public names

    -w
        writeback mode: use final simulation state as new init state

    -r <filename>
        read simulation or formal results file
            File formats supported: FST, VCD, AIW, WIT and .yw
            VCD support requires vcd2fst external tool to be present

    -append <integer>
        number of extra clock cycles to simulate for a Yosys witness input

    -summary <filename>
        write a JSON summary to the given file

    -map <filename>
        read file with port and latch symbols, needed for AIGER witness input

    -scope <name>
        scope of simulation top model

    -at <time>
        sets start and stop time

    -start <time>
        start co-simulation in arbitary time (default 0)

    -stop <time>
        stop co-simulation in arbitary time (default END)

    -sim
        simulation with stimulus from FST (default)

    -sim-cmp
        co-simulation expect exact match

    -sim-gold
        co-simulation, x in simulation can match any value in FST

    -sim-gate
        co-simulation, x in FST can match any value in simulation

    -assert
        fail the simulation command if, in the course of simulating,
        any of the asserts in the design fail

    -fst-noinit
        do not initialize latches and memories from an input FST or VCD file
        (use the initial defined by the design instead)

    -q
        disable per-cycle/sample log message

    -d
        enable debug output


    simplemap [selection]

This pass maps a small selection of simple coarse-grain cells to yosys gate
primitives. The following internal cell types are mapped by this pass:

  $not, $pos, $and, $or, $xor, $xnor
  $reduce_and, $reduce_or, $reduce_xor, $reduce_xnor, $reduce_bool
  $logic_not, $logic_and, $logic_or, $mux, $tribuf
  $sr, $ff, $dff, $dffe, $dffsr, $dffsre, $adff, $adffe, $aldff, $aldffe, $sdff,
  $sdffe, $sdffce, $dlatch, $adlatch, $dlatchsr


    splice [options] [selection]

This command adds $slice and $concat cells to the design to make the splicing
of multi-bit signals explicit. This for example is useful for coarse grain
synthesis, where dedicated hardware is needed to splice signals.

    -sel_by_cell
        only select the cell ports to rewire by the cell. if the selection
        contains a cell, than all cell inputs are rewired, if necessary.

    -sel_by_wire
        only select the cell ports to rewire by the wire. if the selection
        contains a wire, than all cell ports driven by this wire are wired,
        if necessary.

    -sel_any_bit
        it is sufficient if the driver of any bit of a cell port is selected.
        by default all bits must be selected.

    -wires
        also add $slice and $concat cells to drive otherwise unused wires.

    -no_outputs
        do not rewire selected module outputs.

    -port <name>
        only rewire cell ports with the specified name. can be used multiple
        times. implies -no_output.

    -no_port <name>
        do not rewire cell ports with the specified name. can be used multiple
        times. can not be combined with -port <name>.

By default selected output wires and all cell ports of selected cells driven
by selected wires are rewired.


    splitcells [options] [selection]

This command splits multi-bit cells into smaller chunks, based on usage of the
cell output bits.

This command operates only in cells such as $or, $and, and $mux, that are easily
cut into bit-slices.

    -format char1[char2[char3]]
        the first char is inserted between the cell name and the bit index, the
        second char is appended to the cell name. e.g. -format () creates cell
        names like 'mycell(42)'. the 3rd character is the range separation
        character when creating multi-bit cells. the default is '[]:'.


    splitnets [options] [selection]

This command splits multi-bit nets into single-bit nets.

    -format char1[char2[char3]]
        the first char is inserted between the net name and the bit index, the
        second char is appended to the netname. e.g. -format () creates net
        names like 'mysignal(42)'. the 3rd character is the range separation
        character when creating multi-bit wires. the default is '[]:'.

    -ports
        also split module ports. per default only internal signals are split.

    -driver
        don't blindly split nets in individual bits. instead look at the driver
        and split nets so that no driver drives only part of a net.


    sta [options] [selection]

This command performs static timing analysis on the design. (Only considers
paths within a single module, so the design must be flattened.)


    stat [options] [selection]

Print some statistics (number of objects) on the selected portion of the
design.

    -top <module>
        print design hierarchy with this module as top. if the design is fully
        selected and a module has the 'top' attribute set, this module is used
        default value for this option.

    -liberty <liberty_file>
        use cell area information from the provided liberty file

    -tech <technology>
        print area estimate for the specified technology. Currently supported
        values for <technology>: xilinx, cmos

    -width
        annotate internal cell types with their word width.
        e.g. $add_8 for an 8 bit wide $add cell.

    -json
        output the statistics in a machine-readable JSON format.
        this is output to the console; use "tee" to output to a file.


    submod [options] [selection]

This pass identifies all cells with the 'submod' attribute and moves them to
a newly created module. The value of the attribute is used as name for the
cell that replaces the group of cells with the same attribute value.

This pass can be used to create a design hierarchy in flat design. This can
be useful for analyzing or reverse-engineering a design.

This pass only operates on completely selected modules with no processes
or memories.

    -copy
        by default the cells are 'moved' from the source module and the source
        module will use an instance of the new module after this command is
        finished. call with -copy to not modify the source module.

    -name <name>
        don't use the 'submod' attribute but instead use the selection. only
        objects from one module might be selected. the value of the -name option
        is used as the value of the 'submod' attribute instead.

    -hidden
        instead of creating submodule ports with public names, create ports with
        private names so that a subsequent 'flatten; clean' call will restore
        the original module with original public names.


    supercover [options] [selection]

This command adds two cover cells for each bit of each selected wire, one
checking for a hi signal level and one checking for lo level.


    synth [options]

This command runs the default synthesis script. This command does not operate
on partly selected designs.

    -top <module>
        use the specified module as top module (default='top')

    -auto-top
        automatically determine the top of the design hierarchy

    -flatten
        flatten the design before synthesis. this will pass '-auto-top' to
        'hierarchy' if no top module is specified.

    -encfile <file>
        passed to 'fsm_recode' via 'fsm'

    -lut <k>
        perform synthesis for a k-LUT architecture.

    -nofsm
        do not run FSM optimization

    -noabc
        do not run abc (as if yosys was compiled without ABC support)

    -booth
        run the booth pass to map $mul to Booth encoded multipliers

    -noalumacc
        do not run 'alumacc' pass. i.e. keep arithmetic operators in
        their direct form ($add, $sub, etc.).

    -nordff
        passed to 'memory'. prohibits merging of FFs into memory read ports

    -noshare
        do not run SAT-based resource sharing

    -run <from_label>[:<to_label>]
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

    -flowmap
        use FlowMap LUT techmapping instead of ABC

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).

    -extra-map filename
        source extra rules from the given file to complement the default
        mapping library in the `techmap` step. this option can be
        repeated.

The following commands are executed by this synthesis command:

    begin:
        hierarchy -check [-top <top> | -auto-top]

    coarse:
        proc
        flatten      (if -flatten)
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm          (unless -nofsm)
        opt
        wreduce
        peepopt
        opt_clean
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
        booth        (if -booth)
        alumacc      (unless -noalumacc)
        share        (unless -noshare)
        opt
        memory -nomap
        opt_clean

    fine:
        opt -fast -full
        memory_map
        opt -full
        techmap                      (unless -extra-map)
        techmap -map +/techmap.v -map <inject>      (if -extra-map)
        techmap -map +/gate2lut.v    (if -noabc and -lut)
        clean; opt_lut               (if -noabc and -lut)
        flowmap -maxlut K            (if -flowmap and -lut)
        opt -fast
        abc -fast           (unless -noabc, unless -lut)
        abc -fast -lut k    (unless -noabc, if -lut)
        opt -fast           (unless -noabc)

    check:
        hierarchy -check
        stat
        check


    synth_achronix [options]

This command runs synthesis for Achronix Speedster eFPGAs. This work is still experimental.

    -top <module>
        use the specified module as top module (default='top')

    -vout <file>
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options


The following commands are executed by this synthesis command:

    begin:
        read_verilog -sv -lib +/achronix/speedster22i/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    fine:
        opt -fast -mux_undef -undriven -fine -full
        memory_map
        opt -undriven -fine
        opt -fine
        techmap -map +/techmap.v
        opt -full
        clean -purge
        setundef -undriven -zero
        dfflegalize -cell $_DFF_P_ x
        abc -markgroups -dff -D 1    (only if -retime)

    map_luts:
        abc -lut 4
        clean

    map_cells:
        iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I
        techmap -map +/achronix/speedster22i/cells_map.v
        clean -purge

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    vout:
        write_verilog -nodec -attr2comment -defparam -renameprefix syn_ <file-name>


    synth_anlogic [options]

This command runs synthesis for Anlogic FPGAs.

    -top <module>
        use the specified module as top module

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options

    -nolutram
        do not use EG_LOGIC_DRAM16X4 cells in output netlist

    -nobram
        do not use EG_PHY_BRAM or EG_PHY_BRAM32K cells in output netlist


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/anlogic/cells_sim.v +/anlogic/eagle_bb.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    map_ram:
        memory_libmap -lib +/anlogic/lutrams.txt -lib +/anlogic/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -nolutram)
        techmap -map +/anlogic/lutrams_map.v -map +/anlogic/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v -map +/anlogic/arith_map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        dfflegalize -cell $_DFFE_P??P_ r -cell $_SDFFE_P??P_ r -cell $_DLATCH_N??_ r
        techmap -D NO_LUT -map +/anlogic/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        abc -lut 4:6
        clean

    map_cells:
        techmap -map +/anlogic/cells_map.v
        clean

    map_anlogic:
        anlogic_fixcarry
        anlogic_eqn

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif <file-name>

    json:
        write_json <file-name>


    synth_coolrunner2 [options]

This command runs synthesis for Coolrunner-II CPLDs. This work is experimental.
It is intended to be used with https://github.com/azonenberg/openfpga as the
place-and-route.

    -top <module>
        use the specified module as top module (default='top')

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/coolrunner2/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic

    coarse:
        synth -run coarse

    fine:
        extract_counter -dir up -allow_arst no
        techmap -map +/coolrunner2/cells_counter_map.v
        clean
        opt -fast -full
        techmap -map +/techmap.v -map +/coolrunner2/cells_latch.v
        opt -fast
        dfflibmap -prepare -liberty +/coolrunner2/xc2_dff.lib

    map_tff:
        abc -g AND,XOR
        clean
        extract -map +/coolrunner2/tff_extract.v

    map_pla:
        abc -sop -I 40 -P 56
        clean

    map_cells:
        dfflibmap -liberty +/coolrunner2/xc2_dff.lib
        dffinit -ff FDCP Q INIT
        dffinit -ff FDCP_N Q INIT
        dffinit -ff FTCP Q INIT
        dffinit -ff FTCP_N Q INIT
        dffinit -ff LDCP Q INIT
        dffinit -ff LDCP_N Q INIT
        coolrunner2_sop
        clean
        iopadmap -bits -inpad IBUF O:I -outpad IOBUFE I:IO -inoutpad IOBUFE O:IO -toutpad IOBUFE E:I:IO -tinoutpad IOBUFE E:O:I:IO
        attrmvcp -attr src -attr LOC t:IOBUFE n:*
        attrmvcp -attr src -attr LOC -driven t:IBUF n:*
        coolrunner2_fixup
        splitnets
        clean

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    json:
        write_json <file-name>


    synth_easic [options]

This command runs synthesis for eASIC platform.

    -top <module>
        use the specified module as top module

    -vlog <file>
        write the design to the specified structural Verilog file. writing of
        an output file is omitted if this parameter is not specified.

    -etools <path>
        set path to the eTools installation. (default=/opt/eTools)

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options


The following commands are executed by this synthesis command:

    begin:
        read_liberty -lib <etools_phys_clk_lib>
        read_liberty -lib <etools_logic_lut_lib>
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten

    coarse:
        synth -run coarse

    fine:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap
        opt -fast
        abc -dff -D 1     (only if -retime)
        opt_clean    (only if -retime)

    map:
        dfflibmap -liberty <etools_phys_clk_lib>
        abc -liberty <etools_logic_lut_lib>
        opt_clean

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    vlog:
        write_verilog -noexpr -attr2comment <file-name>


    synth_ecp5 [options]

This command runs synthesis for ECP5 FPGAs.

    -top <module>
        use the specified module as top module

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -dff
        run 'abc'/'abc9' with -dff option

    -retime
        run 'abc' with '-dff -D 1' options

    -noccu2
        do not use CCU2 cells in output netlist

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use block RAM cells in output netlist

    -nolutram
        do not use LUT RAM cells in output netlist

    -nowidelut
        do not use PFU muxes to implement LUTs larger than LUT4s

    -asyncprld
        use async PRLD mode to implement ALDFF (EXPERIMENTAL)

    -abc2
        run two passes of 'abc' for slightly improved logic density

    -noabc9
        disable use of new ABC9 flow

    -vpr
        generate an output netlist (and BLIF file) suitable for VPR
        (this feature is experimental and incomplete)

    -iopad
        insert IO buffers

    -nodsp
        do not map multipliers to MULT18X18D

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/ecp5/cells_sim.v +/ecp5/cells_bb.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        techmap -map +/mul2dsp.v -map +/ecp5/dsp_map.v -D DSP_A_MAXWIDTH=18 -D DSP_B_MAXWIDTH=18  -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2  -D DSP_NAME=$__MUL18X18    (unless -nodsp)
        chtype -set $mul t:$__soft_mul    (unless -nodsp)
        alumacc
        opt
        memory -nomap [-no-rw-check]
        opt_clean

    map_ram:
        memory_libmap -lib +/ecp5/lutrams.txt -lib +/ecp5/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -nolutram)
        techmap -map +/ecp5/lutrams_map.v -map +/ecp5/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v -map +/ecp5/arith_map.v
        iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top    (only if '-iopad')
        attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]
        attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        opt_clean
        dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r] [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]    ($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)
        zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*    (only if -abc9 and -dff)
        techmap -D NO_LUT -map +/ecp5/cells_map.v
        opt_expr -undriven -mux_undef
        simplemap
        lattice_gsr
        attrmvcp -copy -attr syn_useioff
        opt_clean

    map_luts:
        abc          (only if -abc2)
        techmap -map +/ecp5/latches_map.v    (skip if -asyncprld)
        abc9 -W 300
        clean

    map_cells:
        techmap -map +/ecp5/cells_map.v    (skip if -vpr)
        opt_lut_ins -tech lattice
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    blif:
        opt_clean -purge                                     (vpr mode)
        write_blif -attr -cname -conn -param <file-name>     (vpr mode)
        write_blif -gates -attr -param <file-name>           (non-vpr mode)

    edif:
        write_edif <file-name>

    json:
        write_json <file-name>


    synth_efinix [options]

This command runs synthesis for Efinix FPGAs.

    -top <module>
        use the specified module as top module

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options

    -nobram
        do not use EFX_RAM_5K cells in output netlist


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/efinix/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    map_ram:
        memory_libmap -lib +/efinix/brams.txt [-no-auto-block]    (-no-auto-block if -nobram)
        techmap -map +/efinix/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v -map +/efinix/arith_map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        dfflegalize -cell $_DFFE_????_ 0 -cell $_SDFFE_????_ 0 -cell $_SDFFCE_????_ 0 -cell $_DLATCH_?_ x
        techmap -D NO_LUT -map +/efinix/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        abc -lut 4
        clean

    map_cells:
        techmap -map +/efinix/cells_map.v
        clean

    map_gbuf:
        clkbufmap -buf $__EFX_GBUF O:I
        techmap -map +/efinix/gbuf_map.v
        efinix_fixcarry
        clean

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif <file-name>

    json:
        write_json <file-name>


    synth_fabulous [options]

This command runs synthesis for FPGA fabrics generated with FABulous. This command does not operate
on partly selected designs.

    -top <module>
        use the specified module as top module (default='top')

    -auto-top
        automatically determine the top of the design hierarchy

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -lut <k>
        perform synthesis for a k-LUT architecture (default 4).

    -vpr
        perform synthesis for the FABulous VPR flow (using slightly different techmapping).

    -plib <primitive_library.v>
        use the specified Verilog file as a primitive library.

    -extra-plib <primitive_library.v>
        use the specified Verilog file for extra primitives (can be specified multiple
        times).

    -extra-map <techamp.v>
        use the specified Verilog file for extra techmap rules (can be specified multiple
        times).

    -encfile <file>
        passed to 'fsm_recode' via 'fsm'

    -nofsm
        do not run FSM optimization

    -noalumacc
        do not run 'alumacc' pass. i.e. keep arithmetic operators in
        their direct form ($add, $sub, etc.).

    -carry <none|ha>
        carry mapping style (none, half-adders, ...) default=none

    -noregfile
        do not map register files

    -iopad
        enable automatic insertion of IO buffers (otherwise a wrapper
        with manually inserted and constrained IO should be used.)

    -complex-dff
        enable support for FFs with enable and synchronous SR (must also be
        supported by the target fabric.)

    -noflatten
        do not flatten design after elaboration

    -nordff
        passed to 'memory'. prohibits merging of FFs into memory read ports

    -noshare
        do not run SAT-based resource sharing

    -run <from_label>[:<to_label>]
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


The following commands are executed by this synthesis command:
        read_verilog  -lib +/fabulous/prims.v
        read_verilog -lib <extra_plib.v>    (for each -extra-plib)

    begin:
        hierarchy -check
        proc

    flatten:    (unless -noflatten)
        flatten
        tribuf -logic
        deminout

    coarse:
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm          (unless -nofsm)
        opt
        wreduce
        peepopt
        opt_clean
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v     (if -lut)
        alumacc      (unless -noalumacc)
        share        (unless -noshare)
        opt
        memory -nomap
        opt_clean

    map_ram:    (unless -noregfile)
        memory_libmap -lib +/fabulous/ram_regfile.txt
        techmap -map +/fabulous/regfile_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        opt -full
        techmap -map +/techmap.v -map +/fabulous/arith_map.v -D ARITH_<carry>
        opt -fast

    map_iopad:    (if -iopad)
        opt -full
        iopadmap -bits -outpad $__FABULOUS_OBUF I:PAD -inpad $__FABULOUS_IBUF O:PAD -toutpad IO_1_bidirectional_frame_config_pass ~T:I:PAD -tinoutpad IO_1_bidirectional_frame_config_pass ~T:O:I:PAD A:top    (skip if '-noiopad')
        techmap -map +/fabulous/io_map.v

    map_ffs:
        dfflegalize -cell $_DFF_P_ 0 -cell $_DLATCH_?_ x    without -complex-dff
        techmap -map +/fabulous/latches_map.v
        techmap -map +/fabulous/ff_map.v
        techmap -map <extra_map.v>...    (for each -extra-map)
        clean

    map_luts:
        abc -lut 4 -dress
        clean

    map_cells:
        techmap -D LUT_K=4 -map +/fabulous/cells_map.v
        clean

    check:
        hierarchy -check
        stat

    blif:
        opt_clean -purge
        write_blif -attr -cname -conn -param <file-name>

    json:
        write_json <file-name>


    synth_gatemate [options]

This command runs synthesis for Cologne Chip AG GateMate FPGAs.

    -top <module>
        use the specified module as top module.

    -vlog <file>
        write the design to the specified verilog file. Writing of an output
        file is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. Writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). An empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis.

    -nobram
        do not use CC_BRAM_20K or CC_BRAM_40K cells in output netlist.

    -noaddf
        do not use CC_ADDF full adder cells in output netlist.

    -nomult
        do not use CC_MULT multiplier cells in output netlist.

    -nomx8, -nomx4
        do not use CC_MX{8,4} multiplexer cells in output netlist.

    -luttree
        use new LUT tree mapping approach (EXPERIMENTAL).

    -dff
        run 'abc' with -dff option

    -retime
        run 'abc' with '-dff -D 1' options

    -noiopad
        disable I/O buffer insertion (useful for hierarchical or 
        out-of-context flows).

    -noclkbuf
        disable automatic clock buffer insertion.

The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/gatemate/cells_sim.v +/gatemate/cells_bb.v
        hierarchy -check -top <top>

    prepare:
        proc
        flatten
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        muxpack
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean

    map_mult:    (skip if '-nomult')
        techmap -map +/gatemate/mul_map.v

    coarse:
        alumacc
        opt
        memory -nomap
        opt_clean

    map_bram:    (skip if '-nobram')
        memory_libmap -lib +/gatemate/brams.txt
        techmap -map +/gatemate/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v  -map +/gatemate/arith_map.v
        opt -fast

    map_io:    (skip if '-noiopad')
        iopadmap -bits -inpad CC_IBUF Y:I -outpad CC_OBUF A:O -toutpad CC_TOBUF ~T:A:O -tinoutpad CC_IOBUF ~T:Y:A:IO
        clean

    map_regs:
        opt_clean
        dfflegalize -cell $_DFFE_????_ 01 -cell $_DLATCH_???_ 01
        techmap -map +/gatemate/reg_map.v
        opt_expr -mux_undef
        simplemap
        opt_clean

    map_muxs:
        muxcover  -mux4 -mux8
        opt -full
        techmap -map +/gatemate/mux_map.v

    map_luts:
        abc  -genlib +/gatemate/lut_tree_cells.genlib    (with -luttree)
        techmap -map +/gatemate/lut_tree_map.v    (with -luttree)
        gatemate_foldinv    (with -luttree)
        techmap -map +/gatemate/inv_map.v    (with -luttree)
        abc  -dress -lut 4    (without -luttree)
        clean

    map_cells:
        techmap -map +/gatemate/lut_map.v
        clean

    map_bufg:    (skip if '-noclkbuf')
        clkbufmap -buf CC_BUFG O:I
        clean

    check:
        hierarchy -check
        stat -width
        check -noinit
        blackbox =A:whitebox

    vlog:
        opt_clean -purge
        write_verilog -noattr <file-name>

    json:
        write_json <file-name>


    synth_gowin [options]

This command runs synthesis for Gowin FPGAs. This work is experimental.

    -top <module>
        use the specified module as top module (default='top')

    -vout <file>
        write the design to the specified Verilog netlist file. writing of an
        output file is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON netlist file. writing of an
        output file is omitted if this parameter is not specified.
        This disables features not yet supported by nexpnr-gowin.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use BRAM cells in output netlist

    -nolutram
        do not use distributed RAM cells in output netlist

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options

    -nowidelut
        do not use muxes to implement LUTs larger than LUT4s

    -noiopads
        do not emit IOB at top level ports

    -noalu
        do not use ALU cells

    -noabc9
        disable use of new ABC9 flow

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


The following commands are executed by this synthesis command:

    begin:
        read_verilog -specify -lib +/gowin/cells_sim.v
        read_verilog -specify -lib +/gowin/cells_xtra.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse [-no-rw-check]

    map_ram:
        memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -nolutram)
        techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v -map +/gowin/arith_map.v
        opt -fast
        abc -dff -D 1    (only if -retime)
        iopadmap -bits -inpad IBUF O:I -outpad OBUF I:O -toutpad TBUF ~OEN:I:O -tinoutpad IOBUF ~OEN:O:I:IO    (unless -noiopads)

    map_ffs:
        opt_clean
        dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_SDFF_?P?_ r -cell $_SDFFE_?P?P_ r -cell $_DFF_?P?_ r -cell $_DFFE_?P?P_ r
        techmap -map +/gowin/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        read_verilog -icells -lib -specify +/abc9_model.v
        abc9 -maxlut 8 -W 500
        clean

    map_cells:
        techmap -map +/gowin/cells_map.v
        opt_lut_ins -tech gowin
        setundef -undriven -params -zero
        hilomap -singleton -hicell VCC V -locell GND G
        splitnets -ports    (only if -vout used)
        clean
        autoname

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    vout:
        write_verilog -simple-lhs -decimal -attr2comment -defparam -renameprefix gen <file-name>
        write_json <file-name>


    synth_greenpak4 [options]

This command runs synthesis for GreenPAK4 FPGAs. This work is experimental.
It is intended to be used with https://github.com/azonenberg/openfpga as the
place-and-route.

    -top <module>
        use the specified module as top module (default='top')

    -part <part>
        synthesize for the specified part. Valid values are SLG46140V,
        SLG46620V, and SLG46621V (default).

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/greenpak4/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic

    coarse:
        synth -run coarse

    fine:
        extract_counter -pout GP_DCMP,GP_DAC -maxwidth 14
        clean
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/greenpak4/cells_latch.v
        dfflibmap -prepare -liberty +/greenpak4/gp_dff.lib
        opt -fast -noclkinv -noff
        abc -dff -D 1    (only if -retime)

    map_luts:
        nlutmap -assert -luts 0,6,8,2     (for -part SLG46140V)
        nlutmap -assert -luts 2,8,16,2    (for -part SLG46620V)
        nlutmap -assert -luts 2,8,16,2    (for -part SLG46621V)
        clean

    map_cells:
        shregmap -tech greenpak4
        dfflibmap -liberty +/greenpak4/gp_dff.lib
        dffinit -ff GP_DFF Q INIT
        dffinit -ff GP_DFFR Q INIT
        dffinit -ff GP_DFFS Q INIT
        dffinit -ff GP_DFFSR Q INIT
        iopadmap -bits -inpad GP_IBUF OUT:IN -outpad GP_OBUF IN:OUT -inoutpad GP_OBUF OUT:IN -toutpad GP_OBUFT OE:IN:OUT -tinoutpad GP_IOBUF OE:OUT:IN:IO
        attrmvcp -attr src -attr LOC t:GP_OBUF t:GP_OBUFT t:GP_IOBUF n:*
        attrmvcp -attr src -attr LOC -driven t:GP_IBUF n:*
        techmap -map +/greenpak4/cells_map.v
        greenpak4_dffinv
        clean

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    json:
        write_json <file-name>


    synth_ice40 [options]

This command runs synthesis for iCE40 FPGAs.

    -device < hx | lp | u >
        relevant only for '-abc9' flow, optimise timing for the specified
        device. default: hx

    -top <module>
        use the specified module as top module

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -dff
        run 'abc'/'abc9' with -dff option

    -retime
        run 'abc' with '-dff -D 1' options

    -nocarry
        do not use SB_CARRY cells in output netlist

    -nodffe
        do not use SB_DFFE* cells in output netlist

    -dffe_min_ce_use <min_ce_use>
        do not use SB_DFFE* cells if the resulting CE line would go to less
        than min_ce_use SB_DFFE* in output netlist

    -nobram
        do not use SB_RAM40_4K* cells in output netlist

    -spram
        enable automatic inference of SB_SPRAM256KA

    -dsp
        use iCE40 UltraPlus DSP cells for large arithmetic

    -noabc
        use built-in Yosys LUT techmapping instead of abc

    -abc2
        run two passes of 'abc' for slightly improved logic density

    -vpr
        generate an output netlist (and BLIF file) suitable for VPR
        (this feature is experimental and incomplete)

    -noabc9
        disable use of new ABC9 flow

    -flowmap
        use FlowMap LUT techmapping instead of abc (EXPERIMENTAL)

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


The following commands are executed by this synthesis command:

    begin:
        read_verilog -D ICE40_HX -lib -specify +/ice40/cells_sim.v
        hierarchy -check -top <top>
        proc

    flatten:    (unless -noflatten)
        flatten
        tribuf -logic
        deminout

    coarse:
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        memory_dff [-no-rw-check]
        wreduce t:$mul
        techmap -map +/mul2dsp.v -map +/ice40/dsp_map.v -D DSP_A_MAXWIDTH=16 -D DSP_B_MAXWIDTH=16 -D DSP_A_MINWIDTH=2 -D DSP_B_MINWIDTH=2 -D DSP_Y_MINWIDTH=11 -D DSP_NAME=$__MUL16X16    (if -dsp)
        select a:mul2dsp                  (if -dsp)
        setattr -unset mul2dsp            (if -dsp)
        opt_expr -fine                    (if -dsp)
        wreduce                           (if -dsp)
        select -clear                     (if -dsp)
        ice40_dsp                         (if -dsp)
        chtype -set $mul t:$__soft_mul    (if -dsp)
        alumacc
        opt
        memory -nomap [-no-rw-check]
        opt_clean

    map_ram:
        memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt [-no-auto-huge] [-no-auto-block]    (-no-auto-huge unless -spram, -no-auto-block if -nobram)
        techmap -map +/ice40/brams_map.v -map +/ice40/spram_map.v
        ice40_braminit

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        ice40_wrapcarry
        techmap -map +/techmap.v -map +/ice40/arith_map.v
        opt -fast
        abc -dff -D 1    (only if -retime)
        ice40_opt

    map_ffs:
        dfflegalize -cell $_DFF_?_ 0 -cell $_DFFE_?P_ 0 -cell $_DFF_?P?_ 0 -cell $_DFFE_?P?P_ 0 -cell $_SDFF_?P?_ 0 -cell $_SDFFCE_?P?P_ 0 -cell $_DLATCH_?_ x -mince -1
        techmap -map +/ice40/ff_map.v
        opt_expr -mux_undef
        simplemap
        ice40_opt -full

    map_luts:
        abc          (only if -abc2)
        ice40_opt    (only if -abc2)
        techmap -map +/ice40/latches_map.v
        simplemap                                   (if -noabc or -flowmap)
        techmap -map +/gate2lut.v -D LUT_WIDTH=4    (only if -noabc)
        flowmap -maxlut 4    (only if -flowmap)
        read_verilog -D ICE40_HX -icells -lib -specify +/ice40/abc9_model.v
        abc9  -W 250
        ice40_wrapcarry -unwrap
        techmap -map +/ice40/ff_map.v
        clean
        opt_lut -tech ice40

    map_cells:
        techmap -map +/ice40/cells_map.v    (skip if -vpr)
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    blif:
        opt_clean -purge                                     (vpr mode)
        write_blif -attr -cname -conn -param <file-name>     (vpr mode)
        write_blif -gates -attr -param <file-name>           (non-vpr mode)

    edif:
        write_edif <file-name>

    json:
        write_json <file-name>


    synth_intel [options]

This command runs synthesis for Intel FPGAs.

    -family <max10 | cyclone10lp | cycloneiv | cycloneive>
        generate the synthesis netlist for the specified family.
        MAX10 is the default target if no family argument specified.
        For Cyclone IV GX devices, use cycloneiv argument; for Cyclone IV E, use
        cycloneive. For Cyclone V and Cyclone 10 GX, use the synth_intel_alm
        backend instead.

    -top <module>
        use the specified module as top module (default='top')

    -vqm <file>
        write the design to the specified Verilog Quartus Mapping File. Writing
        of an output file is omitted if this parameter is not specified.
        Note that this backend has not been tested and is likely incompatible
        with recent versions of Quartus.

    -vpr <file>
        write BLIF files for VPR flow experiments. The synthesized BLIF output
        file is not compatible with the Quartus flow. Writing of an
        output file is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -iopads
        use IO pad cells in output netlist

    -nobram
        do not use block RAM cells in output netlist

    -noflatten
        do not flatten design before synthesis

    -retime
        run 'abc' with '-dff -D 1' options

The following commands are executed by this synthesis command:

    begin:

    family:
        read_verilog -sv -lib +/intel/max10/cells_sim.v
        read_verilog -sv -lib +/intel/common/m9k_bb.v
        read_verilog -sv -lib +/intel/common/altpll_bb.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        synth -run coarse

    map_bram:    (skip if -nobram)
        memory_bram -rules +/intel/common/brams_m9k.txt    (if applicable for family)
        techmap -map +/intel/common/brams_map_m9k.v    (if applicable for family)

    map_ffram:
        opt -fast -mux_undef -undriven -fine -full
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v
        opt -full
        clean -purge
        setundef -undriven -zero
        abc -markgroups -dff -D 1    (only if -retime)

    map_ffs:
        dfflegalize -cell $_DFFE_PN0P_ 01
        techmap -map +/intel/common/ff_map.v

    map_luts:
        abc -lut 4
        clean

    map_cells:
        iopadmap -bits -outpad $__outpad I:O -inpad $__inpad O:I    (if -iopads)
        techmap -map +/intel/max10/cells_map.v
        clean -purge

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    vqm:
        write_verilog -attr2comment -defparam -nohex -decimal -renameprefix syn_ <file-name>

    vpr:
        opt_clean -purge
        write_blif <file-name>


WARNING: THE 'synth_intel' COMMAND IS EXPERIMENTAL.


    synth_intel_alm [options]

This command runs synthesis for ALM-based Intel FPGAs.

    -top <module>
        use the specified module as top module

    -family <family>
        target one of:
        "cyclonev"    - Cyclone V (default)

    -noflatten
        do not flatten design before synthesis; useful for per-module area
        statistics

    -dff
        pass DFFs to ABC to perform sequential logic optimisations
        (EXPERIMENTAL)

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -nolutram
        do not use LUT RAM cells in output netlist

    -nobram
        do not use block RAM cells in output netlist

    -nodsp
        do not map multipliers to MISTRAL_MUL cells

    -noiopad
        do not instantiate IO buffers

    -noclkbuf
        do not insert global clock buffers

The following commands are executed by this synthesis command:

    begin:
        read_verilog -specify -lib -D <family> +/intel_alm/common/alm_sim.v
        read_verilog -specify -lib -D <family> +/intel_alm/common/dff_sim.v
        read_verilog -specify -lib -D <family> +/intel_alm/common/dsp_sim.v
        read_verilog -specify -lib -D <family> +/intel_alm/common/mem_sim.v
        read_verilog -specify -lib -D <family> +/intel_alm/common/misc_sim.v
        read_verilog -specify -lib -D <family> -icells +/intel_alm/common/abc9_model.v
        read_verilog -lib +/intel/common/altpll_bb.v
        read_verilog -lib +/intel_alm/common/megafunction_bb.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten    (skip if -noflatten)
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=6
        opt_expr
        opt_clean
        techmap -map +/mul2dsp.v [...]    (unless -nodsp)
        alumacc
        iopadmap -bits -outpad MISTRAL_OB I:PAD -inpad MISTRAL_IB O:PAD -toutpad MISTRAL_IO OE:O:PAD -tinoutpad MISTRAL_IO OE:O:I:PAD A:top    (unless -noiopad)
        techmap -map +/intel_alm/common/arith_alm_map.v -map +/intel_alm/common/dsp_map.v
        opt
        memory -nomap
        opt_clean

    map_bram:    (skip if -nobram)
        memory_bram -rules +/intel_alm/common/bram_<bram_type>.txt
        techmap -map +/intel_alm/common/bram_<bram_type>_map.v

    map_lutram:    (skip if -nolutram)
        memory_bram -rules +/intel_alm/common/lutram_mlab.txt    (for Cyclone V)

    map_ffram:
        memory_map
        opt -full

    map_ffs:
        techmap
        dfflegalize -cell $_DFFE_PN0P_ 0 -cell $_SDFFCE_PP0P_ 0
        techmap -map +/intel_alm/common/dff_map.v
        opt -full -undriven -mux_undef
        clean -purge
        clkbufmap -buf MISTRAL_CLKBUF Q:A    (unless -noclkbuf)

    map_luts:
        techmap -map +/intel_alm/common/abc9_map.v
        abc9 [-dff] -maxlut 6 -W 600
        techmap -map +/intel_alm/common/abc9_unmap.v
        techmap -map +/intel_alm/common/alm_map.v
        opt -fast
        autoname
        clean

    check:
        hierarchy -check
        stat
        check
        blackbox =A:whitebox


    synth_lattice [options]

This command runs synthesis for Lattice FPGAs (excluding iCE40 and Nexus).

    -top <module>
        use the specified module as top module

    -family <family>
        run synthesis for the specified Lattice architecture
        generate the synthesis netlist for the specified family.
        supported values:
        - ecp5: ECP5
        - xo2: MachXO2
        - xo3: MachXO3L/LF
        - xo3d: MachXO3D

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -dff
        run 'abc'/'abc9' with -dff option

    -retime
        run 'abc' with '-dff -D 1' options

    -noccu2
        do not use CCU2 cells in output netlist

    -nodffe
        do not use flipflops with CE in output netlist

    -nobram
        do not use block RAM cells in output netlist

    -nolutram
        do not use LUT RAM cells in output netlist

    -nowidelut
        do not use PFU muxes to implement LUTs larger than LUT4s
        (by default enabled on MachXO2/XO3/XO3D)

    -widelut
        force use of PFU muxes to implement LUTs larger than LUT4s

    -asyncprld
        use async PRLD mode to implement ALDFF (EXPERIMENTAL)

    -abc2
        run two passes of 'abc' for slightly improved logic density

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

    -iopad
        insert IO buffers

    -nodsp
        do not map multipliers to MULT18X18D

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).

    -cmp2softlogic
        implement constant comparisons in soft logic, do not involve
        hard carry chains


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/lattice/cells_sim.v +/lattice/cells_bb.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        booth    (only if '-family xo3')
        alumacc
        opt
        memory -nomap [-no-rw-check]
        opt_clean

    map_ram:
        memory_libmap -lib +/lattice/lutrams.txt -lib +/lattice/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -nolutram)
        techmap -map +/lattice/lutrams_map.v -map +/lattice/brams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine -mux_undef

    map_gates:
        techmap -map +/techmap.v -map +/lattice/arith_map.v
        iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top    (only if '-iopad')
        attrmvcp -attr src -attr LOC t:OB %x:+[O] t:OBZ %x:+[O] t:BB %x:+[B]
        attrmvcp -attr src -attr LOC -driven t:IB %x:+[I]
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        opt_clean
        dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r [-cell $_DFFE_??_ 01 -cell $_DFFE_?P??_ r -cell $_SDFFE_?P??_ r] [-cell $_ALDFF_?P_ x -cell $_ALDFFE_?P?_ x] [-cell $_DLATCH_?_ x]    ($_ALDFF_*_ only if -asyncprld, $_DLATCH_* only if not -asyncprld, $_*DFFE_* only if not -nodffe)
        opt_merge
        zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*    (only if -abc9 and -dff)
        techmap -D NO_LUT -map +/lattice/cells_map.v
        opt_expr -undriven -mux_undef
        simplemap
        lattice_gsr
        attrmvcp -copy -attr syn_useioff
        opt_clean

    map_luts:
        abc          (only if -abc2)
        techmap -map +/lattice/latches_map.v    (skip if -asyncprld)
        abc -dress -lut 4:7
        clean

    map_cells:
        techmap -map +/lattice/cells_map.v
        opt_lut_ins -tech lattice
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif <file-name>

    json:
        write_json <file-name>


    synth_microchip [options]

This command runs synthesis for Microchip FPGAs. This command creates 
netlists that are compatible with Microchip PolarFire devices. 

    -top <module>
        use the specified module as the top module

    -family <family>
        Run synthesis for the specified Microchip architecture. 
        Generate the synthesis netlist for the specified family.
        supported values:
        - polarfire: PolarFire

    -edif <file>
        Write the design to the specified edif file. Writing of an output file
        is omitted if this parameter is not specified.

    -blif <file>
        Write the design to the specified BLIF file. Writing of an output file
        is omitted if this parameter is not specified.

    -vlog <file>
        write the design to the specified Verilog file. writing of an output
        file is omitted if this parameter is not specified.
    -nobram
        Do not use block RAM cells in output netlist

    -nocarry
        Do not use ARI1 cells in output netlist

    -nodsp
        Do not use MATH blocks to implement multipliers and associated logic

    -noiopad
        Disable I/O buffer insertion (useful for hierarchical or 
        out-of-context flows)

    -noclkbuf
        Disable automatic clock buffer insertion

    -run <from_label>:<to_label>
        Only run the commands between the labels (see below). an empty
        'from_label' is synonymous to 'begin', and empty 'to_label' is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -dff
        Run 'abc'/'abc9' with -dff option

    -retime
        Run 'abc' with '-D 1' option to enable flip-flop retiming.
        implies -dff.

    -noabc9
        Use classic ABC flow instead of ABC9

    -discard-ffinit
        discard FF init value instead of emitting an error


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/microchip/cells_sim.v
        hierarchy -check -auto-top

    prepare:
        proc
        flatten    (with '-flatten')
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean

    map_dsp:    (skip if '-nodsp')
        memory_dff
        techmap -map +/mul2dsp.v -map +/microchip/{family}_dsp_map.v {options}
        select a:mul2dsp
        setattr -unset mul2dsp
        opt_expr -fine
        wreduce
        select -clear
        microchip_dsp -family <family>
        chtype -set $mul t:$__soft_mul

    coarse:
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=[4]
        alumacc
        share
        opt
        memory -nomap
        opt_clean
        attrmap -remove init    (only if -discard-ffinit)

    map_memory:
        memory_libmap [...]
        techmap -map +/microchip/LSRAM_map.v
        techmap -map +/microchip/uSRAM_map.v

    map_ffram:
        opt -fast -full
        memory_map

    fine:
        opt -full
        simplemap t:$mux
        simplemap t:$xor
        extract_reduce
        muxcover -nodecode -mux4=220
        techmap -map +/microchip/arith_map.v
        techmap -map +/techmap.v
        opt -fast

    map_cells:
        iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD    (unless -noiobs)
        techmap -map +/techmap.v -map +/microchip/cells_map.v
        clean

    map_ffs:
        dfflegalize -cell $_DFFE_PN?P_ x -cell $_SDFFCE_PN?P_ x -cell $_DLATCH_PN?_ x    (Converts FFs to supported types)
        zinit -all w:* t:$_SDFFCE_*    ('-dff' only)
        techmap -D NO_LUT -map +/microchip/cells_map.v    ('-abc9' only)

    map_luts:
        opt_expr -mux_undef -noclkinv
        abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]    (option for '-nowidelut', '-dff', '-retime')
        clean
        techmap -D NO_LUT -map +/microchip/cells_map.v    (only if not '-abc9')
        techmap -map +/microchip/cells_map.v -D FINAL_MAP -D LUT_WIDTH=[4]
        microchip_dffopt
        clkbufmap -buf CLKINT Y:A -inpad CLKBUF Y:PAD
        clean -purge

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif -pvector bra 

    blif:
        write_blif 

    vlog:
        write_verilog <file-name>


    synth_nanoxplore [options]

This command runs synthesis for NanoXplore FPGAs.

    -top <module>
        use the specified module as top module

    -family <family>
        run synthesis for the specified NanoXplore architecture
        generate the synthesis netlist for the specified family.
        supported values:
        - medium: NG-Medium
        - large: NG-Large
        - ultra: NG-Ultra

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

    -nocy
        do not map adders to CY cells

    -nodffe
        do not use flipflops with L in output netlist

    -min_ce_use <min_ce_use>
        do not use flip-flops with load signal if the resulting count is less
        than min_ce_use in output netlist

    -min_srst_use <min_srst_use>
        do not use flip-flops with async reset signal if the resulting count is less
        than min_srst_use in output netlist

    -norfram
        do not use Register File RAM cells in output netlist

    -nobram
        do not use block NX_RAM cells in output netlist

    -noiopad
        do not insert IO buffers

    -no-rw-check
        marks all recognized read ports as "return don't-care value on
        read/write collision" (same result as setting the no_rw_check
        attribute on all memories).


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/nanoxplore/cells_sim.v +/nanoxplore/cells_sim.v +/nanoxplore/cells_bb.v +/nanoxplore/cells_bb.v
        techmap -map +/nanoxplore/cells_wrap.v
        techmap -map +/nanoxplore/cells_wrap.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten    (skip if -noflatten)
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        alumacc
        opt
        memory -nomap [-no-rw-check]
        opt_clean

    map_ram:
        memory_libmap -lib +/nanoxplore/rf_rams.txt -lib +/nanoxplore/brams.txt [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -norfram)
        techmap -map +/nanoxplore/rf_rams_map.v -map +/nanoxplore/brams_map.v
        techmap -map +/nanoxplore/cells_wrap.v t:NX_RAM*
        techmap -map +/nanoxplore/cells_wrap.v t:NX_XRFB* t:NX_RFB*

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine -mux_undef

    map_gates:
        techmap -map +/techmap.v -map +/nanoxplore/arith_map.v
        nx_carry
        iopadmap -bits -outpad $__BEYOND_OBUF I:PAD -toutpad $__BEYOND_TOBUF C:I:PAD -inpad $__BEYOND_IBUF O:PAD -tinoutpad $__BEYOND_IOBUF C:O:I:PAD A:top    (skip if '-noiopad')
        techmap -map +/nanoxplore/io_map.v
        opt -fast

    map_ffs:
        dfflegalize -cell $_DFF_?_ 01 -cell $_DFF_?P?_ r -cell $_SDFF_?P?_ r [-cell $_DFFE_?P_ 01 -cell $_DFFE_?P?P_ r -cell $_SDFFE_?P?P_ r] -cell $_DLATCH_?_ x -mince 8 -minsrst 8    ($_*DFFE_* only if not -nodffe)
        opt_merge
        techmap -map +/nanoxplore/latches_map.v
        techmap -map +/nanoxplore/cells_map.v
        opt_expr -undriven -mux_undef
        clean -purge

    map_luts:
        abc -dress -lut 4
        techmap -map +/nanoxplore/cells_map.v t:$lut
        opt -fast
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox
        setundef -zero -undriven

    json:
        write_json <file-name>


    synth_nexus [options]

This command runs synthesis for Lattice Nexus FPGAs.

    -top <module>
        use the specified module as top module

    -family <device>
        run synthesis for the specified Nexus device
        supported values: lifcl, lfd2nx

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -vm <file>
        write the design to the specified structural Verilog file. writing of
        an output file is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -dff
        run 'abc'/'abc9' with -dff option

    -retime
        run 'abc' with '-dff -D 1' options

    -noccu2
        do not use CCU2 cells in output netlist

    -nodffe
        do not use flipflops with CE in output netlist

    -nolram
        do not use large RAM cells in output netlist
        note that large RAM must be explicitly requested with a (* lram *)
        attribute on the memory.

    -nobram
        do not use block RAM cells in output netlist

    -nolutram
        do not use LUT RAM cells in output netlist

    -nowidelut
        do not use PFU muxes to implement LUTs larger than LUT4s

    -noiopad
        do not insert IO buffers

    -nodsp
        do not infer DSP multipliers

    -abc9
        use new ABC9 flow (EXPERIMENTAL)

The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/nexus/cells_sim.v +/nexus/cells_xtra.v
        hierarchy -check -top <top>

    coarse:
        proc
        flatten
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        techmap -map +/mul2dsp.v [...]    (unless -nodsp)
        techmap -map +/nexus/dsp_map.v    (unless -nodsp)
        alumacc
        opt
        memory -nomap
        opt_clean

    map_ram:
        memory_libmap -lib +/nexus/lutrams.txt -lib +/nexus/brams.txt -lib +/nexus/lrams.txt -no-auto-huge [-no-auto-block] [-no-auto-distributed]    (-no-auto-block if -nobram, -no-auto-distributed if -nolutram)
        techmap -map +/nexus/lutrams_map.v -map +/nexus/brams_map.v -map +/nexus/lrams_map.v

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine

    map_gates:
        techmap -map +/techmap.v -map +/nexus/arith_map.v
        iopadmap -bits -outpad OB I:O -inpad IB O:I -toutpad OBZ ~T:I:O -tinoutpad BB ~T:O:I:B A:top    (skip if '-noiopad')
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        opt_clean
        dfflegalize -cell $_DFF_P_ 01 -cell $_DFF_PP?_ r -cell $_SDFF_PP?_ r -cell $_DLATCH_?_ x [-cell $_DFFE_PP_ 01 -cell $_DFFE_PP?P_ r -cell $_SDFFE_PP?P_ r]    ($_*DFFE_* only if not -nodffe)
        zinit -all w:* t:$_DFF_?_ t:$_DFFE_??_ t:$_SDFF*    (only if -abc9 and -dff
        techmap -D NO_LUT -map +/nexus/cells_map.v
        opt_expr -undriven -mux_undef
        simplemap
        attrmvcp -copy -attr syn_useioff
        opt_clean

    map_luts:
        techmap -map +/nexus/latches_map.v
        abc -dress -lut 4:5
        clean

    map_cells:
        techmap -map +/nexus/cells_map.v
        setundef -zero
        hilomap -singleton -hicell VHI Z -locell VLO Z
        clean

    check:
        autoname
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    json:
        write_json <file-name>

    vm:
        write_verilog <file-name>


   synth_quicklogic [options]
This command runs synthesis for QuickLogic FPGAs

    -top <module>
         use the specified module as top module

    -family <family>
        run synthesis for the specified QuickLogic architecture
        generate the synthesis netlist for the specified family.
        supported values:
        - pp3: PolarPro 3 
        - qlf_k6n10f: K6N10f

    -nodsp
        do not use dsp_t1_* to implement multipliers and associated logic
        (qlf_k6n10f only).

    -nocarry
        do not use adder_carry cells in output netlist.

    -nobram
        do not use block RAM cells in output netlist.

    -bramtypes
        Emit specialized BRAM cells for particular address and data width
        configurations.

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -verilog <file>
        write the design to the specified verilog file. writing of an output
        file is omitted if this parameter is not specified.

    -abc
        use old ABC flow, which has generally worse mapping results but is less
        likely to have bugs.

The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/quicklogic/common/cells_sim.v +/quicklogic/<family>/cells_sim.v
        hierarchy -check -top <top>

    prepare:
        proc
        flatten
        tribuf -logic                       (for pp3)
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce
        peepopt
        opt_clean
        share

    map_dsp:    (for qlf_k6n10f, skip if -nodsp)
        wreduce t:$mul
        ql_dsp_macc
        techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=20 -D DSP_B_MAXWIDTH=18 -D DSP_A_MINWIDTH=11 -D DSP_B_MINWIDTH=10 -D DSP_NAME=$__QL_MUL20X18
        techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=10 -D DSP_B_MAXWIDTH=9 -D DSP_A_MINWIDTH=4 -D DSP_B_MINWIDTH=4 -D DSP_NAME=$__QL_MUL10X9
        chtype -set $mul t:$__soft_mul
        techmap -map +/quicklogic/<family>/dsp_map.v -D USE_DSP_CFG_PARAMS=0
        ql_dsp_simd
        techmap -map +/quicklogic/<family>/dsp_final_map.v
        ql_dsp_io_regs

    coarse:
        techmap -map +/cmp2lut.v -D LUT_WIDTH=4
        opt_expr
        opt_clean
        alumacc
        pmuxtree
        opt
        memory -nomap
        opt_clean

    map_bram:    (for qlf_k6n10f, skip if -no_bram)
        memory_libmap -lib +/quicklogic/<family>/libmap_brams.txt
        ql_bram_merge
        techmap -map +/quicklogic/<family>/libmap_brams_map.v
        techmap -autoproc -map +/quicklogic/<family>/brams_map.v
        ql_bram_types    (if -bramtypes)

    map_ffram:
        opt -fast -mux_undef -undriven -fine
        memory_map -iattr -attr !ram_block -attr !rom_block -attr logic_block -attr syn_ramstyle=auto -attr syn_ramstyle=registers -attr syn_romstyle=auto -attr syn_romstyle=logic
        opt -undriven -fine

    map_gates:
        techmap
        opt -fast
        muxcover -mux8 -mux4    (for pp3)

    map_ffs:
        opt_expr
        shregmap -minlen <min> -maxlen <max>    (for qlf_k6n10f)
        dfflegalize -cell <supported FF types>
        techmap -map +/quicklogic/<family>/cells_map.v    (for pp3)
        techmap -map +/quicklogic/<family>/ffs_map.v    (for ql_k6n10f)
        opt

    map_luts:    (for pp3)
        techmap -map +/quicklogic/<family>/latches_map.v
        read_verilog -lib -specify -icells +/quicklogic/<family>/abc9_model.v
        techmap -map +/quicklogic/<family>/abc9_map.v
        abc9 -maxlut 4 -dff
        techmap -map +/quicklogic/<family>/abc9_unmap.v
        clean

    map_luts:    (for qlf_k6n10f)
        abc9 -maxlut 6
        clean
        opt_lut

    map_cells:    (for pp3)
        techmap -map +/quicklogic/<family>/lut_map.v
        clean
        opt_lut

    check:
        autoname
        hierarchy -check
        stat
        check -noinit

    iomap:    (for pp3)
        clkbufmap -inpad ckpad Q:P
        iopadmap -bits -outpad outpad A:P -inpad inpad Q:P -tinoutpad bipad EN:Q:A:P A:top

    finalize:
        setundef -zero -params -undriven    (for pp3)
        opt_clean -purge
        check
        blackbox =A:whitebox

    blif:    (if -blif)
        write_blif -attr -param -auto-top 

    verilog:    (if -verilog)
        write_verilog -noattr -nohex <file-name>


    synth_sf2 [options]

This command runs synthesis for SmartFusion2 and IGLOO2 FPGAs.

    -top <module>
        use the specified module as top module

    -edif <file>
        write the design to the specified EDIF file. writing of an output file
        is omitted if this parameter is not specified.

    -vlog <file>
        write the design to the specified Verilog file. writing of an output
        file is omitted if this parameter is not specified.

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -noflatten
        do not flatten design before synthesis

    -noiobs
        run synthesis in "block mode", i.e. do not insert IO buffers

    -clkbuf
        insert direct PAD->global_net buffers

    -discard-ffinit
        discard FF init value instead of emitting an error

    -retime
        run 'abc' with '-dff -D 1' options


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib +/sf2/cells_sim.v
        hierarchy -check -top <top>

    flatten:    (unless -noflatten)
        proc
        flatten
        tribuf -logic
        deminout

    coarse:
        attrmap -remove init    (only if -discard-ffinit)
        synth -run coarse

    fine:
        opt -fast -mux_undef -undriven -fine
        memory_map
        opt -undriven -fine
        techmap -map +/techmap.v -map +/sf2/arith_map.v
        opt -fast
        abc -dff -D 1    (only if -retime)

    map_ffs:
        dfflegalize -cell $_DFFE_PN?P_ x -cell $_SDFFCE_PN?P_ x -cell $_DLATCH_PN?_ x
        techmap -D NO_LUT -map +/sf2/cells_map.v
        opt_expr -mux_undef
        simplemap

    map_luts:
        abc -lut 4
        clean

    map_cells:
        techmap -map +/sf2/cells_map.v
        clean

    map_iobs:
        clkbufmap -buf CLKINT Y:A [-inpad CLKBUF Y:PAD]    (unless -noiobs, -inpad only passed if -clkbuf)
        iopadmap -bits -inpad INBUF Y:PAD -outpad OUTBUF D:PAD -toutpad TRIBUFF E:D:PAD -tinoutpad BIBUF E:Y:D:PAD    (unless -noiobs)
        clean -purge

    check:
        hierarchy -check
        stat
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif -gndvccy <file-name>

    vlog:
        write_verilog <file-name>

    json:
        write_json <file-name>


    synth_xilinx [options]

This command runs synthesis for Xilinx FPGAs. This command does not operate on
partly selected designs. At the moment this command creates netlists that are
compatible with 7-Series Xilinx devices.

    -top <module>
        use the specified module as top module

    -family <family>
        run synthesis for the specified Xilinx architecture
        generate the synthesis netlist for the specified family.
        supported values:
        - xcup: Ultrascale Plus
        - xcu: Ultrascale
        - xc7: Series 7 (default)
        - xc6s: Spartan 6
        - xc6v: Virtex 6
        - xc5v: Virtex 5 (EXPERIMENTAL)
        - xc4v: Virtex 4 (EXPERIMENTAL)
        - xc3sda: Spartan 3A DSP (EXPERIMENTAL)
        - xc3sa: Spartan 3A (EXPERIMENTAL)
        - xc3se: Spartan 3E (EXPERIMENTAL)
        - xc3s: Spartan 3 (EXPERIMENTAL)
        - xc2vp: Virtex 2 Pro (EXPERIMENTAL)
        - xc2v: Virtex 2 (EXPERIMENTAL)
        - xcve: Virtex E, Spartan 2E (EXPERIMENTAL)
        - xcv: Virtex, Spartan 2 (EXPERIMENTAL)

    -edif <file>
        write the design to the specified edif file. writing of an output file
        is omitted if this parameter is not specified.

    -blif <file>
        write the design to the specified BLIF file. writing of an output file
        is omitted if this parameter is not specified.

    -ise
        generate an output netlist suitable for ISE

    -nobram
        do not use block RAM cells in output netlist

    -nolutram
        do not use distributed RAM cells in output netlist

    -nosrl
        do not use distributed SRL cells in output netlist

    -nocarry
        do not use XORCY/MUXCY/CARRY4 cells in output netlist

    -nowidelut
        do not use MUXF[5-9] resources to implement LUTs larger than native for
        the target

    -nodsp
        do not use DSP48*s to implement multipliers and associated logic

    -noiopad
        disable I/O buffer insertion (useful for hierarchical or 
        out-of-context flows)

    -noclkbuf
        disable automatic clock buffer insertion

    -uram
        infer URAM288s for large memories (xcup only)

    -widemux <int>
        enable inference of hard multiplexer resources (MUXF[78]) for muxes at
        or above this number of inputs (minimum value 2, recommended value >= 5)
        default: 0 (no inference)

    -json <file>
        write the design to the specified JSON file. writing of an output file
        is omitted if this parameter is not specified.

    -run <from_label>:<to_label>
        only run the commands between the labels (see below). an empty
        from label is synonymous to 'begin', and empty to label is
        synonymous to the end of the command list.

    -flatten
        flatten design before synthesis

    -dff
        run 'abc'/'abc9' with -dff option

    -retime
        run 'abc' with '-D 1' option to enable flip-flop retiming.
        implies -dff.

    -abc9
        use new ABC9 flow (EXPERIMENTAL)


The following commands are executed by this synthesis command:

    begin:
        read_verilog -lib -specify +/xilinx/cells_sim.v
        read_verilog -lib +/xilinx/cells_xtra.v
        hierarchy -check -auto-top

    prepare:
        proc
        flatten    (with '-flatten')
        tribuf -logic
        deminout
        opt_expr
        opt_clean
        check
        opt -nodffe -nosdff
        fsm
        opt
        wreduce [-keepdc]    (option for '-widemux')
        peepopt
        opt_clean
        muxpack        ('-widemux' only)
        pmux2shiftx    (skip if '-nosrl' and '-widemux=0')
        clean          (skip if '-nosrl' and '-widemux=0')

    map_dsp:    (skip if '-nodsp')
        memory_dff
        techmap -map +/mul2dsp.v -map +/xilinx/{family}_dsp_map.v {options}
        select a:mul2dsp
        setattr -unset mul2dsp
        opt_expr -fine
        wreduce
        select -clear
        xilinx_dsp -family <family>
        chtype -set $mul t:$__soft_mul

    coarse:
        techmap -map +/cmp2lut.v -map +/cmp2lcu.v -D LUT_WIDTH=[46]
        alumacc
        share
        opt
        memory -nomap
        opt_clean

    map_memory:
        memory_libmap [...]
        techmap -map +/xilinx/lutrams_<family>_map.v
        techmap -map +/xilinx/brams_<family>_map.v

    map_ffram:
        opt -fast -full
        memory_map

    fine:
        simplemap t:$mux    ('-widemux' only)
        muxcover <internal options>    ('-widemux' only)
        opt -full
        xilinx_srl -variable -minlen 3    (skip if '-nosrl')
        techmap  -map +/techmap.v -D LUT_SIZE=[46] [-map +/xilinx/mux_map.v] -map +/xilinx/arith_map.v
        opt -fast

    map_cells:
        iopadmap -bits -outpad OBUF I:O -inpad IBUF O:I -toutpad OBUFT ~T:I:O -tinoutpad IOBUF ~T:O:I:IO A:top    (skip if '-noiopad')
        techmap -map +/techmap.v -map +/xilinx/cells_map.v
        clean

    map_ffs:
        dfflegalize -cell $_DFFE_?P?P_ 01 -cell $_SDFFE_?P?P_ 01 -cell $_DLATCH_?P?_ 01    (for xc6v, xc7, xcu, xcup)
        zinit -all w:* t:$_SDFFE_*    ('-dff' only)
        techmap -map +/xilinx/ff_map.v    ('-abc9' only)

    map_luts:
        opt_expr -mux_undef -noclkinv
        abc -luts 2:2,3,6:5[,10,20] [-dff] [-D 1]    (option for '-nowidelut', '-dff', '-retime')
        clean
        techmap -map +/xilinx/ff_map.v    (only if not '-abc9')
        xilinx_srl -fixed -minlen 3    (skip if '-nosrl')
        techmap -map +/xilinx/lut_map.v -map +/xilinx/cells_map.v -D LUT_WIDTH=[46]
        xilinx_dffopt [-lut4]
        opt_lut_ins -tech xilinx

    finalize:
        clkbufmap -buf BUFG O:I    (skip if '-noclkbuf')
        extractinv -inv INV O:I    (only if '-ise')
        clean

    check:
        hierarchy -check
        stat -tech xilinx
        check -noinit
        blackbox =A:whitebox

    edif:
        write_edif -pvector bra 

    blif:
        write_blif 

    json:
        write_json <file-name>


    synthprop [options]

This creates synthesizable properties for the selected module.


    -name <portname>
        name of the output port for assertions (default: assertions).

    -map <filename>
        write the port mapping for synthesizable properties into the given file.

    -or_outputs
        Or all outputs together to create a single output that goes high when
        any property is violated, instead of generating individual output bits.

    -reset <portname>
        name of the top-level reset input. Latch a high state on the generated
        outputs until an asynchronous top-level reset input is activated.

    -resetn <portname>
        like above but with inverse polarity



    tcl <filename> [args]

This command executes the tcl commands in the specified file.
Use 'yosys cmd' to run the yosys command 'cmd' from tcl.

The tcl command 'yosys -import' can be used to import all yosys
commands directly as tcl commands to the tcl shell. Yosys commands
'proc' and 'rename' are wrapped to tcl commands 'procs' and 'renames'
in order to avoid a name collision with the built in commands.

If any arguments are specified, these arguments are provided to the script via
the standard $argc and $argv variables.

Note, tcl will not recieve the output of any yosys command. If the output
of the tcl commands are needed, use the yosys command 'tee -s result.string'
to redirect yosys's output to the 'result.string' scratchpad value.


    techmap [-map filename] [selection]

This pass implements a very simple technology mapper that replaces cells in
the design with implementations given in form of a Verilog or RTLIL source
file.

    -map filename
        the library of cell implementations to be used.
        without this parameter a builtin library is used that
        transforms the internal RTL cells to the internal gate
        library.

    -map %<design-name>
        like -map above, but with an in-memory design instead of a file.

    -extern
        load the cell implementations as separate modules into the design
        instead of inlining them.

    -max_iter <number>
        only run the specified number of iterations on each module.
        default: unlimited

    -recursive
        instead of the iterative breadth-first algorithm use a recursive
        depth-first algorithm. both methods should yield equivalent results,
        but may differ in performance.

    -autoproc
        Automatically call "proc" on implementations that contain processes.

    -wb
        Ignore the 'whitebox' attribute on cell implementations.

    -assert
        this option will cause techmap to exit with an error if it can't map
        a selected cell. only cell types that end on an underscore are accepted
        as final cell types by this mode.

    -D <define>, -I <incdir>
        this options are passed as-is to the Verilog frontend for loading the
        map file. Note that the Verilog frontend is also called with the
        '-nooverwrite' option set.

When a module in the map file has the 'techmap_celltype' attribute set, it will
match cells with a type that match the text value of this attribute. Otherwise
the module name will be used to match the cell.  Multiple space-separated cell
types can be listed, and wildcards using [] will be expanded (ie.
"$_DFF_[PN]_" is the same as "$_DFF_P_ $_DFF_N_").

When a module in the map file has the 'techmap_simplemap' attribute set, techmap
will use 'simplemap' (see 'help simplemap') to map cells matching the module.

When a module in the map file has the 'techmap_maccmap' attribute set, techmap
will use 'maccmap' (see 'help maccmap') to map cells matching the module.

When a module in the map file has the 'techmap_wrap' attribute set, techmap
will create a wrapper for the cell and then run the command string that the
attribute is set to on the wrapper module.

When a port on a module in the map file has the 'techmap_autopurge' attribute
set, and that port is not connected in the instantiation that is mapped, then
a cell port connected only to such wires will be omitted in the mapped version
of the circuit.

All wires in the modules from the map file matching the pattern _TECHMAP_*
or *._TECHMAP_* are special wires that are used to pass instructions from
the mapping module to the techmap command. At the moment the following special
wires are supported:

    _TECHMAP_FAIL_
        When this wire is set to a non-zero constant value, techmap will not
        use this module and instead try the next module with a matching
        'techmap_celltype' attribute.

        When such a wire exists but does not have a constant value after all
        _TECHMAP_DO_* commands have been executed, an error is generated.

    _TECHMAP_DO_*
        This wires are evaluated in alphabetical order. The constant text value
        of this wire is a yosys command (or sequence of commands) that is run
        by techmap on the module. A common use case is to run 'proc' on modules
        that are written using always-statements.

        When such a wire has a non-constant value at the time it is to be
        evaluated, an error is produced. That means it is possible for such a
        wire to start out as non-constant and evaluate to a constant value
        during processing of other _TECHMAP_DO_* commands.

        A _TECHMAP_DO_* command may start with the special token 'CONSTMAP; '.
        in this case techmap will create a copy for each distinct configuration
        of constant inputs and shorted inputs at this point and import the
        constant and connected bits into the map module. All further commands
        are executed in this copy. This is a very convenient way of creating
        optimized specializations of techmap modules without using the special
        parameters described below.

        A _TECHMAP_DO_* command may start with the special token 'RECURSION; '.
        then techmap will recursively replace the cells in the module with their
        implementation. This is not affected by the -max_iter option.

        It is possible to combine both prefixes to 'RECURSION; CONSTMAP; '.

    _TECHMAP_REMOVEINIT_<port-name>_
        When this wire is set to a constant value, the init attribute of the
        wire(s) connected to this port will be consumed.  This wire must have
        the same width as the given port, and for every bit that is set to 1 in
        the value, the corresponding init attribute bit will be changed to 1'bx.
        If all bits of an init attribute are left as x, it will be removed.

In addition to this special wires, techmap also supports special parameters in
modules in the map file:

    _TECHMAP_CELLTYPE_
        When a parameter with this name exists, it will be set to the type name
        of the cell that matches the module.

    _TECHMAP_CELLNAME_
        When a parameter with this name exists, it will be set to the name
        of the cell that matches the module.

    _TECHMAP_CONSTMSK_<port-name>_
    _TECHMAP_CONSTVAL_<port-name>_
        When this pair of parameters is available in a module for a port, then
        former has a 1-bit for each constant input bit and the latter has the
        value for this bit. The unused bits of the latter are set to undef (x).

    _TECHMAP_WIREINIT_<port-name>_
        When a parameter with this name exists, it will be set to the initial
        value of the wire(s) connected to the given port, as specified by the
        init attribute. If the attribute doesn't exist, x will be filled for the
        missing bits.  To remove the init attribute bits used, use the
        _TECHMAP_REMOVEINIT_*_ wires.

    _TECHMAP_BITS_CONNMAP_
    _TECHMAP_CONNMAP_<port-name>_
        For an N-bit port, the _TECHMAP_CONNMAP_<port-name>_ parameter, if it
        exists, will be set to an N*_TECHMAP_BITS_CONNMAP_ bit vector containing
        N words (of _TECHMAP_BITS_CONNMAP_ bits each) that assign each single
        bit driver a unique id. The values 0-3 are reserved for 0, 1, x, and z.
        This can be used to detect shorted inputs.

When a module in the map file has a parameter where the according cell in the
design has a port, the module from the map file is only used if the port in
the design is connected to a constant value. The parameter is then set to the
constant value.

A cell with the name _TECHMAP_REPLACE_ in the map file will inherit the name
and attributes of the cell that is being replaced.
A cell with a name of the form `_TECHMAP_REPLACE_.<suffix>` in the map file will
be named thus but with the `_TECHMAP_REPLACE_' prefix substituted with the name
of the cell being replaced.
Similarly, a wire named in the form `_TECHMAP_REPLACE_.<suffix>` will cause a
new wire alias to be created and named as above but with the `_TECHMAP_REPLACE_'
prefix also substituted.

A cell with the type _TECHMAP_PLACEHOLDER_ in the map file will have its type
changed to the content of the techmap_chtype attribute. This allows for choosing
the cell type dynamically.

See 'help extract' for a pass that does the opposite thing.

See 'help flatten' for a pass that does flatten the design (which is
essentially techmap but using the design itself as map library).


    tee [-q] [-o logfile|-a logfile] cmd

Execute the specified command, optionally writing the commands output to the
specified logfile(s).

    -q
        Do not print output to the normal destination (console and/or log file).

    -o logfile
        Write output to this file, truncate if exists.

    -a logfile
        Write output to this file, append if exists.

    -s scratchpad
        Write output to this scratchpad value, truncate if it exists.

    +INT, -INT
        Add/subtract INT from the -v setting for this command.


    test_abcloop [options]

Test handling of logic loops in ABC.

    -n {integer}
        create this number of circuits and test them (default = 100).

    -s {positive_integer}
        use this value as rng seed value (default = unix time).


    test_autotb [options] [filename]

Automatically create primitive Verilog test benches for all modules in the
design. The generated testbenches toggle the input pins of the module in
a semi-random manner and dumps the resulting output signals.

This can be used to check the synthesis results for simple circuits by
comparing the testbench output for the input files and the synthesis results.

The backend automatically detects clock signals. Additionally a signal can
be forced to be interpreted as clock signal by setting the attribute
'gentb_clock' on the signal.

The attribute 'gentb_constant' can be used to force a signal to a constant
value after initialization. This can e.g. be used to force a reset signal
low in order to explore more inner states in a state machine.

The attribute 'gentb_skip' can be attached to modules to suppress testbench
generation.

    -n <int>
        number of iterations the test bench should run (default = 1000)

    -seed <int>
        seed used for pseudo-random number generation (default = 0).
        a value of 0 will cause an arbitrary seed to be chosen, based on
        the current system time.


    test_cell [options] {cell-types}

Tests the internal implementation of the given cell type (for example '$add')
by comparing SAT solver, EVAL and TECHMAP implementations of the cell types..

Run with 'all' instead of a cell type to run the test on all supported
cell types. Use for example 'all /$add' for all cell types except $add.

    -n {integer}
        create this number of cell instances and test them (default = 100).

    -s {positive_integer}
        use this value as rng seed value (default = unix time).

    -f {rtlil_file}
        don't generate circuits. instead load the specified RTLIL file.

    -w {filename_prefix}
        don't test anything. just generate the circuits and write them
        to RTLIL files with the specified prefix

    -map {filename}
        pass this option to techmap.

    -simlib
        use "techmap -D SIMLIB_NOCHECKS -map +/simlib.v -max_iter 2 -autoproc"

    -aigmap
        instead of calling "techmap", call "aigmap"

    -muxdiv
        when creating test benches with dividers, create an additional mux
        to mask out the division-by-zero case

    -script {script_file}
        instead of calling "techmap", call "script {script_file}".

    -const
        set some input bits to random constant values

    -nosat
        do not check SAT model or run SAT equivalence checking

    -noeval
        do not check const-eval models

    -noopt
        do not opt tecchmapped design

    -edges
        test cell edges db creator against sat-based implementation

    -v
        print additional debug information to the console

    -vlog {filename}
        create a Verilog test bench to test simlib and write_verilog
    -bloat {factor}
        increase cell size limits b{factor} times where possible
    -check_cost
        check if the estimated cell cost is a valid upper bound for
        the techmapped cell count 


TODO: add help message


    test_pmgen -reduce_chain [options] [selection]

Demo for recursive pmgen patterns. Map chains of AND/OR/XOR to $reduce_*.


    test_pmgen -reduce_tree [options] [selection]

Demo for recursive pmgen patterns. Map trees of AND/OR/XOR to $reduce_*.


    test_pmgen -eqpmux [options] [selection]

Demo for recursive pmgen patterns. Optimize EQ/NE/PMUX circuits.


    test_pmgen -generate [options] <pattern_name>

Create modules that match the specified pattern.


    torder [options] [selection]

This command prints the selected cells in topological order.

    -stop <cell_type> <cell_port>
        do not use the specified cell port in topological sorting

    -noautostop
        by default Q outputs of internal FF cells and memory read port outputs
        are not used in topological sorting. this option deactivates that.


    trace cmd

Execute the specified command, logging all changes the command performs on
the design in real time.


    tribuf [options] [selection]

This pass transforms $mux cells with 'z' inputs to tristate buffers.

    -merge
        merge multiple tri-state buffers driving the same net
        into a single buffer.

    -logic
        convert tri-state buffers that do not drive output ports
        to non-tristate logic. this option implies -merge.

    -formal
        convert all tri-state buffers to non-tristate logic and
        add a formal assertion that no two buffers are driving the
        same net simultaneously. this option implies -merge.


    uniquify [selection]

By default, a module that is instantiated by several other modules is only
kept once in the design. This preserves the original modularity of the design
and reduces the overall size of the design in memory. But it prevents certain
optimizations and other operations on the design. This pass creates unique
modules for all selected cells. The created modules are marked with the
'unique' attribute.

This commands only operates on modules that by themself have the 'unique'
attribute set (the 'top' module is unique implicitly).


    verific [-work <libname>] {-sv|-vhdl|...} <hdl-file>

Load the specified Verilog/SystemVerilog/VHDL file into the specified library.
(default library when -work is not present: "work")


    verific [-L <libname>] {-sv|-vhdl|...} <hdl-file>

Look up external definitions in the specified library.
(-L may be used more than once)


    verific -set-error <msg_id>..
    verific -set-warning <msg_id>..
    verific -set-info <msg_id>..
    verific -set-ignore <msg_id>..

Set message severity. <msg_id> is the string in square brackets when a message
is printed, such as VERI-1209.
Also errors, warnings, infos and comments could be used to set new severity for
all messages of certain type.


    verific -import [options] <top>..

Elaborate the design for the specified top modules or configurations, import to
Yosys and reset the internal state of Verific.

Import options:

  -all
    Elaborate all modules, not just the hierarchy below the given top
    modules. With this option the list of modules to import is optional.

  -gates
    Create a gate-level netlist.

  -flatten
    Flatten the design in Verific before importing.

  -extnets
    Resolve references to external nets by adding module ports as needed.

  -no-split-complex-ports
    Complex ports (structs or arrays) are not split and remain packed as a single port.

  -fullinit
    Keep all register initializations, even those for non-FF registers.

  -cells
    Import all cell definitions from Verific loaded libraries even if they are
    unused in design. Useful with "-edif" and "-liberty" option.

  -chparam name value 
    Elaborate the specified top modules (all modules when -all given) using
    this parameter value. Modules on which this parameter does not exist will
    cause Verific to produce a VERI-1928 or VHDL-1676 message. This option
    can be specified multiple times to override multiple parameters.
    String values must be passed in double quotes (").

  -v, -vv
    Verbose log messages. (-vv is even more verbose than -v.)

  -pp <filename>
    Pretty print design after elaboration to specified file.

The following additional import options are useful for debugging the Verific
bindings (for Yosys and/or Verific developers):

  -k
    Keep going after an unsupported verific primitive is found. The
    unsupported primitive is added as blockbox module to the design.
    This will also add all SVA related cells to the design parallel to
    the checker logic inferred by it.

  -V
    Import Verific netlist as-is without translating to Yosys cell types. 

  -n
    Keep all Verific names on instances and nets. By default only
    user-declared names are preserved.

  -d <dump_file>
    Dump the Verific netlist as a verilog file.


    verific [-work <libname>] -pp [options] <filename> [<module>]..

Pretty print design (or just module) to the specified file from the
specified library. (default library when -work is not present: "work")

Pretty print options:

  -verilog
    Save output for Verilog/SystemVerilog design modules (default).

  -vhdl
    Save output for VHDL design units.


    verific -cfg [<name> [<value>]]

Get/set Verific runtime flags.


Use YosysHQ Tabby CAD Suite if you need Yosys+Verific.
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binaries of YosysHQ Tabby CAD Suite.


    verilog_defaults -add [options]

Add the specified options to the list of default options to read_verilog.


    verilog_defaults -clear

Clear the list of Verilog default options.


    verilog_defaults -push
    verilog_defaults -pop

Push or pop the list of default options to a stack. Note that -push does
not imply -clear.


    verilog_defines [options]

Define and undefine verilog preprocessor macros.

    -Dname[=definition]
        define the preprocessor symbol 'name' and set its optional value
        'definition'

    -Uname[=definition]
        undefine the preprocessor symbol 'name'

    -reset
        clear list of defined preprocessor symbols

    -list
        list currently defined preprocessor symbols


    viz [options] [selection]

Create a graphviz DOT file for the selected part of the design, showing the
relationships between the selected wires, and compile it to a graphics
file (usually SVG or PostScript).

    -viewer <viewer>
        Run the specified command with the graphics file as parameter.
        On Windows, this pauses yosys until the viewer exits.

    -format <format>
        Generate a graphics file in the specified format. Use 'dot' to just
        generate a .dot file, or other <format> strings such as 'svg' or 'ps'
        to generate files in other formats (this calls the 'dot' command).

    -prefix <prefix>
        generate <prefix>.* instead of ~/.yosys_viz.*

    -pause
        wait for the user to press enter to before returning

    -nobg
        don't run viewer in the background, IE wait for the viewer tool to
        exit before returning

    -set-vg-attr
        set their group index as 'vg' attribute on cells and wires

    -g <selection>
        manually define a group of terminal signals. this group is not being
        merged with other terminal groups.

    -u <selection>
        manually define a unique group for each wire in the selection.

    -x <selection>
        manually exclude wires from being considered. (usually this is
        used for global signals, such as reset.)

    -s <selection>
        like -g, but mark group as 'special', changing the algorithm to
        preserve as much info about this groups connectivity as possible.

    -G <selection_expr> .
    -U <selection_expr> .
    -X <selection_expr> .
    -S <selection_expr> .
        like -u, -g, -x, and -s, but parse all arguments up to a terminating .
        as a single select expression. (see 'help select' for details)

    -0, -1, -2, -3, -4, -5, -6, -7, -8, -9
        select effort level. each level corresponds to an incresingly more
        aggressive sequence of strategies for merging nodes of the data flow
        graph. (default: 9)

When no <format> is specified, 'dot' is used. When no <format> and <viewer> is
specified, 'xdot' is used to display the schematic (POSIX systems only).

The generated output files are '~/.yosys_viz.dot' and '~/.yosys_viz.<format>',
unless another prefix is specified using -prefix <prefix>.

Yosys on Windows and YosysJS use different defaults: The output is written
to 'show.dot' in the current directory and new viewer is launched each time
the 'show' command is executed.


    wbflip [selection]

Flip the whitebox attribute on selected cells. I.e. if it's set, unset it, and
vice-versa. Blackbox cells are not effected by this command.


    wreduce [options] [selection]

This command reduces the word size of operations. For example it will replace
the 32 bit adders in the following code with adders of more appropriate widths:

    module test(input [3:0] a, b, c, output [7:0] y);
        assign y = a + b + c + 1;
    endmodule

Options:

    -memx
        Do not change the width of memory address ports. Use this options in
        flows that use the 'memory_memx' pass.

    -mux_undef
        remove 'undef' inputs from $mux, $pmux and $_MUX_ cells

    -keepdc
        Do not optimize explicit don't-care values.


    write_aiger [options] [filename]

Write the current design to an AIGER file. The design must be flattened and
must not contain any cell types except $_AND_, $_NOT_, simple FF types,
$assert and $assume cells, and $initstate cells.

$assert and $assume cells are converted to AIGER bad state properties and
invariant constraints.

    -ascii
        write ASCII version of AIGER format

    -zinit
        convert FFs to zero-initialized FFs, adding additional inputs for
        uninitialized FFs.

    -miter
        design outputs are AIGER bad state properties

    -symbols
        include a symbol table in the generated AIGER file

    -map <filename>
        write an extra file with port and latch symbols

    -vmap <filename>
        like -map, but more verbose

    -no-startoffset
        make indexes zero based, enable using map files with smt solvers.

    -ywmap <filename>
        write a map file for conversion to and from yosys witness traces.

    -I, -O, -B, -L
        If the design contains no input/output/assert/flip-flop then create one
        dummy input/output/bad_state-pin or latch to make the tools reading the
        AIGER file happy.


    write_aiger2 [options] [filename]

Write the selected module to an AIGER file.

    -strash
        perform structural hashing while writing

    -flatten
        allow descending into submodules and write a flattened view of the design
        hierarchy starting at the selected top

This command is able to ingest all combinational cells except for:

    $alu, $lcu, $demux, $bweqx, $macc, $concat, $pow, $modfloor, $divfloor, 
    $mod, $div, $mul, $sub, $add, $nex, $eqx, $shiftx, $shift, $sshr, 
    $sshl, $shr, $shl, $sop, $lut, $slice, $neg, 

And all combinational gates except for:

    $_TBUF_, $_MUX16_, $_MUX8_, $_MUX4_, 

WARNING: THE 'write_aiger2' COMMAND IS EXPERIMENTAL.


    write_blif [options] [filename]

Write the current design to an BLIF file.

    -top top_module
        set the specified module as design top module

    -buf <cell-type> <in-port> <out-port>
        use cells of type <cell-type> with the specified port names for buffers

    -unbuf <cell-type> <in-port> <out-port>
        replace buffer cells with the specified name and port names with
        a .names statement that models a buffer

    -true <cell-type> <out-port>
    -false <cell-type> <out-port>
    -undef <cell-type> <out-port>
        use the specified cell types to drive nets that are constant 1, 0, or
        undefined. when '-' is used as <cell-type>, then <out-port> specifies
        the wire name to be used for the constant signal and no cell driving
        that wire is generated. when '+' is used as <cell-type>, then <out-port>
        specifies the wire name to be used for the constant signal and a .names
        statement is generated to drive the wire.

    -noalias
        if a net name is aliasing another net name, then by default a net
        without fanout is created that is driven by the other net. This option
        suppresses the generation of this nets without fanout.

The following options can be useful when the generated file is not going to be
read by a BLIF parser but a custom tool. It is recommended not to name the
output file *.blif when any of these options are used.

    -icells
        do not translate Yosys's internal gates to generic BLIF logic
        functions. Instead create .subckt or .gate lines for all cells.

    -gates
        print .gate instead of .subckt lines for all cells that are not
        instantiations of other modules from this design.

    -conn
        do not generate buffers for connected wires. instead use the
        non-standard .conn statement.

    -attr
        use the non-standard .attr statement to write cell attributes

    -param
        use the non-standard .param statement to write cell parameters

    -cname
        use the non-standard .cname statement to write cell names

    -iname, -iattr
        enable -cname and -attr functionality for .names statements
        (the .cname and .attr statements will be included in the BLIF
        output after the truth table for the .names statement)

    -blackbox
        write blackbox cells with .blackbox statement.

    -impltf
        do not write definitions for the $true, $false and $undef wires.


    write_btor [options] [filename]

Write a BTOR description of the current design.

  -v
    Add comments and indentation to BTOR output file

  -s
    Output only a single bad property for all asserts

  -c
    Output cover properties using 'bad' statements instead of asserts

  -i <filename>
    Create additional info file with auxiliary information

  -x
    Output symbols for internal netnames (starting with '$')

  -ywmap <filename>
    Create a map file for conversion to and from Yosys witness traces


    write_cxxrtl [options] [filename]

Write C++ code that simulates the design. The generated code requires a driver
that instantiates the design, toggles its clock, and interacts with its ports.

The following driver may be used as an example for a design with a single clock
driving rising edge triggered flip-flops:

    #include "top.cc"

    int main() {
      cxxrtl_design::p_top top;
      top.step();
      while (1) {
        /* user logic */
        top.p_clk.set(false);
        top.step();
        top.p_clk.set(true);
        top.step();
      }
    }

Note that CXXRTL simulations, just like the hardware they are simulating, are
subject to race conditions. If, in the example above, the user logic would run
simultaneously with the rising edge of the clock, the design would malfunction.

This backend supports replacing parts of the design with black boxes implemented
in C++. If a module marked as a CXXRTL black box, its implementation is ignored,
and the generated code consists only of an interface and a factory function.
The driver must implement the factory function that creates an implementation of
the black box, taking into account the parameters it is instantiated with.

For example, the following Verilog code defines a CXXRTL black box interface for
a synchronous debug sink:

    (* cxxrtl_blackbox *)
    module debug(...);
      (* cxxrtl_edge = "p" *) input clk;
      input en;
      input [7:0] i_data;
      (* cxxrtl_sync *) output [7:0] o_data;
    endmodule

For this HDL interface, this backend will generate the following C++ interface:

    struct bb_p_debug : public module {
      value<1> p_clk;
      bool posedge_p_clk() const { /* ... */ }
      value<1> p_en;
      value<8> p_i_data;
      wire<8> p_o_data;

      bool eval(performer *performer) override;
      virtual bool commit(observer &observer);
      bool commit() override;

      static std::unique_ptr<bb_p_debug>
      create(std::string name, metadata_map parameters, metadata_map attributes);
    };

The `create' function must be implemented by the driver. For example, it could
always provide an implementation logging the values to standard error stream:

    namespace cxxrtl_design {

    struct stderr_debug : public bb_p_debug {
      bool eval(performer *performer) override {
        if (posedge_p_clk() && p_en)
          fprintf(stderr, "debug: %02x\n", p_i_data.data[0]);
        p_o_data.next = p_i_data;
        return bb_p_debug::eval(performer);
      }
    };

    std::unique_ptr<bb_p_debug>
    bb_p_debug::create(std::string name, cxxrtl::metadata_map parameters,
                       cxxrtl::metadata_map attributes) {
      return std::make_unique<stderr_debug>();
    }

    }

For complex applications of black boxes, it is possible to parameterize their
port widths. For example, the following Verilog code defines a CXXRTL black box
interface for a configurable width debug sink:

    (* cxxrtl_blackbox, cxxrtl_template = "WIDTH" *)
    module debug(...);
      parameter WIDTH = 8;
      (* cxxrtl_edge = "p" *) input clk;
      input en;
      (* cxxrtl_width = "WIDTH" *) input [WIDTH - 1:0] i_data;
      (* cxxrtl_width = "WIDTH" *) output [WIDTH - 1:0] o_data;
    endmodule

For this parametric HDL interface, this backend will generate the following C++
interface (only the differences are shown):

    template<size_t WIDTH>
    struct bb_p_debug : public module {
      // ...
      value<WIDTH> p_i_data;
      wire<WIDTH> p_o_data;
      // ...
      static std::unique_ptr<bb_p_debug<WIDTH>>
      create(std::string name, metadata_map parameters, metadata_map attributes);
    };

The `create' function must be implemented by the driver, specialized for every
possible combination of template parameters. (Specialization is necessary to
enable separate compilation of generated code and black box implementations.)

    template<size_t SIZE>
    struct stderr_debug : public bb_p_debug<SIZE> {
      // ...
    };

    template<>
    std::unique_ptr<bb_p_debug<8>>
    bb_p_debug<8>::create(std::string name, cxxrtl::metadata_map parameters,
                          cxxrtl::metadata_map attributes) {
      return std::make_unique<stderr_debug<8>>();
    }

The following attributes are recognized by this backend:

    cxxrtl_blackbox
        only valid on modules. if specified, the module contents are ignored,
        and the generated code includes only the module interface and a factory
        function, which will be called to instantiate the module.

    cxxrtl_edge
        only valid on inputs of black boxes. must be one of "p", "n", "a".
        if specified on signal `clk`, the generated code includes edge detectors
        `posedge_p_clk()` (if "p"), `negedge_p_clk()` (if "n"), or both (if
        "a"), simplifying implementation of clocked black boxes.

    cxxrtl_template
        only valid on black boxes. must contain a space separated sequence of
        identifiers that have a corresponding black box parameters. for each
        of them, the generated code includes a `size_t` template parameter.

    cxxrtl_width
        only valid on ports of black boxes. must be a constant expression, which
        is directly inserted into generated code.

    cxxrtl_comb, cxxrtl_sync
        only valid on outputs of black boxes. if specified, indicates that every
        bit of the output port is driven, correspondingly, by combinatorial or
        synchronous logic. this knowledge is used for scheduling optimizations.
        if neither is specified, the output will be pessimistically treated as
        driven by both combinatorial and synchronous logic.

The following options are supported by this backend:

    -print-wire-types, -print-debug-wire-types
        enable additional debug logging, for pass developers.

    -header
        generate separate interface (.h) and implementation (.cc) files.
        if specified, the backend must be called with a filename, and filename
        of the interface is derived from filename of the implementation.
        otherwise, interface and implementation are generated together.

    -namespace <ns-name>
        place the generated code into namespace <ns-name>. if not specified,
        "cxxrtl_design" is used.

    -print-output <stream>
        $print cells in the generated code direct their output to <stream>.
        must be one of "std::cout", "std::cerr". if not specified,
        "std::cout" is used. explicitly provided performer overrides this.

    -nohierarchy
        use design hierarchy as-is. in most designs, a top module should be
        present as it is exposed through the C API and has unbuffered outputs
        for improved performance; it will be determined automatically if absent.

    -noflatten
        don't flatten the design. fully flattened designs can evaluate within
        one delta cycle if they have no combinatorial feedback.
        note that the debug interface and waveform dumps use full hierarchical
        names for all wires even in flattened designs.

    -noproc
        don't convert processes to netlists. in most designs, converting
        processes significantly improves evaluation performance at the cost of
        slight increase in compilation time.

    -O <level>
        set the optimization level. the default is -O6. higher optimization
        levels dramatically decrease compile and run time, and highest level
        possible for a design should be used.

    -O0
        no optimization.

    -O1
        unbuffer internal wires if possible.

    -O2
        like -O1, and localize internal wires if possible.

    -O3
        like -O2, and inline internal wires if possible.

    -O4
        like -O3, and unbuffer public wires not marked (*keep*) if possible.

    -O5
        like -O4, and localize public wires not marked (*keep*) if possible.

    -O6
        like -O5, and inline public wires not marked (*keep*) if possible.

    -g <level>
        set the debug level. the default is -g4. higher debug levels provide
        more visibility and generate more code, but do not pessimize evaluation.

    -g0
        no debug information. the C API is disabled.

    -g1
        include bare minimum of debug information necessary to access all design
        state. the C API is enabled.

    -g2
        like -g1, but include debug information for all public wires that are
        directly accessible through the C++ interface.

    -g3
        like -g2, and include debug information for public wires that are tied
        to a constant or another public wire.

    -g4
        like -g3, and compute debug information on demand for all public wires
        that were optimized out.


    write_edif [options] [filename]

Write the current design to an EDIF netlist file.

    -top top_module
        set the specified module as design top module

    -nogndvcc
        do not create "GND" and "VCC" cells. (this will produce an error
        if the design contains constant nets. use "hilomap" to map to custom
        constant drivers first)

    -gndvccy
        create "GND" and "VCC" cells with "Y" outputs. (the default is
        "G" for "GND" and "P" for "VCC".)

    -attrprop
        create EDIF properties for cell attributes

    -keep
        create extra KEEP nets by allowing a cell to drive multiple nets.

    -pvector {par|bra|ang}
        sets the delimiting character for module port rename clauses to
        parentheses, square brackets, or angle brackets.

    -lsbidx
        use index 0 for the LSB bit of a net or port instead of MSB.

Unfortunately there are different "flavors" of the EDIF file format. This
command generates EDIF files for the Xilinx place&route tools. It might be
necessary to make small modifications to this command when a different tool
is targeted.


    write_file [options] output_file [input_file]

Write the text from the input file to the output file.

    -a
        Append to output file (instead of overwriting)


Inside a script the input file can also can a here-document:

    write_file hello.txt <<EOT
    Hello World!
    EOT


    write_firrtl [options] [filename]

Write a FIRRTL netlist of the current design.
The following commands are executed by this command:
        pmuxtree
        bmuxmap
        demuxmap
        bwmuxmap


TODO: add help message


    write_functional_rosette [options] [selection] [filename]

Functional Rosette Backend.

    -provides
        include 'provide' statement(s) for loading output as a module


Functional SMT Backend.


    write_intersynth [options] [filename]

Write the current design to an 'intersynth' netlist file. InterSynth is
a tool for Coarse-Grain Example-Driven Interconnect Synthesis.

    -notypes
        do not generate celltypes and conntypes commands. i.e. just output
        the netlists. this is used for postsilicon synthesis.

    -lib <verilog_or_rtlil_file>
        Use the specified library file for determining whether cell ports are
        inputs or outputs. This option can be used multiple times to specify
        more than one library.

    -selected
        only write selected modules. modules must be selected entirely or
        not at all.

http://bygone.clairexen.net/intersynth/


    jny [options] [selection]

Write JSON netlist metadata for the current design

    -no-connections
        Don't include connection information in the netlist output.

    -no-attributes
        Don't include attributed information in the netlist output.

    -no-properties
        Don't include property information in the netlist output.

The JSON schema for JNY output files is located in the "jny.schema.json" file
which is located at "https://raw.githubusercontent.com/YosysHQ/yosys/main/misc/jny.schema.json"


    write_json [options] [filename]

Write a JSON netlist of the current design.

    -aig
        include AIG models for the different gate types

    -compat-int
        emit 32-bit or smaller fully-defined parameter values directly
        as JSON numbers (for compatibility with old parsers)


The general syntax of the JSON output created by this command is as follows:

    {
      "creator": "Yosys <version info>",
      "modules": {
        <module_name>: {
          "attributes": {
            <attribute_name>: <attribute_value>,
            ...
          },
          "parameter_default_values": {
            <parameter_name>: <parameter_value>,
            ...
          },
          "ports": {
            <port_name>: <port_details>,
            ...
          },
          "cells": {
            <cell_name>: <cell_details>,
            ...
          },
          "memories": {
            <memory_name>: <memory_details>,
            ...
          },
          "netnames": {
            <net_name>: <net_details>,
            ...
          }
        }
      },
      "models": {
        ...
      },
    }

Where <port_details> is:

    {
      "direction": <"input" | "output" | "inout">,
      "bits": <bit_vector>
      "offset": <the lowest bit index in use, if non-0>
      "upto": <1 if the port bit indexing is MSB-first>
      "signed": <1 if the port is signed>
    }

The "offset" and "upto" fields are skipped if their value would be 0.
They don't affect connection semantics, and are only used to preserve original
HDL bit indexing.And <cell_details> is:

    {
      "hide_name": <1 | 0>,
      "type": <cell_type>,
      "model": <AIG model name, if -aig option used>,
      "parameters": {
        <parameter_name>: <parameter_value>,
        ...
      },
      "attributes": {
        <attribute_name>: <attribute_value>,
        ...
      },
      "port_directions": {
        <port_name>: <"input" | "output" | "inout">,
        ...
      },
      "connections": {
        <port_name>: <bit_vector>,
        ...
      },
    }

And <memory_details> is:

    {
      "hide_name": <1 | 0>,
      "attributes": {
        <attribute_name>: <attribute_value>,
        ...
      },
      "width": <memory width>
      "start_offset": <the lowest valid memory address>
      "size": <memory size>
    }

And <net_details> is:

    {
      "hide_name": <1 | 0>,
      "bits": <bit_vector>
      "offset": <the lowest bit index in use, if non-0>
      "upto": <1 if the port bit indexing is MSB-first>
      "signed": <1 if the port is signed>
    }

The "hide_name" fields are set to 1 when the name of this cell or net is
automatically created and is likely not of interest for a regular user.

The "port_directions" section is only included for cells for which the
interface is known.

Module and cell ports and nets can be single bit wide or vectors of multiple
bits. Each individual signal bit is assigned a unique integer. The <bit_vector>
values referenced above are vectors of this integers. Signal bits that are
connected to a constant driver are denoted as string "0", "1", "x", or
"z" instead of a number.

Bit vectors (including integers) are written as string holding the binary
representation of the value. Strings are written as strings, with an appended
blank in cases of strings of the form /[01xz]* */.

For example the following Verilog code:

    module test(input x, y);
      (* keep *) foo #(.P(42), .Q(1337))
          foo_inst (.A({x, y}), .B({y, x}), .C({4'd10, {4{x}}}));
    endmodule

Translates to the following JSON output:

    {
      "creator": "Yosys 0.9+2406 (git sha1 fb1168d8, clang 9.0.1 -fPIC -Os)",
      "modules": {
        "test": {
          "attributes": {
            "cells_not_processed": "00000000000000000000000000000001",
            "src": "test.v:1.1-4.10"
          },
          "ports": {
            "x": {
              "direction": "input",
              "bits": [ 2 ]
            },
            "y": {
              "direction": "input",
              "bits": [ 3 ]
            }
          },
          "cells": {
            "foo_inst": {
              "hide_name": 0,
              "type": "foo",
              "parameters": {
                "P": "00000000000000000000000000101010",
                "Q": "00000000000000000000010100111001"
              },
              "attributes": {
                "keep": "00000000000000000000000000000001",
                "module_not_derived": "00000000000000000000000000000001",
                "src": "test.v:3.1-3.55"
              },
              "connections": {
                "A": [ 3, 2 ],
                "B": [ 2, 3 ],
                "C": [ 2, 2, 2, 2, "0", "1", "0", "1" ]
              }
            }
          },
          "netnames": {
            "x": {
              "hide_name": 0,
              "bits": [ 2 ],
              "attributes": {
                "src": "test.v:1.19-1.20"
              }
            },
            "y": {
              "hide_name": 0,
              "bits": [ 3 ],
              "attributes": {
                "src": "test.v:1.22-1.23"
              }
            }
          }
        }
      }
    }

The models are given as And-Inverter-Graphs (AIGs) in the following form:

    "models": {
      <model_name>: [
        /*   0 */ [ <node-spec> ],
        /*   1 */ [ <node-spec> ],
        /*   2 */ [ <node-spec> ],
        ...
      ],
      ...
    },

The following node-types may be used:

    [ "port", <portname>, <bitindex>, <out-list> ]
      - the value of the specified input port bit

    [ "nport", <portname>, <bitindex>, <out-list> ]
      - the inverted value of the specified input port bit

    [ "and", <node-index>, <node-index>, <out-list> ]
      - the ANDed value of the specified nodes

    [ "nand", <node-index>, <node-index>, <out-list> ]
      - the inverted ANDed value of the specified nodes

    [ "true", <out-list> ]
      - the constant value 1

    [ "false", <out-list> ]
      - the constant value 0

All nodes appear in topological order. I.e. only nodes with smaller indices
are referenced by "and" and "nand" nodes.

The optional <out-list> at the end of a node specification is a list of
output portname and bitindex pairs, specifying the outputs driven by this node.

For example, the following is the model for a 3-input 3-output $reduce_and cell
inferred by the following code:

    module test(input [2:0] in, output [2:0] out);
      assign in = &out;
    endmodule

    "$reduce_and:3U:3": [
      /*   0 */ [ "port", "A", 0 ],
      /*   1 */ [ "port", "A", 1 ],
      /*   2 */ [ "and", 0, 1 ],
      /*   3 */ [ "port", "A", 2 ],
      /*   4 */ [ "and", 2, 3, "Y", 0 ],
      /*   5 */ [ "false", "Y", 1, "Y", 2 ]
    ]

Future version of Yosys might add support for additional fields in the JSON
format. A program processing this format must ignore all unknown fields.


    write_rtlil [filename]

Write the current design to an RTLIL file. (RTLIL is a text representation
of a design in yosys's internal format.)

    -selected
        only write selected parts of the design.


    write_simplec [options] [filename]

Write simple C code for simulating the design. The C code written can be used to
simulate the design in a C environment, but the purpose of this command is to
generate code that works well with C-based formal verification.

    -verbose
        this will print the recursive walk used to export the modules.

    -i8, -i16, -i32, -i64
        set the maximum integer bit width to use in the generated code.

THIS COMMAND IS UNDER CONSTRUCTION


    write_smt2 [options] [filename]

Write a SMT-LIBv2 [1] description of the current design. For a module with name
'<mod>' this will declare the sort '<mod>_s' (state of the module) and will
define and declare functions operating on that state.

The following SMT2 functions are generated for a module with name '<mod>'.
Some declarations/definitions are printed with a special comment. A prover
using the SMT2 files can use those comments to collect all relevant metadata
about the design.

    ; yosys-smt2-module <mod>
    (declare-sort |<mod>_s| 0)
        The sort representing a state of module <mod>.

    (define-fun |<mod>_h| ((state |<mod>_s|)) Bool (...))
        This function must be asserted for each state to establish the
        design hierarchy.

    ; yosys-smt2-input <wirename> <width>
    ; yosys-smt2-output <wirename> <width>
    ; yosys-smt2-register <wirename> <width>
    ; yosys-smt2-wire <wirename> <width>
    (define-fun |<mod>_n <wirename>| (|<mod>_s|) (_ BitVec <width>))
    (define-fun |<mod>_n <wirename>| (|<mod>_s|) Bool)
        For each port, register, and wire with the 'keep' attribute set an
        accessor function is generated. Single-bit wires are returned as Bool,
        multi-bit wires as BitVec.

    ; yosys-smt2-cell <submod> <instancename>
    (declare-fun |<mod>_h <instancename>| (|<mod>_s|) |<submod>_s|)
        There is a function like that for each hierarchical instance. It
        returns the sort that represents the state of the sub-module that
        implements the instance.

    (declare-fun |<mod>_is| (|<mod>_s|) Bool)
        This function must be asserted 'true' for initial states, and 'false'
        otherwise.

    (define-fun |<mod>_i| ((state |<mod>_s|)) Bool (...))
        This function must be asserted 'true' for initial states. For
        non-initial states it must be left unconstrained.

    (define-fun |<mod>_t| ((state |<mod>_s|) (next_state |<mod>_s|)) Bool (...))
        This function evaluates to 'true' if the states 'state' and
        'next_state' form a valid state transition.

    (define-fun |<mod>_a| ((state |<mod>_s|)) Bool (...))
        This function evaluates to 'true' if all assertions hold in the state.

    (define-fun |<mod>_u| ((state |<mod>_s|)) Bool (...))
        This function evaluates to 'true' if all assumptions hold in the state.

    ; yosys-smt2-assert <id> <filename:linenum>
    (define-fun |<mod>_a <id>| ((state |<mod>_s|)) Bool (...))
        Each $assert cell is converted into one of this functions. The function
        evaluates to 'true' if the assert statement holds in the state.

    ; yosys-smt2-assume <id> <filename:linenum>
    (define-fun |<mod>_u <id>| ((state |<mod>_s|)) Bool (...))
        Each $assume cell is converted into one of this functions. The function
        evaluates to 'true' if the assume statement holds in the state.

    ; yosys-smt2-cover <id> <filename:linenum>
    (define-fun |<mod>_c <id>| ((state |<mod>_s|)) Bool (...))
        Each $cover cell is converted into one of this functions. The function
        evaluates to 'true' if the cover statement is activated in the state.

Options:

    -verbose
        this will print the recursive walk used to export the modules.

    -stbv
        Use a BitVec sort to represent a state instead of an uninterpreted
        sort. As a side-effect this will prevent use of arrays to model
        memories.

    -stdt
        Use SMT-LIB 2.6 style datatypes to represent a state instead of an
        uninterpreted sort.

    -nobv
        disable support for BitVec (FixedSizeBitVectors theory). without this
        option multi-bit wires are represented using the BitVec sort and
        support for coarse grain cells (incl. arithmetic) is enabled.

    -nomem
        disable support for memories (via ArraysEx theory). this option is
        implied by -nobv. only $mem cells without merged registers in
        read ports are supported. call "memory" with -nordff to make sure
        that no registers are merged into $mem read ports. '<mod>_m' functions
        will be generated for accessing the arrays that are used to represent
        memories.

    -wires
        create '<mod>_n' functions for all public wires. by default only ports,
        registers, and wires with the 'keep' attribute are exported.

    -tpl <template_file>
        use the given template file. the line containing only the token '%%'
        is replaced with the regular output of this command.

    -solver-option <option> <value>
        emit a `; yosys-smt2-solver-option` directive for yosys-smtbmc to write
        the given option as a `(set-option ...)` command in the SMT-LIBv2.

[1] For more information on SMT-LIBv2 visit http://smt-lib.org/ or read David
R. Cok's tutorial: https://smtlib.github.io/jSMTLIB/SMTLIBTutorial.pdf

---------------------------------------------------------------------------

Example:

Consider the following module (test.v). We want to prove that the output can
never transition from a non-zero value to a zero value.

        module test(input clk, output reg [3:0] y);
          always @(posedge clk)
            y <= (y << 1) | ^y;
        endmodule

For this proof we create the following template (test.tpl).

        ; we need QF_UFBV for this proof
        (set-logic QF_UFBV)

        ; insert the auto-generated code here
        %%

        ; declare two state variables s1 and s2
        (declare-fun s1 () test_s)
        (declare-fun s2 () test_s)

        ; state s2 is the successor of state s1
        (assert (test_t s1 s2))

        ; we are looking for a model with y non-zero in s1
        (assert (distinct (|test_n y| s1) #b0000))

        ; we are looking for a model with y zero in s2
        (assert (= (|test_n y| s2) #b0000))

        ; is there such a model?
        (check-sat)

The following yosys script will create a 'test.smt2' file for our proof:

        read_verilog test.v
        hierarchy -check; proc; opt; check -assert
        write_smt2 -bv -tpl test.tpl test.smt2

Running 'cvc4 test.smt2' will print 'unsat' because y can never transition
from non-zero to zero in the test design.


    write_smv [options] [filename]

Write an SMV description of the current design.

    -verbose
        this will print the recursive walk used to export the modules.

    -tpl <template_file>
        use the given template file. the line containing only the token '%%'
        is replaced with the regular output of this command.

THIS COMMAND IS UNDER CONSTRUCTION


    write_spice [options] [filename]

Write the current design to an SPICE netlist file.

    -big_endian
        generate multi-bit ports in MSB first order
        (default is LSB first)

    -neg net_name
        set the net name for constant 0 (default: Vss)

    -pos net_name
        set the net name for constant 1 (default: Vdd)

    -buf DC|subckt_name
        set the name for jumper element (default: DC)
        (used to connect different nets)

    -nc_prefix
        prefix for not-connected nets (default: _NC)

    -inames
        include names of internal ($-prefixed) nets in outputs
        (default is to use net numbers instead)

    -top top_module
        set the specified module as design top module


    write_table [options] [filename]

Write the current design as connectivity table. The output is a tab-separated
ASCII table with the following columns:

  module name
  cell name
  cell type
  cell port
  direction
  signal

module inputs and outputs are output using cell type and port '-' and with
'pi' (primary input) or 'po' (primary output) or 'pio' as direction.

    write_verilog [options] [filename]

Write the current design to a Verilog file.

    -sv
        with this option, SystemVerilog constructs like always_comb are used

    -norename
        without this option all internal object names (the ones with a dollar
        instead of a backslash prefix) are changed to short names in the
        format '_<number>_'.

    -renameprefix <prefix>
        insert this prefix in front of auto-generated instance names

    -noattr
        with this option no attributes are included in the output

    -attr2comment
        with this option attributes are included as comments in the output

    -noexpr
        without this option all internal cells are converted to Verilog
        expressions.

    -noparallelcase
        With this option no parallel_case attributes are used. Instead, a case
        statement that assigns don't-care values for priority dependent inputs
        is generated.

    -siminit
        add initial statements with hierarchical refs to initialize FFs when
        in -noexpr mode.

    -nodec
        32-bit constant values are by default dumped as decimal numbers,
        not bit pattern. This option deactivates this feature and instead
        will write out all constants in binary.

    -decimal
        dump 32-bit constants in decimal and without size and radix

    -nohex
        constant values that are compatible with hex output are usually
        dumped as hex values. This option deactivates this feature and
        instead will write out all constants in binary.

    -nostr
        Parameters and attributes that are specified as strings in the
        original input will be output as strings by this back-end. This
        deactivates this feature and instead will write string constants
        as binary numbers.

    -simple-lhs
        Connection assignments with simple left hand side without
        concatenations.

    -extmem
        instead of initializing memories using assignments to individual
        elements, use the '$readmemh' function to read initialization data
        from a file. This data is written to a file named by appending
        a sequential index to the Verilog filename and replacing the extension
        with '.mem', e.g. 'write_verilog -extmem foo.v' writes 'foo-1.mem',
        'foo-2.mem' and so on.

    -defparam
        use 'defparam' statements instead of the Verilog-2001 syntax for
        cell parameters.

    -blackboxes
        usually modules with the 'blackbox' attribute are ignored. with
        this option set only the modules with the 'blackbox' attribute
        are written to the output file.

    -selected
        only write selected modules. modules must be selected entirely or
        not at all.

    -v
        verbose output (print new names of all renamed wires and cells)

Note that RTLIL processes can't always be mapped directly to Verilog
always blocks. This frontend should only be used to export an RTLIL
netlist, i.e. after the "proc" pass has been used to convert all
processes to logic networks and registers. A warning is generated when
this command is called on a design with RTLIL processes.


    write_xaiger [options] [filename]

Write the top module (according to the (* top *) attribute or if only one module
is currently selected) to an XAIGER file. Any non $_NOT_, $_AND_, (optionally
$_DFF_N_, $_DFF_P_), or non (* abc9_box *) cells will be converted into psuedo-
inputs and pseudo-outputs. Whitebox contents will be taken from the equivalent
module in the '$abc9_holes' design, if it exists.

    -ascii
        write ASCII version of AIGER format

    -map <filename>
        write an extra file with port and box symbols

    -dff
        write $_DFF_[NP]_ cells


    write_xaiger2 [options] [filename]

Write the selected module to a XAIGER file including the 'h' and 'a' extensions
with box information for ABC.

    -strash
        perform structural hashing while writing

    -flatten
        allow descending into submodules and write a flattened view of the design
        hierarchy starting at the selected top

    -mapping_prep
        after the file is written, prepare the module for reintegration of
        a mapping in a subsequent command. all cells which are not blackboxed nor
        whiteboxed are removed from the design as well as all wires which only
        connect to removed cells
        (conflicts with -flatten)

    -map2 <file>
        write a map2 file which 'read_xaiger2 -sc_mapping' can read to
        reintegrate a mapping
        (conflicts with -flatten)


WARNING: THE 'write_xaiger2' COMMAND IS EXPERIMENTAL.


    xilinx_dffopt [options] [selection]

Converts hardware clock enable and set/reset signals on FFs to emulation
using LUTs, if doing so would improve area.  Operates on post-techmap Xilinx
cells (LUT*, FD*).

    -lut4
        Assume a LUT4-based device (instead of a LUT6-based device).


    xilinx_dsp [options] [selection]

Pack input registers (A2, A1, B2, B1, C, D, AD; with optional enable/reset),
pipeline registers (M; with optional enable/reset), output registers (P; with
optional enable/reset), pre-adder and/or post-adder into Xilinx DSP resources.

Multiply-accumulate operations using the post-adder with feedback on the 'C'
input will be folded into the DSP. In this scenario only, the 'C' input can be
used to override the current accumulation result with a new value, which will
be added to the multiplier result to form the next accumulation result.

Use of the dedicated 'PCOUT' -> 'PCIN' cascade path is detected for 'P' -> 'C'
connections (optionally, where 'P' is right-shifted by 17-bits and used as an
input to the post-adder -- a pattern common for summing partial products to
implement wide multipliers). Limited support also exists for similar cascading
for A and B using '[AB]COUT' -> '[AB]CIN'. Currently, cascade chains are limited
to a maximum length of 20 cells, corresponding to the smallest Xilinx 7 Series
device.

This pass is a no-op if the scratchpad variable 'xilinx_dsp.multonly' is set
to 1.


Experimental feature: addition/subtractions less than 12 or 24 bits with the
'(* use_dsp="simd" *)' attribute attached to the output wire or attached to
the add/subtract operator will cause those operations to be implemented using
the 'SIMD' feature of DSPs.

Experimental feature: the presence of a `$ge' cell attached to the registered
P output implementing the operation "(P >= <power-of-2>)" will be transformed
into using the DSP48E1's pattern detector feature for overflow detection.

    -family {xcup|xcu|xc7|xc6v|xc5v|xc4v|xc6s|xc3sda}
        select the family to target
        default: xc7


    xilinx_srl [options] [selection]

This pass converts chains of built-in flops (bit-level: $_DFF_[NP]_, $_DFFE_*
and word-level: $dff, $dffe) as well as Xilinx flops (FDRE, FDRE_1) into a
$__XILINX_SHREG cell. Chains must be of the same cell type, clock, clock
polarity, enable, and enable polarity (where relevant).
Flops with resets cannot be mapped to Xilinx devices and will not be inferred.

    -minlen N
        min length of shift register (default = 3)

    -fixed
        infer fixed-length shift registers.

    -variable
        infer variable-length shift registers (i.e. fixed-length shifts where
        each element also fans-out to a $shiftx cell).


    xprop [options] [selection]

This pass transforms the circuit into an equivalent circuit that explicitly
encodes the propagation of x values using purely 2-valued logic. On the
interface between xprop-transformed and non-transformed parts of the design,
appropriate conversions are inserted automatically.

    -split-inputs
    -split-outputs
    -split-ports
        Replace each input/output/port with two new ports, one carrying the
        defined values (named <portname>_d) and one carrying the mask of which
        bits are x (named <portname>_x). When a bit in the <portname>_x is set
        the corresponding bit in <portname>_d is ignored for inputs and
        guaranteed to be 0 for outputs.

    -split-public
        Replace each public non-port wire with two new wires, one carrying the
        defined values (named <wirename>_d) and one carrying the mask of which
        bits are x (named <wirename>_x). When a bit in the <portname>_x is set
        the corresponding bit in <wirename>_d is guaranteed to be 0 for
        outputs.

    -assume-encoding
        Add encoding invariants as assumptions. This can speed up formal
        verification tasks.

    -assert-encoding
        Add encoding invariants as assertions. Used for testing the xprop
        pass itself.

    -assume-def-inputs
        Assume all inputs are fully defined. This adds corresponding
        assumptions to the design and uses these assumptions to optimize the
        xprop encoding.

    -required
        Produce a runtime error if any encountered cell could not be encoded.

    -formal
        Produce a runtime error if any encoded cell uses a signal that is
		 neither known to be non-x nor driven by another encoded cell.

    -debug-asserts
        Add assertions checking that the encoding used by this pass never
        produces x values within the encoded signals.


    zinit [options] [selection]

Add inverters as needed to make all FFs zero-initialized.

    -all
        also add zero initialization to uninitialized FFs

End of script. Logfile hash: a7e7bc8a41, CPU: user 0.01s system 0.01s, MEM: 15.84 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 100% 1x help (0 sec)

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `help -dump-cells-json docs/source/generated/cells.json' --

End of script. Logfile hash: 435b0c1a21, CPU: user 0.00s system 0.00s, MEM: 15.84 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 100% 1x help (0 sec)
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs'
make examples
make[2]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs'
make -C source/code_examples/extensions examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/extensions'
../../../../yosys-config --exec --cxx -O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1 -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -Wall -Wextra -ggdb -I/usr/include/yosys -MD -MP -D_YOSYS_ -fPIC -I/usr/include -std=c++17 -O3 -DYOSYS_ENABLE_READLINE -DYOSYS_ENABLE_PLUGINS -DYOSYS_ENABLE_GLOB -DYOSYS_ENABLE_ZLIB -DWITH_GZFILEOP -DYOSYS_ENABLE_TCL -DYOSYS_ENABLE_ABC -DYOSYS_ENABLE_COVER -I../../../../ --ldflags -o my_cmd.so -shared my_cmd.cc --ldlibs
../../../../yosys -QTl test0.log_new -m ./my_cmd.so -p 'my_cmd foo bar' -f verilog absval_ref.v

-- Parsing `absval_ref.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend: absval_ref.v
Parsing Verilog input from `absval_ref.v' to AST representation.
Generating RTLIL representation for module `\absval_ref'.
Successfully finished Verilog frontend.

-- Running command `my_cmd foo bar' --
Arguments to my_cmd:
  my_cmd
  foo
  bar
Modules in current design:
  absval_ref (4 wires, 2 cells)
mv test0.log_new test0.log
../../../../yosys -QTl test1.log_new -m ./my_cmd.so -p 'clean; test1; dump' -f verilog absval_ref.v

-- Parsing `absval_ref.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend: absval_ref.v
Parsing Verilog input from `absval_ref.v' to AST representation.
Generating RTLIL representation for module `\absval_ref'.
Successfully finished Verilog frontend.

-- Running command `clean; test1; dump' --
Removed 0 unused cells and 1 unused wires.
Name of this module: absval

autoidx 6

module \absval

  wire width 4 $auto$my_cmd.cc:41:execute$3

  wire width 4 output 2 \y

  wire width 4 input 1 \a

  cell $mux $auto$my_cmd.cc:43:execute$5
    parameter \WIDTH 4
    connect \Y \y
    connect \S \a [3]
    connect \B $auto$my_cmd.cc:41:execute$3
    connect \A \a
  end

  cell $neg $auto$my_cmd.cc:42:execute$4
    parameter \Y_WIDTH 4
    parameter \A_WIDTH 4
    parameter \A_SIGNED 1
    connect \Y $auto$my_cmd.cc:41:execute$3
    connect \A \a
  end
end

attribute \cells_not_processed 1
attribute \src "absval_ref.v:1.1-3.10"
module \absval_ref

  attribute \src "absval_ref.v:2.20-2.22"
  wire width 4 signed $neg$absval_ref.v:2$1_Y

  attribute \src "absval_ref.v:1.38-1.39"
  wire width 4 input 1 signed \a

  attribute \src "absval_ref.v:1.54-1.55"
  wire width 4 output 2 \y

  attribute \src "absval_ref.v:2.20-2.22"
  cell $neg $neg$absval_ref.v:2$1
    parameter \A_SIGNED 1
    parameter \A_WIDTH 4
    parameter \Y_WIDTH 4
    connect \A \a
    connect \Y $neg$absval_ref.v:2$1_Y
  end

  attribute \src "absval_ref.v:2.13-2.26"
  cell $mux $ternary$absval_ref.v:2$2
    parameter \WIDTH 4
    connect \A \a
    connect \B $neg$absval_ref.v:2$1_Y
    connect \S \a [3]
    connect \Y \y
  end
end
mv test1.log_new test1.log
../../../../yosys -QTl test2.log_new -m ./my_cmd.so -p 'hierarchy -top test; test2' -f verilog sigmap_test.v

-- Parsing `sigmap_test.v' using frontend `verilog' --

1. Executing Verilog-2005 frontend: sigmap_test.v
Parsing Verilog input from `sigmap_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

-- Running command `hierarchy -top test; test2' --

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.
0 0 0
1 1 1
Mapped signal x: \a

3. Doing important stuff!
Log message #0.
Log message #1.
Log message #2.
Log message #3.
Log message #4.
Log message #5.
Log message #6.
Log message #7.
Log message #8.
Log message #9.
mv test2.log_new test2.log
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/extensions'
make -C source/code_examples/fifo examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/fifo'
../../../../yosys fifo.ys -l fifo.out -Q -T

-- Executing script file `fifo.ys' --
$ yosys fifo.v

-- Parsing `fifo.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: fifo.v
Parsing Verilog input from `fifo.v' to AST representation.
Storing AST representation for module `$abstract\addr_gen'.
Storing AST representation for module `$abstract\fifo'.
Successfully finished Verilog frontend.
echo on

yosys> hierarchy -top addr_gen

2. Executing HIERARCHY pass (managing design hierarchy).

3. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
Generating RTLIL representation for module `\addr_gen'.

3.1. Analyzing design hierarchy..
Top module:  \addr_gen

3.2. Analyzing design hierarchy..
Top module:  \addr_gen
Removing unused module `$abstract\fifo'.
Removing unused module `$abstract\addr_gen'.
Removed 2 unused modules.

yosys> select -module addr_gen

yosys [addr_gen]> select -list
addr_gen
addr_gen/$1\addr[7:0]
addr_gen/$add$fifo.v:19$3_Y
addr_gen/$eq$fifo.v:16$2_Y
addr_gen/$0\addr[7:0]
addr_gen/addr
addr_gen/rst
addr_gen/clk
addr_gen/en
addr_gen/$add$fifo.v:19$3
addr_gen/$eq$fifo.v:16$2
addr_gen/$proc$fifo.v:0$4
addr_gen/$proc$fifo.v:12$1

yosys [addr_gen]> select t:*

yosys [addr_gen]*> select -list
addr_gen/$add$fifo.v:19$3
addr_gen/$eq$fifo.v:16$2

yosys [addr_gen]*> select -set new_cells %

yosys [addr_gen]*> select -clear

yosys> show -format dot -prefix addr_gen_show addr_gen

4. Generating Graphviz representation of design.
Writing dot description to `addr_gen_show.dot'.
Dumping module addr_gen to page 1.

yosys> show -format dot -prefix new_cells_show -notitle @new_cells

5. Generating Graphviz representation of design.
Writing dot description to `new_cells_show.dot'.
Dumping selected parts of module addr_gen to page 1.

yosys> show -color maroon3 @new_cells -color cornflowerblue p:* -notitle -format dot -prefix addr_gen_hier

6. Generating Graphviz representation of design.
Writing dot description to `addr_gen_hier.dot'.
Dumping module addr_gen to page 1.

yosys> proc -noopt

7. Executing PROC pass (convert processes to netlists).

yosys> proc_clean

7.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

yosys> proc_rmdead

7.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 2 switch rules as full_case in process $proc$fifo.v:12$1 in module addr_gen.
Removed a total of 0 dead cases.

yosys> proc_prune

7.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 1 assignment to connection.

yosys> proc_init

7.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\addr_gen.$proc$fifo.v:0$4'.
  Set init value: \addr = 8'00000000

yosys> proc_arst

7.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst in `\addr_gen.$proc$fifo.v:12$1'.

yosys> proc_rom

7.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~2 debug messages>

yosys> proc_mux

7.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\addr_gen.$proc$fifo.v:0$4'.
Creating decoders for process `\addr_gen.$proc$fifo.v:12$1'.
     1/1: $0\addr[7:0]

yosys> proc_dlatch

7.8. Executing PROC_DLATCH pass (convert process syncs to latches).

yosys> proc_dff

7.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\addr_gen.\addr' using process `\addr_gen.$proc$fifo.v:12$1'.
  created $adff cell `$procdff$12' with positive edge clock and positive level reset.

yosys> proc_memwr

7.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

yosys> proc_clean

7.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `addr_gen.$proc$fifo.v:0$4'.
Found and cleaned up 2 empty switches in `\addr_gen.$proc$fifo.v:12$1'.
Removing empty process `addr_gen.$proc$fifo.v:12$1'.
Cleaned up 2 empty switches.

yosys> select -set new_cells t:$mux t:*dff

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix addr_gen_proc

8. Generating Graphviz representation of design.
Writing dot description to `addr_gen_proc.dot'.
Dumping module addr_gen to page 1.

yosys> opt_expr

9. Executing OPT_EXPR pass (perform const folding).
Optimizing module addr_gen.
<suppressed ~1 debug messages>

yosys> clean
Removed 0 unused cells and 5 unused wires.

yosys> select -set new_cells t:$eq

yosys> show -color cornflowerblue @new_cells -notitle -format dot -prefix addr_gen_clean

10. Generating Graphviz representation of design.
Writing dot description to `addr_gen_clean.dot'.
Dumping module addr_gen to page 1.

yosys> design -reset

yosys> read_verilog fifo.v

11. Executing Verilog-2005 frontend: fifo.v
Parsing Verilog input from `fifo.v' to AST representation.
Generating RTLIL representation for module `\addr_gen'.
Generating RTLIL representation for module `\fifo'.
Successfully finished Verilog frontend.

yosys> hierarchy -check -top fifo

12. Executing HIERARCHY pass (managing design hierarchy).

12.1. Analyzing design hierarchy..
Top module:  \fifo
Used module:     \addr_gen
Parameter \MAX_DATA = 256

12.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
Parameter \MAX_DATA = 256
Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
Parameter \MAX_DATA = 256
Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.

12.3. Analyzing design hierarchy..
Top module:  \fifo
Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000

12.4. Analyzing design hierarchy..
Top module:  \fifo
Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
Removing unused module `\addr_gen'.
Removed 1 unused modules.

yosys> proc

13. Executing PROC pass (convert processes to netlists).

yosys> proc_clean

13.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

yosys> proc_rmdead

13.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 2 switch rules as full_case in process $proc$fifo.v:62$26 in module fifo.
Marked 1 switch rules as full_case in process $proc$fifo.v:36$18 in module fifo.
Marked 2 switch rules as full_case in process $proc$fifo.v:12$34 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
Removed a total of 0 dead cases.

yosys> proc_prune

13.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 6 assignments to connections.

yosys> proc_init

13.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\fifo.$proc$fifo.v:0$33'.
  Set init value: \count = 9'000000000
Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$37'.
  Set init value: \addr = 8'00000000

yosys> proc_arst

13.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst in `\fifo.$proc$fifo.v:62$26'.
Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$34'.

yosys> proc_rom

13.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~5 debug messages>

yosys> proc_mux

13.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\fifo.$proc$fifo.v:0$33'.
Creating decoders for process `\fifo.$proc$fifo.v:62$26'.
     1/1: $0\count[8:0]
Creating decoders for process `\fifo.$proc$fifo.v:36$18'.
     1/3: $1$memwr$\data$fifo.v:38$17_EN[7:0]$24
     2/3: $1$memwr$\data$fifo.v:38$17_DATA[7:0]$23
     3/3: $1$memwr$\data$fifo.v:38$17_ADDR[7:0]$22
Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$37'.
Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$34'.
     1/1: $0\addr[7:0]

yosys> proc_dlatch

13.8. Executing PROC_DLATCH pass (convert process syncs to latches).

yosys> proc_dff

13.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:62$26'.
  created $adff cell `$procdff$59' with positive edge clock and positive level reset.
Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:36$18'.
  created $dff cell `$procdff$60' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$17_ADDR' using process `\fifo.$proc$fifo.v:36$18'.
  created $dff cell `$procdff$61' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$17_DATA' using process `\fifo.$proc$fifo.v:36$18'.
  created $dff cell `$procdff$62' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$17_EN' using process `\fifo.$proc$fifo.v:36$18'.
  created $dff cell `$procdff$63' with positive edge clock.
Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$34'.
  created $adff cell `$procdff$66' with positive edge clock and positive level reset.

yosys> proc_memwr

13.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

yosys> proc_clean

13.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `fifo.$proc$fifo.v:0$33'.
Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:62$26'.
Removing empty process `fifo.$proc$fifo.v:62$26'.
Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:36$18'.
Removing empty process `fifo.$proc$fifo.v:36$18'.
Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$37'.
Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$34'.
Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$34'.
Cleaned up 5 empty switches.

yosys> opt_expr -keepdc

13.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~1 debug messages>
Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
<suppressed ~1 debug messages>

yosys> select -set new_cells t:$memrd

yosys> show -color maroon3 c:fifo_reader -color cornflowerblue @new_cells -notitle -format dot -prefix rdata_proc o:rdata %ci*

14. Generating Graphviz representation of design.
Writing dot description to `rdata_proc.dot'.
Dumping selected parts of module fifo to page 1.

yosys> flatten

15. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
<suppressed ~2 debug messages>

yosys> clean
Removed 3 unused cells and 28 unused wires.

yosys> select -set rdata_path o:rdata %ci*

yosys> select -set new_cells @rdata_path o:rdata %ci3 %d i:* %d

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_flat @rdata_path

16. Generating Graphviz representation of design.
Writing dot description to `rdata_flat.dot'.
Dumping selected parts of module fifo to page 1.

yosys> opt_dff

17. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$59 ($adff) from module fifo (D = $0\count[8:0], Q = \count).
Adding EN signal on $flatten\fifo_writer.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$53_Y, Q = \fifo_writer.addr).
Adding EN signal on $flatten\fifo_reader.$procdff$66 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$53_Y, Q = \fifo_reader.addr).

yosys> select -set new_cells t:$adffe

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_adffe o:rdata %ci*

18. Generating Graphviz representation of design.
Writing dot description to `rdata_adffe.dot'.
Dumping selected parts of module fifo to page 1.

yosys> wreduce

19. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$29 ($add).
Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$29 ($add).
Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$32 ($sub).
Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$32 ($sub).
Removed top 1 bits (of 2) from port B of cell fifo.$auto$opt_dff.cc:195:make_patterns_logic$72 ($ne).
Removed cell fifo.$flatten\fifo_writer.$procmux$55 ($mux).
Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add).
Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$36 ($add).
Removed cell fifo.$flatten\fifo_reader.$procmux$55 ($mux).
Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add).
Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$36 ($add).
Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$29_Y.
Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_reader.$add$fifo.v:19$36_Y.
Removed top 24 bits (of 32) from wire fifo.$flatten\fifo_writer.$add$fifo.v:19$36_Y.

yosys> show -notitle -format dot -prefix rdata_wreduce o:rdata %ci*

20. Generating Graphviz representation of design.
Writing dot description to `rdata_wreduce.dot'.
Dumping selected parts of module fifo to page 1.

yosys> opt_clean

21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>

yosys> memory_dff

22. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\data'[0] in module `\fifo': merging output FF to cell.
    Write port 0: non-transparent.

yosys> select -set new_cells t:$memrd_v2

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_memrdv2 o:rdata %ci*

23. Generating Graphviz representation of design.
Writing dot description to `rdata_memrdv2.dot'.
Dumping selected parts of module fifo to page 1.

yosys> alumacc

24. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module fifo:
  creating $macc model for $add$fifo.v:66$29 ($add).
  creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$36 ($add).
  creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$36 ($add).
  creating $macc model for $sub$fifo.v:68$32 ($sub).
  creating $alu model for $macc $sub$fifo.v:68$32.
  creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$36.
  creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$36.
  creating $alu model for $macc $add$fifo.v:66$29.
  creating $alu cell for $add$fifo.v:66$29: $auto$alumacc.cc:485:replace_alu$87
  creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$36: $auto$alumacc.cc:485:replace_alu$90
  creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$36: $auto$alumacc.cc:485:replace_alu$93
  creating $alu cell for $sub$fifo.v:68$32: $auto$alumacc.cc:485:replace_alu$96
  created 4 $alu and 0 $macc cells.

yosys> select -set new_cells t:$alu t:$macc

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_alumacc o:rdata %ci*

25. Generating Graphviz representation of design.
Writing dot description to `rdata_alumacc.dot'.
Dumping selected parts of module fifo to page 1.

yosys> memory_collect

26. Executing MEMORY_COLLECT pass (generating $mem cells).

yosys> select -set new_cells t:$mem_v2

yosys> select -set rdata_path @new_cells %ci*:-$mem_v2[WR_DATA,WR_ADDR,WR_EN] @new_cells %co* %%

yosys> show -color maroon3 @new_cells -notitle -format dot -prefix rdata_coarse @rdata_path

27. Generating Graphviz representation of design.
Writing dot description to `rdata_coarse.dot'.
Dumping selected parts of module fifo to page 1.
../../../../yosys fifo_map.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `fifo_map.ys' --

1. Executing Verilog-2005 frontend: fifo.v
Parsing Verilog input from `fifo.v' to AST representation.
Generating RTLIL representation for module `\addr_gen'.
Generating RTLIL representation for module `\fifo'.
Successfully finished Verilog frontend.
echo on

yosys> tee -o fifo.stat stat

yosys> stat

2. Printing statistics.

=== fifo ===

   Number of wires:                 28
   Number of wire bits:            219
   Number of public wires:           9
   Number of public wire bits:      45
   Number of ports:                  7
   Number of port bits:             29
   Number of memories:               1
   Number of memory bits:         2048
   Number of processes:              3
   Number of cells:                  9
     $add                            1
     $logic_and                      2
     $logic_not                      2
     $memrd                          1
     $sub                            1
     addr_gen                        2

=== addr_gen ===

   Number of wires:                  8
   Number of wire bits:             60
   Number of public wires:           4
   Number of public wire bits:      11
   Number of ports:                  4
   Number of port bits:             11
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              2
   Number of cells:                  2
     $add                            1
     $eq                             1


yosys> echo off
echo off

3. Executing SYNTH_ICE40 pass.

3.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

3.2. Executing HIERARCHY pass (managing design hierarchy).

3.2.1. Analyzing design hierarchy..
Top module:  \fifo
Used module:     \addr_gen
Parameter \MAX_DATA = 256

3.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\addr_gen'.
Parameter \MAX_DATA = 256
Generating RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.
Parameter \MAX_DATA = 256
Found cached RTLIL representation for module `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000'.

3.2.3. Analyzing design hierarchy..
Top module:  \fifo
Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000

3.2.4. Analyzing design hierarchy..
Top module:  \fifo
Used module:     $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000
Removing unused module `\addr_gen'.
Removed 1 unused modules.

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1353$255 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1212$244 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1138$241 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1088$238 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1017$235 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:967$232 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:742$217 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:601$206 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:527$203 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:477$200 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:406$197 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:356$194 in module SB_DFFSR.
Marked 2 switch rules as full_case in process $proc$fifo.v:62$14 in module fifo.
Marked 1 switch rules as full_case in process $proc$fifo.v:36$6 in module fifo.
Marked 2 switch rules as full_case in process $proc$fifo.v:12$402 in module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 8 redundant assignments.
Promoted 28 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$265'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$261'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$254'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$250'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$243'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$240'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$237'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$234'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$231'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$229'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$227'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$223'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$216'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$212'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$205'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$202'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$199'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$196'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$193'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$191'.
  Set init value: \Q = 1'0
Found init rule in `\fifo.$proc$fifo.v:0$21'.
  Set init value: \count = 9'000000000
Found init rule in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$405'.
  Set init value: \addr = 8'00000000

3.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \S in `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262'.
Found async reset \R in `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251'.
Found async reset \S in `\SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1138$241'.
Found async reset \R in `\SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1017$235'.
Found async reset \S in `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224'.
Found async reset \R in `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213'.
Found async reset \S in `\SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:527$203'.
Found async reset \R in `\SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:406$197'.
Found async reset \rst in `\fifo.$proc$fifo.v:62$14'.
Found async reset \rst in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$402'.

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~23 debug messages>

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$265'.
Creating decoders for process `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$261'.
Creating decoders for process `\SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1353$255'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$254'.
Creating decoders for process `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$250'.
Creating decoders for process `\SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1212$244'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$243'.
Creating decoders for process `\SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1138$241'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$240'.
Creating decoders for process `\SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1088$238'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$237'.
Creating decoders for process `\SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1017$235'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$234'.
Creating decoders for process `\SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:967$232'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$231'.
Creating decoders for process `\SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:922$230'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$229'.
Creating decoders for process `\SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:882$228'.
Creating decoders for process `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$227'.
Creating decoders for process `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$223'.
Creating decoders for process `\SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:742$217'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$216'.
Creating decoders for process `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$212'.
Creating decoders for process `\SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:601$206'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$205'.
Creating decoders for process `\SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:527$203'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$202'.
Creating decoders for process `\SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:477$200'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$199'.
Creating decoders for process `\SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:406$197'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$196'.
Creating decoders for process `\SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:356$194'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$193'.
Creating decoders for process `\SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:311$192'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$191'.
Creating decoders for process `\SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:271$190'.
Creating decoders for process `\fifo.$proc$fifo.v:0$21'.
Creating decoders for process `\fifo.$proc$fifo.v:62$14'.
     1/1: $0\count[8:0]
Creating decoders for process `\fifo.$proc$fifo.v:36$6'.
     1/3: $1$memwr$\data$fifo.v:38$5_EN[7:0]$12
     2/3: $1$memwr$\data$fifo.v:38$5_DATA[7:0]$11
     3/3: $1$memwr$\data$fifo.v:38$5_ADDR[7:0]$10
Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$405'.
Creating decoders for process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$402'.
     1/1: $0\addr[7:0]

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262'.
  created $adff cell `$procdff$471' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1353$255'.
  created $dff cell `$procdff$472' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251'.
  created $adff cell `$procdff$475' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1212$244'.
  created $dff cell `$procdff$476' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1138$241'.
  created $adff cell `$procdff$479' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1088$238'.
  created $dff cell `$procdff$480' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1017$235'.
  created $adff cell `$procdff$483' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:967$232'.
  created $dff cell `$procdff$484' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:922$230'.
  created $dff cell `$procdff$485' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:882$228'.
  created $dff cell `$procdff$486' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224'.
  created $adff cell `$procdff$489' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:742$217'.
  created $dff cell `$procdff$490' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213'.
  created $adff cell `$procdff$493' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:601$206'.
  created $dff cell `$procdff$494' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:527$203'.
  created $adff cell `$procdff$497' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:477$200'.
  created $dff cell `$procdff$498' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:406$197'.
  created $adff cell `$procdff$501' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:356$194'.
  created $dff cell `$procdff$502' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:311$192'.
  created $dff cell `$procdff$503' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:271$190'.
  created $dff cell `$procdff$504' with positive edge clock.
Creating register for signal `\fifo.\count' using process `\fifo.$proc$fifo.v:62$14'.
  created $adff cell `$procdff$507' with positive edge clock and positive level reset.
Creating register for signal `\fifo.\rdata' using process `\fifo.$proc$fifo.v:36$6'.
  created $dff cell `$procdff$508' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$5_ADDR' using process `\fifo.$proc$fifo.v:36$6'.
  created $dff cell `$procdff$509' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$5_DATA' using process `\fifo.$proc$fifo.v:36$6'.
  created $dff cell `$procdff$510' with positive edge clock.
Creating register for signal `\fifo.$memwr$\data$fifo.v:38$5_EN' using process `\fifo.$proc$fifo.v:36$6'.
  created $dff cell `$procdff$511' with positive edge clock.
Creating register for signal `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.\addr' using process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$402'.
  created $adff cell `$procdff$514' with positive edge clock and positive level reset.

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$265'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262'.
Removing empty process `SB_DFFNES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1414$262'.
Removing empty process `SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$261'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1353$255'.
Removing empty process `SB_DFFNESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1353$255'.
Removing empty process `SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$254'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251'.
Removing empty process `SB_DFFNER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1273$251'.
Removing empty process `SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$250'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1212$244'.
Removing empty process `SB_DFFNESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1212$244'.
Removing empty process `SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$243'.
Removing empty process `SB_DFFNS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1138$241'.
Removing empty process `SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$240'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1088$238'.
Removing empty process `SB_DFFNSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1088$238'.
Removing empty process `SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$237'.
Removing empty process `SB_DFFNR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:1017$235'.
Removing empty process `SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$234'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:967$232'.
Removing empty process `SB_DFFNSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:967$232'.
Removing empty process `SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$231'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:922$230'.
Removing empty process `SB_DFFNE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:922$230'.
Removing empty process `SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$229'.
Removing empty process `SB_DFFN.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:882$228'.
Removing empty process `SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$227'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224'.
Removing empty process `SB_DFFES.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:803$224'.
Removing empty process `SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$223'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:742$217'.
Removing empty process `SB_DFFESS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:742$217'.
Removing empty process `SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$216'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213'.
Removing empty process `SB_DFFER.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:662$213'.
Removing empty process `SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$212'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:601$206'.
Removing empty process `SB_DFFESR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:601$206'.
Removing empty process `SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$205'.
Removing empty process `SB_DFFS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:527$203'.
Removing empty process `SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$202'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:477$200'.
Removing empty process `SB_DFFSS.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:477$200'.
Removing empty process `SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$199'.
Removing empty process `SB_DFFR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:406$197'.
Removing empty process `SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$196'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:356$194'.
Removing empty process `SB_DFFSR.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:356$194'.
Removing empty process `SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$193'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:311$192'.
Removing empty process `SB_DFFE.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:311$192'.
Removing empty process `SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:0$191'.
Removing empty process `SB_DFF.$proc$/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:271$190'.
Removing empty process `fifo.$proc$fifo.v:0$21'.
Found and cleaned up 2 empty switches in `\fifo.$proc$fifo.v:62$14'.
Removing empty process `fifo.$proc$fifo.v:62$14'.
Found and cleaned up 1 empty switch in `\fifo.$proc$fifo.v:36$6'.
Removing empty process `fifo.$proc$fifo.v:36$6'.
Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:0$405'.
Found and cleaned up 2 empty switches in `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$402'.
Removing empty process `$paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.$proc$fifo.v:12$402'.
Cleaned up 23 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~1 debug messages>
Optimizing module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
<suppressed ~1 debug messages>

3.4. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\addr_gen\MAX_DATA=s32'00000000000000000000000100000000.
<suppressed ~2 debug messages>

3.5. Executing TRIBUF pass.

3.6. Executing DEMINOUT pass (demote inout ports to input or output).

3.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 3 unused cells and 28 unused wires.
<suppressed ~4 debug messages>

3.9. Executing CHECK pass (checking for obvious problems).
Checking module fifo...
Found and reported 0 problems.

3.10. Executing OPT pass (performing simple optimizations).

3.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

3.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
    Consolidated identical input bits for $mux cell $procmux$456:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\data$fifo.v:38$5_EN[7:0]$9
      New ports: A=1'0, B=1'1, Y=$0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0]
      New connections: $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [7:1] = { $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] $0$memwr$\data$fifo.v:38$5_EN[7:0]$9 [0] }
  Optimizing cells in module \fifo.
Performed a total of 1 changes.

3.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.10.6. Executing OPT_DFF pass (perform DFF optimizations).

3.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.10.9. Rerunning OPT passes. (Maybe there is more to do..)

3.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

3.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

3.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.10.13. Executing OPT_DFF pass (perform DFF optimizations).

3.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.10.16. Finished OPT passes. (There is nothing left to do.)

3.11. Executing FSM pass (extract and optimize FSM).

3.11.1. Executing FSM_DETECT pass (finding FSMs in design).

3.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).

3.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).

3.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).

3.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

3.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

3.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

3.12. Executing OPT pass (performing simple optimizations).

3.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

3.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

3.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$507 ($adff) from module fifo (D = $0\count[8:0], Q = \count).
Adding EN signal on $flatten\fifo_writer.$procdff$514 ($adff) from module fifo (D = $flatten\fifo_writer.$procmux$465_Y, Q = \fifo_writer.addr).
Adding EN signal on $flatten\fifo_reader.$procdff$514 ($adff) from module fifo (D = $flatten\fifo_reader.$procmux$465_Y, Q = \fifo_reader.addr).

3.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 2 unused cells and 2 unused wires.
<suppressed ~3 debug messages>

3.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~1 debug messages>

3.12.9. Rerunning OPT passes. (Maybe there is more to do..)

3.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

3.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

3.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.12.13. Executing OPT_DFF pass (perform DFF optimizations).

3.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.12.16. Finished OPT passes. (There is nothing left to do.)

3.13. Executing WREDUCE pass (reducing word size of cells).
Removed top 31 bits (of 32) from port B of cell fifo.$add$fifo.v:66$17 ($add).
Removed top 23 bits (of 32) from port Y of cell fifo.$add$fifo.v:66$17 ($add).
Removed top 31 bits (of 32) from port B of cell fifo.$sub$fifo.v:68$20 ($sub).
Removed top 23 bits (of 32) from port Y of cell fifo.$sub$fifo.v:68$20 ($sub).
Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$404 ($add).
Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_writer.$add$fifo.v:19$404 ($add).
Removed top 31 bits (of 32) from port B of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$404 ($add).
Removed top 24 bits (of 32) from port Y of cell fifo.$flatten\fifo_reader.$add$fifo.v:19$404 ($add).
Removed top 23 bits (of 32) from wire fifo.$add$fifo.v:66$17_Y.

3.14. Executing PEEPOPT pass (run peephole optimizers).

3.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

3.16. Executing SHARE pass (SAT-based resource sharing).

3.17. Executing TECHMAP pass (map to technology primitives).

3.17.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/cmp2lut.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

3.17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~6 debug messages>

3.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.20. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module fifo:
  creating $macc model for $add$fifo.v:66$17 ($add).
  creating $macc model for $flatten\fifo_reader.$add$fifo.v:19$404 ($add).
  creating $macc model for $flatten\fifo_writer.$add$fifo.v:19$404 ($add).
  creating $macc model for $sub$fifo.v:68$20 ($sub).
  creating $alu model for $macc $sub$fifo.v:68$20.
  creating $alu model for $macc $flatten\fifo_writer.$add$fifo.v:19$404.
  creating $alu model for $macc $flatten\fifo_reader.$add$fifo.v:19$404.
  creating $alu model for $macc $add$fifo.v:66$17.
  creating $alu cell for $add$fifo.v:66$17: $auto$alumacc.cc:485:replace_alu$525
  creating $alu cell for $flatten\fifo_reader.$add$fifo.v:19$404: $auto$alumacc.cc:485:replace_alu$528
  creating $alu cell for $flatten\fifo_writer.$add$fifo.v:19$404: $auto$alumacc.cc:485:replace_alu$531
  creating $alu cell for $sub$fifo.v:68$20: $auto$alumacc.cc:485:replace_alu$534
  created 4 $alu and 0 $macc cells.

3.21. Executing OPT pass (performing simple optimizations).

3.21.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.21.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.21.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

3.21.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

3.21.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

3.21.6. Executing OPT_DFF pass (perform DFF optimizations).

3.21.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.21.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

3.21.9. Finished OPT passes. (There is nothing left to do.)

3.22. Executing MEMORY pass.

3.22.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.22.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

3.22.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing fifo.data write port 0.

3.22.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

3.22.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\data'[0] in module `\fifo': merging output FF to cell.
    Write port 0: non-transparent.

3.22.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>

3.22.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

3.22.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.22.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

3.22.10. Executing MEMORY_COLLECT pass (generating $mem cells).

3.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
echo on

yosys> tee -o fifo.libmap debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge

yosys> debug memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge

yosys> memory_libmap -lib +/ice40/brams.txt -lib +/ice40/spram.txt -no-auto-huge

4. Executing MEMORY_LIBMAP pass (mapping memories to cells).
Memory fifo.data mapping candidates (post-geometry):
- logic fallback
  - cost: 2048.000000
- $__ICE40_RAM4K_:
  - option HAS_BE 0
  - emulation score: 7
  - replicates (for ports): 1
  - replicates (for data): 1
  - mux score: 0
  - demux score: 0
  - cost: 78.000000
  - abits 11 dbits 2 4 8 16
  - chosen base width 8
  - swizzle 0 1 2 3 4 5 6 7
  - emulate read-first behavior
  - write port 0: port group W
    - widths 2 4 8
  - read port 0: port group R
    - widths 2 4 8 16
    - emulate transparency with write port 0
- $__ICE40_RAM4K_:
  - option HAS_BE 1
  - emulation score: 7
  - replicates (for ports): 1
  - replicates (for data): 1
  - mux score: 0
  - demux score: 0
  - cost: 78.000000
  - abits 11 dbits 2 4 8 16
  - byte width 1
  - chosen base width 8
  - swizzle 0 1 2 3 4 5 6 7
  - emulate read-first behavior
  - write port 0: port group W
    - widths 16
  - read port 0: port group R
    - widths 2 4 8 16
    - emulate transparency with write port 0
Memory fifo.data mapping candidates (after post-geometry prune):
- logic fallback
  - cost: 2048.000000
- $__ICE40_RAM4K_:
  - option HAS_BE 0
  - emulation score: 7
  - replicates (for ports): 1
  - replicates (for data): 1
  - mux score: 0
  - demux score: 0
  - cost: 78.000000
  - abits 11 dbits 2 4 8 16
  - chosen base width 8
  - swizzle 0 1 2 3 4 5 6 7
  - emulate read-first behavior
  - write port 0: port group W
    - widths 2 4 8
  - read port 0: port group R
    - widths 2 4 8 16
    - emulate transparency with write port 0
mapping memory fifo.data via $__ICE40_RAM4K_

yosys> echo off
echo off

5. Executing SYNTH_ICE40 pass.

5.1. Executing MEMORY_LIBMAP pass (mapping memories to cells).

5.2. Executing TECHMAP pass (map to technology primitives).

5.2.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/brams_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
Successfully finished Verilog frontend.

5.2.2. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/spram_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/spram_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
Successfully finished Verilog frontend.

5.2.3. Continuing TECHMAP pass.
Using template $paramod$13b3947419e62b7bbba1b93c77e4155efbe69a94\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
No more expansions possible.
<suppressed ~26 debug messages>

5.3. Executing ICE40_BRAMINIT pass.

6. Generating Graphviz representation of design.
Writing dot description to `rdata_map_ram.dot'.
Dumping selected parts of module fifo to page 1.

7. Executing SYNTH_ICE40 pass.

7.1. Executing OPT pass (performing simple optimizations).

7.1.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~13 debug messages>

7.1.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

7.1.3. Executing OPT_DFF pass (perform DFF optimizations).
Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$553 ($dffe) from module fifo.

7.1.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 0 unused cells and 18 unused wires.
<suppressed ~1 debug messages>

7.1.5. Rerunning OPT passes. (Removed registers in this run.)

7.1.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

7.1.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

7.1.8. Executing OPT_DFF pass (perform DFF optimizations).

7.1.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

7.1.10. Finished fast OPT passes.

7.2. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

7.3. Executing OPT pass (performing simple optimizations).

7.3.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

7.3.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

7.3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~4 debug messages>

7.3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

7.3.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

7.3.6. Executing OPT_DFF pass (perform DFF optimizations).

7.3.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

7.3.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

7.3.9. Finished OPT passes. (There is nothing left to do.)

8. Generating Graphviz representation of design.
Writing dot description to `rdata_map_ffram.dot'.
Dumping selected parts of module fifo to page 1.

9. Executing SYNTH_ICE40 pass.

9.1. Executing ICE40_WRAPCARRY pass (wrap carries).

9.2. Executing TECHMAP pass (map to technology primitives).

9.2.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

9.2.2. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/arith_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

9.2.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$c3cd1564c35d873179656addd6052d7ea8b6d991\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $adffe.
Using extmapper simplemap for cells of type $mux.
Using template $paramod$6f67705c43e5e94c02b6ebb52209ce5aa5ade4c1\_80_ice40_alu for cells of type $alu.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $dff.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $pos.
No more expansions possible.
<suppressed ~175 debug messages>

9.3. Executing OPT pass (performing simple optimizations).

9.3.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~109 debug messages>

9.3.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
<suppressed ~81 debug messages>
Removed a total of 27 cells.

9.3.3. Executing OPT_DFF pass (perform DFF optimizations).

9.3.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 11 unused cells and 83 unused wires.
<suppressed ~12 debug messages>

9.3.5. Finished fast OPT passes.

9.4. Executing ICE40_OPT pass (performing simple optimizations).

9.4.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$525.slice[0].carry: CO=\count [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$528.slice[0].carry: CO=\fifo_reader.addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$531.slice[0].carry: CO=\fifo_writer.addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) fifo.$auto$alumacc.cc:485:replace_alu$534.slice[0].carry: CO=\count [0]

9.4.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

9.4.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

9.4.4. Executing OPT_DFF pass (perform DFF optimizations).

9.4.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

9.4.6. Rerunning OPT passes. (Removed registers in this run.)

9.4.7. Running ICE40 specific optimizations.

9.4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

9.4.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

9.4.10. Executing OPT_DFF pass (perform DFF optimizations).

9.4.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

9.4.12. Finished OPT passes. (There is nothing left to do.)

10. Generating Graphviz representation of design.
Writing dot description to `rdata_map_gates.dot'.
Dumping selected parts of module fifo to page 1.

11. Executing SYNTH_ICE40 pass.

11.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

11.2. Executing TECHMAP pass (map to technology primitives).

11.2.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/ff_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

11.2.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
No more expansions possible.
<suppressed ~73 debug messages>

11.3. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

11.4. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping fifo.$auto$alumacc.cc:485:replace_alu$528.slice[0].carry ($lut).
Mapping fifo.$auto$alumacc.cc:485:replace_alu$531.slice[0].carry ($lut).
Mapping fifo.$auto$alumacc.cc:485:replace_alu$534.slice[0].carry ($lut).
Mapping fifo.$auto$alumacc.cc:485:replace_alu$525.slice[0].carry ($lut).

11.5. Executing ICE40_OPT pass (performing simple optimizations).

11.5.1. Running ICE40 specific optimizations.

11.5.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~71 debug messages>

11.5.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

11.5.4. Executing OPT_DFF pass (perform DFF optimizations).

11.5.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 0 unused cells and 270 unused wires.
<suppressed ~1 debug messages>

11.5.6. Rerunning OPT passes. (Removed registers in this run.)

11.5.7. Running ICE40 specific optimizations.

11.5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~1 debug messages>

11.5.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

11.5.10. Executing OPT_DFF pass (perform DFF optimizations).

11.5.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

11.5.12. Rerunning OPT passes. (Removed registers in this run.)

11.5.13. Running ICE40 specific optimizations.

11.5.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

11.5.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

11.5.16. Executing OPT_DFF pass (perform DFF optimizations).

11.5.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

11.5.18. Finished OPT passes. (There is nothing left to do.)

12. Generating Graphviz representation of design.
Writing dot description to `rdata_map_ffs.dot'.
Dumping selected parts of module fifo to page 1.

13. Executing SYNTH_ICE40 pass.

13.1. Executing TECHMAP pass (map to technology primitives).

13.1.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/latches_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

13.1.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

13.2. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/abc9_model.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'.
Successfully finished Verilog frontend.

13.3. Executing ABC9 pass.

13.3.1. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.2. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module fifo.
Found 0 SCCs.

13.3.4. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.5. Executing PROC pass (convert processes to netlists).

13.3.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

13.3.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

13.3.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

13.3.5.4. Executing PROC_INIT pass (extract init attributes).

13.3.5.5. Executing PROC_ARST pass (detect async resets in processes).

13.3.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

13.3.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

13.3.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

13.3.5.9. Executing PROC_DFF pass (convert process syncs to FFs).

13.3.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

13.3.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

13.3.5.12. Executing OPT_EXPR pass (perform const folding).

13.3.6. Executing TECHMAP pass (map to technology primitives).

13.3.6.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.3.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~128 debug messages>

13.3.7. Executing OPT pass (performing simple optimizations).

13.3.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module SB_DFFER.

13.3.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\SB_DFFER'.
Removed a total of 0 cells.

13.3.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \SB_DFFER..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.3.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \SB_DFFER.
Performed a total of 0 changes.

13.3.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\SB_DFFER'.
Removed a total of 0 cells.

13.3.7.6. Executing OPT_DFF pass (perform DFF optimizations).

13.3.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \SB_DFFER..

13.3.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module SB_DFFER.

13.3.7.9. Finished OPT passes. (There is nothing left to do.)

13.3.8. Executing TECHMAP pass (map to technology primitives).

13.3.8.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

13.3.8.2. Continuing TECHMAP pass.
Using template SB_DFFER for cells of type SB_DFFER.
No more expansions possible.
<suppressed ~28 debug messages>

13.3.9. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_model.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

13.3.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~86 debug messages>

13.3.11. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

13.3.13. Executing TECHMAP pass (map to technology primitives).

13.3.13.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

13.3.13.2. Continuing TECHMAP pass.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4.
Using template SB_CARRY for cells of type SB_CARRY.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $logic_or.
No more expansions possible.
<suppressed ~155 debug messages>

13.3.14. Executing OPT pass (performing simple optimizations).

13.3.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.
<suppressed ~4 debug messages>

13.3.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
<suppressed ~29 debug messages>
Removed a total of 12 cells.

13.3.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.3.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

13.3.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

13.3.14.6. Executing OPT_DFF pass (perform DFF optimizations).

13.3.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..
Removed 0 unused cells and 24 unused wires.
<suppressed ~1 debug messages>

13.3.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

13.3.14.9. Rerunning OPT passes. (Maybe there is more to do..)

13.3.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \fifo..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

13.3.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \fifo.
Performed a total of 0 changes.

13.3.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\fifo'.
Removed a total of 0 cells.

13.3.14.13. Executing OPT_DFF pass (perform DFF optimizations).

13.3.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \fifo..

13.3.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module fifo.

13.3.14.16. Finished OPT passes. (There is nothing left to do.)

13.3.15. Executing AIGMAP pass (map logic to AIG).
Module fifo: replaced 7 cells with 43 new cells, skipped 11 cells.
  replaced 2 cell types:
       2 $_OR_
       5 $_MUX_
  not replaced 3 cell types:
       8 $specify2
       1 $_NOT_
       2 $_AND_

13.3.16. Executing AIGMAP pass (map logic to AIG).
Module fifo: replaced 46 cells with 256 new cells, skipped 232 cells.
  replaced 3 cell types:
      22 $_OR_
       8 $_XOR_
      16 $_MUX_
  not replaced 16 cell types:
       2 $scopeinfo
      20 $_NOT_
      19 $_AND_
      26 SB_DFF
      25 SB_DFFER
       1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000001100010
       2 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001011
      25 SB_DFFER_$abc9_byp
       1 $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K
      16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010100001
      11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011001011
      30 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1
       1 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010000101
      11 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011100000
      16 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100010010
      26 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000000010101

13.3.16.1. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.16.2. Executing ABC9_OPS pass (helper functions for ABC9).

13.3.16.3. Executing XAIGER backend.
<suppressed ~78 debug messages>
Extracted 113 AND gates and 562 wires from module `fifo' to a netlist network with 71 inputs and 127 outputs.

13.3.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).

13.3.16.5. Executing ABC9.
Running ABC command: "/usr/bin/abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =     71/    127  and =     113  lev =    6 (0.27)  mem = 0.01 MB  box = 139  bb = 109
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =     71/    127  and =     161  lev =    6 (0.12)  mem = 0.01 MB  ch =   20  box = 139  bb = 109
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
ABC: + &if -W 250 -v 
ABC: K = 4. Memory (bytes): Truth =    0. Cut =   52. Obj =  136. Set =  564. CutMin = no
ABC: Node =     161.  Ch =    19.  Total mem =    0.12 MB. Peak cut mem =    0.01 MB.
ABC: P:  Del = 2712.00.  Ar =      28.0.  Edge =       81.  Cut =      578.  T =     0.00 sec
ABC: P:  Del = 2712.00.  Ar =      27.0.  Edge =       87.  Cut =      572.  T =     0.00 sec
ABC: P:  Del = 2712.00.  Ar =      27.0.  Edge =       87.  Cut =      574.  T =     0.00 sec
ABC: F:  Del = 2712.00.  Ar =      26.0.  Edge =       88.  Cut =      557.  T =     0.00 sec
ABC: A:  Del = 2712.00.  Ar =      26.0.  Edge =       86.  Cut =      555.  T =     0.00 sec
ABC: A:  Del = 2712.00.  Ar =      26.0.  Edge =       86.  Cut =      562.  T =     0.00 sec
ABC: Total time =     0.00 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: The network is not changed by "&mfs".
ABC: + &ps -l 
ABC: <abc-temp-dir>/input : i/o =     71/    127  and =      91  lev =    6 (0.12)  mem = 0.01 MB  box = 139  bb = 109
ABC: Mapping (K=4)  :  lut =     26  edge =      86  lev =    3 (0.05)  levB =   10  mem = 0.00 MB
ABC: LUT = 26 : 2=4 15.4 %  3=10 38.5 %  4=12 46.2 %  Ave = 3.31
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 20 carries.
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + time 
ABC: elapse: 0.01 seconds, total: 0.01 seconds

13.3.16.6. Executing AIGER frontend.
<suppressed ~408 debug messages>
Removed 175 unused cells and 883 unused wires.

13.3.16.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:       29
ABC RESULTS:   \SB_DFFER_$abc9_byp cells:       25
ABC RESULTS:   $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells:       30
ABC RESULTS:           input signals:       36
ABC RESULTS:          output signals:       91
Removing temp directory.

13.3.17. Executing TECHMAP pass (map to technology primitives).

13.3.17.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_unmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

13.3.17.2. Continuing TECHMAP pass.
Using template SB_DFFER_$abc9_byp for cells of type SB_DFFER_$abc9_byp.
Using template $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K for cells of type $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
No more expansions possible.
<suppressed ~64 debug messages>

13.4. Executing ICE40_WRAPCARRY pass (wrap carries).

13.5. Executing TECHMAP pass (map to technology primitives).

13.5.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/ff_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

13.5.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 7 unused cells and 1055 unused wires.

13.6. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:       58
  1-LUT                3
  2-LUT                8
  3-LUT               35
  4-LUT               12
  with \SB_CARRY    (#0)   25
  with \SB_CARRY    (#1)   26

Eliminating LUTs.
Number of LUTs:       58
  1-LUT                3
  2-LUT                8
  3-LUT               35
  4-LUT               12
  with \SB_CARRY    (#0)   25
  with \SB_CARRY    (#1)   26

Combining LUTs.
Number of LUTs:       58
  1-LUT                3
  2-LUT                8
  3-LUT               35
  4-LUT               12
  with \SB_CARRY    (#0)   25
  with \SB_CARRY    (#1)   26

Eliminated 0 LUTs.
Combined 0 LUTs.
<suppressed ~334 debug messages>

14. Generating Graphviz representation of design.
Writing dot description to `rdata_map_luts.dot'.
Dumping selected parts of module fifo to page 1.

15. Executing SYNTH_ICE40 pass.

15.1. Executing TECHMAP pass (map to technology primitives).

15.1.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_map.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

15.1.2. Continuing TECHMAP pass.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010000 for cells of type $lut.
Using template $paramod$c71ed138d834112b80a85f4478e2e21f72e5c48b\$lut for cells of type $lut.
Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut.
Using template $paramod$5183b4454493323aca6310872659274580528fcf\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod$e87f431398fe61dc3cef677df705fdf1c11aa0f7\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~256 debug messages>
Removed 0 unused cells and 126 unused wires.

15.2. Executing AUTONAME pass.
Renamed 1132 objects in module fifo (19 iterations).
<suppressed ~217 debug messages>

15.3. Executing HIERARCHY pass (managing design hierarchy).

15.3.1. Analyzing design hierarchy..
Top module:  \fifo

15.3.2. Analyzing design hierarchy..
Top module:  \fifo
Removed 0 unused modules.

15.4. Printing statistics.

=== fifo ===

   Number of wires:                 95
   Number of wire bits:            262
   Number of public wires:          95
   Number of public wire bits:     262
   Number of ports:                  7
   Number of port bits:             29
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                138
     $scopeinfo                      2
     SB_CARRY                       26
     SB_DFF                         26
     SB_DFFER                       25
     SB_LUT4                        58
     SB_RAM40_4K                     1

15.5. Executing CHECK pass (checking for obvious problems).
Checking module fifo...
Found and reported 0 problems.

16. Generating Graphviz representation of design.
Writing dot description to `rdata_map_cells.dot'.
Dumping selected parts of module fifo to page 1.
echo on

yosys> tee -a fifo.stat stat -top fifo

yosys> stat -top fifo

17. Printing statistics.

=== fifo ===

   Number of wires:                 95
   Number of wire bits:            262
   Number of public wires:          95
   Number of public wire bits:     262
   Number of ports:                  7
   Number of port bits:             29
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                138
     $scopeinfo                      2
     SB_CARRY                       26
     SB_DFF                         26
     SB_DFFER                       25
     SB_LUT4                        58
     SB_RAM40_4K                     1


yosys> echo off
echo off

End of script. Logfile hash: f2626467ec, CPU: user 1.03s system 0.03s, MEM: 33.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 34% 21x read_verilog (0 sec), 30% 11x techmap (0 sec), ...
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/fifo'
make -C source/code_examples/intro examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/intro'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/intro'
make -C source/code_examples/macc examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/macc'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/macc'
make -C source/code_examples/opt examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/opt'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/opt'
make -C source/code_examples/scrambler examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/scrambler'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/scrambler'
make -C source/code_examples/selections examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/selections'
../../../../yosys sumprod.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `sumprod.ys' --

1. Executing Verilog-2005 frontend: sumprod.v
Parsing Verilog input from `sumprod.v' to AST representation.
Generating RTLIL representation for module `\sumprod'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Analyzing design hierarchy..
Top module:  \sumprod

2.1.2. Analyzing design hierarchy..
Top module:  \sumprod
Removed 0 unused modules.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module sumprod.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module sumprod.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \sumprod..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module sumprod...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module sumprod.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\sumprod'.
Removed a total of 0 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \sumprod..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \sumprod.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\sumprod'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \sumprod..

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module sumprod.

2.7.8. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \sumprod..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module sumprod.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\sumprod'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \sumprod..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== sumprod ===

   Number of wires:                  7
   Number of wire bits:             56
   Number of public wires:           5
   Number of public wire bits:      40
   Number of ports:                  5
   Number of port bits:             40
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  4
     $add                            2
     $mul                            2

2.13. Executing CHECK pass (checking for obvious problems).
Checking module sumprod...
Found and reported 0 problems.

3. Generating Graphviz representation of design.
Writing dot description to `sumprod_00.dot'.
Dumping selected parts of module sumprod to page 1.

4. Generating Graphviz representation of design.
Writing dot description to `sumprod_01.dot'.
Dumping selected parts of module sumprod to page 1.

5. Generating Graphviz representation of design.
Writing dot description to `sumprod_02.dot'.
Dumping selected parts of module sumprod to page 1.

6. Generating Graphviz representation of design.
Writing dot description to `sumprod_03.dot'.
Dumping selected parts of module sumprod to page 1.

7. Generating Graphviz representation of design.
Writing dot description to `sumprod_04.dot'.
Dumping selected parts of module sumprod to page 1.

8. Generating Graphviz representation of design.
Writing dot description to `sumprod_05.dot'.
Dumping selected parts of module sumprod to page 1.

End of script. Logfile hash: ad287e9838, CPU: user 0.01s system 0.01s, MEM: 13.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 6x show (0 sec), 24% 5x opt_expr (0 sec), ...
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/selections'
make -C source/code_examples/show examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/show'
../../../../yosys example_lscd.ys -l example.out -Q -T

-- Executing script file `example_lscd.ys' --

1. Executing Verilog-2005 frontend: example.v
Parsing Verilog input from `example.v' to AST representation.
Generating RTLIL representation for module `\example'.
Successfully finished Verilog frontend.
echo on

yosys> ls

1 modules:
  example

yosys> cd example

yosys [example]> ls

8 wires:
  $0\y[1:0]
  $add$example.v:5$2_Y
  $ternary$example.v:5$3_Y
  a
  b
  c
  clk
  y

2 cells:
  $add$example.v:5$2
  $ternary$example.v:5$3

1 processes:
  $proc$example.v:3$1

yosys [example]> dump $2


  attribute \src "example.v:5.22-5.27"
  cell $add $add$example.v:5$2
    parameter \Y_WIDTH 2
    parameter \B_WIDTH 1
    parameter \A_WIDTH 1
    parameter \B_SIGNED 0
    parameter \A_SIGNED 0
    connect \Y $add$example.v:5$2_Y
    connect \B \b
    connect \A \a
  end

yosys [example]> cd ..

yosys> echo off
echo off
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/show'
make -C source/code_examples/stubnets examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/stubnets'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/stubnets'
make -C source/code_examples/synth_flow examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/synth_flow'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/synth_flow'
make -C source/code_examples/techmap examples
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/techmap'
make[3]: Nothing to be done for 'examples'.
make[3]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/techmap'
make[2]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs'
make images
make[2]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs'
make -C source/_images
make[3]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/_images'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/extensions'
../../../../yosys -m ./my_cmd.so -p 'test1; show -format dot -prefix test1'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `test1; show -format dot -prefix test1' --
Name of this module: absval

1. Generating Graphviz representation of design.
Writing dot description to `test1.dot'.
Dumping module absval to page 1.

End of script. Logfile hash: 2e5f50e91f, CPU: user 0.00s system 0.00s, MEM: 9.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 84% 1x show (0 sec), 15% 1x test1 (0 sec)
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/extensions'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/fifo'
make[4]: Nothing to be done for 'dots'.
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/fifo'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/intro'
../../../../yosys counter.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `counter.ys' --

1. Executing Verilog-2005 frontend: counter.v
Parsing Verilog input from `counter.v' to AST representation.
Generating RTLIL representation for module `\counter'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \counter

2.2. Analyzing design hierarchy..
Top module:  \counter
Removed 0 unused modules.

3. Generating Graphviz representation of design.
Writing dot description to `counter_00.dot'.
Dumping module counter to page 1.

4. Executing PROC pass (convert processes to netlists).

4.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$counter.v:6$1 in module counter.
Removed a total of 0 dead cases.

4.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

4.4. Executing PROC_INIT pass (extract init attributes).

4.5. Executing PROC_ARST pass (detect async resets in processes).

4.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~2 debug messages>

4.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\counter.$proc$counter.v:6$1'.
     1/1: $0\count[1:0]

4.8. Executing PROC_DLATCH pass (convert process syncs to latches).

4.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\counter.\count' using process `\counter.$proc$counter.v:6$1'.
  created $dff cell `$procdff$8' with positive edge clock.

4.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

4.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 2 empty switches in `\counter.$proc$counter.v:6$1'.
Removing empty process `counter.$proc$counter.v:6$1'.
Cleaned up 2 empty switches.

4.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

5.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $procdff$8 ($dff) from module counter (D = $procmux$3_Y, Q = \count, rval = 2'00).
Adding EN signal on $auto$ff.cc:266:slice$9 ($sdff) from module counter (D = $add$counter.v:10$2_Y, Q = \count).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..
Removed 2 unused cells and 5 unused wires.
<suppressed ~3 debug messages>

5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

5.9. Rerunning OPT passes. (Maybe there is more to do..)

5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

5.13. Executing OPT_DFF pass (perform DFF optimizations).

5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

5.16. Finished OPT passes. (There is nothing left to do.)

6. Executing MEMORY pass.

6.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

6.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

6.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

6.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

6.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

6.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

6.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

6.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

6.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

6.10. Executing MEMORY_COLLECT pass (generating $mem cells).

6.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).

7. Executing OPT pass (performing simple optimizations).

7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

7.6. Executing OPT_DFF pass (perform DFF optimizations).

7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

7.9. Finished OPT passes. (There is nothing left to do.)

8. Executing FSM pass (extract and optimize FSM).

8.1. Executing FSM_DETECT pass (finding FSMs in design).

8.2. Executing FSM_EXTRACT pass (extracting FSM from design).

8.3. Executing FSM_OPT pass (simple optimizations of FSMs).

8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

8.5. Executing FSM_OPT pass (simple optimizations of FSMs).

8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).

8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).

9. Executing OPT pass (performing simple optimizations).

9.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

9.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

9.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

9.6. Executing OPT_DFF pass (perform DFF optimizations).

9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

9.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

9.9. Finished OPT passes. (There is nothing left to do.)

10. Generating Graphviz representation of design.
Writing dot description to `counter_01.dot'.
Dumping module counter to page 1.

11. Executing TECHMAP pass (map to technology primitives).

11.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

11.2. Continuing TECHMAP pass.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=2:B_SIGNED=0:B_WIDTH=2:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using extmapper simplemap for cells of type $sdffe.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~229 debug messages>

12. Executing OPT pass (performing simple optimizations).

12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.
<suppressed ~11 debug messages>

12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

12.6. Executing OPT_DFF pass (perform DFF optimizations).

12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..
Removed 2 unused cells and 32 unused wires.
<suppressed ~3 debug messages>

12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

12.9. Rerunning OPT passes. (Maybe there is more to do..)

12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \counter..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \counter.
Performed a total of 0 changes.

12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\counter'.
Removed a total of 0 cells.

12.13. Executing OPT_DFF pass (perform DFF optimizations).

12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \counter..

12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module counter.

12.16. Finished OPT passes. (There is nothing left to do.)

13. Executing SPLITNETS pass (splitting up multi-bit signals).
Removed 0 unused cells and 2 unused wires.

14. Generating Graphviz representation of design.
Writing dot description to `counter_02.dot'.
Dumping module counter to page 1.

15. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
  cell DFF (noninv, pins=3, area=18.00) is a direct match for cell type $_DFF_P_.
  final dff cell mappings:
    unmapped dff cell: $_DFF_N_
    \DFF _DFF_P_ (.C( C), .D( D), .Q( Q));
    unmapped dff cell: $_DFF_NN0_
    unmapped dff cell: $_DFF_NN1_
    unmapped dff cell: $_DFF_NP0_
    unmapped dff cell: $_DFF_NP1_
    unmapped dff cell: $_DFF_PN0_
    unmapped dff cell: $_DFF_PN1_
    unmapped dff cell: $_DFF_PP0_
    unmapped dff cell: $_DFF_PP1_
    unmapped dff cell: $_DFFSR_NNN_
    unmapped dff cell: $_DFFSR_NNP_
    unmapped dff cell: $_DFFSR_NPN_
    unmapped dff cell: $_DFFSR_NPP_
    unmapped dff cell: $_DFFSR_PNN_
    unmapped dff cell: $_DFFSR_PNP_
    unmapped dff cell: $_DFFSR_PPN_
    unmapped dff cell: $_DFFSR_PPP_

15.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
Mapping DFF cells in module `\counter':
  mapped 2 $_DFF_P_ cells to \DFF cells.

16. Executing ABC pass (technology mapping using ABC).

16.1. Extracting gate netlist of module `\counter' to `<abc-temp-dir>/input.blif'..
Extracted 6 gates and 11 wires to a netlist network with 4 inputs and 2 outputs.

16.1.1. Executing ABC.
Running ABC command: "/usr/bin/abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w <yosys-exe-dir>/docs/source/code_examples/intro/mycells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Warning: Templates are not defined.
ABC: Liberty parser cannot read "time_unit".  Assuming   time_unit : "1ns".
ABC: Liberty parser cannot read "capacitive_load_unit". Assuming   capacitive_load_unit(1, pf).
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF".
ABC: Library "demo" from "<yosys-exe-dir>/docs/source/code_examples/intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.01 MB. Time =     0.00 sec
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 

16.1.2. Re-integrating ABC results.
ABC RESULTS:               NOT cells:        3
ABC RESULTS:              NAND cells:        4
ABC RESULTS:               NOR cells:        4
ABC RESULTS:        internal signals:        5
ABC RESULTS:           input signals:        4
ABC RESULTS:          output signals:        2
Removing temp directory.
Removed 0 unused cells and 10 unused wires.

17. Generating Graphviz representation of design.

17.1. Executing Verilog-2005 frontend: mycells.v
Parsing Verilog input from `mycells.v' to AST representation.
Generating RTLIL representation for module `\NOT'.
Generating RTLIL representation for module `\NAND'.
Generating RTLIL representation for module `\NOR'.
Generating RTLIL representation for module `\DFF'.
Successfully finished Verilog frontend.

17.2. Continuing show pass.
Writing dot description to `counter_03.dot'.
Dumping module counter to page 1.

18. Executing Verilog backend.

18.1. Executing BMUXMAP pass.

18.2. Executing DEMUXMAP pass.
Dumping module `\counter'.

End of script. Logfile hash: d35f026f62, CPU: user 0.04s system 0.01s, MEM: 17.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 59% 1x abc (0 sec), 9% 13x opt_expr (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/intro'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/macc'
../../../../yosys macc_simple_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `macc_simple_test.ys' --

1. Executing Verilog-2005 frontend: macc_simple_test.v
Parsing Verilog input from `macc_simple_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.
Removed 0 unused cells and 1 unused wires.

3. Generating Graphviz representation of design.

3.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

3.2. Continuing show pass.
Writing dot description to `macc_simple_test_00a.dot'.
Dumping module test to page 1.

4. Executing EXTRACT pass (map subcircuits to cells).

4.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

4.2. Executing PROC pass (convert processes to netlists).

4.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

4.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

4.2.4. Executing PROC_INIT pass (extract init attributes).

4.2.5. Executing PROC_ARST pass (detect async resets in processes).

4.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

4.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

4.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

4.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

4.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

4.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

4.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module macc_16_16_32.

4.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \macc_16_16_32..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

4.4. Creating graphs for SubCircuit library.
Creating needle graph needle_macc_16_16_32.
Creating haystack graph haystack_test.

4.5. Running solver from SubCircuit library.
Solving for needle_macc_16_16_32 in haystack_test.
Found 1 matches.

4.6. Substitute SubCircuits with cells.

Match #0: (needle_macc_16_16_32 in haystack_test)
  $add$macc_simple_xmap.v:5$7 -> $add$macc_simple_test.v:5$2 \A:\A \B:\B \Y:\Y
  $const$0 -> $const$0 \Y:\Y
  $const$1 -> $const$1 \Y:\Y
  $const$x -> $const$x \Y:\Y
  $const$z -> $const$z \Y:\Y
  $mul$macc_simple_xmap.v:5$6 -> $mul$macc_simple_test.v:5$1 \A:\A \B:\B \Y:\Y
  new cell: $extract$\macc_16_16_32$8
Removed 0 unused cells and 1 unused wires.

5. Generating Graphviz representation of design.

5.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

5.2. Continuing show pass.
Writing dot description to `macc_simple_test_00b.dot'.
Dumping module test to page 1.

6. Executing Verilog-2005 frontend: macc_simple_test_01.v
Parsing Verilog input from `macc_simple_test_01.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

7. Executing HIERARCHY pass (managing design hierarchy).

7.1. Analyzing design hierarchy..
Top module:  \test

7.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.
Removed 0 unused cells and 1 unused wires.

8. Generating Graphviz representation of design.

8.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

8.2. Continuing show pass.
Writing dot description to `macc_simple_test_01a.dot'.
Dumping module test to page 1.

9. Executing EXTRACT pass (map subcircuits to cells).

9.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

9.2. Executing PROC pass (convert processes to netlists).

9.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

9.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

9.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

9.2.4. Executing PROC_INIT pass (extract init attributes).

9.2.5. Executing PROC_ARST pass (detect async resets in processes).

9.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

9.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

9.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

9.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

9.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

9.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

9.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module macc_16_16_32.

9.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \macc_16_16_32..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

9.4. Creating graphs for SubCircuit library.
Creating needle graph needle_macc_16_16_32.
Creating haystack graph haystack_test.

9.5. Running solver from SubCircuit library.
Solving for needle_macc_16_16_32 in haystack_test.
Found 1 matches.

9.6. Substitute SubCircuits with cells.

Match #0: (needle_macc_16_16_32 in haystack_test)
  $add$macc_simple_xmap.v:5$18 -> $add$macc_simple_test_01.v:5$13 \A:\A \B:\B \Y:\Y
  $mul$macc_simple_xmap.v:5$17 -> $mul$macc_simple_test_01.v:5$11 \A:\A \B:\B \Y:\Y
  new cell: $extract$\macc_16_16_32$19
Removed 0 unused cells and 1 unused wires.

10. Generating Graphviz representation of design.

10.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

10.2. Continuing show pass.
Writing dot description to `macc_simple_test_01b.dot'.
Dumping module test to page 1.

11. Executing Verilog-2005 frontend: macc_simple_test_02.v
Parsing Verilog input from `macc_simple_test_02.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

12. Executing HIERARCHY pass (managing design hierarchy).

12.1. Analyzing design hierarchy..
Top module:  \test

12.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.
Removed 0 unused cells and 1 unused wires.

13. Generating Graphviz representation of design.

13.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

13.2. Continuing show pass.
Writing dot description to `macc_simple_test_02a.dot'.
Dumping module test to page 1.

14. Executing EXTRACT pass (map subcircuits to cells).

14.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

14.2. Executing PROC pass (convert processes to netlists).

14.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

14.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

14.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

14.2.4. Executing PROC_INIT pass (extract init attributes).

14.2.5. Executing PROC_ARST pass (detect async resets in processes).

14.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

14.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

14.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

14.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

14.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

14.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

14.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module macc_16_16_32.

14.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \macc_16_16_32..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

14.4. Creating graphs for SubCircuit library.
Creating needle graph needle_macc_16_16_32.
Creating haystack graph haystack_test.

14.5. Running solver from SubCircuit library.
Solving for needle_macc_16_16_32 in haystack_test.
Found 2 matches.

14.6. Substitute SubCircuits with cells.

Match #0: (needle_macc_16_16_32 in haystack_test)
  $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$24 \A:\A \B:\B \Y:\Y
  $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$23 \A:\A \B:\B \Y:\Y
  new cell: $extract$\macc_16_16_32$30

Match #1: (needle_macc_16_16_32 in haystack_test)
  $add$macc_simple_xmap.v:5$29 -> $add$macc_simple_test_02.v:5$25 \A:\A \B:\B \Y:\Y
  $mul$macc_simple_xmap.v:5$28 -> $mul$macc_simple_test_02.v:5$22 \A:\A \B:\B \Y:\Y
  new cell: $extract$\macc_16_16_32$31
Removed 0 unused cells and 2 unused wires.

15. Generating Graphviz representation of design.

15.1. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

15.2. Continuing show pass.
Writing dot description to `macc_simple_test_02b.dot'.
Dumping module test to page 1.

16. Executing Verilog-2005 frontend: macc_simple_xmap.v
Parsing Verilog input from `macc_simple_xmap.v' to AST representation.
Generating RTLIL representation for module `\macc_16_16_32'.
Successfully finished Verilog frontend.

17. Executing HIERARCHY pass (managing design hierarchy).

17.1. Analyzing design hierarchy..
Top module:  \macc_16_16_32

17.2. Analyzing design hierarchy..
Top module:  \macc_16_16_32
Removed 0 unused modules.
Removed 0 unused cells and 1 unused wires.

18. Generating Graphviz representation of design.
Writing dot description to `macc_simple_xmap.dot'.
Dumping module macc_16_16_32 to page 1.

End of script. Logfile hash: a39cb7f441, CPU: user 0.02s system 0.00s, MEM: 12.88 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 28% 7x clean (0 sec), 18% 3x extract (0 sec), ...
../../../../yosys macc_xilinx_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `macc_xilinx_test.ys' --

1. Executing Verilog-2005 frontend: macc_xilinx_test.v
Parsing Verilog input from `macc_xilinx_test.v' to AST representation.
Generating RTLIL representation for module `\test1'.
Generating RTLIL representation for module `\test2'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v
Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation.
Generating RTLIL representation for module `$__mul_wrapper'.
Generating RTLIL representation for module `$__add_wrapper'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: macc_xilinx_xmap.v
Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation.
Generating RTLIL representation for module `\DSP48_MACC'.
Successfully finished Verilog frontend.

4. Executing HIERARCHY pass (managing design hierarchy).
Removed 0 unused cells and 2 unused wires.

5. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test1a.dot'.
Dumping module test1 to page 1.

6. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test2a.dot'.
Dumping module test2 to page 1.

7. Executing TECHMAP pass (map to technology primitives).

7.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v
Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation.
Generating RTLIL representation for module `\mul_swap_ports'.
Successfully finished Verilog frontend.

7.2. Continuing TECHMAP pass.
Using template $paramod$cb31b7e2c27e209b1e5fc8ca3c6ec22d65eb4c07\mul_swap_ports for cells of type $mul.
No more expansions possible.
<suppressed ~80 debug messages>
Removed 0 unused cells and 8 unused wires.

8. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test1b.dot'.
Dumping module test1 to page 1.

9. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test2b.dot'.
Dumping module test2 to page 1.

10. Executing TECHMAP pass (map to technology primitives).

10.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v
Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation.
Generating RTLIL representation for module `\mul_wrap'.
Generating RTLIL representation for module `\add_wrap'.
Successfully finished Verilog frontend.

10.2. Continuing TECHMAP pass.
Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\mul_wrap for cells of type $mul.
Using template $paramod$48197a291a9e3825142389e9d2e41385cae2467c\mul_wrap for cells of type $mul.
Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\add_wrap for cells of type $add.
No more expansions possible.
<suppressed ~341 debug messages>

11. Executing CONNWRAPPERS pass (connect extended ports of wrapper cells).
Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:A: { 6'000000 $add$macc_xilinx_test.v:5$3_Y } -> { $techmap24$add$macc_xilinx_test.v:5$3.Y_48 [47:42] $add$macc_xilinx_test.v:5$3_Y }
Connected extended bits of test1.$add$macc_xilinx_test.v:5$5:B: { 6'000000 $mul$macc_xilinx_test.v:5$4_Y } -> { $techmap25$mul$macc_xilinx_test.v:5$4.Y_48 [47:42] $mul$macc_xilinx_test.v:5$4_Y }
Connected extended bits of test1.$add$macc_xilinx_test.v:5$3:B: { 6'000000 $mul$macc_xilinx_test.v:5$2_Y } -> { $techmap23$mul$macc_xilinx_test.v:5$2.Y_48 [47:42] $mul$macc_xilinx_test.v:5$2_Y }
Connected extended bits of test2.$add$macc_xilinx_test.v:12$10:B: { 6'000000 $add$macc_xilinx_test.v:12$9_Y } -> { $techmap21$add$macc_xilinx_test.v:12$9.Y_48 [47:42] $add$macc_xilinx_test.v:12$9_Y }
Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:A: { 6'000000 $mul$macc_xilinx_test.v:12$7_Y } -> { $techmap19$mul$macc_xilinx_test.v:12$7.Y_48 [47:42] $mul$macc_xilinx_test.v:12$7_Y }
Connected extended bits of test2.$add$macc_xilinx_test.v:12$9:B: { 6'000000 $mul$macc_xilinx_test.v:12$8_Y } -> { $techmap17$mul$macc_xilinx_test.v:12$8.Y_48 [47:42] $mul$macc_xilinx_test.v:12$8_Y }
Removed 0 unused cells and 56 unused wires.

12. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test1c.dot'.
Dumping module test1 to page 1.

13. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test2c.dot'.
Dumping module test2 to page 1.

14. Executing Verilog-2005 frontend: macc_xilinx_xmap.v
Parsing Verilog input from `macc_xilinx_xmap.v' to AST representation.
Generating RTLIL representation for module `\DSP48_MACC'.
Successfully finished Verilog frontend.

15. Executing TECHMAP pass (map to technology primitives).

15.1. Executing Verilog-2005 frontend: macc_xilinx_swap_map.v
Parsing Verilog input from `macc_xilinx_swap_map.v' to AST representation.
Generating RTLIL representation for module `\mul_swap_ports'.
Successfully finished Verilog frontend.

15.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~23 debug messages>

16. Executing TECHMAP pass (map to technology primitives).

16.1. Executing Verilog-2005 frontend: macc_xilinx_wrap_map.v
Parsing Verilog input from `macc_xilinx_wrap_map.v' to AST representation.
Generating RTLIL representation for module `\mul_wrap'.
Generating RTLIL representation for module `\add_wrap'.
Successfully finished Verilog frontend.

16.2. Continuing TECHMAP pass.
Using template $paramod$81421da67e3cf07e7ac8b39f28efc75ee750e82a\mul_wrap for cells of type $mul.
Using template $paramod$88aad6f8473fb7e4e5fbfb8335ddebad03429eaa\add_wrap for cells of type $add.
No more expansions possible.
<suppressed ~172 debug messages>
Removed 0 unused cells and 17 unused wires.

17. Executing EXTRACT pass (map subcircuits to cells).

17.1. Creating graphs for SubCircuit library.
Creating needle graph needle_DSP48_MACC.
Creating haystack graph haystack_$__add_wrapper.
Creating haystack graph haystack_$__mul_wrapper.
Creating haystack graph haystack_DSP48_MACC.
Creating haystack graph haystack_test1.
Creating haystack graph haystack_test2.

17.2. Running solver from SubCircuit library.
Solving for needle_DSP48_MACC in haystack_$__add_wrapper.
Solving for needle_DSP48_MACC in haystack_$__mul_wrapper.
Solving for needle_DSP48_MACC in haystack_DSP48_MACC.
Solving for needle_DSP48_MACC in haystack_test1.
Solving for needle_DSP48_MACC in haystack_test2.
Found 3 matches.

17.3. Substitute SubCircuits with cells.

Match #0: (needle_DSP48_MACC in haystack_test1)
  $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$3 \A:\B \B:\A \Y:\Y
  $const$0 -> $const$0 \Y:\Y
  $const$1 -> $const$1 \Y:\Y
  $const$x -> $const$x \Y:\Y
  $const$z -> $const$z \Y:\Y
  $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$2 \A:\A \B:\B \Y:\Y
  new cell: $extract$\DSP48_MACC$35

Match #1: (needle_DSP48_MACC in haystack_test1)
  $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:5$5 \A:\B \B:\A \Y:\Y
  $const$0 -> $const$0 \Y:\Y
  $const$1 -> $const$1 \Y:\Y
  $const$x -> $const$x \Y:\Y
  $const$z -> $const$z \Y:\Y
  $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:5$4 \A:\A \B:\B \Y:\Y
  new cell: $extract$\DSP48_MACC$36

Match #2: (needle_DSP48_MACC in haystack_test2)
  $add$macc_xilinx_xmap.v:8$28 -> $add$macc_xilinx_test.v:12$9 \A:\A \B:\B \Y:\Y
  $const$0 -> $const$0 \Y:\Y
  $const$1 -> $const$1 \Y:\Y
  $const$x -> $const$x \Y:\Y
  $const$z -> $const$z \Y:\Y
  $mul$macc_xilinx_xmap.v:8$27 -> $mul$macc_xilinx_test.v:12$7 \A:\A \B:\B \Y:\Y
  new cell: $extract$\DSP48_MACC$37
Removed 0 unused cells and 6 unused wires.

18. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test1d.dot'.
Dumping module test1 to page 1.

19. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test2d.dot'.
Dumping module test2 to page 1.

20. Executing TECHMAP pass (map to technology primitives).

20.1. Executing Verilog-2005 frontend: macc_xilinx_unwrap_map.v
Parsing Verilog input from `macc_xilinx_unwrap_map.v' to AST representation.
Generating RTLIL representation for module `\$__mul_wrapper'.
Generating RTLIL representation for module `\$__add_wrapper'.
Successfully finished Verilog frontend.

20.2. Continuing TECHMAP pass.
Using template $paramod$7714b1debbef4f2cb52c6ca29c9bc451325cf285\$__mul_wrapper for cells of type $__mul_wrapper.
Using template $paramod$7ad0a2715cbe7438acc372ec84186a7c022b6ee1\$__add_wrapper for cells of type $__add_wrapper.
No more expansions possible.
<suppressed ~44 debug messages>
Removed 0 unused cells and 14 unused wires.

21. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test1e.dot'.
Dumping module test1 to page 1.

22. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_test2e.dot'.
Dumping module test2 to page 1.

23. Generating Graphviz representation of design.
Writing dot description to `macc_xilinx_xmap.dot'.
Dumping module DSP48_MACC to page 1.

End of script. Logfile hash: 750c951a95, CPU: user 0.05s system 0.01s, MEM: 14.43 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 33% 12x clean (0 sec), 17% 5x techmap (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/macc'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/opt'
../../../../yosys opt_share.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `opt_share.ys' --

1. Executing Verilog-2005 frontend: <<EOT
Parsing Verilog input from `<<EOT' to AST representation.
Generating RTLIL representation for module `\uut'.
Successfully finished Verilog frontend.

2. Executing OPT_SHARE pass.
    Found cells that share an operand and can be merged by moving the $mux $ternary$<<EOT:7$3 in front of them:
        $add$<<EOT:7$1
        $sub$<<EOT:7$2

Removed 0 unused cells and 4 unused wires.

3. Generating Graphviz representation of design.
Writing dot description to `opt_share_full.dot'.
Dumping module after to page 1.
Dumping module uut to page 2.

End of script. Logfile hash: 7082042be4, CPU: user 0.01s system 0.00s, MEM: 11.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 48% 1x clean (0 sec), 22% 1x show (0 sec), ...
gvpack -u -o opt_share.dot opt_share_full.dot
Warning: node n4 in graph[1] uut already defined
Some nodes will be renamed.
../../../../yosys opt_muxtree.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `opt_muxtree.ys' --

1. Executing Verilog-2005 frontend: <<EOT
Parsing Verilog input from `<<EOT' to AST representation.
Generating RTLIL representation for module `\uut'.
Successfully finished Verilog frontend.

2. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \after..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $ternary$<<EOT:6$1.
Removed 1 multiplexer ports.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

3. Generating Graphviz representation of design.
Writing dot description to `opt_muxtree_full.dot'.
Dumping module after to page 1.
Dumping module uut to page 2.

End of script. Logfile hash: b6e098eb19, CPU: user 0.00s system 0.00s, MEM: 11.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 47% 1x clean (0 sec), 25% 1x show (0 sec), ...
gvpack -u -o opt_muxtree.dot opt_muxtree_full.dot
Warning: node n2 in graph[1] uut already defined
Some nodes will be renamed.
../../../../yosys opt_merge.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `opt_merge.ys' --

1. Executing Verilog-2005 frontend: <<EOT
Parsing Verilog input from `<<EOT' to AST representation.
Generating RTLIL representation for module `\uut'.
Successfully finished Verilog frontend.

2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\after'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.
Removed 0 unused cells and 4 unused wires.

3. Generating Graphviz representation of design.
Writing dot description to `opt_merge_full.dot'.
Dumping module after to page 1.
Dumping module uut to page 2.

End of script. Logfile hash: dedbdef5c2, CPU: user 0.00s system 0.01s, MEM: 11.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 38% 1x clean (0 sec), 24% 1x opt_merge (0 sec), ...
gvpack -u -o opt_merge.dot opt_merge_full.dot
Warning: node n1 in graph[1] uut already defined
Some nodes will be renamed.
../../../../yosys opt_expr.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `opt_expr.ys' --

1. Executing Verilog-2005 frontend: <<EOT
Parsing Verilog input from `<<EOT' to AST representation.
Generating RTLIL representation for module `\uut'.
Successfully finished Verilog frontend.

2. Executing OPT_EXPR pass (perform const folding).
Optimizing module after.
<suppressed ~2 debug messages>
Removed 0 unused cells and 4 unused wires.

3. Generating Graphviz representation of design.
Writing dot description to `opt_expr_full.dot'.
Dumping module after to page 1.
Dumping module uut to page 2.

End of script. Logfile hash: 1d1df32b64, CPU: user 0.01s system 0.00s, MEM: 11.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 43% 1x opt_expr (0 sec), 25% 1x clean (0 sec), ...
gvpack -u -o opt_expr.dot opt_expr_full.dot
Warning: node n1 in graph[1] uut already defined
Some nodes will be renamed.
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/opt'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/scrambler'
../../../../yosys scrambler.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `scrambler.ys' --

1. Executing Verilog-2005 frontend: scrambler.v
Parsing Verilog input from `scrambler.v' to AST representation.
Generating RTLIL representation for module `\scrambler'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$scrambler.v:6$1 in module scrambler.
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\scrambler.$proc$scrambler.v:6$1'.
     1/1: $1\xs[31:0]

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\scrambler.\out_bit' using process `\scrambler.$proc$scrambler.v:6$1'.
  created $dff cell `$procdff$12' with positive edge clock.
Creating register for signal `\scrambler.\xs' using process `\scrambler.$proc$scrambler.v:6$1'.
  created $dff cell `$procdff$13' with positive edge clock.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\scrambler.$proc$scrambler.v:6$1'.
Removing empty process `scrambler.$proc$scrambler.v:6$1'.
Cleaned up 1 empty switch.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module scrambler.
<suppressed ~3 debug messages>
Removed 0 unused cells and 5 unused wires.

4. Executing SUBMOD pass (moving cells to submodules as requested).

4.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \scrambler..

4.2. Continuing SUBMOD pass.
Creating submodule xorshift32 (\xorshift32) of module \scrambler.
  signal $1\xs[31:0]: input \n1
  signal $0\xs[31:0]: output \n2
  signal $shl$scrambler.v:11$6_Y: internal
  signal $xor$scrambler.v:9$3_Y: internal
  signal $shr$scrambler.v:10$4_Y: internal
  signal $xor$scrambler.v:10$5_Y: internal
  cell $xor$scrambler.v:9$3 ($xor)
  cell $xor$scrambler.v:11$7 ($xor)
  cell $xor$scrambler.v:10$5 ($xor)

5. Generating Graphviz representation of design.
Writing dot description to `scrambler_p01.dot'.
Dumping module scrambler to page 1.

6. Generating Graphviz representation of design.
Writing dot description to `scrambler_p02.dot'.
Dumping module xorshift32 to page 1.
echo on

yosys> cd xorshift32

yosys [xorshift32]> rename n2 in
Renaming wire n2 to in in module xorshift32.

yosys [xorshift32]> rename n1 out
Renaming wire n1 to out in module xorshift32.

yosys [xorshift32]> eval -set in 1 -show out

7. Executing EVAL pass (evaluate the circuit given an input).
Failed to evaluate signal \out: Missing value for \out.

yosys [xorshift32]> eval -set in 270369 -show out

8. Executing EVAL pass (evaluate the circuit given an input).
Failed to evaluate signal \out: Missing value for \out.

yosys [xorshift32]> sat -set out 632435482

9. Executing SAT pass (solving SAT problems in the circuit).

Setting up SAT problem:
Import set-constraint: \out = 632435482
Final constraint equation: \out = 632435482
Imported 3 cells to SAT database.

Solving problem with 665 variables and 1735 clauses..
SAT solving finished - model found:

  Signal Name             Dec       Hex                                 Bin
  --------------- ----------- --------- -----------------------------------
  \out              632435482  25b2331a    00100101101100100011001100011010

End of script. Logfile hash: 46ebf2918d, CPU: user 0.01s system 0.01s, MEM: 14.25 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 23% 1x sat (0 sec), 18% 1x submod (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/scrambler'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/selections'
../../../../yosys select.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `select.ys' --

1. Executing Verilog-2005 frontend: select.v
Parsing Verilog input from `select.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Analyzing design hierarchy..
Top module:  \test

2.1.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 2 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$select.v:7$1'.

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\test.\b' using process `\test.$proc$select.v:7$1'.
  created $dff cell `$procdff$8' with positive edge clock.
Creating register for signal `\test.\c' using process `\test.$proc$select.v:7$1'.
  created $dff cell `$procdff$9' with positive edge clock.

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `test.$proc$select.v:7$1'.
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~1 debug messages>

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module test...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

2.7.8. Rerunning OPT passes. (Maybe there is more to do..)

2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

2.7.11. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.7.13. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

2.7.14. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== test ===

   Number of wires:                  9
   Number of wire bits:            114
   Number of public wires:           8
   Number of public wire bits:      98
   Number of ports:                  4
   Number of port bits:             34
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  6
     $add                            1
     $dff                            2
     $mux                            1
     $sub                            1
     $xor                            1

2.13. Executing CHECK pass (checking for obvious problems).
Checking module test...
Found and reported 0 problems.

3. Generating Graphviz representation of design.
Writing dot description to `select.dot'.
Dumping module test to page 1.

End of script. Logfile hash: f11d6793ac, CPU: user 0.02s system 0.00s, MEM: 13.25 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 28% 6x opt_expr (0 sec), 25% 5x opt_clean (0 sec), ...
../../../../yosys memdemo.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `memdemo.ys' --

1. Executing Verilog-2005 frontend: memdemo.v
Parsing Verilog input from `memdemo.v' to AST representation.
Generating RTLIL representation for module `\memdemo'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Analyzing design hierarchy..
Top module:  \memdemo

2.1.2. Analyzing design hierarchy..
Top module:  \memdemo
Removed 0 unused modules.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 14 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'.

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$35' with positive edge clock.
Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$36' with positive edge clock.
Creating register for signal `\memdemo.\s1' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$37' with positive edge clock.
Creating register for signal `\memdemo.\s2' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$38' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$39' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$40' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$41' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$42' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$43' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$44' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$45' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$46' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_ADDR' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$47' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$48' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$49' with positive edge clock.

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `memdemo.$proc$memdemo.v:11$7'.
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 12 unused cells and 26 unused wires.
<suppressed ~14 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module memdemo...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 4 unused wires.
<suppressed ~1 debug messages>

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.8. Rerunning OPT passes. (Maybe there is more to do..)

2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

2.7.11. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.7.13. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.14. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$53 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$19 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$20 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$23 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== memdemo ===

   Number of wires:                 18
   Number of wire bits:             58
   Number of public wires:           5
   Number of public wire bits:      13
   Number of ports:                  3
   Number of port bits:              9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $add                            4
     $dff                            3
     $mem_v2                         1
     $mux                            1
     $reduce_bool                    1
     $xor                            1

2.13. Executing CHECK pass (checking for obvious problems).
Checking module memdemo...
Found and reported 0 problems.

3. Executing MEMORY pass.

3.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 6 transformations.

3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing memdemo.mem write port 0.
  Analyzing memdemo.mem write port 1.
  Analyzing memdemo.mem write port 2.
  Analyzing memdemo.mem write port 3.
  Analyzing memdemo.mem write port 4.

3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell.
    Write port 0: non-transparent.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
    Write port 3: non-transparent.
    Write port 4: non-transparent.
Checking read port `\mem'[1] in module `\memdemo': no output FF found.
Checking read port `\mem'[2] in module `\memdemo': no output FF found.
Checking read port `\mem'[3] in module `\memdemo': no output FF found.
Checking read port `\mem'[4] in module `\memdemo': no output FF found.
Checking read port address `\mem'[1] in module `\memdemo': no address FF found.
Checking read port address `\mem'[2] in module `\memdemo': no address FF found.
Checking read port address `\mem'[3] in module `\memdemo': no address FF found.
Checking read port address `\mem'[4] in module `\memdemo': no address FF found.

3.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 1 unused cells and 5 unused wires.
<suppressed ~2 debug messages>

3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory memdemo.mem by address:
  Merging ports 1, 4 (address 2'00).
  Merging ports 2, 3 (address 2'11).
Consolidating read ports of memory memdemo.mem by address:
  Merging ports 1, 2 (address 2'00).
Consolidating read ports of memory memdemo.mem by address:
Consolidating write ports of memory memdemo.mem by address:
  Merging ports 0, 1 (address 2'00).
  Merging ports 0, 2 (address 2'00).
Consolidating write ports of memory memdemo.mem by address:

3.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>

3.10. Executing MEMORY_COLLECT pass (generating $mem cells).

3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \mem in module \memdemo:
  created 4 $dff cells and 0 static cells of width 4.
Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0]
  read interface: 1 $dff and 3 $mux cells.
  write interface: 12 write mux blocks.

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.
<suppressed ~20 debug messages>

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 28 unused wires.
<suppressed ~1 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Generating Graphviz representation of design.
Writing dot description to `memdemo_00.dot'.
Dumping module memdemo to page 1.

6. Generating Graphviz representation of design.
Writing dot description to `memdemo_01.dot'.
Dumping selected parts of module memdemo to page 1.

7. Generating Graphviz representation of design.
Writing dot description to `memdemo_02.dot'.
Dumping selected parts of module memdemo to page 1.

8. Generating Graphviz representation of design.
Writing dot description to `memdemo_03.dot'.
Dumping selected parts of module memdemo to page 1.

9. Generating Graphviz representation of design.
Writing dot description to `memdemo_04.dot'.
Dumping selected parts of module memdemo to page 1.

10. Generating Graphviz representation of design.
Writing dot description to `memdemo_05.dot'.
Dumping selected parts of module memdemo to page 1.

End of script. Logfile hash: ade9f67caf, CPU: user 0.03s system 0.01s, MEM: 14.25 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 22% 9x opt_expr (0 sec), 20% 9x opt_clean (0 sec), ...
../../../../yosys submod.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `submod.ys' --

1. Executing Verilog-2005 frontend: memdemo.v
Parsing Verilog input from `memdemo.v' to AST representation.
Generating RTLIL representation for module `\memdemo'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Analyzing design hierarchy..
Top module:  \memdemo

2.1.2. Analyzing design hierarchy..
Top module:  \memdemo
Removed 0 unused modules.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 14 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\memdemo.$proc$memdemo.v:11$7'.

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\memdemo.\y' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$35' with positive edge clock.
Creating register for signal `\memdemo.\i' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$36' with positive edge clock.
Creating register for signal `\memdemo.\s1' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$37' with positive edge clock.
Creating register for signal `\memdemo.\s2' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$38' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$39' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$2_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$40' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$41' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$3_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$42' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$43' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$4_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$44' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$45' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:13$5_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$46' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_ADDR' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$47' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_DATA' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$48' with positive edge clock.
Creating register for signal `\memdemo.$memwr$\mem$memdemo.v:15$6_EN' using process `\memdemo.$proc$memdemo.v:11$7'.
  created $dff cell `$procdff$49' with positive edge clock.

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `memdemo.$proc$memdemo.v:11$7'.
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 12 unused cells and 26 unused wires.
<suppressed ~14 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module memdemo...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
<suppressed ~12 debug messages>
Removed a total of 4 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 4 unused wires.
<suppressed ~1 debug messages>

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.8. Rerunning OPT passes. (Maybe there is more to do..)

2.7.9. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

2.7.10. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

2.7.11. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.7.12. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.7.13. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.7.14. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$50 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$51 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$52 (mem).
Removed top 30 address bits (of 32) from memory init port memdemo.$auto$proc_memwr.cc:45:proc_memwr$53 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$19 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$20 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$23 (mem).
Removed top 30 address bits (of 32) from memory read port memdemo.$memrd$\mem$memdemo.v:13$26 (mem).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== memdemo ===

   Number of wires:                 18
   Number of wire bits:             58
   Number of public wires:           5
   Number of public wire bits:      13
   Number of ports:                  3
   Number of port bits:              9
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                 11
     $add                            4
     $dff                            3
     $mem_v2                         1
     $mux                            1
     $reduce_bool                    1
     $xor                            1

2.13. Executing CHECK pass (checking for obvious problems).
Checking module memdemo...
Found and reported 0 problems.

3. Executing MEMORY pass.

3.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

3.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 6 transformations.

3.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing memdemo.mem write port 0.
  Analyzing memdemo.mem write port 1.
  Analyzing memdemo.mem write port 2.
  Analyzing memdemo.mem write port 3.
  Analyzing memdemo.mem write port 4.

3.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

3.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\mem'[0] in module `\memdemo': merging output FF to cell.
    Write port 0: non-transparent.
    Write port 1: non-transparent.
    Write port 2: non-transparent.
    Write port 3: non-transparent.
    Write port 4: non-transparent.
Checking read port `\mem'[1] in module `\memdemo': no output FF found.
Checking read port `\mem'[2] in module `\memdemo': no output FF found.
Checking read port `\mem'[3] in module `\memdemo': no output FF found.
Checking read port `\mem'[4] in module `\memdemo': no output FF found.
Checking read port address `\mem'[1] in module `\memdemo': no address FF found.
Checking read port address `\mem'[2] in module `\memdemo': no address FF found.
Checking read port address `\mem'[3] in module `\memdemo': no address FF found.
Checking read port address `\mem'[4] in module `\memdemo': no address FF found.

3.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 1 unused cells and 5 unused wires.
<suppressed ~2 debug messages>

3.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory memdemo.mem by address:
  Merging ports 1, 4 (address 2'00).
  Merging ports 2, 3 (address 2'11).
Consolidating read ports of memory memdemo.mem by address:
  Merging ports 1, 2 (address 2'00).
Consolidating read ports of memory memdemo.mem by address:
Consolidating write ports of memory memdemo.mem by address:
  Merging ports 0, 1 (address 2'00).
  Merging ports 0, 2 (address 2'00).
Consolidating write ports of memory memdemo.mem by address:

3.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

3.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 5 unused wires.
<suppressed ~1 debug messages>

3.10. Executing MEMORY_COLLECT pass (generating $mem cells).

3.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \mem in module \memdemo:
  created 4 $dff cells and 0 static cells of width 4.
Extracted data FF from read port 0 of memdemo.mem: $\mem$rdreg[0]
  read interface: 1 $dff and 3 $mux cells.
  write interface: 12 write mux blocks.

4. Executing OPT pass (performing simple optimizations).

4.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.
<suppressed ~20 debug messages>

4.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

4.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

4.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.6. Executing OPT_DFF pass (perform DFF optimizations).

4.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 28 unused wires.
<suppressed ~1 debug messages>

4.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

4.9. Rerunning OPT passes. (Maybe there is more to do..)

4.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \memdemo..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~6 debug messages>

4.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \memdemo.
Performed a total of 0 changes.

4.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\memdemo'.
Removed a total of 0 cells.

4.13. Executing OPT_DFF pass (perform DFF optimizations).

4.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

4.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module memdemo.

4.16. Finished OPT passes. (There is nothing left to do.)

5. Executing SUBMOD pass (moving cells to submodules as requested).

5.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..

5.2. Continuing SUBMOD pass.
Creating submodule scramble (\scramble) of module \memdemo.
  signal \clk: input \clk
  signal \d: input \d
  signal $memory\mem$wrmux[2][2][0]$y$131: internal
  signal $auto$rtlil.cc:2771:And$103: internal
  signal \mem[2]: output \mem[2]
  signal $auto$rtlil.cc:2771:And$141: internal
  signal \mem[3]: output \mem[3]
  signal $memory\mem$wrmux[0][2][0]$y$105: internal
  signal $auto$rtlil.cc:2778:Eq$99: internal
  signal $0$memwr$\mem$memdemo.v:13$2_DATA[3:0]$8: internal
  signal $0$memwr$\mem$memdemo.v:13$3_DATA[3:0]$10: internal
  signal $0$memwr$\mem$memdemo.v:13$4_DATA[3:0]$12: internal
  signal $0$memwr$\mem$memdemo.v:13$5_DATA[3:0]$14: internal
  signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: input \n1
  signal $auto$rtlil.cc:2778:Eq$101: internal
  signal $memory\mem$wrmux[3][2][0]$y$143: internal
  signal $memory\mem$wrmux[1][2][0]$y$119: internal
  signal \mem[1]: output \mem[1]
  signal $auto$rtlil.cc:2771:And$129: internal
  signal \mem[0]: output \mem[0]
  signal $auto$rtlil.cc:2771:And$117: internal
  cell $memory\mem[3]$77 ($dff)
  cell $memory\mem[2]$75 ($dff)
  cell $memory\mem[1]$73 ($dff)
  cell $memory\mem[0]$71 ($dff)
  cell $memory\mem$wrmux[3][2][0]$142 ($mux)
  cell $memory\mem$wrmux[2][2][0]$130 ($mux)
  cell $memory\mem$wrmux[1][2][0]$118 ($mux)
  cell $memory\mem$wrmux[0][2][0]$104 ($mux)
  cell $auto$memory_map.cc:97:addr_decode$140 ($and)
  cell $auto$memory_map.cc:97:addr_decode$128 ($and)
  cell $auto$memory_map.cc:97:addr_decode$116 ($and)
  cell $auto$memory_map.cc:97:addr_decode$102 ($and)
  cell $auto$memory_map.cc:92:addr_decode$98 ($not)
  cell $auto$memory_map.cc:92:addr_decode$100 ($not)
  cell $add$memdemo.v:13$30 ($add)
  cell $add$memdemo.v:13$27 ($add)
  cell $add$memdemo.v:13$24 ($add)
  cell $add$memdemo.v:13$21 ($add)

6. Executing SUBMOD pass (moving cells to submodules as requested).

6.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 14 unused wires.
<suppressed ~1 debug messages>

6.2. Continuing SUBMOD pass.
Creating submodule outstage (\outstage) of module \memdemo.
  signal \clk: input \clk
  signal \mem[2]: input \mem[2]
  signal \mem[3]: input \mem[3]
  signal $\mem$rdreg[0]$d: internal
  signal \y: output \y
  signal $0\s2[1:0]: input \n1
  signal $memory\mem$rdmux[0][0][0]$a$80: internal
  signal $memory\mem$rdmux[0][0][0]$b$81: internal
  signal \mem[1]: input \mem[1]
  signal \mem[0]: input \mem[0]
  cell $memory\mem$rdmux[0][1][1]$85 ($mux)
  cell $memory\mem$rdmux[0][1][0]$82 ($mux)
  cell $memory\mem$rdmux[0][0][0]$79 ($mux)
  cell $\mem$rdreg[0] ($dff)

7. Executing SUBMOD pass (moving cells to submodules as requested).

7.1. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \memdemo..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

7.2. Continuing SUBMOD pass.
Creating submodule selstage (\selstage) of module \memdemo.
  signal \d: input \d
  signal \s1: input \s1
  signal \s2: input \s2
  signal $0\s2[1:0]: output \n1
  signal $0$memwr$\mem$memdemo.v:15$6_ADDR[1:0]$16: output \n2
  signal $reduce_bool$memdemo.v:14$32_Y: internal
  signal $xor$memdemo.v:14$31_Y: internal
  cell $xor$memdemo.v:14$31 ($xor)
  cell $ternary$memdemo.v:14$33 ($mux)
  cell $reduce_bool$memdemo.v:14$32 ($reduce_bool)

8. Generating Graphviz representation of design.
Writing dot description to `submod_00.dot'.
Dumping module memdemo to page 1.

9. Generating Graphviz representation of design.
Writing dot description to `submod_01.dot'.
Dumping module scramble to page 1.

10. Generating Graphviz representation of design.
Writing dot description to `submod_02.dot'.
Dumping module outstage to page 1.

11. Generating Graphviz representation of design.
Writing dot description to `submod_03.dot'.
Dumping module selstage to page 1.

End of script. Logfile hash: af1a08dc26, CPU: user 0.04s system 0.00s, MEM: 14.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 24% 12x opt_clean (0 sec), 21% 9x opt_expr (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/selections'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/show'
../../../../yosys -p 'prep -top splice_demo; show -format dot -prefix splice' splice.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Parsing `splice.v' using frontend ` -vlog2k' --

1. Executing Verilog-2005 frontend: splice.v
Parsing Verilog input from `splice.v' to AST representation.
Storing AST representation for module `$abstract\splice_demo'.
Successfully finished Verilog frontend.

-- Running command `prep -top splice_demo; show -format dot -prefix splice' --

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\splice_demo'.
Generating RTLIL representation for module `\splice_demo'.

2.2.1. Analyzing design hierarchy..
Top module:  \splice_demo

2.2.2. Analyzing design hierarchy..
Top module:  \splice_demo
Removing unused module `$abstract\splice_demo'.
Removed 1 unused modules.

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).

2.3.5. Executing PROC_ARST pass (detect async resets in processes).

2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module splice_demo.

2.4. Executing FUTURE pass.

2.5. Executing OPT_EXPR pass (perform const folding).
Optimizing module splice_demo.

2.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \splice_demo..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

2.7. Executing CHECK pass (checking for obvious problems).
Checking module splice_demo...
Found and reported 0 problems.

2.8. Executing OPT pass (performing simple optimizations).

2.8.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module splice_demo.

2.8.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\splice_demo'.
Removed a total of 0 cells.

2.8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \splice_demo..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \splice_demo.
Performed a total of 0 changes.

2.8.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\splice_demo'.
Removed a total of 0 cells.

2.8.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \splice_demo..

2.8.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module splice_demo.

2.8.8. Finished OPT passes. (There is nothing left to do.)

2.9. Executing WREDUCE pass (reducing word size of cells).

2.10. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \splice_demo..

2.11. Executing MEMORY_COLLECT pass (generating $mem cells).

2.12. Executing OPT pass (performing simple optimizations).

2.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module splice_demo.

2.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\splice_demo'.
Removed a total of 0 cells.

2.12.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \splice_demo..

2.12.4. Finished fast OPT passes.

2.13. Printing statistics.

=== splice_demo ===

   Number of wires:                  8
   Number of wire bits:             26
   Number of public wires:           8
   Number of public wire bits:      26
   Number of ports:                  8
   Number of port bits:             26
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  2
     $neg                            1
     $not                            1

2.14. Executing CHECK pass (checking for obvious problems).
Checking module splice_demo...
Found and reported 0 problems.

3. Generating Graphviz representation of design.
Writing dot description to `splice.dot'.
Dumping module splice_demo to page 1.

End of script. Logfile hash: 2eeb6955f1, CPU: user 0.01s system 0.01s, MEM: 13.12 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 32% 5x opt_expr (0 sec), 25% 4x opt_clean (0 sec), ...
../../../../yosys example.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `example.ys' --

1. Executing Verilog-2005 frontend: example.v
Parsing Verilog input from `example.v' to AST representation.
Generating RTLIL representation for module `\example'.
Successfully finished Verilog frontend.

2. Generating Graphviz representation of design.
Writing dot description to `example_first.dot'.
Dumping module example to page 1.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\example.$proc$example.v:3$1'.
     1/1: $0\y[1:0]

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\example.\y' using process `\example.$proc$example.v:3$1'.
  created $dff cell `$procdff$6' with positive edge clock.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\example.$proc$example.v:3$1'.
Removing empty process `example.$proc$example.v:3$1'.
Cleaned up 1 empty switch.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module example.

4. Generating Graphviz representation of design.
Writing dot description to `example_second.dot'.
Dumping module example to page 1.

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module example.

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\example'.
Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \example..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $ternary$example.v:5$3.
Removed 1 multiplexer ports.
<suppressed ~1 debug messages>

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \example.
Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\example'.
Removed a total of 0 cells.

5.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $procdff$6 ($dff) from module example (D = $ternary$example.v:5$3_Y, Q = \y).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \example..
Removed 1 unused cells and 4 unused wires.
<suppressed ~2 debug messages>

5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module example.

5.9. Rerunning OPT passes. (Maybe there is more to do..)

5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \example..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \example.
Performed a total of 0 changes.

5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\example'.
Removed a total of 0 cells.

5.13. Executing OPT_DFF pass (perform DFF optimizations).

5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \example..

5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module example.

5.16. Finished OPT passes. (There is nothing left to do.)

6. Generating Graphviz representation of design.
Writing dot description to `example_third.dot'.
Dumping module example to page 1.

End of script. Logfile hash: 1968fcbfd1, CPU: user 0.01s system 0.01s, MEM: 13.25 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 31% 4x opt_expr (0 sec), 15% 3x show (0 sec), ...
../../../../yosys cmos.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `cmos.ys' --

1. Executing Verilog-2005 frontend: cmos.v
Parsing Verilog input from `cmos.v' to AST representation.
Generating RTLIL representation for module `\cmos_demo'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Analyzing design hierarchy..
Top module:  \cmos_demo

2.1.2. Analyzing design hierarchy..
Top module:  \cmos_demo
Removed 0 unused modules.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module cmos_demo...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cmos_demo..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cmos_demo.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

2.7.8. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== cmos_demo ===

   Number of wires:                  3
   Number of wire bits:              4
   Number of public wires:           3
   Number of public wire bits:       4
   Number of ports:                  3
   Number of port bits:              4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     $add                            1

2.13. Executing CHECK pass (checking for obvious problems).
Checking module cmos_demo...
Found and reported 0 problems.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

3.2. Continuing TECHMAP pass.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $and.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $mux.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~228 debug messages>

4. Executing ABC pass (technology mapping using ABC).

4.1. Extracting gate netlist of module `\cmos_demo' to `<abc-temp-dir>/input.blif'..
Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs.

4.1.1. Executing ABC.
Running ABC command: "/usr/bin/abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w <yosys-exe-dir>/docs/source/code_examples/show/../intro/mycells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Warning: Templates are not defined.
ABC: Liberty parser cannot read "time_unit".  Assuming   time_unit : "1ns".
ABC: Liberty parser cannot read "capacitive_load_unit". Assuming   capacitive_load_unit(1, pf).
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF".
ABC: Library "demo" from "<yosys-exe-dir>/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.01 MB. Time =     0.00 sec
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 

4.1.2. Re-integrating ABC results.
ABC RESULTS:               NOT cells:        2
ABC RESULTS:               NOR cells:        3
ABC RESULTS:        internal signals:       14
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        2
Removing temp directory.
Removed 0 unused cells and 36 unused wires.

5. Generating Graphviz representation of design.
Writing dot description to `cmos_00.dot'.
Dumping module cmos_demo to page 1.

6. Executing Verilog-2005 frontend: cmos.v
Parsing Verilog input from `cmos.v' to AST representation.
Generating RTLIL representation for module `\cmos_demo'.
Successfully finished Verilog frontend.

7. Executing PREP pass.

7.1. Executing HIERARCHY pass (managing design hierarchy).

7.1.1. Analyzing design hierarchy..
Top module:  \cmos_demo

7.1.2. Analyzing design hierarchy..
Top module:  \cmos_demo
Removed 0 unused modules.

7.2. Executing PROC pass (convert processes to netlists).

7.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

7.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

7.2.4. Executing PROC_INIT pass (extract init attributes).

7.2.5. Executing PROC_ARST pass (detect async resets in processes).

7.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

7.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

7.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

7.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

7.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

7.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

7.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

7.3. Executing FUTURE pass.

7.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

7.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

7.6. Executing CHECK pass (checking for obvious problems).
Checking module cmos_demo...
Found and reported 0 problems.

7.7. Executing OPT pass (performing simple optimizations).

7.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

7.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

7.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \cmos_demo..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

7.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \cmos_demo.
Performed a total of 0 changes.

7.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

7.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

7.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

7.7.8. Finished OPT passes. (There is nothing left to do.)

7.8. Executing WREDUCE pass (reducing word size of cells).

7.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

7.10. Executing MEMORY_COLLECT pass (generating $mem cells).

7.11. Executing OPT pass (performing simple optimizations).

7.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module cmos_demo.

7.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\cmos_demo'.
Removed a total of 0 cells.

7.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \cmos_demo..

7.11.4. Finished fast OPT passes.

7.12. Printing statistics.

=== cmos_demo ===

   Number of wires:                  3
   Number of wire bits:              4
   Number of public wires:           3
   Number of public wire bits:       4
   Number of ports:                  3
   Number of port bits:              4
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                  1
     $add                            1

7.13. Executing CHECK pass (checking for obvious problems).
Checking module cmos_demo...
Found and reported 0 problems.

8. Executing TECHMAP pass (map to technology primitives).

8.1. Executing Verilog-2005 frontend: /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v
Parsing Verilog input from `/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

8.2. Continuing TECHMAP pass.
Running "alumacc" on wrapper $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47 for cells of type $extern:wrap:$add:A_SIGNED=0:A_WIDTH=1:B_SIGNED=0:B_WIDTH=1:Y_WIDTH=2:394426c56d1a028ba8fdd5469b163e04011def47.
Using template $paramod$1d1e68f77481583066c6d429218f48ea9d5739b3\_90_alu for cells of type $alu.
Using extmapper simplemap for cells of type $xor.
Using extmapper simplemap for cells of type $pos.
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $mux.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $or.
No more expansions possible.
<suppressed ~228 debug messages>

9. Executing SPLITNETS pass (splitting up multi-bit signals).

10. Executing ABC pass (technology mapping using ABC).

10.1. Extracting gate netlist of module `\cmos_demo' to `<abc-temp-dir>/input.blif'..
Extracted 15 gates and 18 wires to a netlist network with 2 inputs and 2 outputs.

10.1.1. Executing ABC.
Running ABC command: "/usr/bin/abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_blif <abc-temp-dir>/input.blif 
ABC: + read_lib -w <yosys-exe-dir>/docs/source/code_examples/show/../intro/mycells.lib 
ABC: Parsing finished successfully.  Parsing time =     0.00 sec
ABC: Warning: Templates are not defined.
ABC: Liberty parser cannot read "time_unit".  Assuming   time_unit : "1ns".
ABC: Liberty parser cannot read "capacitive_load_unit". Assuming   capacitive_load_unit(1, pf).
ABC: Scl_LibertyReadGenlib() skipped sequential cell "DFF".
ABC: Library "demo" from "<yosys-exe-dir>/docs/source/code_examples/show/../intro/mycells.lib" has 4 cells (1 skipped: 1 seq; 0 tri-state; 0 no func; 0 dont_use).  Time =     0.00 sec
ABC: Memory =    0.01 MB. Time =     0.00 sec
ABC: + strash 
ABC: + &get -n 
ABC: + &fraig -x 
ABC: + &put 
ABC: + scorr 
ABC: Warning: The network is combinational (run "fraig" or "fraig_sweep").
ABC: + dc2 
ABC: + dretime 
ABC: + strash 
ABC: + &get -n 
ABC: + &dch -f 
ABC: + &nf 
ABC: + &put 
ABC: + write_blif <abc-temp-dir>/output.blif 

10.1.2. Re-integrating ABC results.
ABC RESULTS:               NOT cells:        2
ABC RESULTS:               NOR cells:        3
ABC RESULTS:        internal signals:       14
ABC RESULTS:           input signals:        2
ABC RESULTS:          output signals:        2
Removing temp directory.
Removed 0 unused cells and 1142 unused wires.

11. Generating Graphviz representation of design.

11.1. Executing Verilog-2005 frontend: ../intro/mycells.v
Parsing Verilog input from `../intro/mycells.v' to AST representation.
Generating RTLIL representation for module `\NOT'.
Generating RTLIL representation for module `\NAND'.
Generating RTLIL representation for module `\NOR'.
Generating RTLIL representation for module `\DFF'.
Successfully finished Verilog frontend.

11.2. Continuing show pass.
Writing dot description to `cmos_01.dot'.
Dumping module cmos_demo to page 1.

End of script. Logfile hash: 6d0be817d0, CPU: user 0.06s system 0.00s, MEM: 17.12 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 70% 2x abc (0 sec), 10% 7x read_verilog (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/show'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/stubnets'
make[4]: Nothing to be done for 'dots'.
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/stubnets'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/synth_flow'
../../../../yosys -p 'script proc_01.ys; show -notitle -prefix proc_01 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script proc_01.ys; show -notitle -prefix proc_01 -format dot' --

-- Executing script file `proc_01.ys' --

1. Executing Verilog-2005 frontend: proc_01.v
Parsing Verilog input from `proc_01.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$proc_01.v:2$1 in module test.
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \R in `\test.$proc$proc_01.v:2$1'.

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$proc_01.v:2$1'.
     1/1: $0\Q[0:0]

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\test.\Q' using process `\test.$proc$proc_01.v:2$1'.
  created $adff cell `$procdff$4' with positive edge clock and positive level reset.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `test.$proc$proc_01.v:2$1'.
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~1 debug messages>
Removed 0 unused cells and 2 unused wires.

4. Generating Graphviz representation of design.
Writing dot description to `proc_01.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 4fe5064e83, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 26% 1x opt_expr (0 sec), 22% 1x clean (0 sec), ...
../../../../yosys -p 'script proc_02.ys; show -notitle -prefix proc_02 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script proc_02.ys; show -notitle -prefix proc_02 -format dot' --

-- Executing script file `proc_02.ys' --

1. Executing Verilog-2005 frontend: proc_02.v
Parsing Verilog input from `proc_02.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$proc_02.v:3$1 in module test.
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 0 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \R in `\test.$proc$proc_02.v:3$1'.

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$proc_02.v:3$1'.
     1/1: $0\Q[0:0]

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\test.\Q' using process `\test.$proc$proc_02.v:3$1'.
Warning: Async reset value `\RV' is not constant!
  created $aldff cell `$procdff$4' with positive edge clock and positive level non-const reset.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `test.$proc$proc_02.v:3$1'.
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~1 debug messages>
Removed 0 unused cells and 2 unused wires.

4. Generating Graphviz representation of design.
Writing dot description to `proc_02.dot'.
Dumping module test to page 1.

Warnings: 1 unique messages, 1 total
End of script. Logfile hash: c4b4f83334, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 28% 1x opt_expr (0 sec), 22% 1x clean (0 sec), ...
../../../../yosys -p 'script proc_03.ys; show -notitle -prefix proc_03 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script proc_03.ys; show -notitle -prefix proc_03 -format dot' --

-- Executing script file `proc_03.ys' --

1. Executing Verilog-2005 frontend: proc_03.v
Parsing Verilog input from `proc_03.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~2 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$proc_03.v:3$1'.
     1/1: $0\Y[0:0]

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `\test.\Y' from process `\test.$proc$proc_03.v:3$1'.

3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 2 empty switches in `\test.$proc$proc_03.v:3$1'.
Removing empty process `test.$proc$proc_03.v:3$1'.
Cleaned up 2 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Removed 0 unused cells and 4 unused wires.

4. Generating Graphviz representation of design.
Writing dot description to `proc_03.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 5a538b5f7f, CPU: user 0.00s system 0.01s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 24% 1x opt_expr (0 sec), 23% 1x clean (0 sec), ...
../../../../yosys -p 'script memory_01.ys; show -notitle -prefix memory_01 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script memory_01.ys; show -notitle -prefix memory_01 -format dot' --

-- Executing script file `memory_01.ys' --

1. Executing Verilog-2005 frontend: memory_01.v
Parsing Verilog input from `memory_01.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$memory_01.v:5$2'.

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\test.\DOUT' using process `\test.$proc$memory_01.v:5$2'.
  created $dff cell `$procdff$7' with positive edge clock.
Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_ADDR' using process `\test.$proc$memory_01.v:5$2'.
  created $dff cell `$procdff$8' with positive edge clock.
Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_DATA' using process `\test.$proc$memory_01.v:5$2'.
  created $dff cell `$procdff$9' with positive edge clock.
Creating register for signal `\test.$memwr$\mem$memory_01.v:6$1_EN' using process `\test.$proc$memory_01.v:5$2'.
  created $dff cell `$procdff$10' with positive edge clock.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `test.$proc$memory_01.v:5$2'.
Cleaned up 0 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Removed 3 unused cells and 7 unused wires.

4. Executing MEMORY pass.

4.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing test.mem write port 0.

4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\mem'[0] in module `\test': merging output FF to cell.
    Write port 0: non-transparent.

4.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 1 unused cells and 9 unused wires.
<suppressed ~2 debug messages>

4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).

4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

4.10. Executing MEMORY_COLLECT pass (generating $mem cells).

4.11. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory \mem in module \test:
  created 2 $dff cells and 0 static cells of width 8.
Extracted data FF from read port 0 of test.mem: $\mem$rdreg[0]
  read interface: 1 $dff and 1 $mux cells.
  write interface: 2 write mux blocks.

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~3 debug messages>

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.6. Executing OPT_DFF pass (perform DFF optimizations).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 1 unused cells and 6 unused wires.
<suppressed ~2 debug messages>

5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

5.9. Rerunning OPT passes. (Maybe there is more to do..)

5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~3 debug messages>

5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $memory\mem[1]$23 ($dff) from module test (D = \DIN, Q = \mem[1]).
Adding EN signal on $memory\mem[0]$21 ($dff) from module test (D = \DIN, Q = \mem[0]).

5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 2 unused cells and 2 unused wires.
<suppressed ~3 debug messages>

5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

5.16. Rerunning OPT passes. (Maybe there is more to do..)

5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~1 debug messages>

5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

5.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.20. Executing OPT_DFF pass (perform DFF optimizations).

5.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

5.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

5.23. Finished OPT passes. (There is nothing left to do.)

6. Generating Graphviz representation of design.
Writing dot description to `memory_01.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 3f34ade637, CPU: user 0.02s system 0.00s, MEM: 13.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 30% 5x opt_expr (0 sec), 18% 5x opt_clean (0 sec), ...
../../../../yosys -p 'script memory_02.ys; show -notitle -prefix memory_02 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script memory_02.ys; show -notitle -prefix memory_02 -format dot' --

-- Executing script file `memory_02.ys' --

1. Executing Verilog-2005 frontend: memory_02.v
Parsing Verilog input from `memory_02.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing PROC pass (convert processes to netlists).

3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Marked 1 switch rules as full_case in process $proc$memory_02.v:17$10 in module test.
Marked 1 switch rules as full_case in process $proc$memory_02.v:13$3 in module test.
Removed a total of 0 dead cases.

3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 8 assignments to connections.

3.4. Executing PROC_INIT pass (extract init attributes).

3.5. Executing PROC_ARST pass (detect async resets in processes).

3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~2 debug messages>

3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\test.$proc$memory_02.v:24$19'.
Creating decoders for process `\test.$proc$memory_02.v:21$17'.
Creating decoders for process `\test.$proc$memory_02.v:17$10'.
     1/3: $1$memwr$\memory$memory_02.v:19$2_EN[7:0]$16
     2/3: $1$memwr$\memory$memory_02.v:19$2_DATA[7:0]$15
     3/3: $1$memwr$\memory$memory_02.v:19$2_ADDR[7:0]$14
Creating decoders for process `\test.$proc$memory_02.v:13$3'.
     1/3: $1$memwr$\memory$memory_02.v:15$1_EN[7:0]$9
     2/3: $1$memwr$\memory$memory_02.v:15$1_DATA[7:0]$8
     3/3: $1$memwr$\memory$memory_02.v:15$1_ADDR[7:0]$7

3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\test.\RD2_DATA' using process `\test.$proc$memory_02.v:24$19'.
  created $dff cell `$procdff$39' with positive edge clock.
Creating register for signal `\test.\RD1_DATA' using process `\test.$proc$memory_02.v:21$17'.
  created $dff cell `$procdff$40' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_ADDR' using process `\test.$proc$memory_02.v:17$10'.
  created $dff cell `$procdff$41' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_DATA' using process `\test.$proc$memory_02.v:17$10'.
  created $dff cell `$procdff$42' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:19$2_EN' using process `\test.$proc$memory_02.v:17$10'.
  created $dff cell `$procdff$43' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_ADDR' using process `\test.$proc$memory_02.v:13$3'.
  created $dff cell `$procdff$44' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_DATA' using process `\test.$proc$memory_02.v:13$3'.
  created $dff cell `$procdff$45' with positive edge clock.
Creating register for signal `\test.$memwr$\memory$memory_02.v:15$1_EN' using process `\test.$proc$memory_02.v:13$3'.
  created $dff cell `$procdff$46' with positive edge clock.

3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `test.$proc$memory_02.v:24$19'.
Removing empty process `test.$proc$memory_02.v:21$17'.
Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:17$10'.
Removing empty process `test.$proc$memory_02.v:17$10'.
Found and cleaned up 1 empty switch in `\test.$proc$memory_02.v:13$3'.
Removing empty process `test.$proc$memory_02.v:13$3'.
Cleaned up 2 empty switches.

3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
Removed 6 unused cells and 26 unused wires.

4. Executing MEMORY pass.

4.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 0 transformations.

4.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 0 transformations.

4.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
  Analyzing test.memory write port 0.
  Analyzing test.memory write port 1.

4.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

4.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `\memory'[0] in module `\test': merging output FF to cell.
Checking read port `\memory'[1] in module `\test': merging output FF to cell.

4.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 2 unused cells and 18 unused wires.
<suppressed ~3 debug messages>

4.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating read ports of memory test.memory by address:
Consolidating write ports of memory test.memory by address:
Consolidating write ports of memory test.memory using sat-based resource sharing:

4.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

4.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

4.10. Executing MEMORY_COLLECT pass (generating $mem cells).

5. Executing OPT pass (performing simple optimizations).

5.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~4 debug messages>

5.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~2 debug messages>

5.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
    Consolidated identical input bits for $mux cell $procmux$31:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6
      New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0]
      New connections: $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [7:1] = { $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] $0$memwr$\memory$memory_02.v:15$1_EN[7:0]$6 [0] }
    Consolidated identical input bits for $mux cell $procmux$22:
      Old ports: A=8'00000000, B=8'11111111, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13
      New ports: A=1'0, B=1'1, Y=$0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0]
      New connections: $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [7:1] = { $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] $0$memwr$\memory$memory_02.v:19$2_EN[7:0]$13 [0] }
  Optimizing cells in module \test.
Performed a total of 2 changes.

5.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.6. Executing OPT_DFF pass (perform DFF optimizations).

5.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 0 unused cells and 4 unused wires.
<suppressed ~1 debug messages>

5.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.
<suppressed ~2 debug messages>

5.9. Rerunning OPT passes. (Maybe there is more to do..)

5.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

5.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.13. Executing OPT_DFF pass (perform DFF optimizations).

5.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..
Removed 0 unused cells and 2 unused wires.
<suppressed ~1 debug messages>

5.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

5.16. Rerunning OPT passes. (Maybe there is more to do..)

5.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \test..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

5.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \test.
Performed a total of 0 changes.

5.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\test'.
Removed a total of 0 cells.

5.20. Executing OPT_DFF pass (perform DFF optimizations).

5.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \test..

5.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module test.

5.23. Finished OPT passes. (There is nothing left to do.)

6. Generating Graphviz representation of design.
Writing dot description to `memory_02.dot'.
Dumping module test to page 1.

End of script. Logfile hash: da34c3e279, CPU: user 0.02s system 0.00s, MEM: 13.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 26% 5x opt_expr (0 sec), 19% 5x opt_clean (0 sec), ...
../../../../yosys -p 'script techmap_01.ys; show -notitle -prefix techmap_01 -format dot'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `script techmap_01.ys; show -notitle -prefix techmap_01 -format dot' --

-- Executing script file `techmap_01.ys' --

1. Executing Verilog-2005 frontend: techmap_01.v
Parsing Verilog input from `techmap_01.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: techmap_01_map.v
Parsing Verilog input from `techmap_01_map.v' to AST representation.
Generating RTLIL representation for module `\$add'.
Successfully finished Verilog frontend.

3.2. Continuing TECHMAP pass.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\$add for cells of type $add.
No more expansions possible.
<suppressed ~75 debug messages>
Removed 0 unused cells and 7 unused wires.

4. Generating Graphviz representation of design.
Writing dot description to `techmap_01.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 49c16386d9, CPU: user 0.00s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 34% 1x techmap (0 sec), 27% 1x clean (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/synth_flow'
make[4]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/techmap'
../../../../yosys red_or3x1_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `red_or3x1_test.ys' --

1. Executing Verilog-2005 frontend: red_or3x1_test.v
Parsing Verilog input from `red_or3x1_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: red_or3x1_map.v
Parsing Verilog input from `red_or3x1_map.v' to AST representation.
Generating RTLIL representation for module `\$reduce_or'.
Successfully finished Verilog frontend.

3.2. Continuing TECHMAP pass.
Using template $paramod$53153ae57fdb25b25475408a64760d7986ecfb0e\$reduce_or for cells of type $reduce_or.
Using template $paramod$fe2472242c070f3b22e97f6c8c19c3569e575d97\$reduce_or for cells of type $reduce_or.
Using template $paramod$1a3ccc6b2ad940e0a4ee2fb765a3adeb638fb7f0\$reduce_or for cells of type $reduce_or.
No more expansions possible.
<suppressed ~53 debug messages>
Removed 0 unused cells and 18 unused wires.

4. Executing SPLITNETS pass (splitting up multi-bit signals).

5. Generating Graphviz representation of design.

5.1. Executing Verilog-2005 frontend: red_or3x1_cells.v
Parsing Verilog input from `red_or3x1_cells.v' to AST representation.
Generating RTLIL representation for module `\OR3X1'.
Successfully finished Verilog frontend.

5.2. Continuing show pass.
Writing dot description to `red_or3x1.dot'.
Dumping module test to page 1.

End of script. Logfile hash: d6e7304939, CPU: user 0.00s system 0.01s, MEM: 12.88 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 41% 1x techmap (0 sec), 26% 4x read_verilog (0 sec), ...
../../../../yosys sym_mul_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `sym_mul_test.ys' --

1. Executing Verilog-2005 frontend: sym_mul_test.v
Parsing Verilog input from `sym_mul_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: sym_mul_map.v
Parsing Verilog input from `sym_mul_map.v' to AST representation.
Generating RTLIL representation for module `\$mul'.
Successfully finished Verilog frontend.

3.2. Continuing TECHMAP pass.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul.
No more expansions possible.
<suppressed ~43 debug messages>
Removed 0 unused cells and 6 unused wires.

4. Generating Graphviz representation of design.

4.1. Executing Verilog-2005 frontend: sym_mul_cells.v
Parsing Verilog input from `sym_mul_cells.v' to AST representation.
Generating RTLIL representation for module `\MYMUL'.
Successfully finished Verilog frontend.

4.2. Continuing show pass.
Writing dot description to `sym_mul.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 28982f840f, CPU: user 0.01s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 32% 1x clean (0 sec), 28% 4x read_verilog (0 sec), ...
../../../../yosys mymul_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `mymul_test.ys' --

1. Executing Verilog-2005 frontend: mymul_test.v
Parsing Verilog input from `mymul_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: sym_mul_map.v
Parsing Verilog input from `sym_mul_map.v' to AST representation.
Generating RTLIL representation for module `\$mul'.
Successfully finished Verilog frontend.

3.2. Executing Verilog-2005 frontend: mymul_map.v
Parsing Verilog input from `mymul_map.v' to AST representation.
Generating RTLIL representation for module `\MYMUL'.
Successfully finished Verilog frontend.

3.3. Continuing TECHMAP pass.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\$mul for cells of type $mul.
Using template $paramod\MYMUL\WIDTH=32'00000000000000000000000000000010 for cells of type MYMUL.
No more expansions possible.
<suppressed ~108 debug messages>
Removed 0 unused cells and 10 unused wires.
Renaming module \test to \test_mapped.

4. Executing Verilog-2005 frontend: mymul_test.v
Parsing Verilog input from `mymul_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

5. Executing MITER pass (creating miter circuit).
Creating miter cell "miter" with gold cell "test" and gate cell "test_mapped".

6. Executing FLATTEN pass (flatten design).
<suppressed ~2 debug messages>

7. Executing SAT pass (solving SAT problems in the circuit).

Setting up SAT problem:
Final constraint equation: { } = { }
Imported 9 cells to SAT database.
Import proof-constraint: \trigger = 1'0
Final proof equation: \trigger = 1'0

Solving problem with 107 variables and 283 clauses..
SAT proof finished - no model found: SUCCESS!

                  /$$$$$$      /$$$$$$$$     /$$$$$$$    
                 /$$__  $$    | $$_____/    | $$__  $$   
                | $$  \ $$    | $$          | $$  \ $$   
                | $$  | $$    | $$$$$       | $$  | $$   
                | $$  | $$    | $$__/       | $$  | $$   
                | $$/$$ $$    | $$          | $$  | $$   
                |  $$$$$$/ /$$| $$$$$$$$ /$$| $$$$$$$//$$
                 \____ $$$|__/|________/|__/|_______/|__/
                       \__/                              

8. Executing SPLITNETS pass (splitting up multi-bit signals).

9. Generating Graphviz representation of design.
Writing dot description to `mymul.dot'.
Dumping module test_mapped to page 1.

End of script. Logfile hash: 449524bce2, CPU: user 0.01s system 0.00s, MEM: 14.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 23% 2x clean (0 sec), 16% 1x techmap (0 sec), ...
../../../../yosys mulshift_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `mulshift_test.ys' --

1. Executing Verilog-2005 frontend: mulshift_test.v
Parsing Verilog input from `mulshift_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: sym_mul_map.v
Parsing Verilog input from `sym_mul_map.v' to AST representation.
Generating RTLIL representation for module `\$mul'.
Successfully finished Verilog frontend.

3.2. Executing Verilog-2005 frontend: mulshift_map.v
Parsing Verilog input from `mulshift_map.v' to AST representation.
Generating RTLIL representation for module `\MYMUL'.
Successfully finished Verilog frontend.

3.3. Continuing TECHMAP pass.
Using template $paramod$a1bc51c02ce12ac21eb18988e83292af48ed7d72\$mul for cells of type $mul.
Using template $paramod$fb3c811cfd9dc2fc74fe40190dfcd365f04584f7\MYMUL for cells of type MYMUL.
No more expansions possible.
<suppressed ~185 debug messages>
Removed 0 unused cells and 16 unused wires.

4. Generating Graphviz representation of design.

4.1. Executing Verilog-2005 frontend: sym_mul_cells.v
Parsing Verilog input from `sym_mul_cells.v' to AST representation.
Generating RTLIL representation for module `\MYMUL'.
Successfully finished Verilog frontend.

4.2. Continuing show pass.
Writing dot description to `mulshift.dot'.
Dumping module test to page 1.

End of script. Logfile hash: e40f1e9ccc, CPU: user 0.01s system 0.00s, MEM: 13.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 28% 3x clean (0 sec), 26% 1x techmap (0 sec), ...
../../../../yosys addshift_test.ys

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Executing script file `addshift_test.ys' --

1. Executing Verilog-2005 frontend: addshift_test.v
Parsing Verilog input from `addshift_test.v' to AST representation.
Generating RTLIL representation for module `\test'.
Successfully finished Verilog frontend.

2. Executing HIERARCHY pass (managing design hierarchy).

2.1. Analyzing design hierarchy..
Top module:  \test

2.2. Analyzing design hierarchy..
Top module:  \test
Removed 0 unused modules.

3. Executing TECHMAP pass (map to technology primitives).

3.1. Executing Verilog-2005 frontend: addshift_map.v
Parsing Verilog input from `addshift_map.v' to AST representation.
Generating RTLIL representation for module `\$add'.
Successfully finished Verilog frontend.

3.2. Continuing TECHMAP pass.
Using template $paramod$ba28896eb640c0d0dd7116971c6c5dc347170a6c\$add for cells of type $add.
No more expansions possible.
<suppressed ~51 debug messages>
Removed 0 unused cells and 7 unused wires.

4. Generating Graphviz representation of design.
Writing dot description to `addshift.dot'.
Dumping module test to page 1.

End of script. Logfile hash: 99575363c1, CPU: user 0.01s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 29% 1x clean (0 sec), 25% 1x techmap (0 sec), ...
make[4]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/source/code_examples/techmap'
cd internals && TZ='Z' faketime -f '2022-01-01 00:00:00 x0,001' pdflatex approach_flow.tex --interaction=nonstopmode
This is pdfTeX, Version 3.141592653-2.6-1.40.25 (TeX Live 2023) (preloaded format=pdflatex)
 restricted \write18 enabled.
entering extended mode
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index
 introduction
 getting_started/index
  getting_started/installation
  getting_started/example_synth
  getting_started/scripting_intro
 using_yosys/index
  using_yosys/synthesis/index
   using_yosys/synthesis/synth
   using_yosys/synthesis/proc
   using_yosys/synthesis/fsm
   using_yosys/synthesis/memory
   using_yosys/synthesis/opt
   using_yosys/synthesis/techmap_synth
   using_yosys/synthesis/extract
   using_yosys/synthesis/abc
   using_yosys/synthesis/cell_libs
  using_yosys/more_scripting/index
   using_yosys/more_scripting/load_design
   using_yosys/more_scripting/selections
   using_yosys/more_scripting/interactive_investigation
   using_yosys/more_scripting/model_checking
 yosys_internals/index
  yosys_internals/flow/index
   yosys_internals/flow/overview
   yosys_internals/flow/control_and_data
   yosys_internals/flow/verilog_frontend
  yosys_internals/formats/index
   yosys_internals/formats/rtlil_rep
  yosys_internals/extending_yosys/index
   yosys_internals/extending_yosys/extensions
   yosys_internals/extending_yosys/build_verific
   yosys_internals/extending_yosys/functional_ir
   yosys_internals/extending_yosys/test_suites
  yosys_internals/techmap
  appendix/primer
  appendix/rtlil_text
  appendix/auxlibs
  appendix/auxprogs
  bib
  cell_index
   cell/index_word
    cell/word_unary
    cell/word_binary
    cell/word_mux
    cell/word_reg
    cell/word_mem
    cell/word_fsm
    cell/word_arith
    cell/word_logic
    cell/word_spec
    cell/word_formal
    cell/word_debug
    cell/word_wire
   cell/index_gate
    cell/gate_comb_simple
    cell/gate_comb_combined
    cell/gate_reg_ff
    cell/gate_reg_latch
    cell/gate_other
   cell/properties
  cmd_ref
   appendix/env_vars
   cmd/abc
   cmd/abc9
   cmd/abc9_exe
   cmd/abc9_ops
   cmd/abc_new
   cmd/add
   cmd/aigmap
   cmd/alumacc
   cmd/anlogic_eqn
   cmd/anlogic_fixcarry
   cmd/assertpmux
   cmd/async2sync
   cmd/attrmap
   cmd/attrmvcp
   cmd/autoname
   cmd/blackbox
   cmd/bmuxmap
   cmd/booth
   cmd/box_derive
   cmd/bufnorm
   cmd/bugpoint
   cmd/bwmuxmap
   cmd/cd
   cmd/cellmatch
   cmd/check
   cmd/chformal
   cmd/chparam
   cmd/chtype
   cmd/clean
   cmd/clean_zerowidth
   cmd/clk2fflogic
   cmd/clkbufmap
   cmd/clockgate
   cmd/connect
   cmd/connect_rpc
   cmd/connwrappers
   cmd/coolrunner2_fixup
   cmd/coolrunner2_sop
   cmd/copy
   cmd/cover
   cmd/cutpoint
   cmd/debug
   cmd/delete
   cmd/deminout
   cmd/demuxmap
   cmd/design
   cmd/dffinit
   cmd/dfflegalize
   cmd/dfflibmap
   cmd/dffunmap
   cmd/dft_tag
   cmd/dump
   cmd/echo
   cmd/edgetypes
   cmd/efinix_fixcarry
   cmd/equiv_add
   cmd/equiv_induct
   cmd/equiv_make
   cmd/equiv_mark
   cmd/equiv_miter
   cmd/equiv_opt
   cmd/equiv_purge
   cmd/equiv_remove
   cmd/equiv_simple
   cmd/equiv_status
   cmd/equiv_struct
   cmd/eval
   cmd/example_dt
   cmd/exec
   cmd/expose
   cmd/extract
   cmd/extract_counter
   cmd/extract_fa
   cmd/extract_reduce
   cmd/extractinv
   cmd/flatten
   cmd/flowmap
   cmd/fmcombine
   cmd/fminit
   cmd/formalff
   cmd/freduce
   cmd/fsm
   cmd/fsm_detect
   cmd/fsm_expand
   cmd/fsm_export
   cmd/fsm_extract
   cmd/fsm_info
   cmd/fsm_map
   cmd/fsm_opt
   cmd/fsm_recode
   cmd/fst2tb
   cmd/future
   cmd/gatemate_foldinv
   cmd/glift
   cmd/greenpak4_dffinv
   cmd/help
   cmd/hierarchy
   cmd/hilomap
   cmd/history
   cmd/ice40_braminit
   cmd/ice40_dsp
   cmd/ice40_opt
   cmd/ice40_wrapcarry
   cmd/insbuf
   cmd/internal_stats
   cmd/iopadmap
   cmd/jny
   cmd/json
   cmd/keep_hierarchy
   cmd/lattice_gsr
   cmd/license
   cmd/log
   cmd/logger
   cmd/ls
   cmd/ltp
   cmd/lut2mux
   cmd/maccmap
   cmd/memory
   cmd/memory_bmux2rom
   cmd/memory_bram
   cmd/memory_collect
   cmd/memory_dff
   cmd/memory_libmap
   cmd/memory_map
   cmd/memory_memx
   cmd/memory_narrow
   cmd/memory_nordff
   cmd/memory_share
   cmd/memory_unpack
   cmd/microchip_dffopt
   cmd/microchip_dsp
   cmd/miter
   cmd/mutate
   cmd/muxcover
   cmd/muxpack
   cmd/nlutmap
   cmd/nx_carry
   cmd/onehot
   cmd/opt
   cmd/opt_clean
   cmd/opt_demorgan
   cmd/opt_dff
   cmd/opt_expr
   cmd/opt_ffinv
   cmd/opt_lut
   cmd/opt_lut_ins
   cmd/opt_mem
   cmd/opt_mem_feedback
   cmd/opt_mem_priority
   cmd/opt_mem_widen
   cmd/opt_merge
   cmd/opt_muxtree
   cmd/opt_reduce
   cmd/opt_share
   cmd/paramap
   cmd/peepopt
   cmd/plugin
   cmd/pmux2shiftx
   cmd/pmuxtree
   cmd/portlist
   cmd/prep
   cmd/printattrs
   cmd/proc
   cmd/proc_arst
   cmd/proc_clean
   cmd/proc_dff
   cmd/proc_dlatch
   cmd/proc_init
   cmd/proc_memwr
   cmd/proc_mux
   cmd/proc_prune
   cmd/proc_rmdead
   cmd/proc_rom
   cmd/qbfsat
   cmd/ql_bram_merge
   cmd/ql_bram_types
   cmd/ql_dsp_io_regs
   cmd/ql_dsp_macc
   cmd/ql_dsp_simd
   cmd/read
   cmd/read_aiger
   cmd/read_blif
   cmd/read_json
   cmd/read_liberty
   cmd/read_rtlil
   cmd/read_verilog
   cmd/read_xaiger2
   cmd/recover_names
   cmd/rename
   cmd/rmports
   cmd/sat
   cmd/scatter
   cmd/scc
   cmd/scratchpad
   cmd/script
   cmd/select
   cmd/setattr
   cmd/setparam
   cmd/setundef
   cmd/share
   cmd/shell
   cmd/show
   cmd/shregmap
   cmd/sim
   cmd/simplemap
   cmd/splice
   cmd/splitcells
   cmd/splitnets
   cmd/sta
   cmd/stat
   cmd/submod
   cmd/supercover
   cmd/synth
   cmd/synth_achronix
   cmd/synth_anlogic
   cmd/synth_coolrunner2
   cmd/synth_easic
   cmd/synth_ecp5
   cmd/synth_efinix
   cmd/synth_fabulous
   cmd/synth_gatemate
   cmd/synth_gowin
   cmd/synth_greenpak4
   cmd/synth_ice40
   cmd/synth_intel
   cmd/synth_intel_alm
   cmd/synth_lattice
   cmd/synth_microchip
   cmd/synth_nanoxplore
   cmd/synth_nexus
   cmd/synth_quicklogic
   cmd/synth_sf2
   cmd/synth_xilinx
   cmd/synthprop
   cmd/tcl
   cmd/techmap
   cmd/tee
   cmd/test_abcloop
   cmd/test_autotb
   cmd/test_cell
   cmd/test_generic
   cmd/test_pmgen
   cmd/torder
   cmd/trace
   cmd/tribuf
   cmd/uniquify
   cmd/verific
   cmd/verilog_defaults
   cmd/verilog_defines
   cmd/viz
   cmd/wbflip
   cmd/wreduce
   cmd/write_aiger
   cmd/write_aiger2
   cmd/write_blif
   cmd/write_btor
   cmd/write_cxxrtl
   cmd/write_edif
   cmd/write_file
   cmd/write_firrtl
   cmd/write_functional_cxx
   cmd/write_functional_rosette
   cmd/write_functional_smt2
   cmd/write_intersynth
   cmd/write_jny
   cmd/write_json
   cmd/write_rtlil
   cmd/write_simplec
   cmd/write_smt2
   cmd/write_smv
   cmd/write_spice
   cmd/write_table
   cmd/write_verilog
   cmd/write_xaiger
   cmd/write_xaiger2
   cmd/xilinx_dffopt
   cmd/xilinx_dsp
   cmd/xilinx_srl
   cmd/xprop
   cmd/zinit

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[53] [54]
Chapter 3.

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Chapter 4.
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Chapter 5.

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Chapter 6.
[197] [198]

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Chapter 7.

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Chapter 8.

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Chapter 9.

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Chapter 10.
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\T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s
ion of IEEE Std 1076.6-1999)\T1/lmr/m/n/10 , 2004.

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[]\T1/lmr/m/n/10 IEEE Stan-dards As-so-ci-a-tion and oth-ers. Ieee stan-dard fo
r ver-ilog hard-ware de-

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\T1/lmr/m/n/10 scrip-tion lan-guage. \T1/lmr/m/it/10 IEEE Std 1364-2005 (Re-vi-
sion of IEEE Std 1364-2001)\T1/lmr/m/n/10 , 2006.
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n input line 44664.


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n input line 44667.


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n input line 44676.


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[591]

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n input line 44748.


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n input line 44749.


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n input line 44751.


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[592]

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ine 44777.


LaTeX Warning: Reference `cmd/box_derive:cmd-box_derive' on page 593 undefined 
on input line 44778.


LaTeX Warning: Reference `cmd/bufnorm:cmd-bufnorm' on page 593 undefined on inp
ut line 44779.


LaTeX Warning: Reference `cmd/bugpoint:cmd-bugpoint' on page 593 undefined on i
nput line 44780.


LaTeX Warning: Reference `cmd/bwmuxmap:cmd-bwmuxmap' on page 593 undefined on i
nput line 44781.


LaTeX Warning: Reference `cmd/cd:cmd-cd' on page 593 undefined on input line 44
782.


LaTeX Warning: Reference `cmd/cellmatch:cmd-cellmatch' on page 593 undefined on
 input line 44783.


LaTeX Warning: Reference `cmd/check:cmd-check' on page 593 undefined on input l
ine 44784.


LaTeX Warning: Reference `cmd/chformal:cmd-chformal' on page 593 undefined on i
nput line 44785.


LaTeX Warning: Reference `cmd/chparam:cmd-chparam' on page 593 undefined on inp
ut line 44786.


LaTeX Warning: Reference `cmd/chtype:cmd-chtype' on page 593 undefined on input
 line 44787.


LaTeX Warning: Reference `cmd/clean:cmd-clean' on page 593 undefined on input l
ine 44788.


LaTeX Warning: Reference `cmd/clean_zerowidth:cmd-clean_zerowidth' on page 593 
undefined on input line 44789.


LaTeX Warning: Reference `cmd/clk2fflogic:cmd-clk2fflogic' on page 593 undefine
d on input line 44790.


LaTeX Warning: Reference `cmd/clkbufmap:cmd-clkbufmap' on page 593 undefined on
 input line 44791.


LaTeX Warning: Reference `cmd/clockgate:cmd-clockgate' on page 593 undefined on
 input line 44792.


LaTeX Warning: Reference `cmd/connect:cmd-connect' on page 593 undefined on inp
ut line 44793.


LaTeX Warning: Reference `cmd/connect_rpc:cmd-connect_rpc' on page 593 undefine
d on input line 44794.


LaTeX Warning: Reference `cmd/connwrappers:cmd-connwrappers' on page 593 undefi
ned on input line 44795.


LaTeX Warning: Reference `cmd/coolrunner2_fixup:cmd-coolrunner2_fixup' on page 
593 undefined on input line 44796.


LaTeX Warning: Reference `cmd/coolrunner2_sop:cmd-coolrunner2_sop' on page 593 
undefined on input line 44797.


LaTeX Warning: Reference `cmd/copy:cmd-copy' on page 593 undefined on input lin
e 44798.


LaTeX Warning: Reference `cmd/cover:cmd-cover' on page 593 undefined on input l
ine 44799.


LaTeX Warning: Reference `cmd/cutpoint:cmd-cutpoint' on page 593 undefined on i
nput line 44800.


LaTeX Warning: Reference `cmd/debug:cmd-debug' on page 593 undefined on input l
ine 44801.


LaTeX Warning: Reference `cmd/delete:cmd-delete' on page 593 undefined on input
 line 44802.


LaTeX Warning: Reference `cmd/deminout:cmd-deminout' on page 593 undefined on i
nput line 44803.


LaTeX Warning: Reference `cmd/demuxmap:cmd-demuxmap' on page 593 undefined on i
nput line 44804.


LaTeX Warning: Reference `cmd/design:cmd-design' on page 593 undefined on input
 line 44805.


LaTeX Warning: Reference `cmd/dffinit:cmd-dffinit' on page 593 undefined on inp
ut line 44806.


LaTeX Warning: Reference `cmd/dfflegalize:cmd-dfflegalize' on page 593 undefine
d on input line 44807.


LaTeX Warning: Reference `cmd/dfflibmap:cmd-dfflibmap' on page 593 undefined on
 input line 44808.


LaTeX Warning: Reference `cmd/dffunmap:cmd-dffunmap' on page 593 undefined on i
nput line 44809.


LaTeX Warning: Reference `cmd/dft_tag:cmd-dft_tag' on page 593 undefined on inp
ut line 44810.


LaTeX Warning: Reference `cmd/dump:cmd-dump' on page 593 undefined on input lin
e 44811.


LaTeX Warning: Reference `cmd/echo:cmd-echo' on page 593 undefined on input lin
e 44812.


LaTeX Warning: Reference `cmd/edgetypes:cmd-edgetypes' on page 593 undefined on
 input line 44813.


LaTeX Warning: Reference `cmd/efinix_fixcarry:cmd-efinix_fixcarry' on page 593 
undefined on input line 44814.


LaTeX Warning: Reference `cmd/equiv_add:cmd-equiv_add' on page 593 undefined on
 input line 44815.


LaTeX Warning: Reference `cmd/equiv_induct:cmd-equiv_induct' on page 593 undefi
ned on input line 44816.


LaTeX Warning: Reference `cmd/equiv_make:cmd-equiv_make' on page 593 undefined 
on input line 44817.


LaTeX Warning: Reference `cmd/equiv_mark:cmd-equiv_mark' on page 593 undefined 
on input line 44818.


LaTeX Warning: Reference `cmd/equiv_miter:cmd-equiv_miter' on page 593 undefine
d on input line 44819.


LaTeX Warning: Reference `cmd/equiv_opt:cmd-equiv_opt' on page 593 undefined on
 input line 44820.


LaTeX Warning: Reference `cmd/equiv_purge:cmd-equiv_purge' on page 593 undefine
d on input line 44821.


LaTeX Warning: Reference `cmd/equiv_remove:cmd-equiv_remove' on page 593 undefi
ned on input line 44822.


LaTeX Warning: Reference `cmd/equiv_simple:cmd-equiv_simple' on page 593 undefi
ned on input line 44823.


LaTeX Warning: Reference `cmd/equiv_status:cmd-equiv_status' on page 593 undefi
ned on input line 44824.


LaTeX Warning: Reference `cmd/equiv_struct:cmd-equiv_struct' on page 593 undefi
ned on input line 44825.


LaTeX Warning: Reference `cmd/eval:cmd-eval' on page 593 undefined on input lin
e 44826.


LaTeX Warning: Reference `cmd/example_dt:cmd-example_dt' on page 593 undefined 
on input line 44827.


LaTeX Warning: Reference `cmd/exec:cmd-exec' on page 593 undefined on input lin
e 44828.


LaTeX Warning: Reference `cmd/expose:cmd-expose' on page 593 undefined on input
 line 44829.


LaTeX Warning: Reference `cmd/extract:cmd-extract' on page 593 undefined on inp
ut line 44830.


LaTeX Warning: Reference `cmd/extract_counter:cmd-extract_counter' on page 593 
undefined on input line 44831.


LaTeX Warning: Reference `cmd/extract_fa:cmd-extract_fa' on page 593 undefined 
on input line 44832.


LaTeX Warning: Reference `cmd/extract_reduce:cmd-extract_reduce' on page 593 un
defined on input line 44833.


LaTeX Warning: Reference `cmd/extractinv:cmd-extractinv' on page 593 undefined 
on input line 44834.


LaTeX Warning: Reference `cmd/flatten:cmd-flatten' on page 593 undefined on inp
ut line 44835.


LaTeX Warning: Reference `cmd/flowmap:cmd-flowmap' on page 593 undefined on inp
ut line 44836.


LaTeX Warning: Reference `cmd/fmcombine:cmd-fmcombine' on page 593 undefined on
 input line 44837.


LaTeX Warning: Reference `cmd/fminit:cmd-fminit' on page 593 undefined on input
 line 44838.


LaTeX Warning: Reference `cmd/formalff:cmd-formalff' on page 593 undefined on i
nput line 44839.


LaTeX Warning: Reference `cmd/freduce:cmd-freduce' on page 593 undefined on inp
ut line 44840.


LaTeX Warning: Reference `cmd/fsm:cmd-fsm' on page 593 undefined on input line 
44841.


LaTeX Warning: Reference `cmd/fsm_detect:cmd-fsm_detect' on page 593 undefined 
on input line 44842.


LaTeX Warning: Reference `cmd/fsm_expand:cmd-fsm_expand' on page 593 undefined 
on input line 44843.


LaTeX Warning: Reference `cmd/fsm_export:cmd-fsm_export' on page 593 undefined 
on input line 44844.

[593]

LaTeX Warning: Reference `cmd/fsm_extract:cmd-fsm_extract' on page 594 undefine
d on input line 44845.


LaTeX Warning: Reference `cmd/fsm_info:cmd-fsm_info' on page 594 undefined on i
nput line 44846.


LaTeX Warning: Reference `cmd/fsm_map:cmd-fsm_map' on page 594 undefined on inp
ut line 44847.


LaTeX Warning: Reference `cmd/fsm_opt:cmd-fsm_opt' on page 594 undefined on inp
ut line 44848.


LaTeX Warning: Reference `cmd/fsm_recode:cmd-fsm_recode' on page 594 undefined 
on input line 44849.


LaTeX Warning: Reference `cmd/fst2tb:cmd-fst2tb' on page 594 undefined on input
 line 44850.


LaTeX Warning: Reference `cmd/future:cmd-future' on page 594 undefined on input
 line 44851.


LaTeX Warning: Reference `cmd/gatemate_foldinv:cmd-gatemate_foldinv' on page 59
4 undefined on input line 44852.


LaTeX Warning: Reference `cmd/glift:cmd-glift' on page 594 undefined on input l
ine 44853.


LaTeX Warning: Reference `cmd/greenpak4_dffinv:cmd-greenpak4_dffinv' on page 59
4 undefined on input line 44854.


LaTeX Warning: Reference `cmd/help:cmd-help' on page 594 undefined on input lin
e 44855.


LaTeX Warning: Reference `cmd/hierarchy:cmd-hierarchy' on page 594 undefined on
 input line 44856.


LaTeX Warning: Reference `cmd/hilomap:cmd-hilomap' on page 594 undefined on inp
ut line 44857.


LaTeX Warning: Reference `cmd/history:cmd-history' on page 594 undefined on inp
ut line 44858.


LaTeX Warning: Reference `cmd/ice40_braminit:cmd-ice40_braminit' on page 594 un
defined on input line 44859.


LaTeX Warning: Reference `cmd/ice40_dsp:cmd-ice40_dsp' on page 594 undefined on
 input line 44860.


LaTeX Warning: Reference `cmd/ice40_opt:cmd-ice40_opt' on page 594 undefined on
 input line 44861.


LaTeX Warning: Reference `cmd/ice40_wrapcarry:cmd-ice40_wrapcarry' on page 594 
undefined on input line 44862.


LaTeX Warning: Reference `cmd/insbuf:cmd-insbuf' on page 594 undefined on input
 line 44863.


LaTeX Warning: Reference `cmd/internal_stats:cmd-internal_stats' on page 594 un
defined on input line 44864.


LaTeX Warning: Reference `cmd/iopadmap:cmd-iopadmap' on page 594 undefined on i
nput line 44865.


LaTeX Warning: Reference `cmd/jny:cmd-jny' on page 594 undefined on input line 
44866.


LaTeX Warning: Reference `cmd/json:cmd-json' on page 594 undefined on input lin
e 44867.


LaTeX Warning: Reference `cmd/keep_hierarchy:cmd-keep_hierarchy' on page 594 un
defined on input line 44868.


LaTeX Warning: Reference `cmd/lattice_gsr:cmd-lattice_gsr' on page 594 undefine
d on input line 44869.


LaTeX Warning: Reference `cmd/license:cmd-license' on page 594 undefined on inp
ut line 44870.


LaTeX Warning: Reference `cmd/log:cmd-log' on page 594 undefined on input line 
44871.


LaTeX Warning: Reference `cmd/logger:cmd-logger' on page 594 undefined on input
 line 44872.


LaTeX Warning: Reference `cmd/ls:cmd-ls' on page 594 undefined on input line 44
873.


LaTeX Warning: Reference `cmd/ltp:cmd-ltp' on page 594 undefined on input line 
44874.


LaTeX Warning: Reference `cmd/lut2mux:cmd-lut2mux' on page 594 undefined on inp
ut line 44875.


LaTeX Warning: Reference `cmd/maccmap:cmd-maccmap' on page 594 undefined on inp
ut line 44876.


LaTeX Warning: Reference `cmd/memory:cmd-memory' on page 594 undefined on input
 line 44877.


LaTeX Warning: Reference `cmd/memory_bmux2rom:cmd-memory_bmux2rom' on page 594 
undefined on input line 44878.


LaTeX Warning: Reference `cmd/memory_bram:cmd-memory_bram' on page 594 undefine
d on input line 44879.


LaTeX Warning: Reference `cmd/memory_collect:cmd-memory_collect' on page 594 un
defined on input line 44880.


LaTeX Warning: Reference `cmd/memory_dff:cmd-memory_dff' on page 594 undefined 
on input line 44881.


LaTeX Warning: Reference `cmd/memory_libmap:cmd-memory_libmap' on page 594 unde
fined on input line 44882.


LaTeX Warning: Reference `cmd/memory_map:cmd-memory_map' on page 594 undefined 
on input line 44883.


LaTeX Warning: Reference `cmd/memory_memx:cmd-memory_memx' on page 594 undefine
d on input line 44884.


LaTeX Warning: Reference `cmd/memory_narrow:cmd-memory_narrow' on page 594 unde
fined on input line 44885.


LaTeX Warning: Reference `cmd/memory_nordff:cmd-memory_nordff' on page 594 unde
fined on input line 44886.


LaTeX Warning: Reference `cmd/memory_share:cmd-memory_share' on page 594 undefi
ned on input line 44887.


LaTeX Warning: Reference `cmd/memory_unpack:cmd-memory_unpack' on page 594 unde
fined on input line 44888.


LaTeX Warning: Reference `cmd/microchip_dffopt:cmd-microchip_dffopt' on page 59
4 undefined on input line 44889.


LaTeX Warning: Reference `cmd/microchip_dsp:cmd-microchip_dsp' on page 594 unde
fined on input line 44890.


LaTeX Warning: Reference `cmd/miter:cmd-miter' on page 594 undefined on input l
ine 44891.


LaTeX Warning: Reference `cmd/mutate:cmd-mutate' on page 594 undefined on input
 line 44892.


LaTeX Warning: Reference `cmd/muxcover:cmd-muxcover' on page 594 undefined on i
nput line 44893.


LaTeX Warning: Reference `cmd/muxpack:cmd-muxpack' on page 594 undefined on inp
ut line 44894.


LaTeX Warning: Reference `cmd/nlutmap:cmd-nlutmap' on page 594 undefined on inp
ut line 44895.


LaTeX Warning: Reference `cmd/nx_carry:cmd-nx_carry' on page 594 undefined on i
nput line 44896.


LaTeX Warning: Reference `cmd/onehot:cmd-onehot' on page 594 undefined on input
 line 44897.


LaTeX Warning: Reference `cmd/opt:cmd-opt' on page 594 undefined on input line 
44898.


LaTeX Warning: Reference `cmd/opt_clean:cmd-opt_clean' on page 594 undefined on
 input line 44899.


LaTeX Warning: Reference `cmd/opt_demorgan:cmd-opt_demorgan' on page 594 undefi
ned on input line 44900.


LaTeX Warning: Reference `cmd/opt_dff:cmd-opt_dff' on page 594 undefined on inp
ut line 44901.


LaTeX Warning: Reference `cmd/opt_expr:cmd-opt_expr' on page 594 undefined on i
nput line 44902.


LaTeX Warning: Reference `cmd/opt_ffinv:cmd-opt_ffinv' on page 594 undefined on
 input line 44903.


LaTeX Warning: Reference `cmd/opt_lut:cmd-opt_lut' on page 594 undefined on inp
ut line 44904.


LaTeX Warning: Reference `cmd/opt_lut_ins:cmd-opt_lut_ins' on page 594 undefine
d on input line 44905.


LaTeX Warning: Reference `cmd/opt_mem:cmd-opt_mem' on page 594 undefined on inp
ut line 44906.


LaTeX Warning: Reference `cmd/opt_mem_feedback:cmd-opt_mem_feedback' on page 59
4 undefined on input line 44907.


LaTeX Warning: Reference `cmd/opt_mem_priority:cmd-opt_mem_priority' on page 59
4 undefined on input line 44908.


LaTeX Warning: Reference `cmd/opt_mem_widen:cmd-opt_mem_widen' on page 594 unde
fined on input line 44909.


LaTeX Warning: Reference `cmd/opt_merge:cmd-opt_merge' on page 594 undefined on
 input line 44910.


LaTeX Warning: Reference `cmd/opt_muxtree:cmd-opt_muxtree' on page 594 undefine
d on input line 44911.


LaTeX Warning: Reference `cmd/opt_reduce:cmd-opt_reduce' on page 594 undefined 
on input line 44912.


LaTeX Warning: Reference `cmd/opt_share:cmd-opt_share' on page 594 undefined on
 input line 44913.


LaTeX Warning: Reference `cmd/paramap:cmd-paramap' on page 594 undefined on inp
ut line 44914.


LaTeX Warning: Reference `cmd/peepopt:cmd-peepopt' on page 594 undefined on inp
ut line 44915.


LaTeX Warning: Reference `cmd/plugin:cmd-plugin' on page 594 undefined on input
 line 44916.


LaTeX Warning: Reference `cmd/pmux2shiftx:cmd-pmux2shiftx' on page 594 undefine
d on input line 44917.


LaTeX Warning: Reference `cmd/pmuxtree:cmd-pmuxtree' on page 594 undefined on i
nput line 44918.


LaTeX Warning: Reference `cmd/portlist:cmd-portlist' on page 594 undefined on i
nput line 44919.


LaTeX Warning: Reference `cmd/prep:cmd-prep' on page 594 undefined on input lin
e 44920.


LaTeX Warning: Reference `cmd/printattrs:cmd-printattrs' on page 594 undefined 
on input line 44921.


LaTeX Warning: Reference `cmd/proc:cmd-proc' on page 594 undefined on input lin
e 44922.


LaTeX Warning: Reference `cmd/proc_arst:cmd-proc_arst' on page 594 undefined on
 input line 44923.


LaTeX Warning: Reference `cmd/proc_clean:cmd-proc_clean' on page 594 undefined 
on input line 44924.


LaTeX Warning: Reference `cmd/proc_dff:cmd-proc_dff' on page 594 undefined on i
nput line 44925.


LaTeX Warning: Reference `cmd/proc_dlatch:cmd-proc_dlatch' on page 594 undefine
d on input line 44926.


LaTeX Warning: Reference `cmd/proc_init:cmd-proc_init' on page 594 undefined on
 input line 44927.


LaTeX Warning: Reference `cmd/proc_memwr:cmd-proc_memwr' on page 594 undefined 
on input line 44928.


LaTeX Warning: Reference `cmd/proc_mux:cmd-proc_mux' on page 594 undefined on i
nput line 44929.


LaTeX Warning: Reference `cmd/proc_prune:cmd-proc_prune' on page 594 undefined 
on input line 44930.


LaTeX Warning: Reference `cmd/proc_rmdead:cmd-proc_rmdead' on page 594 undefine
d on input line 44931.


LaTeX Warning: Reference `cmd/proc_rom:cmd-proc_rom' on page 594 undefined on i
nput line 44932.


LaTeX Warning: Reference `cmd/qbfsat:cmd-qbfsat' on page 594 undefined on input
 line 44933.


LaTeX Warning: Reference `cmd/ql_bram_merge:cmd-ql_bram_merge' on page 594 unde
fined on input line 44934.


LaTeX Warning: Reference `cmd/ql_bram_types:cmd-ql_bram_types' on page 594 unde
fined on input line 44935.


LaTeX Warning: Reference `cmd/ql_dsp_io_regs:cmd-ql_dsp_io_regs' on page 594 un
defined on input line 44936.


LaTeX Warning: Reference `cmd/ql_dsp_macc:cmd-ql_dsp_macc' on page 594 undefine
d on input line 44937.


LaTeX Warning: Reference `cmd/ql_dsp_simd:cmd-ql_dsp_simd' on page 594 undefine
d on input line 44938.


LaTeX Warning: Reference `cmd/read:cmd-read' on page 594 undefined on input lin
e 44939.


LaTeX Warning: Reference `cmd/read_aiger:cmd-read_aiger' on page 594 undefined 
on input line 44940.


LaTeX Warning: Reference `cmd/read_blif:cmd-read_blif' on page 594 undefined on
 input line 44941.


LaTeX Warning: Reference `cmd/read_json:cmd-read_json' on page 594 undefined on
 input line 44942.


LaTeX Warning: Reference `cmd/read_liberty:cmd-read_liberty' on page 594 undefi
ned on input line 44943.


LaTeX Warning: Reference `cmd/read_rtlil:cmd-read_rtlil' on page 594 undefined 
on input line 44944.


LaTeX Warning: Reference `cmd/read_verilog:cmd-read_verilog' on page 594 undefi
ned on input line 44945.


LaTeX Warning: Reference `cmd/read_xaiger2:cmd-read_xaiger2' on page 594 undefi
ned on input line 44946.


LaTeX Warning: Reference `cmd/recover_names:cmd-recover_names' on page 594 unde
fined on input line 44947.


LaTeX Warning: Reference `cmd/rename:cmd-rename' on page 594 undefined on input
 line 44948.


LaTeX Warning: Reference `cmd/rmports:cmd-rmports' on page 594 undefined on inp
ut line 44949.


LaTeX Warning: Reference `cmd/sat:cmd-sat' on page 594 undefined on input line 
44950.


LaTeX Warning: Reference `cmd/scatter:cmd-scatter' on page 594 undefined on inp
ut line 44951.


LaTeX Warning: Reference `cmd/scc:cmd-scc' on page 594 undefined on input line 
44952.

[594]

LaTeX Warning: Reference `cmd/scratchpad:cmd-scratchpad' on page 595 undefined 
on input line 44953.


LaTeX Warning: Reference `cmd/script:cmd-script' on page 595 undefined on input
 line 44954.


LaTeX Warning: Reference `cmd/select:cmd-select' on page 595 undefined on input
 line 44955.


LaTeX Warning: Reference `cmd/setattr:cmd-setattr' on page 595 undefined on inp
ut line 44956.


LaTeX Warning: Reference `cmd/setparam:cmd-setparam' on page 595 undefined on i
nput line 44957.


LaTeX Warning: Reference `cmd/setundef:cmd-setundef' on page 595 undefined on i
nput line 44958.


LaTeX Warning: Reference `cmd/share:cmd-share' on page 595 undefined on input l
ine 44959.


LaTeX Warning: Reference `cmd/shell:cmd-shell' on page 595 undefined on input l
ine 44960.


LaTeX Warning: Reference `cmd/show:cmd-show' on page 595 undefined on input lin
e 44961.


LaTeX Warning: Reference `cmd/shregmap:cmd-shregmap' on page 595 undefined on i
nput line 44962.


LaTeX Warning: Reference `cmd/sim:cmd-sim' on page 595 undefined on input line 
44963.


LaTeX Warning: Reference `cmd/simplemap:cmd-simplemap' on page 595 undefined on
 input line 44964.


LaTeX Warning: Reference `cmd/splice:cmd-splice' on page 595 undefined on input
 line 44965.


LaTeX Warning: Reference `cmd/splitcells:cmd-splitcells' on page 595 undefined 
on input line 44966.


LaTeX Warning: Reference `cmd/splitnets:cmd-splitnets' on page 595 undefined on
 input line 44967.


LaTeX Warning: Reference `cmd/sta:cmd-sta' on page 595 undefined on input line 
44968.


LaTeX Warning: Reference `cmd/stat:cmd-stat' on page 595 undefined on input lin
e 44969.


LaTeX Warning: Reference `cmd/submod:cmd-submod' on page 595 undefined on input
 line 44970.


LaTeX Warning: Reference `cmd/supercover:cmd-supercover' on page 595 undefined 
on input line 44971.


LaTeX Warning: Reference `cmd/synth:cmd-synth' on page 595 undefined on input l
ine 44972.


LaTeX Warning: Reference `cmd/synth_achronix:cmd-synth_achronix' on page 595 un
defined on input line 44973.


LaTeX Warning: Reference `cmd/synth_anlogic:cmd-synth_anlogic' on page 595 unde
fined on input line 44974.


LaTeX Warning: Reference `cmd/synth_coolrunner2:cmd-synth_coolrunner2' on page 
595 undefined on input line 44975.


LaTeX Warning: Reference `cmd/synth_easic:cmd-synth_easic' on page 595 undefine
d on input line 44976.


LaTeX Warning: Reference `cmd/synth_ecp5:cmd-synth_ecp5' on page 595 undefined 
on input line 44977.


LaTeX Warning: Reference `cmd/synth_efinix:cmd-synth_efinix' on page 595 undefi
ned on input line 44978.


LaTeX Warning: Reference `cmd/synth_fabulous:cmd-synth_fabulous' on page 595 un
defined on input line 44979.


LaTeX Warning: Reference `cmd/synth_gatemate:cmd-synth_gatemate' on page 595 un
defined on input line 44980.


LaTeX Warning: Reference `cmd/synth_gowin:cmd-synth_gowin' on page 595 undefine
d on input line 44981.


LaTeX Warning: Reference `cmd/synth_greenpak4:cmd-synth_greenpak4' on page 595 
undefined on input line 44982.


LaTeX Warning: Reference `cmd/synth_ice40:cmd-synth_ice40' on page 595 undefine
d on input line 44983.


LaTeX Warning: Reference `cmd/synth_intel:cmd-synth_intel' on page 595 undefine
d on input line 44984.


LaTeX Warning: Reference `cmd/synth_intel_alm:cmd-synth_intel_alm' on page 595 
undefined on input line 44985.


LaTeX Warning: Reference `cmd/synth_lattice:cmd-synth_lattice' on page 595 unde
fined on input line 44986.


LaTeX Warning: Reference `cmd/synth_microchip:cmd-synth_microchip' on page 595 
undefined on input line 44987.


LaTeX Warning: Reference `cmd/synth_nanoxplore:cmd-synth_nanoxplore' on page 59
5 undefined on input line 44988.


LaTeX Warning: Reference `cmd/synth_nexus:cmd-synth_nexus' on page 595 undefine
d on input line 44989.


LaTeX Warning: Reference `cmd/synth_quicklogic:cmd-synth_quicklogic' on page 59
5 undefined on input line 44990.


LaTeX Warning: Reference `cmd/synth_sf2:cmd-synth_sf2' on page 595 undefined on
 input line 44991.


LaTeX Warning: Reference `cmd/synth_xilinx:cmd-synth_xilinx' on page 595 undefi
ned on input line 44992.


LaTeX Warning: Reference `cmd/synthprop:cmd-synthprop' on page 595 undefined on
 input line 44993.


LaTeX Warning: Reference `cmd/tcl:cmd-tcl' on page 595 undefined on input line 
44994.


LaTeX Warning: Reference `cmd/techmap:cmd-techmap' on page 595 undefined on inp
ut line 44995.


LaTeX Warning: Reference `cmd/tee:cmd-tee' on page 595 undefined on input line 
44996.


LaTeX Warning: Reference `cmd/test_abcloop:cmd-test_abcloop' on page 595 undefi
ned on input line 44997.


LaTeX Warning: Reference `cmd/test_autotb:cmd-test_autotb' on page 595 undefine
d on input line 44998.


LaTeX Warning: Reference `cmd/test_cell:cmd-test_cell' on page 595 undefined on
 input line 44999.


LaTeX Warning: Reference `cmd/test_generic:cmd-test_generic' on page 595 undefi
ned on input line 45000.


LaTeX Warning: Reference `cmd/test_pmgen:cmd-test_pmgen' on page 595 undefined 
on input line 45001.


LaTeX Warning: Reference `cmd/torder:cmd-torder' on page 595 undefined on input
 line 45002.


LaTeX Warning: Reference `cmd/trace:cmd-trace' on page 595 undefined on input l
ine 45003.


LaTeX Warning: Reference `cmd/tribuf:cmd-tribuf' on page 595 undefined on input
 line 45004.


LaTeX Warning: Reference `cmd/uniquify:cmd-uniquify' on page 595 undefined on i
nput line 45005.


LaTeX Warning: Reference `cmd/verific:cmd-verific' on page 595 undefined on inp
ut line 45006.


LaTeX Warning: Reference `cmd/verilog_defaults:cmd-verilog_defaults' on page 59
5 undefined on input line 45007.


LaTeX Warning: Reference `cmd/verilog_defines:cmd-verilog_defines' on page 595 
undefined on input line 45008.


LaTeX Warning: Reference `cmd/viz:cmd-viz' on page 595 undefined on input line 
45009.


LaTeX Warning: Reference `cmd/wbflip:cmd-wbflip' on page 595 undefined on input
 line 45010.


LaTeX Warning: Reference `cmd/wreduce:cmd-wreduce' on page 595 undefined on inp
ut line 45011.


LaTeX Warning: Reference `cmd/write_aiger:cmd-write_aiger' on page 595 undefine
d on input line 45012.


LaTeX Warning: Reference `cmd/write_aiger2:cmd-write_aiger2' on page 595 undefi
ned on input line 45013.


LaTeX Warning: Reference `cmd/write_blif:cmd-write_blif' on page 595 undefined 
on input line 45014.


LaTeX Warning: Reference `cmd/write_btor:cmd-write_btor' on page 595 undefined 
on input line 45015.


LaTeX Warning: Reference `cmd/write_cxxrtl:cmd-write_cxxrtl' on page 595 undefi
ned on input line 45016.


LaTeX Warning: Reference `cmd/write_edif:cmd-write_edif' on page 595 undefined 
on input line 45017.


LaTeX Warning: Reference `cmd/write_file:cmd-write_file' on page 595 undefined 
on input line 45018.


LaTeX Warning: Reference `cmd/write_firrtl:cmd-write_firrtl' on page 595 undefi
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LaTeX Warning: Reference `cmd/write_functional_cxx:cmd-write_functional_cxx' on
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Underfull \hbox (badness 10000) in paragraph at lines 45020--45021
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LaTeX Warning: Reference `cmd/write_functional_rosette:cmd-write_functional_ros
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Underfull \hbox (badness 10000) in paragraph at lines 45021--45022
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LaTeX Warning: Reference `cmd/write_functional_smt2:cmd-write_functional_smt2' 
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Underfull \hbox (badness 10000) in paragraph at lines 45022--45023
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LaTeX Warning: Reference `cmd/write_intersynth:cmd-write_intersynth' on page 59
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LaTeX Warning: Reference `cmd/write_jny:cmd-write_jny' on page 595 undefined on
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LaTeX Warning: Reference `cmd/write_json:cmd-write_json' on page 595 undefined 
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LaTeX Warning: Reference `cmd/write_rtlil:cmd-write_rtlil' on page 595 undefine
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LaTeX Warning: Reference `cmd/write_simplec:cmd-write_simplec' on page 595 unde
fined on input line 45027.


LaTeX Warning: Reference `cmd/write_smt2:cmd-write_smt2' on page 595 undefined 
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LaTeX Warning: Reference `cmd/write_smv:cmd-write_smv' on page 595 undefined on
 input line 45029.


LaTeX Warning: Reference `cmd/write_spice:cmd-write_spice' on page 595 undefine
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LaTeX Warning: Reference `cmd/write_table:cmd-write_table' on page 595 undefine
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LaTeX Warning: Reference `cmd/write_verilog:cmd-write_verilog' on page 595 unde
fined on input line 45032.


LaTeX Warning: Reference `cmd/write_xaiger:cmd-write_xaiger' on page 595 undefi
ned on input line 45033.


LaTeX Warning: Reference `cmd/write_xaiger2:cmd-write_xaiger2' on page 595 unde
fined on input line 45034.


LaTeX Warning: Reference `cmd/xilinx_dffopt:cmd-xilinx_dffopt' on page 595 unde
fined on input line 45035.


LaTeX Warning: Reference `cmd/xilinx_dsp:cmd-xilinx_dsp' on page 595 undefined 
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LaTeX Warning: Reference `cmd/xilinx_srl:cmd-xilinx_srl' on page 595 undefined 
on input line 45037.


LaTeX Warning: Reference `cmd/xprop:cmd-xprop' on page 595 undefined on input l
ine 45038.


LaTeX Warning: Reference `cmd/zinit:cmd-zinit' on page 595 undefined on input l
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[595] [596]

LaTeX Warning: Reference `cmd/abc:cmd-abc' on page 597 undefined on input line 
45045.


LaTeX Warning: Reference `cmd/abc9:cmd-abc9' on page 597 undefined on input lin
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LaTeX Warning: Reference `cmd/abc9_ops:cmd-abc9_ops' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/abc_new:cmd-abc_new' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/add:cmd-add' on page 597 undefined on input line 
45050.


LaTeX Warning: Reference `cmd/aigmap:cmd-aigmap' on page 597 undefined on input
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LaTeX Warning: Reference `cmd/alumacc:cmd-alumacc' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/anlogic_eqn:cmd-anlogic_eqn' on page 597 undefine
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LaTeX Warning: Reference `cmd/anlogic_fixcarry:cmd-anlogic_fixcarry' on page 59
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LaTeX Warning: Reference `cmd/assertpmux:cmd-assertpmux' on page 597 undefined 
on input line 45055.


LaTeX Warning: Reference `cmd/async2sync:cmd-async2sync' on page 597 undefined 
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LaTeX Warning: Reference `cmd/attrmap:cmd-attrmap' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/attrmvcp:cmd-attrmvcp' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/autoname:cmd-autoname' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/blackbox:cmd-blackbox' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/bmuxmap:cmd-bmuxmap' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/booth:cmd-booth' on page 597 undefined on input l
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LaTeX Warning: Reference `cmd/box_derive:cmd-box_derive' on page 597 undefined 
on input line 45063.


LaTeX Warning: Reference `cmd/bufnorm:cmd-bufnorm' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/bugpoint:cmd-bugpoint' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/bwmuxmap:cmd-bwmuxmap' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/cd:cmd-cd' on page 597 undefined on input line 45
067.


LaTeX Warning: Reference `cmd/cellmatch:cmd-cellmatch' on page 597 undefined on
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LaTeX Warning: Reference `cmd/check:cmd-check' on page 597 undefined on input l
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LaTeX Warning: Reference `cmd/chformal:cmd-chformal' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/chparam:cmd-chparam' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/chtype:cmd-chtype' on page 597 undefined on input
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LaTeX Warning: Reference `cmd/clean:cmd-clean' on page 597 undefined on input l
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LaTeX Warning: Reference `cmd/clean_zerowidth:cmd-clean_zerowidth' on page 597 
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LaTeX Warning: Reference `cmd/clk2fflogic:cmd-clk2fflogic' on page 597 undefine
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LaTeX Warning: Reference `cmd/clkbufmap:cmd-clkbufmap' on page 597 undefined on
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LaTeX Warning: Reference `cmd/clockgate:cmd-clockgate' on page 597 undefined on
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LaTeX Warning: Reference `cmd/connect:cmd-connect' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/connect_rpc:cmd-connect_rpc' on page 597 undefine
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LaTeX Warning: Reference `cmd/connwrappers:cmd-connwrappers' on page 597 undefi
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LaTeX Warning: Reference `cmd/coolrunner2_fixup:cmd-coolrunner2_fixup' on page 
597 undefined on input line 45081.


LaTeX Warning: Reference `cmd/coolrunner2_sop:cmd-coolrunner2_sop' on page 597 
undefined on input line 45082.


LaTeX Warning: Reference `cmd/copy:cmd-copy' on page 597 undefined on input lin
e 45083.


LaTeX Warning: Reference `cmd/cover:cmd-cover' on page 597 undefined on input l
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LaTeX Warning: Reference `cmd/cutpoint:cmd-cutpoint' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/debug:cmd-debug' on page 597 undefined on input l
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LaTeX Warning: Reference `cmd/delete:cmd-delete' on page 597 undefined on input
 line 45087.


LaTeX Warning: Reference `cmd/deminout:cmd-deminout' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/demuxmap:cmd-demuxmap' on page 597 undefined on i
nput line 45089.


LaTeX Warning: Reference `cmd/design:cmd-design' on page 597 undefined on input
 line 45090.


LaTeX Warning: Reference `cmd/dffinit:cmd-dffinit' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/dfflegalize:cmd-dfflegalize' on page 597 undefine
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LaTeX Warning: Reference `cmd/dfflibmap:cmd-dfflibmap' on page 597 undefined on
 input line 45093.


LaTeX Warning: Reference `cmd/dffunmap:cmd-dffunmap' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/dft_tag:cmd-dft_tag' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/dump:cmd-dump' on page 597 undefined on input lin
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LaTeX Warning: Reference `cmd/echo:cmd-echo' on page 597 undefined on input lin
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LaTeX Warning: Reference `cmd/edgetypes:cmd-edgetypes' on page 597 undefined on
 input line 45098.


LaTeX Warning: Reference `cmd/efinix_fixcarry:cmd-efinix_fixcarry' on page 597 
undefined on input line 45099.


LaTeX Warning: Reference `cmd/equiv_add:cmd-equiv_add' on page 597 undefined on
 input line 45100.


LaTeX Warning: Reference `cmd/equiv_induct:cmd-equiv_induct' on page 597 undefi
ned on input line 45101.


LaTeX Warning: Reference `cmd/equiv_make:cmd-equiv_make' on page 597 undefined 
on input line 45102.


LaTeX Warning: Reference `cmd/equiv_mark:cmd-equiv_mark' on page 597 undefined 
on input line 45103.


LaTeX Warning: Reference `cmd/equiv_miter:cmd-equiv_miter' on page 597 undefine
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LaTeX Warning: Reference `cmd/equiv_opt:cmd-equiv_opt' on page 597 undefined on
 input line 45105.


LaTeX Warning: Reference `cmd/equiv_purge:cmd-equiv_purge' on page 597 undefine
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LaTeX Warning: Reference `cmd/equiv_remove:cmd-equiv_remove' on page 597 undefi
ned on input line 45107.


LaTeX Warning: Reference `cmd/equiv_simple:cmd-equiv_simple' on page 597 undefi
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LaTeX Warning: Reference `cmd/equiv_status:cmd-equiv_status' on page 597 undefi
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LaTeX Warning: Reference `cmd/equiv_struct:cmd-equiv_struct' on page 597 undefi
ned on input line 45110.


LaTeX Warning: Reference `cmd/eval:cmd-eval' on page 597 undefined on input lin
e 45111.


LaTeX Warning: Reference `cmd/example_dt:cmd-example_dt' on page 597 undefined 
on input line 45112.


LaTeX Warning: Reference `cmd/exec:cmd-exec' on page 597 undefined on input lin
e 45113.


LaTeX Warning: Reference `cmd/expose:cmd-expose' on page 597 undefined on input
 line 45114.


LaTeX Warning: Reference `cmd/extract:cmd-extract' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/extract_counter:cmd-extract_counter' on page 597 
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LaTeX Warning: Reference `cmd/extract_fa:cmd-extract_fa' on page 597 undefined 
on input line 45117.


LaTeX Warning: Reference `cmd/extract_reduce:cmd-extract_reduce' on page 597 un
defined on input line 45118.


LaTeX Warning: Reference `cmd/extractinv:cmd-extractinv' on page 597 undefined 
on input line 45119.


LaTeX Warning: Reference `cmd/flatten:cmd-flatten' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/flowmap:cmd-flowmap' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/fmcombine:cmd-fmcombine' on page 597 undefined on
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LaTeX Warning: Reference `cmd/fminit:cmd-fminit' on page 597 undefined on input
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LaTeX Warning: Reference `cmd/formalff:cmd-formalff' on page 597 undefined on i
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LaTeX Warning: Reference `cmd/freduce:cmd-freduce' on page 597 undefined on inp
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LaTeX Warning: Reference `cmd/fsm:cmd-fsm' on page 597 undefined on input line 
45126.


LaTeX Warning: Reference `cmd/fsm_detect:cmd-fsm_detect' on page 597 undefined 
on input line 45127.


LaTeX Warning: Reference `cmd/fsm_expand:cmd-fsm_expand' on page 597 undefined 
on input line 45128.

[597]

LaTeX Warning: Reference `cmd/fsm_export:cmd-fsm_export' on page 598 undefined 
on input line 45129.


LaTeX Warning: Reference `cmd/fsm_extract:cmd-fsm_extract' on page 598 undefine
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LaTeX Warning: Reference `cmd/fsm_info:cmd-fsm_info' on page 598 undefined on i
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LaTeX Warning: Reference `cmd/fsm_map:cmd-fsm_map' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/fsm_opt:cmd-fsm_opt' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/fsm_recode:cmd-fsm_recode' on page 598 undefined 
on input line 45134.


LaTeX Warning: Reference `cmd/fst2tb:cmd-fst2tb' on page 598 undefined on input
 line 45135.


LaTeX Warning: Reference `cmd/future:cmd-future' on page 598 undefined on input
 line 45136.


LaTeX Warning: Reference `cmd/gatemate_foldinv:cmd-gatemate_foldinv' on page 59
8 undefined on input line 45137.


LaTeX Warning: Reference `cmd/glift:cmd-glift' on page 598 undefined on input l
ine 45138.


LaTeX Warning: Reference `cmd/greenpak4_dffinv:cmd-greenpak4_dffinv' on page 59
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LaTeX Warning: Reference `cmd/help:cmd-help' on page 598 undefined on input lin
e 45140.


LaTeX Warning: Reference `cmd/hierarchy:cmd-hierarchy' on page 598 undefined on
 input line 45141.


LaTeX Warning: Reference `cmd/hilomap:cmd-hilomap' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/history:cmd-history' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/ice40_braminit:cmd-ice40_braminit' on page 598 un
defined on input line 45144.


LaTeX Warning: Reference `cmd/ice40_dsp:cmd-ice40_dsp' on page 598 undefined on
 input line 45145.


LaTeX Warning: Reference `cmd/ice40_opt:cmd-ice40_opt' on page 598 undefined on
 input line 45146.


LaTeX Warning: Reference `cmd/ice40_wrapcarry:cmd-ice40_wrapcarry' on page 598 
undefined on input line 45147.


LaTeX Warning: Reference `cmd/insbuf:cmd-insbuf' on page 598 undefined on input
 line 45148.


LaTeX Warning: Reference `cmd/internal_stats:cmd-internal_stats' on page 598 un
defined on input line 45149.


LaTeX Warning: Reference `cmd/iopadmap:cmd-iopadmap' on page 598 undefined on i
nput line 45150.


LaTeX Warning: Reference `cmd/jny:cmd-jny' on page 598 undefined on input line 
45151.


LaTeX Warning: Reference `cmd/json:cmd-json' on page 598 undefined on input lin
e 45152.


LaTeX Warning: Reference `cmd/keep_hierarchy:cmd-keep_hierarchy' on page 598 un
defined on input line 45153.


LaTeX Warning: Reference `cmd/lattice_gsr:cmd-lattice_gsr' on page 598 undefine
d on input line 45154.


LaTeX Warning: Reference `cmd/license:cmd-license' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/log:cmd-log' on page 598 undefined on input line 
45156.


LaTeX Warning: Reference `cmd/logger:cmd-logger' on page 598 undefined on input
 line 45157.


LaTeX Warning: Reference `cmd/ls:cmd-ls' on page 598 undefined on input line 45
158.


LaTeX Warning: Reference `cmd/ltp:cmd-ltp' on page 598 undefined on input line 
45159.


LaTeX Warning: Reference `cmd/lut2mux:cmd-lut2mux' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/maccmap:cmd-maccmap' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/memory:cmd-memory' on page 598 undefined on input
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LaTeX Warning: Reference `cmd/memory_bmux2rom:cmd-memory_bmux2rom' on page 598 
undefined on input line 45163.


LaTeX Warning: Reference `cmd/memory_bram:cmd-memory_bram' on page 598 undefine
d on input line 45164.


LaTeX Warning: Reference `cmd/memory_collect:cmd-memory_collect' on page 598 un
defined on input line 45165.


LaTeX Warning: Reference `cmd/memory_dff:cmd-memory_dff' on page 598 undefined 
on input line 45166.


LaTeX Warning: Reference `cmd/memory_libmap:cmd-memory_libmap' on page 598 unde
fined on input line 45167.


LaTeX Warning: Reference `cmd/memory_map:cmd-memory_map' on page 598 undefined 
on input line 45168.


LaTeX Warning: Reference `cmd/memory_memx:cmd-memory_memx' on page 598 undefine
d on input line 45169.


LaTeX Warning: Reference `cmd/memory_narrow:cmd-memory_narrow' on page 598 unde
fined on input line 45170.


LaTeX Warning: Reference `cmd/memory_nordff:cmd-memory_nordff' on page 598 unde
fined on input line 45171.


LaTeX Warning: Reference `cmd/memory_share:cmd-memory_share' on page 598 undefi
ned on input line 45172.


LaTeX Warning: Reference `cmd/memory_unpack:cmd-memory_unpack' on page 598 unde
fined on input line 45173.


LaTeX Warning: Reference `cmd/microchip_dffopt:cmd-microchip_dffopt' on page 59
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LaTeX Warning: Reference `cmd/microchip_dsp:cmd-microchip_dsp' on page 598 unde
fined on input line 45175.


LaTeX Warning: Reference `cmd/miter:cmd-miter' on page 598 undefined on input l
ine 45176.


LaTeX Warning: Reference `cmd/mutate:cmd-mutate' on page 598 undefined on input
 line 45177.


LaTeX Warning: Reference `cmd/muxcover:cmd-muxcover' on page 598 undefined on i
nput line 45178.


LaTeX Warning: Reference `cmd/muxpack:cmd-muxpack' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/nlutmap:cmd-nlutmap' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/nx_carry:cmd-nx_carry' on page 598 undefined on i
nput line 45181.


LaTeX Warning: Reference `cmd/onehot:cmd-onehot' on page 598 undefined on input
 line 45182.


LaTeX Warning: Reference `cmd/opt:cmd-opt' on page 598 undefined on input line 
45183.


LaTeX Warning: Reference `cmd/opt_clean:cmd-opt_clean' on page 598 undefined on
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LaTeX Warning: Reference `cmd/opt_demorgan:cmd-opt_demorgan' on page 598 undefi
ned on input line 45185.


LaTeX Warning: Reference `cmd/opt_dff:cmd-opt_dff' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/opt_expr:cmd-opt_expr' on page 598 undefined on i
nput line 45187.


LaTeX Warning: Reference `cmd/opt_ffinv:cmd-opt_ffinv' on page 598 undefined on
 input line 45188.


LaTeX Warning: Reference `cmd/opt_lut:cmd-opt_lut' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/opt_lut_ins:cmd-opt_lut_ins' on page 598 undefine
d on input line 45190.


LaTeX Warning: Reference `cmd/opt_mem:cmd-opt_mem' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/opt_mem_feedback:cmd-opt_mem_feedback' on page 59
8 undefined on input line 45192.


LaTeX Warning: Reference `cmd/opt_mem_priority:cmd-opt_mem_priority' on page 59
8 undefined on input line 45193.


LaTeX Warning: Reference `cmd/opt_mem_widen:cmd-opt_mem_widen' on page 598 unde
fined on input line 45194.


LaTeX Warning: Reference `cmd/opt_merge:cmd-opt_merge' on page 598 undefined on
 input line 45195.


LaTeX Warning: Reference `cmd/opt_muxtree:cmd-opt_muxtree' on page 598 undefine
d on input line 45196.


LaTeX Warning: Reference `cmd/opt_reduce:cmd-opt_reduce' on page 598 undefined 
on input line 45197.


LaTeX Warning: Reference `cmd/opt_share:cmd-opt_share' on page 598 undefined on
 input line 45198.


LaTeX Warning: Reference `cmd/paramap:cmd-paramap' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/peepopt:cmd-peepopt' on page 598 undefined on inp
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LaTeX Warning: Reference `cmd/plugin:cmd-plugin' on page 598 undefined on input
 line 45201.


LaTeX Warning: Reference `cmd/pmux2shiftx:cmd-pmux2shiftx' on page 598 undefine
d on input line 45202.


LaTeX Warning: Reference `cmd/pmuxtree:cmd-pmuxtree' on page 598 undefined on i
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LaTeX Warning: Reference `cmd/portlist:cmd-portlist' on page 598 undefined on i
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LaTeX Warning: Reference `cmd/prep:cmd-prep' on page 598 undefined on input lin
e 45205.


LaTeX Warning: Reference `cmd/printattrs:cmd-printattrs' on page 598 undefined 
on input line 45206.


LaTeX Warning: Reference `cmd/proc:cmd-proc' on page 598 undefined on input lin
e 45207.


LaTeX Warning: Reference `cmd/proc_arst:cmd-proc_arst' on page 598 undefined on
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LaTeX Warning: Reference `cmd/proc_clean:cmd-proc_clean' on page 598 undefined 
on input line 45209.


LaTeX Warning: Reference `cmd/proc_dff:cmd-proc_dff' on page 598 undefined on i
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LaTeX Warning: Reference `cmd/proc_dlatch:cmd-proc_dlatch' on page 598 undefine
d on input line 45211.


LaTeX Warning: Reference `cmd/proc_init:cmd-proc_init' on page 598 undefined on
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LaTeX Warning: Reference `cmd/proc_memwr:cmd-proc_memwr' on page 598 undefined 
on input line 45213.


LaTeX Warning: Reference `cmd/proc_mux:cmd-proc_mux' on page 598 undefined on i
nput line 45214.


LaTeX Warning: Reference `cmd/proc_prune:cmd-proc_prune' on page 598 undefined 
on input line 45215.


LaTeX Warning: Reference `cmd/proc_rmdead:cmd-proc_rmdead' on page 598 undefine
d on input line 45216.


LaTeX Warning: Reference `cmd/proc_rom:cmd-proc_rom' on page 598 undefined on i
nput line 45217.


LaTeX Warning: Reference `cmd/qbfsat:cmd-qbfsat' on page 598 undefined on input
 line 45218.


LaTeX Warning: Reference `cmd/ql_bram_merge:cmd-ql_bram_merge' on page 598 unde
fined on input line 45219.


LaTeX Warning: Reference `cmd/ql_bram_types:cmd-ql_bram_types' on page 598 unde
fined on input line 45220.


LaTeX Warning: Reference `cmd/ql_dsp_io_regs:cmd-ql_dsp_io_regs' on page 598 un
defined on input line 45221.


LaTeX Warning: Reference `cmd/ql_dsp_macc:cmd-ql_dsp_macc' on page 598 undefine
d on input line 45222.


LaTeX Warning: Reference `cmd/ql_dsp_simd:cmd-ql_dsp_simd' on page 598 undefine
d on input line 45223.


LaTeX Warning: Reference `cmd/read:cmd-read' on page 598 undefined on input lin
e 45224.


LaTeX Warning: Reference `cmd/read_aiger:cmd-read_aiger' on page 598 undefined 
on input line 45225.


LaTeX Warning: Reference `cmd/read_blif:cmd-read_blif' on page 598 undefined on
 input line 45226.


LaTeX Warning: Reference `cmd/read_json:cmd-read_json' on page 598 undefined on
 input line 45227.


LaTeX Warning: Reference `cmd/read_liberty:cmd-read_liberty' on page 598 undefi
ned on input line 45228.


LaTeX Warning: Reference `cmd/read_rtlil:cmd-read_rtlil' on page 598 undefined 
on input line 45229.


LaTeX Warning: Reference `cmd/read_verilog:cmd-read_verilog' on page 598 undefi
ned on input line 45230.


LaTeX Warning: Reference `cmd/read_xaiger2:cmd-read_xaiger2' on page 598 undefi
ned on input line 45231.


LaTeX Warning: Reference `cmd/recover_names:cmd-recover_names' on page 598 unde
fined on input line 45232.


LaTeX Warning: Reference `cmd/rename:cmd-rename' on page 598 undefined on input
 line 45233.


LaTeX Warning: Reference `cmd/rmports:cmd-rmports' on page 598 undefined on inp
ut line 45234.


LaTeX Warning: Reference `cmd/sat:cmd-sat' on page 598 undefined on input line 
45235.


LaTeX Warning: Reference `cmd/scatter:cmd-scatter' on page 598 undefined on inp
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[598]

LaTeX Warning: Reference `cmd/scc:cmd-scc' on page 599 undefined on input line 
45237.


LaTeX Warning: Reference `cmd/scratchpad:cmd-scratchpad' on page 599 undefined 
on input line 45238.


LaTeX Warning: Reference `cmd/script:cmd-script' on page 599 undefined on input
 line 45239.


LaTeX Warning: Reference `cmd/select:cmd-select' on page 599 undefined on input
 line 45240.


LaTeX Warning: Reference `cmd/setattr:cmd-setattr' on page 599 undefined on inp
ut line 45241.


LaTeX Warning: Reference `cmd/setparam:cmd-setparam' on page 599 undefined on i
nput line 45242.


LaTeX Warning: Reference `cmd/setundef:cmd-setundef' on page 599 undefined on i
nput line 45243.


LaTeX Warning: Reference `cmd/share:cmd-share' on page 599 undefined on input l
ine 45244.


LaTeX Warning: Reference `cmd/shell:cmd-shell' on page 599 undefined on input l
ine 45245.


LaTeX Warning: Reference `cmd/show:cmd-show' on page 599 undefined on input lin
e 45246.


LaTeX Warning: Reference `cmd/shregmap:cmd-shregmap' on page 599 undefined on i
nput line 45247.


LaTeX Warning: Reference `cmd/sim:cmd-sim' on page 599 undefined on input line 
45248.


LaTeX Warning: Reference `cmd/simplemap:cmd-simplemap' on page 599 undefined on
 input line 45249.


LaTeX Warning: Reference `cmd/splice:cmd-splice' on page 599 undefined on input
 line 45250.


LaTeX Warning: Reference `cmd/splitcells:cmd-splitcells' on page 599 undefined 
on input line 45251.


LaTeX Warning: Reference `cmd/splitnets:cmd-splitnets' on page 599 undefined on
 input line 45252.


LaTeX Warning: Reference `cmd/sta:cmd-sta' on page 599 undefined on input line 
45253.


LaTeX Warning: Reference `cmd/stat:cmd-stat' on page 599 undefined on input lin
e 45254.


LaTeX Warning: Reference `cmd/submod:cmd-submod' on page 599 undefined on input
 line 45255.


LaTeX Warning: Reference `cmd/supercover:cmd-supercover' on page 599 undefined 
on input line 45256.


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[6]
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[7]
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[8]
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) [9] [10] (/usr/share/texlive/texmf-dist/tex/latex/lm/ts1lmr.fd)
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\T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s
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[6]
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[7]
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[8]
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) [9] [10] (/usr/share/texlive/texmf-dist/tex/latex/lm/ts1lmr.fd)
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Chapter 3.
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Chapter 4.
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\T1/lmr/m/n/10 (rtl) syn-the-sis. \T1/lmr/m/it/10 IEEE Std 1076.6-2004 (Re-vi-s
ion of IEEE Std 1076.6-1999)\T1/lmr/m/n/10 , 2004.

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[]\T1/lmr/m/n/10 IEEE Stan-dards As-so-ci-a-tion and oth-ers. Ieee stan-dard fo
r ver-ilog hard-ware de-

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\T1/lmr/m/n/10 scrip-tion lan-guage. \T1/lmr/m/it/10 IEEE Std 1364-2005 (Re-vi-
sion of IEEE Std 1364-2001)\T1/lmr/m/n/10 , 2006.
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[]\T1/lmtt/m/n/10 write_functional_cxx

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[]\T1/lmtt/m/n/10 write_functional_smt2
[595] [596] [597] [598] [599] (./yosyshqyosys.ind)

Package sphinx Warning: The package pict2e is required for rounded boxes.
(sphinx)                As it does not seem to be available on your system,
(sphinx)                options setting radii have all been ignored.


Package sphinx Warning: The package ellipse is required for elliptical corners.

(sphinx)                As it does not seem to be available on your system,
(sphinx)                all non-straight corners have used circle arcs..

(./yosyshqyosys.aux) )
(see the transcript file for additional information)</usr/share/texlive/texmf-d
ist/fonts/type1/public/amsfonts/cm/cmr12.pfb></usr/share/texlive/texmf-dist/fon
ts/type1/public/amsfonts/cm/cmr6.pfb></usr/share/texlive/texmf-dist/fonts/type1
/public/amsfonts/cm/cmtt12.pfb></usr/share/texlive/texmf-dist/fonts/type1/publi
c/lm/lmb10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmbo10.pfb>
</usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmcsc10.pfb></usr/share/te
xlive/texmf-dist/fonts/type1/public/lm/lmmi10.pfb></usr/share/texlive/texmf-dis
t/fonts/type1/public/lm/lmmi5.pfb></usr/share/texlive/texmf-dist/fonts/type1/pu
blic/lm/lmr10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr5.pfb
></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmr6.pfb></usr/share/texl
ive/texmf-dist/fonts/type1/public/lm/lmr7.pfb></usr/share/texlive/texmf-dist/fo
nts/type1/public/lm/lmr8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/
lm/lmri10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmss10.pfb><
/usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmss12.pfb></usr/share/texl
ive/texmf-dist/fonts/type1/public/lm/lmssbo10.pfb></usr/share/texlive/texmf-dis
t/fonts/type1/public/lm/lmssbx10.pfb></usr/share/texlive/texmf-dist/fonts/type1
/public/lm/lmsy10.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmsy
5.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/lmtk10.pfb></usr/sha
re/texlive/texmf-dist/fonts/type1/public/lm/lmtko10.pfb></usr/share/texlive/tex
mf-dist/fonts/type1/public/lm/lmtt10.pfb></usr/share/texlive/texmf-dist/fonts/t
ype1/public/lm/lmtt8.pfb></usr/share/texlive/texmf-dist/fonts/type1/public/lm/l
mtti10.pfb>
Output written on yosyshqyosys.pdf (611 pages, 3271474 bytes).
Transcript written on yosyshqyosys.log.
Latexmk: Getting log file 'yosyshqyosys.log'
Latexmk: Examining 'yosyshqyosys.fls'
Latexmk: Examining 'yosyshqyosys.log'
Latexmk: Index file 'yosyshqyosys.idx' was written
Latexmk: Log file says output to 'yosyshqyosys.pdf'
Have index file 'yosyshqyosys.idx', yosyshqyosys.ind yosyshqyosys
Latexmk: All targets (yosyshqyosys.pdf) are up-to-date

make[2]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs/build/latex'
pdflatex finished; the PDF files are in build/latex.
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/docs'
++ stat -c %y debian/man/yosys-smtbmc.txt
++ cut '-d ' -f1
+ date=2023-08-27
+ txt2man -d 2023-08-27 -t YOSYS-SMTBMC debian/man/yosys-smtbmc.txt
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%install): /bin/sh -e /var/tmp/rpm-tmp.pVfSSz
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ '[' /builddir/build/BUILD/yosys-0.47-build/BUILDROOT '!=' / ']'
+ rm -rf /builddir/build/BUILD/yosys-0.47-build/BUILDROOT
++ dirname /builddir/build/BUILD/yosys-0.47-build/BUILDROOT
+ mkdir -p /builddir/build/BUILD/yosys-0.47-build
+ mkdir /builddir/build/BUILD/yosys-0.47-build/BUILDROOT
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ /usr/bin/make install DESTDIR=/builddir/build/BUILD/yosys-0.47-build/BUILDROOT 'INSTALL=/usr/bin/install -p' PREFIX=/usr ABCEXTERNAL=/usr/bin/abc STRIP=/bin/true
[Makefile.conf] CONFIG := gcc
mkdir -p /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/bin
cp yosys yosys-config yosys-filterlib yosys-smtbmc yosys-witness /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/bin
/bin/true -S /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/bin/yosys
/bin/true /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/bin/yosys-filterlib
mkdir -p /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys
cp -r share/. /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/.
+ install -d -m0755 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/include
+ mv /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/include /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/include/yosys
+ install -d -m0755 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/man/man1
+ install -m 0644 yosys-smtbmc.1 debian/yosys.1 debian/yosys-config.1 debian/yosys-filterlib.1 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/man/man1
+ install -d -m0755 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/doc/yosys
+ install -m 0644 docs/build/latex/yosyshqyosys.pdf /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/doc/yosys
+ [[ /usr/bin/python3 =~  - ]]
+ clamp_source_mtime /usr/bin/python3 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
+ python_binary='env /usr/bin/python3'
+ bytecode_compilation_path=/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
+ PYTHONPATH=/usr/lib/rpm/redhat
+ env /usr/bin/python3 -s -B -m clamp_source_mtime /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
Listing '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3'...
Clamping mtime of '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/smtio.py'
Clamping mtime of '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/ywio.py'
++ /usr/bin/python3 -c 'import sys; sys.stdout.write('\''{0.major}{0.minor}'\''.format(sys.version_info))'
+ python_version=313
+ '[' 313 -ge 39 ']'
+ py39_byte_compile /usr/bin/python3 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
+ python_binary='env PYTHONHASHSEED=0 /usr/bin/python3'
+ bytecode_compilation_path=/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
+ env PYTHONHASHSEED=0 /usr/bin/python3 -s -B -m compileall -j2 -o 0 -o 1 -s /builddir/build/BUILD/yosys-0.47-build/BUILDROOT -p / --hardlink-dupes --invalidation-mode=timestamp /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3
Listing '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3'...
Compiling '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/smtio.py'...
Compiling '/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/ywio.py'...
+ /usr/bin/find-debuginfo -j2 --strict-build-id -m -i --build-id-seed 0.47-1.20241110gitf20f913.fc42 --unique-debug-suffix -0.47-1.20241110gitf20f913.fc42.x86_64 --unique-debug-src-base yosys-0.47-1.20241110gitf20f913.fc42.x86_64 --run-dwz --dwz-low-mem-die-limit 10000000 --dwz-max-die-limit 110000000 -S debugsourcefiles.list /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
find-debuginfo: starting
Extracting debug info from 2 files
DWARF-compressing 2 files
dwz: Too few files for multifile optimization
sepdebugcrcfix: Updated 2 CRC32s, 0 CRC32s did match.
Creating .debug symlinks for symlinks to ELF files
Copying sources found by 'debugedit -l' to /usr/src/debug/yosys-0.47-1.20241110gitf20f913.fc42.x86_64
find-debuginfo: done
+ /usr/lib/rpm/check-buildroot
+ /usr/lib/rpm/redhat/brp-ldconfig
+ /usr/lib/rpm/brp-compress
+ /usr/lib/rpm/redhat/brp-strip-lto /usr/bin/strip
+ /usr/lib/rpm/brp-strip-static-archive /usr/bin/strip
+ /usr/lib/rpm/check-rpaths
+ /usr/lib/rpm/redhat/brp-mangle-shebangs
mangling shebang in /usr/bin/yosys-config from /usr/bin/env bash to #!/usr/bin/bash
+ /usr/lib/rpm/brp-remove-la-files
+ env /usr/lib/rpm/redhat/brp-python-bytecompile '' 1 0 -j2
+ /usr/lib/rpm/redhat/brp-python-hardlink
+ /usr/bin/add-determinism --brp -j2 /builddir/build/BUILD/yosys-0.47-build/BUILDROOT
/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/__pycache__/smtio.cpython-313.pyc: replacing with normalized version
/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/__pycache__/ywio.cpython-313.pyc: replacing with normalized version
/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/__pycache__/smtio.cpython-313.opt-1.pyc: replacing with normalized version
/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/yosys/python3/__pycache__/ywio.cpython-313.opt-1.pyc: replacing with normalized version
Scanned 141 directories and 737 files,
               processed 4 inodes,
               4 modified (4 replaced + 0 rewritten),
               0 unsupported format, 0 errors
Reading /builddir/build/BUILD/yosys-0.47-build/SPECPARTS/rpm-debuginfo.specpart
Executing(%check): /bin/sh -e /var/tmp/rpm-tmp.hukDB8
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ CFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CFLAGS
+ CXXFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Werror=format-security -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer '
+ export CXXFLAGS
+ FFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FFLAGS
+ FCFLAGS='-O2 -flto=auto -ffat-lto-objects -fexceptions -g -grecord-gcc-switches -pipe -Wall -Wp,-U_FORTIFY_SOURCE,-D_FORTIFY_SOURCE=3 -Wp,-D_GLIBCXX_ASSERTIONS -specs=/usr/lib/rpm/redhat/redhat-hardened-cc1 -fstack-protector-strong -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -I/usr/lib64/gfortran/modules '
+ export FCFLAGS
+ VALAFLAGS=-g
+ export VALAFLAGS
+ RUSTFLAGS='-Copt-level=3 -Cdebuginfo=2 -Ccodegen-units=1 -Cstrip=none -Cforce-frame-pointers=yes -Clink-arg=-specs=/usr/lib/rpm/redhat/redhat-package-notes --cap-lints=warn'
+ export RUSTFLAGS
+ LDFLAGS='-Wl,-z,relro -Wl,--as-needed  -Wl,-z,pack-relative-relocs -Wl,-z,now -specs=/usr/lib/rpm/redhat/redhat-hardened-ld -specs=/usr/lib/rpm/redhat/redhat-annobin-cc1  -Wl,--build-id=sha1 -specs=/usr/lib/rpm/redhat/redhat-package-notes '
+ export LDFLAGS
+ LT_SYS_LIBRARY_PATH=/usr/lib64:
+ export LT_SYS_LIBRARY_PATH
+ CC=gcc
+ export CC
+ CXX=g++
+ export CXX
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ make test ABCEXTERNAL=/usr/bin/abc SEED=314159265359
[Makefile.conf] CONFIG := gcc
cd tests/simple && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/simple'
+ gcc -Wall -o /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/tools/cmp_tbdata /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/tools/cmp_tbdata.c
Test: arrays02 -> ok
Test: arrays03 -> ok
Test: asgn_binop -> ok
Test: case_expr_extend -> ok
Test: case_expr_query -> ok
Test: defvalue -> ok
Test: implicit_ports -> ok
Test: lesser_size_cast -> ok
Test: local_loop_var -> ok
Test: macro_arg_spaces -> ok
Test: matching_end_labels -> ok
Test: memwr_port_connection -> ok
Test: unnamed_block_decl -> ok
Test: aes_kexp128 -> ok
Test: always01 -> ok
Test: always02 -> ok
Test: always03 -> ok
Test: arraycells -> ok
Test: arrays01 -> ok
Test: attrib01_module -> ok
Test: attrib02_port_decl -> ok
Test: attrib03_parameter -> ok
Test: attrib04_net_var -> ok
Test: attrib06_operator_suffix -> ok
Test: attrib08_mod_inst -> ok
Test: attrib09_case -> ok
Test: carryadd -> ok
Test: case_expr_const -> ok
Test: case_expr_non_const -> ok
Test: case_large -> ok
Test: const_branch_finish -> ok
Test: const_fold_func -> ok
Test: const_func_shadow -> ok
Test: constmuldivmod -> ok
Test: constpower -> ok
Test: dff_different_styles -> ok
Test: dff_init -> ok
Test: dynslice -> ok
Test: fiedler-cooley -> ok
Test: forgen01 -> ok
Test: forgen02 -> ok
Test: forloops -> ok
Test: fsm -> ok
Test: func_block -> ok
Test: func_recurse -> ok
Test: func_width_scope -> ok
Test: genblk_collide -> ok
Test: genblk_dive -> ok
Test: genblk_order -> ok
Test: genblk_port_shadow -> ok
Test: generate -> ok
Test: graphtest -> ok
Test: hierarchy -> ok
Test: hierdefparam -> ok
Test: i2c_master_tests -> ok
Test: ifdef_1 -> ok
Test: ifdef_2 -> ok
Test: localparam_attr -> ok
Test: loop_prefix_case -> ok
Test: loop_var_shadow -> ok
Test: loops -> ok
Test: macro_arg_surrounding_spaces -> ok
Test: macros -> ok
Test: mem2reg -> ok
Test: mem2reg_bounds_tern -> ok
Test: mem_arst -> ok
Test: memory -> ok
Test: module_scope -> ok
Test: module_scope_case -> ok
Test: module_scope_func -> ok
Test: multiplier -> ok
Test: muxtree -> ok
Test: named_genblk -> ok
Test: nested_genblk_resolve -> ok
Test: omsp_dbg_uart -> ok
Test: operators -> ok
Test: param_attr -> ok
Test: paramods -> ok
Test: partsel -> ok
Test: process -> ok
Test: realexpr -> ok
Test: repwhile -> ok
Test: retime -> ok
Test: rotate -> ok
Test: scopes -> ok
Test: sign_part_assign -> ok
Test: signed_full_slice -> ok
Test: signedexpr -> ok
Test: sincos -> ok
Test: specify -> ok
Test: string_format -> ok
Test: subbytes -> ok
Test: task_func -> ok
Test: undef_eqx_nex -> ok
Test: usb_phy_tests -> ok
Test: values -> ok
Test: verilog_primitives -> ok
Test: vloghammer -> ok
Test: wandwor -> ok
Test: wreduce -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/simple'
cd tests/simple_abc9 && bash run-test.sh "-S 314159265359"
ls: cannot access '*.sv': No such file or directory
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/simple_abc9'
Test: abc9 -> ok
Test: aes_kexp128 -> ok
Test: always01 -> ok
Test: always02 -> ok
Test: always03 -> ok
Test: arraycells -> ok
Test: arrays01 -> ok
Test: attrib01_module -> ok
Test: attrib02_port_decl -> ok
Test: attrib03_parameter -> ok
Test: attrib04_net_var -> ok
Test: attrib06_operator_suffix -> ok
Test: attrib08_mod_inst -> ok
Test: attrib09_case -> ok
Test: carryadd -> ok
Test: case_expr_const -> ok
Test: case_expr_non_const -> ok
Test: case_large -> ok
Test: const_branch_finish -> ok
Test: const_fold_func -> ok
Test: const_func_shadow -> ok
Test: constmuldivmod -> ok
Test: constpower -> ok
Test: dff_different_styles -> ok
Test: dff_init -> ok
Test: dynslice -> ok
Test: fiedler-cooley -> ok
Test: forgen01 -> ok
Test: forgen02 -> ok
Test: forloops -> ok
Test: fsm -> ok
Test: func_block -> ok
Test: func_recurse -> ok
Test: func_width_scope -> ok
Test: genblk_collide -> ok
Test: genblk_dive -> ok
Test: genblk_order -> ok
Test: genblk_port_shadow -> ok
Test: generate -> ok
Test: graphtest -> ok
Test: hierarchy -> ok
Test: hierdefparam -> ok
Test: i2c_master_tests -> ok
Test: ifdef_1 -> ok
Test: ifdef_2 -> ok
Test: localparam_attr -> ok
Test: loop_prefix_case -> ok
Test: loop_var_shadow -> ok
Test: loops -> ok
Test: macro_arg_surrounding_spaces -> ok
Test: macros -> ok
Test: mem2reg -> ok
Test: mem2reg_bounds_tern -> ok
Test: mem_arst -> ok
Test: memory -> ok
Test: module_scope -> ok
Test: module_scope_case -> ok
Test: module_scope_func -> ok
Test: multiplier -> ok
Test: muxtree -> ok
Test: named_genblk -> ok
Test: nested_genblk_resolve -> ok
Test: omsp_dbg_uart -> ok
Test: operators -> ok
Test: param_attr -> ok
Test: paramods -> ok
Test: partsel -> ok
Test: process -> ok
Test: realexpr -> ok
Test: repwhile -> ok
Test: retime -> ok
Test: rotate -> ok
Test: scopes -> ok
Test: sign_part_assign -> ok
Test: signed_full_slice -> ok
Test: signedexpr -> ok
Test: sincos -> ok
Test: string_format -> ok
Test: subbytes -> ok
Test: task_func -> ok
Test: undef_eqx_nex -> ok
Test: usb_phy_tests -> ok
Test: values -> ok
Test: verilog_primitives -> ok
Test: vloghammer -> ok
Test: wandwor -> ok
Test: wreduce -> ok
Test: arrays02 -> ok
Test: arrays03 -> ok
Test: asgn_binop -> ok
Test: case_expr_extend -> ok
Test: case_expr_query -> ok
Test: defvalue -> ok
Test: implicit_ports -> ok
Test: lesser_size_cast -> ok
Test: local_loop_var -> ok
Test: macro_arg_spaces -> ok
Test: matching_end_labels -> ok
Test: memwr_port_connection -> ok
Test: unnamed_block_decl -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/simple_abc9'
cd tests/hana && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/hana'
Test: test_intermout -> ok
Test: test_parse2synthtrans -> ok
Test: test_parser -> ok
Test: test_simulation_always -> ok
Test: test_simulation_and -> ok
Test: test_simulation_buffer -> ok
Test: test_simulation_decoder -> ok
Test: test_simulation_inc -> ok
Test: test_simulation_mux -> ok
Test: test_simulation_nand -> ok
Test: test_simulation_nor -> ok
Test: test_simulation_or -> ok
Test: test_simulation_seq -> ok
Test: test_simulation_shifter -> ok
Test: test_simulation_sop -> ok
Test: test_simulation_techmap -> ok
Test: test_simulation_techmap_tech -> ok
Test: test_simulation_vlib -> ok
Test: test_simulation_xnor -> ok
Test: test_simulation_xor -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/hana'
cd tests/asicworld && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/asicworld'
Test: code_hdl_models_GrayCounter -> ok
Test: code_hdl_models_arbiter -> ok
Test: code_hdl_models_cam -> ok
Test: code_hdl_models_clk_div -> ok
Test: code_hdl_models_clk_div_45 -> ok
Test: code_hdl_models_d_ff_gates -> ok
Test: code_hdl_models_d_latch_gates -> ok
Test: code_hdl_models_decoder_2to4_gates -> ok
Test: code_hdl_models_decoder_using_assign -> ok
Test: code_hdl_models_decoder_using_case -> ok
Test: code_hdl_models_dff_async_reset -> ok
Test: code_hdl_models_dff_sync_reset -> ok
Test: code_hdl_models_encoder_4to2_gates -> ok
Test: code_hdl_models_encoder_using_case -> ok
Test: code_hdl_models_encoder_using_if -> ok
Test: code_hdl_models_full_adder_gates -> ok
Test: code_hdl_models_full_subtracter_gates -> ok
Test: code_hdl_models_gray_counter -> ok
Test: code_hdl_models_half_adder_gates -> ok
Test: code_hdl_models_lfsr -> ok
Test: code_hdl_models_lfsr_updown -> ok
Test: code_hdl_models_mux_2to1_gates -> ok
Test: code_hdl_models_mux_using_assign -> ok
Test: code_hdl_models_mux_using_case -> ok
Test: code_hdl_models_mux_using_if -> ok
Test: code_hdl_models_one_hot_cnt -> ok
Test: code_hdl_models_parallel_crc -> ok
Test: code_hdl_models_parity_using_assign -> ok
Test: code_hdl_models_parity_using_bitwise -> ok
Test: code_hdl_models_parity_using_function -> ok
Test: code_hdl_models_pri_encoder_using_assign -> ok
Test: code_hdl_models_rom_using_case -> ok
Test: code_hdl_models_serial_crc -> ok
Test: code_hdl_models_tff_async_reset -> ok
Test: code_hdl_models_tff_sync_reset -> ok
Test: code_hdl_models_uart -> ok
Test: code_hdl_models_up_counter -> ok
Test: code_hdl_models_up_counter_load -> ok
Test: code_hdl_models_up_down_counter -> ok
Test: code_specman_switch_fabric -> ok
Test: code_tidbits_asyn_reset -> ok
Test: code_tidbits_blocking -> ok
Test: code_tidbits_fsm_using_always -> ok
Test: code_tidbits_fsm_using_function -> ok
Test: code_tidbits_fsm_using_single_always -> ok
Test: code_tidbits_nonblocking -> ok
Test: code_tidbits_reg_combo_example -> ok
Test: code_tidbits_reg_seq_example -> ok
Test: code_tidbits_syn_reset -> ok
Test: code_tidbits_wire_example -> ok
Test: code_verilog_tutorial_addbit -> ok
Test: code_verilog_tutorial_always_example -> ok
Test: code_verilog_tutorial_bus_con -> ok
Test: code_verilog_tutorial_comment -> ok
Test: code_verilog_tutorial_counter -> ok
Test: code_verilog_tutorial_d_ff -> ok
Test: code_verilog_tutorial_decoder -> ok
Test: code_verilog_tutorial_decoder_always -> ok
Test: code_verilog_tutorial_escape_id -> ok
Test: code_verilog_tutorial_explicit -> ok
Test: code_verilog_tutorial_first_counter -> ok
Test: code_verilog_tutorial_flip_flop -> ok
Test: code_verilog_tutorial_fsm_full -> ok
Test: code_verilog_tutorial_good_code -> ok
Test: code_verilog_tutorial_if_else -> ok
Test: code_verilog_tutorial_multiply -> ok
Test: code_verilog_tutorial_mux_21 -> ok
Test: code_verilog_tutorial_n_out_primitive -> ok
Test: code_verilog_tutorial_parallel_if -> ok
Test: code_verilog_tutorial_parity -> ok
Test: code_verilog_tutorial_simple_function -> ok
Test: code_verilog_tutorial_simple_if -> ok
Test: code_verilog_tutorial_task_global -> ok
Test: code_verilog_tutorial_tri_buf -> ok
Test: code_verilog_tutorial_v2k_reg -> ok
Test: code_verilog_tutorial_which_clock -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/asicworld'
# +cd tests/realmath && bash run-test.sh "-S 314159265359"
cd tests/share && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
[0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]
cd tests/opt_share && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/opt_share'
[0][1][2][3][4][5][6][7][8][9][10][11][12][13][14][15][16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31][32][33][34][35][36][37][38][39][40][41][42][43][44][45][46][47][48][49][50][51][52][53][54][55][56][57][58][59][60][61][62][63][64][65][66][67][68][69][70][71][72][73][74][75][76][77][78][79][80][81][82][83][84][85][86][87][88][89][90][91][92][93][94][95][96][97][98][99]make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/opt_share'

cd tests/fsm && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/fsm'
[0]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[1]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[2]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[3]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[4]K[5]K[6]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
T[7]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[8]K[9]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[10]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[11]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[12]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[13]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[14]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[15]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[16]K[17]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[18]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[19]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[20]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[21]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[22]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[23]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[24]K[25]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[26]K[27]K[28]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[29]K[30]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[31]K[32]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[33]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[34]K[35]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[36]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[37]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[38]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[39]K[40]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[41]K[42]K[43]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[44]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[45]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[46]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[47]K[48]Warning: Regarding the user-specified fsm_encoding attribute on gate.state:
    Users of state reg look like FSM recoding might result in larger circuit.
    Doesn't look like a proper FSM. Possible simulation-synthesis mismatch!
K[49]K
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/fsm'
cd tests/techmap && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/techmap'
Passed abc9.ys
Warning: wire '\Q' is assigned in a block at <<EOT:9.5-9.11.
Warning: wire '\Q' is assigned in a block at <<EOT:11.5-11.11.
Passed adff2dff.ys
Passed aigmap.ys
Warning: Resizing cell port top.s0.f.j from 2 bits to 1 bits.
Passed autopurge.ys
Passed bmuxmap_pmux.ys
Passed booth.ys
Warning: Feature 'bufnorm' is experimental.
Passed bufnorm.ys
Passed bug2183.ys
Passed bug2321.ys
Passed bug2332.ys
Passed bug2759.ys
Passed bug2972.ys
Passed cellmatch.ys
Passed cellname.ys
Passed clkbufmap.ys
Passed clockgate.ys
Passed cmp2lcu.ys
Warning: wire '\Q' is assigned in a block at <<EOT:8.3-8.9.
Passed dff2ff.ys
Passed dffinit.ys
Passed dfflegalize_adff.ys
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe1_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff1_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adffe0_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for top.adff0_.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe1.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff1.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff3
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adffe0.ff0
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff2
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff1
Warning: Emulating mismatched async reset and init with several FFs and a mux for adff0.ff0
Passed dfflegalize_adff_init.ys
Passed dfflegalize_adlatch.ys
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch1_.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for top.adlatch0_.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch1.ff0
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff2
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff1
Warning: Emulating mismatched async reset and init with several latches and a mux for adlatch0.ff0
Passed dfflegalize_adlatch_init.ys
Passed dfflegalize_aldff.ys
Passed dfflegalize_aldff_init.ys
Passed dfflegalize_dff.ys
Passed dfflegalize_dff_init.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr_.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr.ff0
Passed dfflegalize_dffsr.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff4
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsre0_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dffsr0_.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre1_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr1_.ff0 [$_DFFSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsre0_.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dffsr0_.ff0 [$_DFFSR_PPP_].
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff4
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsre0.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dffsr0.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre1.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr1.ff0 [$_DFFSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff4 [$_DFFSRE_NPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff3 [$_DFFSRE_PNPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff2 [$_DFFSRE_PPNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff1 [$_DFFSRE_PPPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsre0.ff0 [$_DFFSRE_PPPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff3 [$_DFFSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff2 [$_DFFSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff1 [$_DFFSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dffsr0.ff0 [$_DFFSR_PPP_].
Passed dfflegalize_dffsr_init.ys
Passed dfflegalize_dlatch.ys
Passed dfflegalize_dlatch_const.ys
Passed dfflegalize_dlatch_init.ys
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr.ff0
Passed dfflegalize_dlatchsr.ys
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff1
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff2
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff3
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr1_.ff0
Warning: Emulating async set + reset with several FFs and a mux for top.dlatchsr0_.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr1_.ff0 [$_DLATCHSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.dlatchsr0_.ff0 [$_DLATCHSR_PPP_].
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr1.ff0
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff3
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff2
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff1
Warning: Emulating async set + reset with several FFs and a mux for dlatchsr0.ff0
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr1.ff0 [$_DLATCHSR_PPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff3 [$_DLATCHSR_NPP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff2 [$_DLATCHSR_PNP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff1 [$_DLATCHSR_PPN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize dlatchsr0.ff0 [$_DLATCHSR_PPP_].
Passed dfflegalize_dlatchsr_init.ys
Passed dfflegalize_inv.ys
Passed dfflegalize_mince.ys
Passed dfflegalize_minsrst.ys
Passed dfflegalize_sr.ys
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr1_.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize top.sr0_.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr1.ff0 [$_SR_PP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff2 [$_SR_NP_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff1 [$_SR_PN_].
Warning: Flipping D/Q/init and inserting priority fixup to legalize sr0.ff0 [$_SR_PP_].
Passed dfflegalize_sr_init.ys
Warning: Complex async reset for dff `\Q'.
Passed dfflibmap.ys
Passed dffunmap.ys
Passed extractinv.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:23)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:29)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:35)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:58)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:18)
Passed iopadmap.ys
Passed kogge-stone.ys
Passed pmux2mux.ys
Passed shiftx2mux.ys
Passed techmap_chtype.ys
Passed techmap_replace.ys
Passed wireinit.ys
Passed zinit.ys
Passed mem_simple_4x1_runtest.sh
Passed recursive_runtest.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/techmap'
cd tests/memories && bash run-test.sh "-A /usr/bin/abc" "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/memories'
Test: amber23_sram_byte_en -> ok
Test: firrtl_938 -> ok
Test: implicit_en -> ok
Test: issue00335 -> ok
Test: issue00710 -> ok
Test: no_implicit_en -> ok
Test: read_arst -> ok
Test: read_two_mux -> ok
Test: shared_ports -> ok
Test: simple_sram_byte_en -> ok
Test: trans_addr_enable -> ok
Test: trans_sdp -> ok
Test: trans_sp -> ok
Test: wide_all -> ok
Test: wide_read_async -> ok
Test: wide_read_mixed -> ok
Test: wide_read_sync -> ok
Test: wide_read_trans -> ok
Test: wide_thru_priority -> ok
Test: wide_write -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/memories'
egrep: warning: egrep is obsolescent; using grep -E
Testing expectations for amber23_sram_byte_en.v .. ok.
Testing expectations for implicit_en.v .. ok.
Testing expectations for issue00335.v .. ok.
Testing expectations for issue00710.v .. ok.
Testing expectations for no_implicit_en.v .. ok.
Testing expectations for read_arst.v .. ok.
Testing expectations for read_two_mux.v .. ok.
Testing expectations for shared_ports.v .. ok.
Testing expectations for simple_sram_byte_en.v .. ok.
Testing expectations for trans_addr_enable.v .. ok.
Testing expectations for trans_sdp.v .. ok.
Testing expectations for trans_sp.v .. ok.
Testing expectations for wide_all.v .. ok.
Testing expectations for wide_read_async.v .. ok.
Testing expectations for wide_read_mixed.v .. ok.
Testing expectations for wide_read_sync.v .. ok.
Testing expectations for wide_read_trans.v .. ok.
Testing expectations for wide_thru_priority.v .. ok.
Testing expectations for wide_write.v .. ok.
cd tests/memlib && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/memlib'
Test: t_async_big -> ok
Test: t_async_big_block -> ok
Test: t_async_small -> ok
Test: t_async_small_block -> ok
Test: t_sync_big -> ok
Test: t_sync_big_sdp -> ok
Test: t_sync_big_lut -> ok
Test: t_sync_small -> ok
Test: t_sync_small_block -> ok
Test: t_sync_small_block_attr -> ok
Test: t_init_lut_zeros_zero -> ok
Test: t_init_lut_zeros_any -> ok
Test: t_init_lut_val_zero -> ok
Test: t_init_lut_val_any -> ok
Test: t_init_lut_val_no_undef -> ok
Test: t_init_lut_val2_any -> ok
Test: t_init_lut_val2_no_undef -> ok
Test: t_init_lut_x_none -> ok
Test: t_init_lut_x_zero -> ok
Test: t_init_lut_x_any -> ok
Test: t_init_lut_x_no_undef -> ok
Test: t_ram_18b2B -> ok
Test: t_ram_9b1B -> ok
Test: t_ram_4b1B -> ok
Test: t_ram_2b1B -> ok
Test: t_ram_1b1B -> ok
Test: t_init_9b1B_zeros_zero -> ok
Test: t_init_9b1B_zeros_any -> ok
Test: t_init_9b1B_val_zero -> ok
Test: t_init_9b1B_val_any -> ok
Test: t_init_9b1B_val_no_undef -> ok
Test: t_init_13b2B_val_any -> ok
Test: t_init_18b2B_val_any -> ok
Test: t_init_18b2B_val_no_undef -> ok
Test: t_init_4b1B_x_none -> ok
Test: t_init_4b1B_x_zero -> ok
Test: t_init_4b1B_x_any -> ok
Test: t_init_4b1B_x_no_undef -> ok
Test: t_clock_a4_wANYrANYsFalse -> ok
Test: t_clock_a4_wANYrNEGsFalse -> ok
Test: t_clock_a4_wANYrPOSsFalse -> ok
Test: t_clock_a4_wNEGrANYsFalse -> ok
Test: t_clock_a4_wNEGrPOSsFalse -> ok
Test: t_clock_a4_wNEGrNEGsFalse -> ok
Test: t_clock_a4_wPOSrANYsFalse -> ok
Test: t_clock_a4_wPOSrNEGsFalse -> ok
Test: t_clock_a4_wPOSrPOSsFalse -> ok
Test: t_clock_a4_wANYrANYsTrue -> ok
Test: t_clock_a4_wNEGrPOSsTrue -> ok
Test: t_clock_a4_wNEGrNEGsTrue -> ok
Test: t_clock_a4_wPOSrNEGsTrue -> ok
Test: t_clock_a4_wPOSrPOSsTrue -> ok
Test: t_unmixed -> ok
Test: t_mixed_9_18 -> ok
Test: t_mixed_18_9 -> ok
Test: t_mixed_36_9 -> ok
Test: t_mixed_4_2 -> ok
Test: t_tdp -> ok
Test: t_sync_2clk -> ok
Test: t_sync_shared -> ok
Test: t_sync_2clk_shared -> ok
Test: t_sync_trans_old_old -> ok
Test: t_sync_trans_old_new -> ok
Test: t_sync_trans_old_none -> ok
Test: t_sync_trans_new_old -> ok
Test: t_sync_trans_new_new -> ok
Test: t_sync_trans_new_none -> ok
Test: t_sp_nc_none -> ok
Test: t_sp_new_none -> ok
Test: t_sp_old_none -> ok
Test: t_sp_nc_nc -> ok
Test: t_sp_new_nc -> ok
Test: t_sp_old_nc -> ok
Test: t_sp_nc_new -> ok
Test: t_sp_new_new -> ok
Test: t_sp_old_new -> ok
Test: t_sp_nc_old -> ok
Test: t_sp_new_old -> ok
Test: t_sp_old_old -> ok
Test: t_sp_nc_new_only -> ok
Test: t_sp_new_new_only -> ok
Test: t_sp_old_new_only -> ok
Test: t_sp_nc_new_only_be -> ok
Test: t_sp_new_new_only_be -> ok
Test: t_sp_old_new_only_be -> ok
Test: t_sp_nc_new_be -> ok
Test: t_sp_new_new_be -> ok
Test: t_sp_old_new_be -> ok
Test: t_sp_nc_old_be -> ok
Test: t_sp_new_old_be -> ok
Test: t_sp_old_old_be -> ok
Test: t_sp_nc_nc_be -> ok
Test: t_sp_new_nc_be -> ok
Test: t_sp_old_nc_be -> ok
Test: t_sp_nc_auto -> ok
Test: t_sp_new_auto -> ok
Test: t_sp_old_auto -> ok
Test: t_sp_nc_auto_be -> ok
Test: t_sp_new_auto_be -> ok
Test: t_sp_old_auto_be -> ok
Test: t_sp_init_x_x -> ok
Test: t_sp_init_x_x_re -> ok
Test: t_sp_init_x_x_ce -> ok
Test: t_sp_init_0_x -> ok
Test: t_sp_init_0_x_re -> ok
Test: t_sp_init_0_0 -> ok
Test: t_sp_init_0_0_re -> ok
Test: t_sp_init_0_any -> ok
Test: t_sp_init_0_any_re -> ok
Test: t_sp_init_v_x -> ok
Test: t_sp_init_v_x_re -> ok
Test: t_sp_init_v_0 -> ok
Test: t_sp_init_v_0_re -> ok
Test: t_sp_init_v_any -> ok
Test: t_sp_init_v_any_re -> ok
Test: t_sp_arst_x_x -> ok
Test: t_sp_arst_x_x_re -> ok
Test: t_sp_arst_0_x -> ok
Test: t_sp_arst_0_x_re -> ok
Test: t_sp_arst_0_0 -> ok
Test: t_sp_arst_0_0_re -> ok
Test: t_sp_arst_0_any -> ok
Test: t_sp_arst_0_any_re -> ok
Test: t_sp_arst_0_init -> ok
Test: t_sp_arst_0_init_re -> ok
Test: t_sp_arst_v_x -> ok
Test: t_sp_arst_v_x_re -> ok
Test: t_sp_arst_v_0 -> ok
Test: t_sp_arst_v_0_re -> ok
Test: t_sp_arst_v_any -> ok
Test: t_sp_arst_v_any_re -> ok
Test: t_sp_arst_v_init -> ok
Test: t_sp_arst_v_init_re -> ok
Test: t_sp_arst_e_x -> ok
Test: t_sp_arst_e_x_re -> ok
Test: t_sp_arst_e_0 -> ok
Test: t_sp_arst_e_0_re -> ok
Test: t_sp_arst_e_any -> ok
Test: t_sp_arst_e_any_re -> ok
Test: t_sp_arst_e_init -> ok
Test: t_sp_arst_e_init_re -> ok
Test: t_sp_arst_n_x -> ok
Test: t_sp_arst_n_x_re -> ok
Test: t_sp_arst_n_0 -> ok
Test: t_sp_arst_n_0_re -> ok
Test: t_sp_arst_n_any -> ok
Test: t_sp_arst_n_any_re -> ok
Test: t_sp_arst_n_init -> ok
Test: t_sp_arst_n_init_re -> ok
Test: t_sp_srst_x_x -> ok
Test: t_sp_srst_x_x_re -> ok
Test: t_sp_srst_0_x -> ok
Test: t_sp_srst_0_x_re -> ok
Test: t_sp_srst_0_0 -> ok
Test: t_sp_srst_0_0_re -> ok
Test: t_sp_srst_0_any -> ok
Test: t_sp_srst_0_any_re -> ok
Test: t_sp_srst_0_init -> ok
Test: t_sp_srst_0_init_re -> ok
Test: t_sp_srst_v_x -> ok
Test: t_sp_srst_v_x_re -> ok
Test: t_sp_srst_v_0 -> ok
Test: t_sp_srst_v_0_re -> ok
Test: t_sp_srst_v_any -> ok
Test: t_sp_srst_v_any_re -> ok
Test: t_sp_srst_v_any_re_gated -> ok
Test: t_sp_srst_v_any_ce -> ok
Test: t_sp_srst_v_any_ce_gated -> ok
Test: t_sp_srst_v_init -> ok
Test: t_sp_srst_v_init_re -> ok
Test: t_sp_srst_e_x -> ok
Test: t_sp_srst_e_x_re -> ok
Test: t_sp_srst_e_0 -> ok
Test: t_sp_srst_e_0_re -> ok
Test: t_sp_srst_e_any -> ok
Test: t_sp_srst_e_any_re -> ok
Test: t_sp_srst_e_init -> ok
Test: t_sp_srst_e_init_re -> ok
Test: t_sp_srst_n_x -> ok
Test: t_sp_srst_n_x_re -> ok
Test: t_sp_srst_n_0 -> ok
Test: t_sp_srst_n_0_re -> ok
Test: t_sp_srst_n_any -> ok
Test: t_sp_srst_n_any_re -> ok
Test: t_sp_srst_n_init -> ok
Test: t_sp_srst_n_init_re -> ok
Test: t_sp_srst_gv_x -> ok
Test: t_sp_srst_gv_x_re -> ok
Test: t_sp_srst_gv_0 -> ok
Test: t_sp_srst_gv_0_re -> ok
Test: t_sp_srst_gv_any -> ok
Test: t_sp_srst_gv_any_re -> ok
Test: t_sp_srst_gv_any_re_gated -> ok
Test: t_sp_srst_gv_any_ce -> ok
Test: t_sp_srst_gv_any_ce_gated -> ok
Test: t_sp_srst_gv_init -> ok
Test: t_sp_srst_gv_init_re -> ok
Test: t_wren_a4d4_NO_BYTE -> ok
Test: t_wren_a5d4_NO_BYTE -> ok
Test: t_wren_a6d4_NO_BYTE -> ok
Test: t_wren_a3d8_NO_BYTE -> ok
Test: t_wren_a4d8_NO_BYTE -> ok
Test: t_wren_a4d4_W4_B4 -> ok
Test: t_wren_a4d8_W4_B4_separate -> ok
Test: t_wren_a4d8_W8_B4 -> ok
Test: t_wren_a4d8_W8_B4_separate -> ok
Test: t_wren_a4d8_W8_B8 -> ok
Test: t_wren_a4d8_W8_B8_separate -> ok
Test: t_wren_a4d2w8_W16_B4 -> ok
Test: t_wren_a4d2w8_W16_B4_separate -> ok
Test: t_wren_a4d4w4_W16_B4 -> ok
Test: t_wren_a4d4w4_W16_B4_separate -> ok
Test: t_wren_a5d4w2_W16_B4 -> ok
Test: t_wren_a5d4w2_W16_B4_separate -> ok
Test: t_wren_a5d4w4_W16_B4 -> ok
Test: t_wren_a5d4w4_W16_B4_separate -> ok
Test: t_wren_a4d8w2_W16_B4 -> ok
Test: t_wren_a4d8w2_W16_B4_separate -> ok
Test: t_wren_a5d8w1_W16_B4 -> ok
Test: t_wren_a5d8w1_W16_B4_separate -> ok
Test: t_wren_a5d8w2_W16_B4 -> ok
Test: t_wren_a5d8w2_W16_B4_separate -> ok
Test: t_wren_a4d16w1_W16_B4 -> ok
Test: t_wren_a4d16w1_W16_B4_separate -> ok
Test: t_wren_a4d4w2_W8_B8 -> ok
Test: t_wren_a4d4w2_W8_B8_separate -> ok
Test: t_wren_a4d4w1_W8_B8 -> ok
Test: t_wren_a4d4w1_W8_B8_separate -> ok
Test: t_wren_a4d8w2_W8_B8 -> ok
Test: t_wren_a4d8w2_W8_B8_separate -> ok
Test: t_wren_a3d8w2_W8_B8 -> ok
Test: t_wren_a3d8w2_W8_B8_separate -> ok
Test: t_wren_a4d4w2_W8_B4 -> ok
Test: t_wren_a4d4w2_W8_B4_separate -> ok
Test: t_wren_a4d2w4_W8_B4 -> ok
Test: t_wren_a4d2w4_W8_B4_separate -> ok
Test: t_wren_a4d4w4_W8_B4 -> ok
Test: t_wren_a4d4w4_W8_B4_separate -> ok
Test: t_wren_a4d4w4_W4_B4 -> ok
Test: t_wren_a4d4w4_W4_B4_separate -> ok
Test: t_wren_a4d4w5_W4_B4 -> ok
Test: t_wren_a4d4w5_W4_B4_separate -> ok
Test: t_geom_a4d64_wren -> ok
Test: t_geom_a5d32_wren -> ok
Test: t_geom_a5d64_wren -> ok
Test: t_geom_a6d16_wren -> ok
Test: t_geom_a6d30_wren -> ok
Test: t_geom_a6d64_wren -> ok
Test: t_geom_a7d4_wren -> ok
Test: t_geom_a7d6_wren -> ok
Test: t_geom_a7d8_wren -> ok
Test: t_geom_a7d17_wren -> ok
Test: t_geom_a8d4_wren -> ok
Test: t_geom_a8d6_wren -> ok
Test: t_geom_a9d4_wren -> ok
Test: t_geom_a9d8_wren -> ok
Test: t_geom_a9d5_wren -> ok
Test: t_geom_a9d6_wren -> ok
Test: t_geom_a3d18_9b1B -> ok
Test: t_geom_a4d4_9b1B -> ok
Test: t_geom_a4d18_9b1B -> ok
Test: t_geom_a5d32_9b1B -> ok
Test: t_geom_a6d4_9b1B -> ok
Test: t_geom_a7d11_9b1B -> ok
Test: t_geom_a7d18_9b1B -> ok
Test: t_geom_a11d1_9b1B -> ok
Test: t_wide_sdp_a6r1w1b1x1 -> ok
Test: t_wide_sdp_a7r1w1b1x1 -> ok
Test: t_wide_sdp_a8r1w1b1x1 -> ok
Test: t_wide_sdp_a6r0w0b0x0 -> ok
Test: t_wide_sdp_a6r1w0b0x0 -> ok
Test: t_wide_sdp_a6r2w0b0x0 -> ok
Test: t_wide_sdp_a6r3w0b0x0 -> ok
Test: t_wide_sdp_a6r4w0b0x0 -> ok
Test: t_wide_sdp_a6r5w0b0x0 -> ok
Test: t_wide_sdp_a6r0w1b0x0 -> ok
Test: t_wide_sdp_a6r0w1b1x0 -> ok
Test: t_wide_sdp_a6r0w2b0x0 -> ok
Test: t_wide_sdp_a6r0w2b2x0 -> ok
Test: t_wide_sdp_a6r0w3b2x0 -> ok
Test: t_wide_sdp_a6r0w4b2x0 -> ok
Test: t_wide_sdp_a6r0w5b2x0 -> ok
Test: t_wide_sdp_a7r0w0b0x0 -> ok
Test: t_wide_sdp_a7r1w0b0x0 -> ok
Test: t_wide_sdp_a7r2w0b0x0 -> ok
Test: t_wide_sdp_a7r3w0b0x0 -> ok
Test: t_wide_sdp_a7r4w0b0x0 -> ok
Test: t_wide_sdp_a7r5w0b0x0 -> ok
Test: t_wide_sdp_a7r0w1b0x0 -> ok
Test: t_wide_sdp_a7r0w1b1x0 -> ok
Test: t_wide_sdp_a7r0w2b0x0 -> ok
Test: t_wide_sdp_a7r0w2b2x0 -> ok
Test: t_wide_sdp_a7r0w3b2x0 -> ok
Test: t_wide_sdp_a7r0w4b2x0 -> ok
Test: t_wide_sdp_a7r0w5b2x0 -> ok
Test: t_wide_sp_mix_a6r1w1b1 -> ok
Test: t_wide_sp_mix_a7r1w1b1 -> ok
Test: t_wide_sp_mix_a8r1w1b1 -> ok
Test: t_wide_sp_mix_a6r0w0b0 -> ok
Test: t_wide_sp_mix_a6r1w0b0 -> ok
Test: t_wide_sp_mix_a6r2w0b0 -> ok
Test: t_wide_sp_mix_a6r3w0b0 -> ok
Test: t_wide_sp_mix_a6r4w0b0 -> ok
Test: t_wide_sp_mix_a6r5w0b0 -> ok
Test: t_wide_sp_mix_a6r0w1b0 -> ok
Test: t_wide_sp_mix_a6r0w1b1 -> ok
Test: t_wide_sp_mix_a6r0w2b0 -> ok
Test: t_wide_sp_mix_a6r0w2b2 -> ok
Test: t_wide_sp_mix_a6r0w3b2 -> ok
Test: t_wide_sp_mix_a6r0w4b2 -> ok
Test: t_wide_sp_mix_a6r0w5b2 -> ok
Test: t_wide_sp_mix_a7r0w0b0 -> ok
Test: t_wide_sp_mix_a7r1w0b0 -> ok
Test: t_wide_sp_mix_a7r2w0b0 -> ok
Test: t_wide_sp_mix_a7r3w0b0 -> ok
Test: t_wide_sp_mix_a7r4w0b0 -> ok
Test: t_wide_sp_mix_a7r5w0b0 -> ok
Test: t_wide_sp_mix_a7r0w1b0 -> ok
Test: t_wide_sp_mix_a7r0w1b1 -> ok
Test: t_wide_sp_mix_a7r0w2b0 -> ok
Test: t_wide_sp_mix_a7r0w2b2 -> ok
Test: t_wide_sp_mix_a7r0w3b2 -> ok
Test: t_wide_sp_mix_a7r0w4b2 -> ok
Test: t_wide_sp_mix_a7r0w5b2 -> ok
Test: t_wide_sp_tied_a6r1w1b1 -> ok
Test: t_wide_sp_tied_a7r1w1b1 -> ok
Test: t_wide_sp_tied_a8r1w1b1 -> ok
Test: t_wide_sp_tied_a6r0w0b0 -> ok
Test: t_wide_sp_tied_a6r1w0b0 -> ok
Test: t_wide_sp_tied_a6r2w0b0 -> ok
Test: t_wide_sp_tied_a6r3w0b0 -> ok
Test: t_wide_sp_tied_a6r4w0b0 -> ok
Test: t_wide_sp_tied_a6r5w0b0 -> ok
Test: t_wide_sp_tied_a6r0w1b0 -> ok
Test: t_wide_sp_tied_a6r0w1b1 -> ok
Test: t_wide_sp_tied_a6r0w2b0 -> ok
Test: t_wide_sp_tied_a6r0w2b2 -> ok
Test: t_wide_sp_tied_a6r0w3b2 -> ok
Test: t_wide_sp_tied_a6r0w4b2 -> ok
Test: t_wide_sp_tied_a6r0w5b2 -> ok
Test: t_wide_sp_tied_a7r0w0b0 -> ok
Test: t_wide_sp_tied_a7r1w0b0 -> ok
Test: t_wide_sp_tied_a7r2w0b0 -> ok
Test: t_wide_sp_tied_a7r3w0b0 -> ok
Test: t_wide_sp_tied_a7r4w0b0 -> ok
Test: t_wide_sp_tied_a7r5w0b0 -> ok
Test: t_wide_sp_tied_a7r0w1b0 -> ok
Test: t_wide_sp_tied_a7r0w1b1 -> ok
Test: t_wide_sp_tied_a7r0w2b0 -> ok
Test: t_wide_sp_tied_a7r0w2b2 -> ok
Test: t_wide_sp_tied_a7r0w3b2 -> ok
Test: t_wide_sp_tied_a7r0w4b2 -> ok
Test: t_wide_sp_tied_a7r0w5b2 -> ok
Test: t_wide_read_a6r1w1b1 -> ok
Test: t_wide_write_a6r1w1b1 -> ok
Test: t_wide_read_a7r1w1b1 -> ok
Test: t_wide_write_a7r1w1b1 -> ok
Test: t_wide_read_a8r1w1b1 -> ok
Test: t_wide_write_a8r1w1b1 -> ok
Test: t_wide_read_a6r0w0b0 -> ok
Test: t_wide_write_a6r0w0b0 -> ok
Test: t_wide_read_a6r1w0b0 -> ok
Test: t_wide_write_a6r1w0b0 -> ok
Test: t_wide_read_a6r2w0b0 -> ok
Test: t_wide_write_a6r2w0b0 -> ok
Test: t_wide_read_a6r3w0b0 -> ok
Test: t_wide_write_a6r3w0b0 -> ok
Test: t_wide_read_a6r4w0b0 -> ok
Test: t_wide_write_a6r4w0b0 -> ok
Test: t_wide_read_a6r5w0b0 -> ok
Test: t_wide_write_a6r5w0b0 -> ok
Test: t_wide_read_a6r0w1b0 -> ok
Test: t_wide_write_a6r0w1b0 -> ok
Test: t_wide_read_a6r0w1b1 -> ok
Test: t_wide_write_a6r0w1b1 -> ok
Test: t_wide_read_a6r0w2b0 -> ok
Test: t_wide_write_a6r0w2b0 -> ok
Test: t_wide_read_a6r0w2b2 -> ok
Test: t_wide_write_a6r0w2b2 -> ok
Test: t_wide_read_a6r0w3b2 -> ok
Test: t_wide_write_a6r0w3b2 -> ok
Test: t_wide_read_a6r0w4b2 -> ok
Test: t_wide_write_a6r0w4b2 -> ok
Test: t_wide_read_a6r0w5b2 -> ok
Test: t_wide_write_a6r0w5b2 -> ok
Test: t_wide_read_a7r0w0b0 -> ok
Test: t_wide_write_a7r0w0b0 -> ok
Test: t_wide_read_a7r1w0b0 -> ok
Test: t_wide_write_a7r1w0b0 -> ok
Test: t_wide_read_a7r2w0b0 -> ok
Test: t_wide_write_a7r2w0b0 -> ok
Test: t_wide_read_a7r3w0b0 -> ok
Test: t_wide_write_a7r3w0b0 -> ok
Test: t_wide_read_a7r4w0b0 -> ok
Test: t_wide_write_a7r4w0b0 -> ok
Test: t_wide_read_a7r5w0b0 -> ok
Test: t_wide_write_a7r5w0b0 -> ok
Test: t_wide_read_a7r0w1b0 -> ok
Test: t_wide_write_a7r0w1b0 -> ok
Test: t_wide_read_a7r0w1b1 -> ok
Test: t_wide_write_a7r0w1b1 -> ok
Test: t_wide_read_a7r0w2b0 -> ok
Test: t_wide_write_a7r0w2b0 -> ok
Test: t_wide_read_a7r0w2b2 -> ok
Test: t_wide_write_a7r0w2b2 -> ok
Test: t_wide_read_a7r0w3b2 -> ok
Test: t_wide_write_a7r0w3b2 -> ok
Test: t_wide_read_a7r0w4b2 -> ok
Test: t_wide_write_a7r0w4b2 -> ok
Test: t_wide_read_a7r0w5b2 -> ok
Test: t_wide_write_a7r0w5b2 -> ok
Test: t_quad_port_a2d2 -> ok
Test: t_quad_port_a4d2 -> ok
Test: t_quad_port_a5d2 -> ok
Test: t_quad_port_a4d4 -> ok
Test: t_quad_port_a6d2 -> ok
Test: t_quad_port_a4d8 -> ok
Test: t_wide_quad_a4w2r1 -> ok
Test: t_wide_oct_a4w2r1 -> ok
Test: t_wide_quad_a4w2r2 -> ok
Test: t_wide_oct_a4w2r2 -> ok
Test: t_wide_quad_a4w2r3 -> ok
Test: t_wide_oct_a4w2r3 -> ok
Test: t_wide_quad_a4w2r4 -> ok
Test: t_wide_oct_a4w2r4 -> ok
Test: t_wide_quad_a4w2r5 -> ok
Test: t_wide_oct_a4w2r5 -> ok
Test: t_wide_quad_a4w2r6 -> ok
Test: t_wide_oct_a4w2r6 -> ok
Test: t_wide_quad_a4w2r7 -> ok
Test: t_wide_oct_a4w2r7 -> ok
Test: t_wide_quad_a4w2r8 -> ok
Test: t_wide_oct_a4w2r8 -> ok
Test: t_wide_quad_a4w2r9 -> ok
Test: t_wide_oct_a4w2r9 -> ok
Test: t_wide_quad_a4w4r1 -> ok
Test: t_wide_oct_a4w4r1 -> ok
Test: t_wide_quad_a4w4r4 -> ok
Test: t_wide_oct_a4w4r4 -> ok
Test: t_wide_quad_a4w4r6 -> ok
Test: t_wide_oct_a4w4r6 -> ok
Test: t_wide_quad_a4w4r9 -> ok
Test: t_wide_oct_a4w4r9 -> ok
Test: t_wide_quad_a5w2r1 -> ok
Test: t_wide_oct_a5w2r1 -> ok
Test: t_wide_quad_a5w2r4 -> ok
Test: t_wide_oct_a5w2r4 -> ok
Test: t_wide_quad_a5w2r9 -> ok
Test: t_wide_oct_a5w2r9 -> ok
Test: t_no_reset -> ok
Test: t_gclken -> ok
Test: t_ungated -> ok
Test: t_gclken_ce -> ok
Test: t_grden -> ok
Test: t_grden_ce -> ok
Test: t_exclwr -> ok
Test: t_excl_rst -> ok
Test: t_transwr -> ok
Test: t_trans_rst -> ok
Test: t_wr_byte -> ok
Test: t_trans_byte -> ok
Test: t_wr_rst_byte -> ok
Test: t_rst_wr_byte -> ok
Test: t_rdenrst_wr_byte -> ok
Test: t_rom_case -> ok
Test: t_rom_case_block -> ok
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/memlib'
cd tests/bram && bash run-test.sh "-S 314159265359"
generating tests..
PRNG seed: 314159265359
running tests..
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/bram'
Passed memory_bram test 00_01.
Passed memory_bram test 00_02.
Passed memory_bram test 00_03.
Passed memory_bram test 00_04.
Passed memory_bram test 01_00.
Passed memory_bram test 01_02.
Passed memory_bram test 01_03.
Passed memory_bram test 01_04.
Passed memory_bram test 02_00.
Passed memory_bram test 02_01.
Passed memory_bram test 02_03.
Passed memory_bram test 02_04.
Passed memory_bram test 03_00.
Passed memory_bram test 03_01.
Passed memory_bram test 03_02.
Passed memory_bram test 03_04.
Passed memory_bram test 04_00.
Passed memory_bram test 04_01.
Passed memory_bram test 04_02.
Passed memory_bram test 04_03.
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/bram'
cd tests/various && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/various'
Warning: Wire abc9_test027.$abc$91$o is used but has no driver.
Passed abc9.ys
Warning: Feature 'write_aiger2' is experimental.
Passed aiger2.ys
Passed aiger_dff.ys
Passed attrib05_port_conn.ys
Passed attrib07_func_call.ys
Passed autoname.ys
Passed blackbox_wb.ys
Passed box_derive.ys
Passed bug1496.ys
Passed bug1531.ys
Passed bug1614.ys
Passed bug1710.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
<<EOT:3: ERROR: syntax error, unexpected TOK_CONSTVAL
Expected error pattern 'syntax error, unexpected TOK_CONSTVAL' found !!!
Passed bug1745.ys
Passed bug1781.ys
Passed bug1876.ys
Passed bug2014.ys
Passed bug3462.ys
Passed bug4082.ys
Passed cellarray_array_connections.ys
Passed celledges_shift.ys
Passed check.ys
Warning: found logic loop in module top:
    cell $xor$<<EOF:6$2 ($xor) source: <<EOF:6.18-6.59
      A[0] --> Y[0]
    wire \ripple [0] source: <<EOF:2.13-2.19
ERROR: Found 1 problems in 'check -assert'.
Expected error pattern 'Found 1 problems in 'check -assert'' found !!!
Passed check_2.ys
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[2] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[2] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[3] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[3] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[0] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[0] --> DATA[3]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[3] --> DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell $memrd$\mem$<<EOF:10$19 ($memrd) source: <<EOF:10.14-10.17
      ADDR[1] --> DATA[2]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell $memrd$\mem$<<EOF:9$18 ($memrd) source: <<EOF:9.14-9.17
      ADDR[2] --> DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[6] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[2]
    wire \y1 [2] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[6] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[7] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[3]
    wire \y1 [3] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[7] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[4] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
Warning: found logic loop in module pingpong:
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[4] --> RD_DATA[7]
    wire \y2 [3] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[3] --> RD_DATA[1]
    wire \y1 [1] source: <<EOF:1.55-1.57
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[5] --> RD_DATA[6]
    wire \y2 [2] source: <<EOF:1.77-1.79
    cell mem ($mem_v2) source: <<EOF:2.12-2.15
      RD_ADDR[2] --> RD_DATA[0]
    wire \y1 [0] source: <<EOF:1.55-1.57
ERROR: Found 8 problems in 'check -assert'.
Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!!
Passed check_3.ys
Warning: found logic loop in module top:
    cell $auto$memory_dff.cc:512:handle_rd_port$62 ($logic_not)
      A[0] --> Y[0]
    cell $memrd$\mem$<<EOF:15$20 ($memrd_v2) source: <<EOF:15.12-15.15
      ARST[0] --> DATA[0]
    wire \data [0] source: <<EOF:1.68-1.72
ERROR: Found 1 problems in 'check -assert'.
Expected error pattern 'Found [0-9]+ problems in 'check -assert'' found !!!
Passed check_4.ys
Warning: wire '\a_q' is assigned in a block at <<EOT:7.9-7.17.
Warning: wire '\en_q' is assigned in a block at <<EOT:8.9-8.19.
Passed chformal_check.ys
Passed chformal_coverenable.ys
Passed const_arg_loop.ys
Passed const_func.ys
Passed const_func_block_var.ys
Warning: Drivers conflicting with a constant 1'1 driver:
    module input A[0]
Warning: Drivers conflicting with a constant 1'1 driver:
    port Y[0] of cell some_buffer (buffer)
Warning: reg '\Q' is assigned in a continuous assignment at <<EOT:5.9-5.14.
Warning: Drivers conflicting with a constant 1'1 driver:
    action \Q <= $0\Q[0:0] (sync rule) in process $proc$<<EOT:3$1
Passed constant_drive_conflict.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_BASE
Expected error pattern 'syntax error, unexpected TOK_BASE' found !!!
Passed constcomment.ys
Passed constmsk_test.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:3)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:5)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:6)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:7)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:8)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:9)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:10)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:11)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:12)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:13)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:14)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:15)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:52)
Warning: Yosys has only limited support for tri-state logic at the moment. (countbits.sv:53)
Passed countbits.ys
Passed deminout_unused.ys
Passed design.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design1.ys
ERROR: No saved design 'foo' found!
Expected error pattern 'No saved design 'foo' found!' found !!!
Passed design2.ys
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[0] --> Q[0]
    wire \dword [0] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[0] --> Y[0]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[0] --> Y[0]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[1] --> Q[1]
    wire \dword [1] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[1] --> Y[1]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[1] --> Y[1]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[2] --> Q[2]
    wire \dword [2] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[2] --> Y[2]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[2] --> Y[2]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[3] --> Q[3]
    wire \dword [3] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[3] --> Y[3]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[3] --> Y[3]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[4] --> Q[4]
    wire \dword [4] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[4] --> Y[4]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[4] --> Y[4]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[5] --> Q[5]
    wire \dword [5] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[5] --> Y[5]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[5] --> Y[5]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[6] --> Q[6]
    wire \dword [6] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[6] --> Y[6]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[6] --> Y[6]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[7] --> Q[7]
    wire \dword [7] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[7] --> Y[7]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[7] --> Y[7]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[8] --> Q[8]
    wire \dword [8] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[8] --> Y[8]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[8] --> Y[8]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[9] --> Q[9]
    wire \dword [9] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[9] --> Y[9]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[9] --> Y[9]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[10] --> Q[10]
    wire \dword [10] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[10] --> Y[10]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[10] --> Y[10]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[11] --> Q[11]
    wire \dword [11] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[11] --> Y[11]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[11] --> Y[11]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[12] --> Q[12]
    wire \dword [12] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[12] --> Y[12]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[12] --> Y[12]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[13] --> Q[13]
    wire \dword [13] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[13] --> Y[13]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[13] --> Y[13]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[14] --> Q[14]
    wire \dword [14] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[14] --> Y[14]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[14] --> Y[14]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[15] --> Q[15]
    wire \dword [15] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[15] --> Y[15]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[15] --> Y[15]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[16] --> Q[16]
    wire \dword [16] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[16] --> Y[16]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[16] --> Y[16]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[17] --> Q[17]
    wire \dword [17] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[17] --> Y[17]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[17] --> Y[17]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[18] --> Q[18]
    wire \dword [18] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[18] --> Y[18]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[18] --> Y[18]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[19] --> Q[19]
    wire \dword [19] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[19] --> Y[19]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[19] --> Y[19]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[20] --> Q[20]
    wire \dword [20] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[20] --> Y[20]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[20] --> Y[20]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[21] --> Q[21]
    wire \dword [21] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[21] --> Y[21]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[21] --> Y[21]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[22] --> Q[22]
    wire \dword [22] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[22] --> Y[22]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[22] --> Y[22]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[23] --> Q[23]
    wire \dword [23] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[23] --> Y[23]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[23] --> Y[23]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[24] --> Q[24]
    wire \dword [24] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[24] --> Y[24]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[24] --> Y[24]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[25] --> Q[25]
    wire \dword [25] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[25] --> Y[25]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[25] --> Y[25]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[26] --> Q[26]
    wire \dword [26] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[26] --> Y[26]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[26] --> Y[26]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[27] --> Q[27]
    wire \dword [27] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[27] --> Y[27]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[27] --> Y[27]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[28] --> Q[28]
    wire \dword [28] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[28] --> Y[28]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[28] --> Y[28]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[29] --> Q[29]
    wire \dword [29] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[29] --> Y[29]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[29] --> Y[29]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[30] --> Q[30]
    wire \dword [30] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[30] --> Y[30]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[30] --> Y[30]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[31] --> Q[31]
    wire \dword [31] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[31] --> Y[31]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[31] --> Y[31]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[32] --> Q[32]
    wire \dword [32] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[32] --> Y[32]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[32] --> Y[32]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[33] --> Q[33]
    wire \dword [33] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[33] --> Y[33]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[33] --> Y[33]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[34] --> Q[34]
    wire \dword [34] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[34] --> Y[34]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[34] --> Y[34]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[35] --> Q[35]
    wire \dword [35] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[35] --> Y[35]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[35] --> Y[35]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[36] --> Q[36]
    wire \dword [36] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[36] --> Y[36]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[36] --> Y[36]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[37] --> Q[37]
    wire \dword [37] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[37] --> Y[37]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[37] --> Y[37]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[38] --> Q[38]
    wire \dword [38] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[38] --> Y[38]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[38] --> Y[38]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[39] --> Q[39]
    wire \dword [39] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[39] --> Y[39]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[39] --> Y[39]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[40] --> Q[40]
    wire \dword [40] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[40] --> Y[40]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[40] --> Y[40]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[41] --> Q[41]
    wire \dword [41] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[41] --> Y[41]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[41] --> Y[41]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[42] --> Q[42]
    wire \dword [42] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[42] --> Y[42]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[42] --> Y[42]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[43] --> Q[43]
    wire \dword [43] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[43] --> Y[43]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[43] --> Y[43]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[44] --> Q[44]
    wire \dword [44] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[44] --> Y[44]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[44] --> Y[44]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[45] --> Q[45]
    wire \dword [45] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[45] --> Y[45]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[45] --> Y[45]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[46] --> Q[46]
    wire \dword [46] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[46] --> Y[46]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[46] --> Y[46]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[47] --> Q[47]
    wire \dword [47] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[47] --> Y[47]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[47] --> Y[47]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[48] --> Q[48]
    wire \dword [48] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[48] --> Y[48]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[48] --> Y[48]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[49] --> Q[49]
    wire \dword [49] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[49] --> Y[49]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[49] --> Y[49]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[50] --> Q[50]
    wire \dword [50] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[50] --> Y[50]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[50] --> Y[50]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[51] --> Q[51]
    wire \dword [51] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[51] --> Y[51]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[51] --> Y[51]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[52] --> Q[52]
    wire \dword [52] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[52] --> Y[52]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[52] --> Y[52]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[53] --> Q[53]
    wire \dword [53] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[53] --> Y[53]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[53] --> Y[53]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[54] --> Q[54]
    wire \dword [54] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[54] --> Y[54]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[54] --> Y[54]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[55] --> Q[55]
    wire \dword [55] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[55] --> Y[55]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[55] --> Y[55]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[56] --> Q[56]
    wire \dword [56] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[56] --> Y[56]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[56] --> Y[56]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[57] --> Q[57]
    wire \dword [57] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[57] --> Y[57]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[57] --> Y[57]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[58] --> Q[58]
    wire \dword [58] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[58] --> Y[58]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[58] --> Y[58]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[59] --> Q[59]
    wire \dword [59] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[59] --> Y[59]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[59] --> Y[59]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[60] --> Q[60]
    wire \dword [60] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[60] --> Y[60]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[60] --> Y[60]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[61] --> Q[61]
    wire \dword [61] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[61] --> Y[61]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[61] --> Y[61]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[62] --> Q[62]
    wire \dword [62] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[62] --> Y[62]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[62] --> Y[62]
Warning: found logic loop in module latch_002_gate:
    cell $auto$proc_dlatch.cc:433:proc_dlatch$13485 ($dlatch) source: ./dynamic_part_select/latch_002_gate.v:9.4-17.13
      D[63] --> Q[63]
    wire \dword [63] source: ./dynamic_part_select/latch_002_gate.v:3.22-3.27
    cell $and$./dynamic_part_select/latch_002_gate.v:15$13458 ($and) source: ./dynamic_part_select/latch_002_gate.v:15.23-15.40
      A[63] --> Y[63]
    cell $or$./dynamic_part_select/latch_002_gate.v:15$13459 ($or) source: ./dynamic_part_select/latch_002_gate.v:15.22-15.48
      A[63] --> Y[63]
Passed dynamic_part_select.ys
elab_sys_tasks.sv:8: Warning: X is 1.
elab_sys_tasks.sv:22: Warning: 
Passed elab_sys_tasks.ys
Passed equiv_make_make_assert.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/simcells.v:476)
Passed equiv_opt_multiclock.ys
Passed equiv_opt_undef.ys
ERROR: Command stdout did have a line matching given regex "giraffe".
Expected error pattern 'stdout did have a line' found !!!
Passed exec.ys
Passed fib.ys
Passed fib_tern.ys
Passed func_port_implied_dir.ys
Passed gen_if_null.ys
Passed global_scope.ys
Passed gzip_verilog.ys
Passed help.ys
Passed hierarchy_defer.ys
Passed hierarchy_generate.ys
Passed hierarchy_param.ys
Passed ice40_mince_abc9.ys
<<EOT:2: ERROR: syntax error, unexpected '[', expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected' found !!!
Passed integer_range_bad_syntax.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_REAL, expecting TOK_ID or TOK_SIGNED or TOK_UNSIGNED
Expected error pattern 'syntax error, unexpected TOK_REAL' found !!!
Passed integer_real_bad_syntax.ys
attribute \src "\" / \\ \010 \014 \n \015 \t \025 \033"
Passed json_escape_chars.ys
ERROR: Identifier `\b' is implicitly declared.
Expected error pattern 'is implicitly declared.' found !!!
Passed logger_error.ys
Passed logger_nowarning.ys
Warning: Found log message matching -W regex:
Added regex 'Successfully finished Verilog frontend.' to expected warning messages list.
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Warning: Found log message matching -W regex:
Successfully finished Verilog frontend.
Passed logger_warn.ys
<<EOF:2: Warning: Identifier `\b' is implicitly declared.
<<EOF:2: Warning: Identifier `\w' is implicitly declared.
Passed logger_warning.ys
Passed logic_param_simple.ys
Passed mem2reg.ys
Passed memory_word_as_index.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/simcells.v:476)
Passed muxcover.ys
Passed muxpack.ys
Passed param_struct.ys
Passed peepopt.ys
Passed pmgen_reduce.ys
Passed pmux2shiftx.ys
Warning: Resizing cell port act.ou2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.os2.out from 3 bits to 2 bits.
Warning: Resizing cell port act.ou1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.os1.out from 3 bits to 1 bits.
Warning: Resizing cell port act.pt9.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt7.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt6.a from 3 bits to 4 bits.
Warning: Resizing cell port act.pt5.a from 2 bits to 4 bits.
Warning: Resizing cell port act.pt4.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt3.a from 1 bits to 4 bits.
Warning: Resizing cell port act.pt2.a from 1 bits to 4 bits.
Passed port_sign_extend.ys
Passed primitives.ys
Passed printattr.ys
Passed rand_const.ys
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:26.9-26.21.
Warning: wire '\o_reg' is assigned in a block at reg_wire_error.sv:29.3-29.18.
Warning: reg '\l_reg' is assigned in a continuous assignment at reg_wire_error.sv:35.8-35.22.
Warning: wire '\mw2' is assigned in a block at reg_wire_error.sv:62.3-62.16.
Warning: wire '\mw3' is assigned in a block at reg_wire_error.sv:69.3-69.17.
Warning: Replacing memory \ml3 with list of registers. See reg_wire_error.sv:70
Warning: Replacing memory \mr3 with list of registers. See reg_wire_error.sv:68
Warning: Replacing memory \ml2 with list of registers. See reg_wire_error.sv:63
Warning: Replacing memory \mr2 with list of registers. See reg_wire_error.sv:61
Warning: Replacing memory \ml1 with list of registers. See reg_wire_error.sv:58
Passed reg_wire_error.ys
Passed rename_scramble_name.ys
Passed rtlil_signed_attribute.ys
Passed rtlil_z_bits.ys
Passed scopeinfo.ys
Passed scratchpad.ys
Passed script.ys
Passed sformatf.ys
Passed shregmap.ys
<<EOT:2: ERROR: syntax error, unexpected TOK_INTEGER, expecting TOK_ID or '['
Expected error pattern 'syntax error, unexpected TOK_INTEGER' found !!!
Passed signed.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:4)
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:5)
Passed signext.ys
Passed sim_const.ys
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_RISE_MAX = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MIN = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_TYP = 1.500000 with string.
specify.v:28: Warning: Replacing floating point parameter $specify$5.T_FALL_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_RISE_MAX = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MIN = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_TYP = 1.500000 with string.
specify.out:49: Warning: Replacing floating point parameter $specify$24.T_FALL_MAX = 1.500000 with string.
Warning: No SAT model available for cell B_0 ($specrule).
Warning: No SAT model available for cell C_0 ($specrule).
Warning: No SAT model available for cell A_0 ($specify3).
Warning: No SAT model available for cell A_0 ($specify2).
Warning: No SAT model available for cell B_0 ($specify2).
Passed specify.ys
Warning: wire '\o' is assigned in a block at <<EOT:2.11-2.17.
Warning: wire '\p' is assigned in a block at <<EOT:3.11-3.16.
Passed src.ys
Warning: Critical-path does not terminate in a recognised endpoint.
Warning: Cell type 'const0' not recognised! Ignoring.
Passed sta.ys
Passed struct_access.ys
Warning: Port directions for cell \s1 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s2 (\DFF) are unknown. Assuming inout for all ports.
Warning: Port directions for cell \s3 (\DFF) are unknown. Assuming inout for all ports.
Passed submod.ys
Passed submod_extract.ys
Passed sv_defines.ys
ERROR: Duplicate macro arguments with name `x'.
Expected error pattern 'Duplicate macro arguments with name `x'' found !!!
Passed sv_defines_dup.ys
ERROR: Mismatched brackets in macro argument: [ and }.
Expected error pattern 'Mismatched brackets in macro argument: \[ and }.' found !!!
Passed sv_defines_mismatch.ys
ERROR: Cannot expand macro `foo by giving only 1 argument (argument 2 has no default).
Expected error pattern 'Cannot expand macro `foo by giving only 1 argument \(argument 2 has no default\).' found !!!
Passed sv_defines_too_few.ys
Passed wreduce.ys
Passed write_gzip.ys
Passed xaiger.ys
Passed async.sh
Passed chparam.sh
Passed clk2fflogic_effects.sh
Passed hierarchy.sh
Passed logger_cmd_error.sh
Passed logger_fail.sh
Passed plugin.sh
Passed sv_implicit_ports.sh
Passed svalways.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/various'
cd tests/select && bash run-test.sh
Running blackboxes.ys..
Running list_mod.ys..
Running mod-attribute.ys..
Running no_warn_assert.ys..
Running no_warn_prefixed_arg_memb.ys..
Running no_warn_prefixed_empty_select_arg.ys..
Running unset.ys..
ERROR: Selection '\foo' does not exist!
Expected error pattern 'Selection '\\foo' does not exist!' found !!!
Running unset2.ys..
ERROR: Selection @foo is not defined!
Expected error pattern 'Selection @foo is not defined!' found !!!
Running warn_empty_select_arg.ys..
Warning: Selection "foo" did not match any module.
Warning: Selection "bar" did not match any object.
cd tests/sat && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/sat'
Passed asserts.ys
Passed asserts_seq.ys
Passed bug2595.ys
Warning: Complex async reset for dff `\q [12]'.
Warning: Complex async reset for dff `\q [8]'.
Passed clk2fflogic.ys
Passed counters-repeat.ys
Passed counters.ys
Passed dff.ys
Passed expose_dff.ys
Passed grom.ys
Passed initval.ys
Passed share.ys
Warning: Wire top.\cnt [7] is used but has no driver.
Warning: Wire top.\cnt [6] is used but has no driver.
Warning: Wire top.\cnt [5] is used but has no driver.
Warning: Wire top.\cnt [4] is used but has no driver.
Warning: Wire top.\cnt [3] is used but has no driver.
Warning: Wire top.\cnt [2] is used but has no driver.
Warning: Wire top.\cnt [1] is used but has no driver.
Warning: Wire top.\cnt [0] is used but has no driver.
Warning: Signal 'top.cnt' in file 8'x in simulation '8'00000000'
ERROR: Signal difference
Expected error pattern 'Signal difference' found !!!
Passed sim_counter.ys
Passed sizebits.ys
Passed splice.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/sat'
cd tests/sim && bash run-test.sh
Generate FST for sim models
Test tb_adff
FST info: dumpfile tb_adff.fst opened for output.
tb/tb_adff.v:38: $finish called at 110 (1ns)
Test tb_adffe
FST info: dumpfile tb_adffe.fst opened for output.
tb/tb_adffe.v:56: $finish called at 190 (1ns)
Test tb_adlatch
FST info: dumpfile tb_adlatch.fst opened for output.
tb/tb_adlatch.v:68: $finish called at 250 (1ns)
Test tb_aldff
FST info: dumpfile tb_aldff.fst opened for output.
tb/tb_aldff.v:71: $finish called at 270 (1ns)
Test tb_aldffe
FST info: dumpfile tb_aldffe.fst opened for output.
tb/tb_aldffe.v:73: $finish called at 270 (1ns)
Test tb_dff
FST info: dumpfile tb_dff.fst opened for output.
tb/tb_dff.v:45: $finish called at 150 (1ns)
Test tb_dffe
FST info: dumpfile tb_dffe.fst opened for output.
tb/tb_dffe.v:40: $finish called at 120 (1ns)
Test tb_dffsr
FST info: dumpfile tb_dffsr.fst opened for output.
tb/tb_dffsr.v:67: $finish called at 250 (1ns)
Test tb_dlatch
FST info: dumpfile tb_dlatch.fst opened for output.
tb/tb_dlatch.v:48: $finish called at 160 (1ns)
Test tb_dlatchsr
FST info: dumpfile tb_dlatchsr.fst opened for output.
tb/tb_dlatchsr.v:63: $finish called at 250 (1ns)
Test tb_sdff
FST info: dumpfile tb_sdff.fst opened for output.
tb/tb_sdff.v:46: $finish called at 150 (1ns)
Test tb_sdffce
FST info: dumpfile tb_sdffce.fst opened for output.
tb/tb_sdffce.v:77: $finish called at 300 (1ns)
Test tb_sdffe
FST info: dumpfile tb_sdffe.fst opened for output.
tb/tb_sdffe.v:68: $finish called at 250 (1ns)
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/sim'
Passed assume_x_first_step.ys
Passed sim_adff.ys
Passed sim_adffe.ys
Passed sim_adlatch.ys
Warning: Async reset value `\ad' is not constant!
Passed sim_aldff.ys
Warning: Async reset value `\ad' is not constant!
Passed sim_aldffe.ys
Passed sim_dff.ys
Passed sim_dffe.ys
Warning: Complex async reset for dff `\q'.
Passed sim_dffsr.ys
Passed sim_dlatch.ys
Passed sim_dlatchsr.ys
Passed sim_sdff.ys
Passed sim_sdffce.ys
Passed sim_sdffe.ys
Passed vcd_var_reference_whitespace.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/sim'
cd tests/svinterfaces && bash run-test.sh "-S 314159265359"
Test: svinterface1 -> svinterface1_tb.v:50: $finish called at 420000 (10ps)
svinterface1_tb.v:50: $finish called at 420000 (10ps)
ok
Test: svinterface_at_top -> svinterface_at_top_tb.v:61: $finish called at 420000 (10ps)
svinterface_at_top_tb_wrapper.v:61: $finish called at 420000 (10ps)
ERROR!
Test: load_and_derive ->ok
Test: resolve_types ->ok
cd tests/svtypes && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/svtypes'
Passed enum_simple.ys
Passed logic_rom.ys
<<EOT:7: ERROR: Insufficient number of array indices for a.
Expected error pattern 'Insufficient number of array indices for a.' found !!!
Passed multirange_subarray_access.ys
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Passed static_cast_negative.ys
<<EOT:1: ERROR: Static cast with non constant expression!
Expected error pattern 'Static cast with non constant expression' found !!!
Passed static_cast_nonconst.ys
<<EOT:1: ERROR: Static cast is only supported in SystemVerilog mode.
Expected error pattern 'Static cast is only supported in SystemVerilog mode' found !!!
Passed static_cast_verilog.ys
<<EOT:1: ERROR: Static cast with zero or negative size!
Expected error pattern 'Static cast with zero or negative size' found !!!
Passed static_cast_zero.ys
Passed struct_dynamic_range.ys
Warning: reg '\var_12' is assigned in a continuous assignment at typedef_initial_and_assign.sv:67.9-67.19.
Warning: reg '\var_13' is assigned in a continuous assignment at typedef_initial_and_assign.sv:71.9-71.19.
Warning: reg '\var_14' is assigned in a continuous assignment at typedef_initial_and_assign.sv:74.9-74.19.
Warning: reg '\var_15' is assigned in a continuous assignment at typedef_initial_and_assign.sv:78.9-78.19.
Warning: reg '\var_16' is assigned in a continuous assignment at typedef_initial_and_assign.sv:81.9-81.19.
Warning: reg '\var_17' is assigned in a continuous assignment at typedef_initial_and_assign.sv:85.9-85.19.
Warning: reg '\var_18' is assigned in a continuous assignment at typedef_initial_and_assign.sv:88.9-88.19.
Warning: reg '\var_19' is assigned in a continuous assignment at typedef_initial_and_assign.sv:92.9-92.19.
Passed typedef_initial_and_assign.ys
Passed typedef_memory.ys
Passed typedef_memory_2.ys
Passed typedef_struct_port.ys
Passed multirange_array.sv
Passed static_cast_simple.sv
struct_array.sv:22: Warning: Range [3:-4] select out of bounds on signal `\s': Setting 4 LSB bits to undef.
struct_array.sv:23: Warning: Range select [23:16] out of bounds on signal `\s': Setting all 8 result bits to undef.
struct_array.sv:24: Warning: Range [19:12] select out of bounds on signal `\s': Setting 4 MSB bits to undef.
struct_array.sv:45: Warning: Range [3:-4] select out of bounds on signal `\s_s': Setting 4 LSB bits to undef.
struct_array.sv:46: Warning: Range select [23:16] out of bounds on signal `\s_s': Setting all 8 result bits to undef.
struct_array.sv:47: Warning: Range [19:12] select out of bounds on signal `\s_s': Setting 4 MSB bits to undef.
struct_array.sv:15: Warning: Range [-1:-8] select out of bounds on signal `\s': Setting 8 LSB bits to undef.
struct_array.sv:38: Warning: Range [-1:-8] select out of bounds on signal `\s_s': Setting 8 LSB bits to undef.
Passed struct_array.sv
Passed struct_simple.sv
Passed struct_sizebits.sv
Passed typedef_package.sv
Passed typedef_param.sv
Passed typedef_scopes.sv
Passed typedef_simple.sv
Passed typedef_struct.sv
Passed union_simple.sv
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/svtypes'
cd tests/proc && bash run-test.sh
Running bug2619.ys..
Running bug2656.ys..
Warning: wire '\q1' is assigned in a block at <<EOT:8.3-8.11.
Warning: wire '\q2' is assigned in a block at <<EOT:12.3-12.10.
Warning: wire '\q2' is assigned in a block at <<EOT:14.3-14.11.
Running bug2962.ys..
Running bug_1268.ys..
Running clean_undef_case.ys..
Running proc_dff.ys..
Warning: Complex async reset for dff `\q'.
Running proc_rom.ys..
Warning: wire '\d' is assigned in a block at <<EOT:7.10-7.20.
Warning: wire '\d' is assigned in a block at <<EOT:8.10-8.20.
Warning: wire '\d' is assigned in a block at <<EOT:9.10-9.20.
Warning: wire '\d' is assigned in a block at <<EOT:10.10-10.20.
Warning: wire '\d' is assigned in a block at <<EOT:11.10-11.20.
Warning: wire '\d' is assigned in a block at <<EOT:12.10-12.20.
Warning: wire '\d' is assigned in a block at <<EOT:13.10-13.20.
Warning: wire '\d' is assigned in a block at <<EOT:14.10-14.20.
Warning: wire '\d' is assigned in a block at <<EOT:15.10-15.20.
Warning: wire '\d' is assigned in a block at <<EOT:16.10-16.20.
Warning: wire '\d' is assigned in a block at <<EOT:17.10-17.20.
Warning: wire '\d' is assigned in a block at <<EOT:18.10-18.20.
Warning: wire '\d' is assigned in a block at <<EOT:19.10-19.20.
Warning: wire '\d' is assigned in a block at <<EOT:20.10-20.20.
Warning: wire '\d' is assigned in a block at <<EOT:21.10-21.20.
Warning: wire '\d' is assigned in a block at <<EOT:22.10-22.20.
Warning: wire '\d' is assigned in a block at <<EOT:25.3-25.9.
Warning: wire '\d' is assigned in a block at <<EOT:20.13-20.23.
Warning: wire '\d' is assigned in a block at <<EOT:23.3-23.9.
Warning: wire '\d' is assigned in a block at <<EOT:7.7-7.17.
Warning: wire '\d' is assigned in a block at <<EOT:8.7-8.17.
Warning: wire '\d' is assigned in a block at <<EOT:9.7-9.17.
Warning: wire '\d' is assigned in a block at <<EOT:10.7-10.17.
Warning: wire '\d' is assigned in a block at <<EOT:11.7-11.17.
Warning: wire '\d' is assigned in a block at <<EOT:12.7-12.17.
Warning: wire '\d' is assigned in a block at <<EOT:13.7-13.17.
Warning: wire '\d' is assigned in a block at <<EOT:14.7-14.17.
Warning: wire '\d' is assigned in a block at <<EOT:15.7-15.17.
Warning: wire '\d' is assigned in a block at <<EOT:16.7-16.17.
Warning: wire '\d' is assigned in a block at <<EOT:17.8-17.18.
Warning: wire '\d' is assigned in a block at <<EOT:18.8-18.18.
Warning: wire '\d' is assigned in a block at <<EOT:19.8-19.18.
Warning: wire '\d' is assigned in a block at <<EOT:7.9-7.19.
Warning: wire '\d' is assigned in a block at <<EOT:8.9-8.19.
Warning: wire '\d' is assigned in a block at <<EOT:9.9-9.19.
Warning: wire '\d' is assigned in a block at <<EOT:10.9-10.19.
Warning: wire '\d' is assigned in a block at <<EOT:11.9-11.19.
Warning: wire '\d' is assigned in a block at <<EOT:12.9-12.19.
Warning: wire '\d' is assigned in a block at <<EOT:13.9-13.19.
Warning: wire '\d' is assigned in a block at <<EOT:14.9-14.19.
Warning: wire '\d' is assigned in a block at <<EOT:15.9-15.19.
Warning: wire '\d' is assigned in a block at <<EOT:16.9-16.19.
Warning: wire '\d' is assigned in a block at <<EOT:17.9-17.19.
Warning: wire '\d' is assigned in a block at <<EOT:18.9-18.19.
Warning: wire '\d' is assigned in a block at <<EOT:19.9-19.19.
Warning: wire '\d' is assigned in a block at <<EOT:20.9-20.19.
Warning: wire '\d' is assigned in a block at <<EOT:21.9-21.19.
Warning: wire '\d' is assigned in a block at <<EOT:22.9-22.19.
Running rmdead.ys..
cd tests/blif && bash run-test.sh
Running bug2729.ys..
Running bug3374.ys..
ERROR: Syntax error in line 1!
Expected error pattern 'Syntax error in line 1!' found !!!
Running bug3385.ys..
ERROR: Syntax error in line 4: names' input plane must have fewer than 13 signals.
Expected error pattern 'Syntax error in line 4: names' input plane must have fewer than 13 signals.' found !!!
cd tests/opt && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/opt'
Passed bug1525.ys
Passed bug1758.ys
Passed bug1854.ys
Passed bug2010.ys
Passed bug2221.ys
Passed bug2311.ys
Passed bug2318.ys
Passed bug2623.ys
Passed bug2765.ys
Passed bug2766.ys
Passed bug2824.ys
Passed bug2920.ys
Passed bug3047.ys
Passed bug3117.ys
Passed bug3848.ys
Passed bug3867.ys
Passed bug4413.ys
Passed memory_bmux2rom.ys
Passed memory_dff_trans.ys
Passed memory_map_offset.ys
Passed opt_clean_init.ys
Passed opt_clean_mem.ys
Passed opt_dff_arst.ys
Passed opt_dff_clk.ys
Passed opt_dff_const.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:2)
Passed opt_dff_dffmux.ys
<<EOT:19: Warning: Range select [13:12] out of bounds on signal `\Q': Setting all 2 result bits to undef.
<<EOT:20: Warning: Range select [15:14] out of bounds on signal `\Q': Setting all 2 result bits to undef.
Passed opt_dff_en.ys
Passed opt_dff_mux.ys
Passed opt_dff_qd.ys
Passed opt_dff_sr.ys
Passed opt_dff_srst.ys
Passed opt_expr.ys
Passed opt_expr_alu.ys
Passed opt_expr_and.ys
Passed opt_expr_cmp.ys
Warning: wire '\a' is assigned in a block at <<EOT:4.2-4.8.
Warning: wire '\a' is assigned in a block at <<EOT:5.2-5.8.
Warning: wire '\a' is assigned in a block at <<EOT:4.9-4.15.
Warning: wire '\a' is assigned in a block at <<EOT:5.9-5.15.
Passed opt_expr_combined_assign.ys
Passed opt_expr_constconn.ys
Passed opt_expr_consumex.ys
Passed opt_expr_or.ys
Passed opt_expr_xnor.ys
Passed opt_expr_xor.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:41)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:86)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:87)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2153)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2154)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2155)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2156)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2157)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2158)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2925)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2926)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2988)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2989)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:2990)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:3203)
Warning: Yosys has only limited support for tri-state logic at the moment. (/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/ice40/cells_sim.v:3210)
Passed opt_lut.ys
Passed opt_lut_elim.ys
Passed opt_lut_ins.ys
Passed opt_lut_port.ys
Passed opt_mem_feedback.ys
Passed opt_mem_priority.ys
Passed opt_merge_init.ys
Passed opt_merge_keep.ys
Passed opt_reduce_bmux.ys
Passed opt_reduce_demux.ys
Warning: Wire opt_rmdff_test.\Q [22] is used but has no driver.
Passed opt_rmdff.ys
Passed opt_rmdff_sat.ys
Passed opt_share_add_sub.ys
Passed opt_share_bug2334.ys
Passed opt_share_bug2335.ys
Passed opt_share_bug2336.ys
Passed opt_share_bug2538.ys
Passed opt_share_cat.ys
Passed opt_share_cat_multiuser.ys
Passed opt_share_diff_port_widths.ys
Passed opt_share_extend.ys
Passed opt_share_large_pmux_cat.ys
Passed opt_share_large_pmux_cat_multipart.ys
Passed opt_share_large_pmux_multipart.ys
Passed opt_share_large_pmux_part.ys
Passed opt_share_mux_tree.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/opt'
cd tests/aiger && bash run-test.sh "-A /usr/bin/abc"
Checking and_.aag.
Checking and_to_bad_out.aag.
Checking buffer.aag.
Checking cnt1.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking cnt1e.aag.
Checking empty.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
Checking false.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking halfadder.aag.
Checking inverter.aag.
Checking notcnt1.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking notcnt1e.aag.
Checking or_.aag.
Checking symbols.aag.
Checking toggle-re.aag.
Checking toggle.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking true.aag.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking and_.aig.
Checking and_to_bad_out.aig.
Checking buffer.aig.
Checking cnt1.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking cnt1e.aig.
Checking empty.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Warning: The current network has no primary outputs. Some commands may not work correctly.
Checking false.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking halfadder.aig.
Checking inverter.aig.
Checking notcnt1.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking notcnt1e.aig.
Checking or_.aig.
Checking symbols.aig.
Checking toggle-re.aig.
Checking toggle.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Checking true.aig.
Warning: The new network has no primary inputs. It is recommended
to add a dummy PI to make sure all commands work correctly.
Running neg.ys.
cd tests/arch && bash run-test.sh
Running syntax check on arch sim models
Test ../../techlibs/achronix/speedster22i/cells_sim.v -> ok
Test ../../techlibs/anlogic/cells_sim.v -> ok
Test ../../techlibs/coolrunner2/cells_sim.v -> ok
Test ../../techlibs/ecp5/cells_sim.v -> ok
Test ../../techlibs/efinix/cells_sim.v -> ok
Test ../../techlibs/gatemate/cells_sim.v -> ok
Test ../../techlibs/gowin/cells_sim.v -> ok
Test ../../techlibs/greenpak4/cells_sim.v -> ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_HX ->../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2231: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2233: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2235: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2237: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2239: warning: Choosing typ expression.
 ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_LP ->../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2295: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2297: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2299: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2301: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2303: warning: Choosing typ expression.
 ok
Test ../../techlibs/ice40/cells_sim.v -DICE40_U ->../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2359: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2361: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2363: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2365: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
../../techlibs/ice40/cells_sim.v:2367: warning: Choosing typ expression.
 ok
Test ../../techlibs/intel/cyclone10lp/cells_sim.v -> ok
Test ../../techlibs/intel/cycloneiv/cells_sim.v -> ok
Test ../../techlibs/intel/cycloneive/cells_sim.v -> ok
Test ../../techlibs/intel/max10/cells_sim.v -> ok
Test ../../techlibs/intel_alm/cyclonev/cells_sim.v -> ok
Test ../../techlibs/microchip/cells_sim.v -> ok
Test ../../techlibs/nanoxplore/cells_sim.v -> ok
Test ../../techlibs/nexus/cells_sim.v -> ok
Test ../../techlibs/quicklogic/common/cells_sim.v -> ok
Test ../../techlibs/quicklogic/pp3/cells_sim.v -> ok
Test ../../techlibs/quicklogic/qlf_k6n10f/cells_sim.v -> ok
Test ../../techlibs/sf2/cells_sim.v -> ok
Test ../../techlibs/xilinx/cells_sim.v -> ok
Test ../../techlibs/common/simcells.v -> ok
Test ../../techlibs/common/simlib.v -> ok
cd tests/arch/ice40 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/ice40'
Passed add_sub.ys
Passed adffs.ys
Warning: Resizing cell port SSCounter6o.l0.I3 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.c0.CI from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I0 from 32 bits to 1 bits.
Warning: Resizing cell port SSCounter6o.lien.I1 from 32 bits to 1 bits.
Passed bug1597.ys
Passed bug1598.ys
Passed bug1626.ys
Passed bug1644.ys
Passed bug2061.ys
Passed counter.ys
Passed dffs.ys
Passed dpram.ys
Passed fsm.ys
Passed ice40_dsp.ys
Passed ice40_opt.ys
Passed ice40_wrapcarry.ys
Passed latches.ys
Passed logic.ys
Passed macc.ys
Passed memories.ys
Passed mul.ys
Passed mux.ys
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.5-12.15.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.6-15.16.
Warning: wire '\data' is assigned in a block at rom.v:16.11-16.21.
Passed rom.ys
Passed shifter.ys
Warning: wire '\read_data' is assigned in a block at spram.v:19.3-19.25.
Passed spram.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/ice40'
cd tests/arch/xilinx && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/xilinx'
Warning: Whitebox '$paramod\FDRE\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox 'FDSE' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDRE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Warning: Whitebox '$paramod\FDSE_1\INIT=s32'00000000000000000000000000000001' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Passed abc9_dff.ys
Warning: Shift register inference not yet supported for family xc3s.
Passed add_sub.ys
Passed adffs.ys
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_read_wider.RAM.0.0.WEBWE from 1 bits to 4 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port asym_ram_sdp_write_wider.RAM.0.0.WEA from 4 bits to 2 bits.
Warning: Selection "asym_ram_sdp_read_wider" did not match any module.
Passed asym_ram_sdp.ys
Warning: Resizing cell port block_ram.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port block_ram.memory.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port distributed_ram_manual.memory.0.0.WEA from 4 bits to 2 bits.
Passed attributes_test.ys
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 16 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.WEA from 4 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 2 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIADI from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DIPADIP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOADO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOBDO from 64 bits to 32 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPADOP from 8 bits to 4 bits.
Warning: Resizing cell port sync_ram_sdp.memory.0.0.DOPBDOP from 8 bits to 4 bits.
Passed blockram.ys
Passed bug1460.ys
Passed bug1462.ys
Passed bug1480.ys
Passed bug1598.ys
Warning: Wire top.\t is used but has no driver.
Warning: Wire top.\in is used but has no driver.
Passed bug1605.ys
Passed bug3670.ys
Passed counter.ys
Passed dffs.ys
Passed dsp_abc9.ys
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed dsp_cascade.ys
Passed dsp_fastfir.ys
Passed dsp_simd.ys
Warning: Shift register inference not yet supported for family xc3se.
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Warning: Shift register inference not yet supported for family xc3s.
Passed lutram.ys
Passed macc.ys
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed mul.ys
Warning: Replacing memory \M with list of registers. See mul_unsigned.v:25
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:220: Warning: Range [1:0] select out of bounds on signal `\PORT_W_WR_EN': Setting 1 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/xilinx/brams_xc3sda_map.v:221: Warning: Range select [3:2] out of bounds on signal `\PORT_W_WR_EN': Setting all 2 result bits to undef.
Passed mul_unsigned.ys
Passed mux.ys
Warning: Shift register inference not yet supported for family xc3se.
Passed mux_lut4.ys
Passed nosrl.ys
Passed opt_lut_ins.ys
Passed pmgen_xilinx_srl.ys
Warning: Resizing cell port priority_memory.mem.0.0.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.0.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.1.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.2.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.3.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.4.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.5.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.6.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRARDADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.ADDRBWRADDR from 16 bits to 15 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINADIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINBDIN from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPADINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DINPBDINP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTADOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTBDOUT from 64 bits to 32 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPADOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.DOUTPBDOUTP from 8 bits to 4 bits.
Warning: Resizing cell port priority_memory.mem.0.7.WEBWE from 4 bits to 8 bits.
Warning: Resizing cell port priority_memory.mem.0.0.BWE_A from 8 bits to 9 bits.
Warning: Resizing cell port priority_memory.mem.0.0.BWE_B from 8 bits to 9 bits.
Warning: Resizing cell port sp_write_first.mem.0.0.BWE_A from 8 bits to 9 bits.
Warning: Resizing cell port sp_read_first.mem.0.0.BWE_B from 8 bits to 9 bits.
Passed priority_memory.ys
Passed shifter.ys
Passed tribuf.ys
Passed xilinx_dffopt.ys
Passed xilinx_dsp.ys
Passed xilinx_srl.ys
Passed macc.sh
Passed tribuf.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/xilinx'
cd tests/arch/ecp5 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/ecp5'
Passed add_sub.ys
Passed adffs.ys
Passed bug1459.ys
Passed bug1598.ys
Passed bug1630.ys
Warning: Literal has a width of 16 bit, but value requires 184 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 183 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 182 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 165 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 152 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 126 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 108 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 150 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 164 bit. (<<EOT:1)
Warning: Literal has a width of 16 bit, but value requires 181 bit. (<<EOT:1)
Passed bug1836.ys
Passed bug2409.ys
Warning: Whitebox '$paramod\TRELLIS_FF\REGSET=t24'010100110100010101010100' with (* abc9_flop *) contains a $dff cell with non-zero initial state -- this is not supported for ABC9 sequential synthesis. Treating as a blackbox.
Passed bug2731.ys
Passed counter.ys
Passed dffs.ys
Passed dpram.ys
Passed fsm.ys
Passed latches.ys
Passed latches_abc9.ys
Passed logic.ys
Passed lutram.ys
Passed macc.ys
Passed memories.ys
Passed mul.ys
Passed mux.ys
Passed opt_lut_ins.ys
Warning: wire '\data' is assigned in a block at rom.v:9.5-9.15.
Warning: wire '\data' is assigned in a block at rom.v:10.5-10.15.
Warning: wire '\data' is assigned in a block at rom.v:11.5-11.15.
Warning: wire '\data' is assigned in a block at rom.v:12.6-12.16.
Warning: wire '\data' is assigned in a block at rom.v:13.6-13.16.
Warning: wire '\data' is assigned in a block at rom.v:14.6-14.16.
Warning: wire '\data' is assigned in a block at rom.v:15.11-15.21.
Passed rom.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/ecp5'
cd tests/arch/machxo2 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/machxo2'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/machxo2'
cd tests/arch/efinix && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/efinix'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/efinix'
cd tests/arch/anlogic && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/anlogic'
Passed add_sub.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/anlogic'
cd tests/arch/gowin && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/gowin'
Passed add_sub.ys
Passed adffs.ys
Passed compare.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
ERROR: FF myDFFP.$auto$ff.cc:266:slice$814 (type $_DFF_PP1_) cannot be legalized: unsupported initial value and async reset value combination
Expected error pattern 'unsupported initial value and async reset value combination' found !!!
Passed init-error.ys
Passed init.ys
Passed logic.ys
Passed lutram.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/gowin'
cd tests/arch/intel_alm && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/intel_alm'
Passed add_sub.ys
Passed adffs.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mul.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/intel_alm'
cd tests/arch/nanoxplore && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/nanoxplore'
Passed add_sub.ys
Passed adffs.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed lutram.ys
Passed meminit.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/nanoxplore'
cd tests/arch/nexus && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/nexus'
Passed add_sub.ys
Passed adffs.ys
Passed blockram.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed logic.ys
Passed lutram.ys
Passed mul.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/nexus'
cd tests/arch/quicklogic/pp3 && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/quicklogic/pp3'
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed add_sub.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed adffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed counter.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed dffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed fsm.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed latches.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed logic.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed mux.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/quicklogic/pp3'
cd tests/arch/quicklogic/qlf_k6n10f && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/quicklogic/qlf_k6n10f'
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed add_sub.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire adff.q has an unprocessed 'init' attribute.
Warning: Wire adffn.q has an unprocessed 'init' attribute.
Warning: Wire dffs.q has an unprocessed 'init' attribute.
Warning: Wire ndffnr.q has an unprocessed 'init' attribute.
Passed adffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed counter.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire my_dffe.q has an unprocessed 'init' attribute.
Passed dffs.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed div.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed dsp.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed fsm.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed latches.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed logic.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2663: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_RDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2709: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_RDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Range [4:1] select out of bounds on signal `\PORT_A1_WR_BE': Setting 3 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2578: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_A1_WR_BE [1] } = 4'0000
    new assignment: \PORT_A1_WR_BE [1] = 1'0.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Range [3:0] select out of bounds on signal `\PORT_A1_WR_BE': Setting 2 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2579: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_A1_WR_BE } = \PORT_A1_WR_BE_i
    new assignment: \PORT_A1_WR_BE = \PORT_A1_WR_BE_i [1:0].
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Range [4:1] select out of bounds on signal `\PORT_B1_WR_BE': Setting 3 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2588: Warning: Ignoring assignment to constant bits:
    old assignment: { 3'x \PORT_B1_WR_BE [1] } = 4'0000
    new assignment: \PORT_B1_WR_BE [1] = 1'0.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Range [3:0] select out of bounds on signal `\PORT_B1_WR_BE': Setting 2 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2589: Warning: Ignoring assignment to constant bits:
    old assignment: { 2'x \PORT_B1_WR_BE } = \PORT_B1_WR_BE_i
    new assignment: \PORT_B1_WR_BE = \PORT_B1_WR_BE_i [1:0].
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Range [36:17] select out of bounds on signal `\PORT_A1_WDATA': Setting 19 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2635: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_A1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_A1_WDATA [17] = 1'0.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Range [35:0] select out of bounds on signal `\PORT_A1_WDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2636: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_A1_WDATA } = \PORT_A1_WR_DATA_i
    new assignment: \PORT_A1_WDATA = \PORT_A1_WR_DATA_i [17:0].
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Range [36:17] select out of bounds on signal `\PORT_B1_WDATA': Setting 19 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2681: Warning: Ignoring assignment to constant bits:
    old assignment: { 19'x \PORT_B1_WDATA [17] } = 20'00000000000000000000
    new assignment: \PORT_B1_WDATA [17] = 1'0.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Range [35:0] select out of bounds on signal `\PORT_B1_WDATA': Setting 18 MSB bits to undef.
/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/share/quicklogic/qlf_k6n10f/brams_sim.v:2682: Warning: Ignoring assignment to constant bits:
    old assignment: { 18'x \PORT_B1_WDATA } = \PORT_B1_WR_DATA_i
    new assignment: \PORT_B1_WDATA = \PORT_B1_WR_DATA_i [17:0].
Warning: Complex async reset for dff `\Q'.
Warning: Drivers conflicting with a constant 1'0 driver:
    module input PORT_A1_WR_BE_i[1]
    module input PORT_A1_WR_DATA_i[17]
    module input PORT_B1_WR_BE_i[1]
    module input PORT_B1_WR_DATA_i[17]
Passed meminit.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed mux.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Wire TB.\rq_b [35] is used but has no driver.
Warning: Wire TB.\rq_b [34] is used but has no driver.
Warning: Wire TB.\rq_b [33] is used but has no driver.
Warning: Wire TB.\rq_b [32] is used but has no driver.
Warning: Wire TB.\rq_b [31] is used but has no driver.
Warning: Wire TB.\rq_b [30] is used but has no driver.
Warning: Wire TB.\rq_b [29] is used but has no driver.
Warning: Wire TB.\rq_b [28] is used but has no driver.
Warning: Wire TB.\rq_b [27] is used but has no driver.
Warning: Wire TB.\rq_b [26] is used but has no driver.
Warning: Wire TB.\rq_b [25] is used but has no driver.
Warning: Wire TB.\rq_b [24] is used but has no driver.
Warning: Wire TB.\rq_b [23] is used but has no driver.
Warning: Wire TB.\rq_b [22] is used but has no driver.
Warning: Wire TB.\rq_b [21] is used but has no driver.
Warning: Wire TB.\rq_b [20] is used but has no driver.
Warning: Wire TB.\rq_b [19] is used but has no driver.
Warning: Wire TB.\rq_b [18] is used but has no driver.
Warning: Wire TB.\rq_b [17] is used but has no driver.
Warning: Wire TB.\rq_b [16] is used but has no driver.
Warning: Wire TB.\rq_b [15] is used but has no driver.
Warning: Wire TB.\rq_b [14] is used but has no driver.
Warning: Wire TB.\rq_b [13] is used but has no driver.
Warning: Wire TB.\rq_b [12] is used but has no driver.
Warning: Wire TB.\rq_b [11] is used but has no driver.
Warning: Wire TB.\rq_b [10] is used but has no driver.
Warning: Wire TB.\rq_b [9] is used but has no driver.
Warning: Wire TB.\rq_b [8] is used but has no driver.
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [35] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [34] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [33] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [32] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [31] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [30] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [29] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [28] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [27] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [26] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [25] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [24] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [23] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [22] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [21] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [20] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [19] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [18] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [17] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [16] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [15] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [14] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [13] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [12] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [11] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [10] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [9] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [8] is used but has no driver.
Warning: Wire TB.$auto$wreduce.cc:461:run$18097 [7] is used but has no driver.
Warning: Resizing cell port TB.uut.address_in_w from 11 bits to 10 bits.
Warning: Resizing cell port TB.uut.data_in from 18 bits to 36 bits.
Warning: Resizing cell port TB.uut.address_in_w from 10 bits to 8 bits.
Warning: Resizing cell port TB.uut.data_in from 8 bits to 32 bits.
Warning: Resizing cell port TB.uut.data_out from 18 bits to 36 bits.
Warning: Resizing cell port TB.uut.address_in_r from 11 bits to 10 bits.
Passed t_mem0.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Warning: Resizing cell port TB.uut.data_out from 8 bits to 32 bits.
Warning: Resizing cell port TB.uut.address_in_r from 10 bits to 8 bits.
Warning: Wire TB.\rq_b [7] is used but has no driver.
Warning: Wire TB.\rq_b [6] is used but has no driver.
Warning: Wire TB.\rq_b [5] is used but has no driver.
Warning: Wire TB.\rq_b [4] is used but has no driver.
Warning: Wire TB.\rq_b [3] is used but has no driver.
Warning: Wire TB.\rq_b [2] is used but has no driver.
Warning: Wire TB.\rq_b [1] is used but has no driver.
Warning: Wire TB.\rq_b [0] is used but has no driver.
Passed t_mem1.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem2.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem3.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem4.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem5.ys
Warning: delay target has not been set via SDC or scratchpad; assuming 12 MHz clock.
Warning: Complex async reset for dff `\Q'.
Passed t_mem6.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/quicklogic/qlf_k6n10f'
cd tests/arch/gatemate && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/gatemate'
Passed add_sub.ys
Passed adffs.ys
Passed counter.ys
Passed dffs.ys
Passed fsm.ys
Passed latches.ys
Passed logic.ys
Passed luttrees.ys
Passed memory.ys
Passed mul.ys
Passed mux.ys
Passed shifter.ys
Passed tribuf.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/gatemate'
cd tests/arch/microchip && bash run-test.sh "-S 314159265359"
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/microchip'
Passed dff.ys
Passed dff_opt.ys
Warning: Resizing cell port pre_post_adder.$mul$<<EOT:8$770.A from 6 bits to 18 bits.
Warning: Resizing cell port mac.$mul$<<EOT:13$1157.A from 5 bits to 18 bits.
Warning: Resizing cell port cas.$mul$<<EOT:11$1550.A from 6 bits to 18 bits.
Warning: Resizing cell port pipeline.$mul$<<EOT:69$2337.A from 6 bits to 18 bits.
Passed dsp.ys
Passed mult.ys
Passed ram_SDP.ys
Passed ram_TDP.ys
Passed reduce.ys
Passed simple_ram.ys
Passed uram_ar.ys
Passed uram_sr.ys
Passed widemux.ys
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/arch/microchip'
cd tests/rpc && bash run-test.sh
Running exec.ys..
cd tests/memfile && bash run-test.sh
Running from the parent directory with content1.dat
Running from the parent directory with temp/content2.dat
Running from the parent directory with memfile/temp/content2.dat
Running from the same directory with content1.dat
Running from the same directory with temp/content2.dat
Running from a child directory with content1.dat
Running from a child directory with temp/content2.dat
Running from a child directory with content2.dat
Checking a failure when zero length filename is provided
memory.v:15: ERROR: Can not open file `` for \$readmemb.
Execution failed, which is OK.
Checking a failure when not existing filename is provided
memory.v:15: ERROR: Can not open file `content3.dat` for \$readmemb.
Execution failed, which is OK.
cd tests/verilog && bash run-test.sh
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/verilog'
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width.ys
<<EOF:0: ERROR: Expression width 1073741824 exceeds implementation limit of 16777216!
Expected error pattern 'Expression width 1073741824 exceeds implementation limit of 16777216!' found !!!
Passed absurd_width_const.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_1.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_2.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$1.y' from always_comb process `\top.$proc$<<EOF:0$2'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$1\.y' from always_comb process' found !!!
Passed always_comb_latch_3.ys
ERROR: Latch inferred for signal `\top.$unnamed_block$3.y' from always_comb process `\top.$proc$<<EOF:0$4'.
Expected error pattern '^Latch inferred for signal `\\top\.\$unnamed_block\$3\.y' from always_comb process' found !!!
Passed always_comb_latch_4.ys
Passed always_comb_nolatch_1.ys
Passed always_comb_nolatch_2.ys
Passed always_comb_nolatch_3.ys
Passed always_comb_nolatch_4.ys
Passed always_comb_nolatch_5.ys
Passed always_comb_nolatch_6.ys
Passed asgn_expr.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_1.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_2.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_3.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_4.ys
<<EOF:3: ERROR: Assignments within expressions are only permitted within procedures.
Expected error pattern 'Assignments within expressions are only permitted within procedures.' found !!!
Passed asgn_expr_not_proc_5.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_1.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_2.ys
<<EOF:3: ERROR: Assignments within expressions are only supported in SystemVerilog mode.
Expected error pattern 'Assignments within expressions are only supported in SystemVerilog mode.' found !!!
Passed asgn_expr_not_sv_3.ys
<<EOF:3: ERROR: syntax error, unexpected TOK_ID
Expected error pattern 'syntax error, unexpected TOK_ID' found !!!
Passed asgn_expr_not_sv_4.ys
Passed assign_to_reg.ys
Passed atom_type_signedness.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed block_end_label_wrong.ys
<<EOT:5: ERROR: Begin label (a) and end label (b) don't match.
Expected error pattern 'Begin label \(a\) and end label \(b\) don't match\.' found !!!
Passed block_labels.ys
Passed bug2037.ys
<<EOT:6: ERROR: syntax error, unexpected TOK_ENDTASK, expecting ';'
Expected error pattern 'syntax error, unexpected TOK_ENDTASK, expecting ';'' found !!!
Passed bug2042-sv.ys
<<EOT:5: ERROR: task/function argument direction missing
Expected error pattern 'task/function argument direction missing' found !!!
Passed bug2042.ys
<<EOT:6: ERROR: Failed to detect width for identifier \genblk1.y!
Expected error pattern 'Failed to detect width for identifier \\genblk1\.y!' found !!!
Passed bug2493.ys
Passed bug656.ys
<<EOT:4: ERROR: Cannot add procedural assertion `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add procedural assertion `\\x' because a signal with the same name was already created' found !!!
Passed conflict_assert.ys
<<EOT:5: ERROR: Cannot add cell `\x' because a memory with the same name was already created at <<EOT:4.15-4.16!
Expected error pattern 'Cannot add cell `\\x' because a memory with the same name was already created' found !!!
Passed conflict_cell_memory.ys
<<EOT:0: ERROR: Cannot add interface port `\i' because a signal with the same name was already created at <<EOT:9.10-9.11!
Expected error pattern 'Cannot add interface port `\\i' because a signal with the same name was already created' found !!!
Passed conflict_interface_port.ys
<<EOT:3: ERROR: Cannot add memory `\x' because a signal with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add memory `\\x' because a signal with the same name was already created' found !!!
Passed conflict_memory_wire.ys
<<EOT:3: Warning: Ignoring assignment to constant bits:
    old assignment: 2 = 1
    new assignment: { } = { }.
<<EOT:4: ERROR: Cannot add pwire `\x' because a signal with the same name was already created at <<EOT:2.10-2.11!
Expected error pattern 'Cannot add pwire `\\x' because a signal with the same name was already created' found !!!
Passed conflict_pwire.ys
<<EOT:3: ERROR: Cannot add signal `\x' because a memory with the same name was already created at <<EOT:2.15-2.16!
Expected error pattern 'Cannot add signal `\\x' because a memory with the same name was already created' found !!!
Passed conflict_wire_memory.ys
Passed const_arst.ys
Warning: Complex async reset for dff `\q'.
Passed const_sr.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_mintypmax.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (<<EOT:3)
Passed delay_risefall.ys
Passed delay_time_scale.ys
Passed doubleslash.ys
<<EOT:4: ERROR: For loop variable declaration is missing initialization!
Expected error pattern 'For loop variable declaration is missing initialization!' found !!!
Passed for_decl_no_init.ys
<<EOT:4: ERROR: For loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'For loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed for_decl_no_sv.ys
Passed for_decl_shadow.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_1.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_2.ys
<<EOT:8: ERROR: Incompatible re-declaration of wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of wire' found !!!
Passed func_arg_mismatch_3.ys
<<EOT:0: ERROR: Incompatible re-declaration of constant function wire \f$func$<<EOT:8$1.inp.
Expected error pattern 'Incompatible re-declaration of constant function wire' found !!!
Passed func_arg_mismatch_4.ys
Passed func_tern_hint.ys
Passed func_typename_ret.ys
Passed func_upto.ys
<<EOF:5: ERROR: Begin label missing where end label (incorrect_name) was given.
Expected error pattern 'Begin label missing where end label \(incorrect_name\) was given\.' found !!!
Passed gen_block_end_label_only.ys
<<EOF:5: ERROR: Begin label (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Begin label \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed gen_block_end_label_wrong.ys
Passed genblk_case.ys
<<EOT:4: ERROR: Cannot declare module port `\x' within a generate block.
Expected error pattern 'Cannot declare module port `\\x' within a generate block\.' found !!!
Passed genblk_port_decl.ys
<<EOT:2: ERROR: Generate for loop variable declaration is missing initialization!
Expected error pattern 'Generate for loop variable declaration is missing initialization!' found !!!
Passed genfor_decl_no_init.ys
<<EOT:2: ERROR: Generate for loop inline variable declaration is only supported in SystemVerilog mode!
Expected error pattern 'Generate for loop inline variable declaration is only supported in SystemVerilog mode!' found !!!
Passed genfor_decl_no_sv.ys
Passed genvar_loop_decl_1.ys
Passed genvar_loop_decl_2.ys
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:13.12-13.21.
Warning: reg '\y' is assigned in a continuous assignment at genvar_loop_decl_3.sv:27.12-27.21.
Passed genvar_loop_decl_3.ys
<<EOF:0: ERROR: Can't find object for defparam `$1`!
Expected error pattern 'Can't find object for defparam' found !!!
Passed global_parameter.ys
<<EOT:7: ERROR: Identifier `\y' is implicitly declared and `default_nettype is set to none.
Expected error pattern 'Identifier `\\y' is implicitly declared and `default_nettype is set to none' found !!!
Passed hidden_decl.ys
Passed ifdef_nest.ys
ERROR: Unterminated preprocessor conditional!
Expected error pattern 'Unterminated preprocessor conditional!' found !!!
Passed ifdef_unterminated.ys
Passed include_self.ys
Passed int_types.ys
<<EOF:3: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_1.ys
<<EOF:2: ERROR: localparam initialization is missing!
Expected error pattern 'localparam initialization is missing!' found !!!
Passed localparam_no_default_2.ys
Passed macro_arg_tromp.ys
ERROR: Expected to find '(' to begin macro arguments for 'MACRO', but instead found ';'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'MACRO', but instead found ';'' found !!!
Passed macro_unapplied.ys
ERROR: Expected to find '(' to begin macro arguments for 'foo', but instead found '\x0a'
Expected error pattern 'Expected to find '\(' to begin macro arguments for 'foo', but instead found '\\x0a'' found !!!
Passed macro_unapplied_newline.ys
Passed mem_bounds.ys
<<EOF:3: ERROR: Module name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Module name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed module_end_label.ys
Passed net_types.ys
<<EOF:3: ERROR: Package name (correct_name) and end label (incorrect_name) don't match.
Expected error pattern 'Package name \(correct_name\) and end label \(incorrect_name\) don't match\.' found !!!
Passed package_end_label.ys
Passed package_task_func.ys
Passed param_int_types.ys
Passed param_no_default.ys
<<EOF:3: ERROR: Parameter defaults can only be omitted in SystemVerilog mode!
Expected error pattern 'Parameter defaults can only be omitted in SystemVerilog mode!' found !!!
Passed param_no_default_not_svmode.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_1.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_2.ys
<<EOF:2: ERROR: Parameter `\Y' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\Y' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_3.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_4.ys
<<EOF:2: ERROR: Parameter `\X' has no default value and has not been overridden!
Expected error pattern 'Parameter `\\X' has no default value and has not been overridden!' found !!!
Passed param_no_default_unbound_5.ys
Passed parameters_across_files.ys
Passed past_signedness.ys
Passed port_int_types.ys
Passed prefix.ys
Warning: Module top contains RTLIL processes with sync rules. Such RTLIL processes can't always be mapped directly to Verilog always blocks. unintended changes in simulation behavior are possible! Use "proc" to convert processes to logic networks and registers.
Passed roundtrip_proc.ys
Passed sign_array_query.ys
Passed size_cast.ys
Passed struct_access.ys
<<EOT:6: ERROR: syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT
Expected error pattern 'syntax error, unexpected ';', expecting ATTR_BEGIN or TOK_INCREMENT or TOK_DECREMENT' found !!!
Passed task_attr.ys
Passed typedef_across_files.ys
Passed typedef_const_shadow.ys
Passed typedef_legacy_conflict.ys
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:17)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:21)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:25)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:30)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:34)
Warning: Yosys has only limited support for tri-state logic at the moment. (unbased_unsized.sv:38)
Passed unbased_unsized.ys
Warning: Resizing cell port top.pt.inp from 32 bits to 64 bits.
Passed unbased_unsized_shift.ys
Warning: Resizing cell port gate.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gate.pt1.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt4.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt3.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt2.out from 64 bits to 40 bits.
Warning: Resizing cell port gold.pt1.out from 64 bits to 40 bits.
Passed unbased_unsized_tern.ys
ERROR: Found `else outside of macro conditional branch!
Expected error pattern 'Found `else outside of macro conditional branch!' found !!!
Passed unmatched_else.ys
ERROR: Found `elsif outside of macro conditional branch!
Expected error pattern 'Found `elsif outside of macro conditional branch!' found !!!
Passed unmatched_elsif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif.ys
ERROR: Found `endif outside of macro conditional branch!
Expected error pattern 'Found `endif outside of macro conditional branch!' found !!!
Passed unmatched_endif_2.ys
<<EOT:3: ERROR: Local declaration in unnamed block is only supported in SystemVerilog mode!
Expected error pattern 'Local declaration in unnamed block is only supported in SystemVerilog mode!' found !!!
Passed unnamed_block.ys
Passed unnamed_genblk.ys
Passed unreachable_case_sign.ys
Passed upto.ys
Warning: wire '\b' is assigned in a block at <<EOF:2.38-2.43.
Warning: wire '\b' is assigned in a block at <<EOF:3.42-3.48.
Warning: wire '\b' is assigned in a block at <<EOF:12.29-12.34.
Warning: wire '\b' is assigned in a block at <<EOF:13.33-13.39.
Warning: wire '\b' is assigned in a block at <<EOF:23.9-23.14.
Warning: wire '\b' is assigned in a block at <<EOF:24.9-24.15.
Warning: wire '\b' is assigned in a block at <<EOF:25.9-25.15.
Passed void_func.ys
Warning: wire '\wire_1' is assigned in a block at wire_and_var.sv:21.41-21.51.
Warning: reg '\reg_2' is assigned in a continuous assignment at wire_and_var.sv:22.57-22.66.
Warning: reg '\var_reg_2' is assigned in a continuous assignment at wire_and_var.sv:26.77-26.90.
Warning: wire '\wire_logic_1' is assigned in a block at wire_and_var.sv:30.65-30.81.
Warning: wire '\wire_integer_1' is assigned in a block at wire_and_var.sv:31.73-31.91.
Passed wire_and_var.ys
Passed dynamic_range_lhs.sh
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/verilog'
cd tests/xprop && bash run-test.sh "-S 314159265359"
xprop PRNG seed: 314159265359
make[1]: Entering directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/xprop'
xprop_not_3s_5: ok
xprop_not_3s_5: ok
xprop_pos_3s_5: ok
xprop_pos_3s_5: ok
xprop_neg_3s_5: ok
xprop_neg_3s_5: ok
xprop_and_1u1_1: ok
xprop_and_1u1_1: ok
xprop_and_1s1_2: ok
xprop_and_1s1_2: ok
xprop_and_2u2_2: ok
xprop_and_2u2_2: ok
xprop_or_1u1_1: ok
xprop_or_1u1_1: ok
xprop_or_1s1_2: ok
xprop_or_1s1_2: ok
xprop_or_2u2_2: ok
xprop_or_2u2_2: ok
xprop_xor_1u1_1: ok
xprop_xor_1u1_1: ok
xprop_xor_1s1_2: ok
xprop_xor_1s1_2: ok
xprop_xor_2u2_2: ok
xprop_xor_2u2_2: ok
xprop_xnor_1u1_1: ok
xprop_xnor_1u1_1: ok
xprop_xnor_1s1_2: ok
xprop_xnor_1s1_2: ok
xprop_xnor_2u2_2: ok
xprop_xnor_2u2_2: ok
xprop_add_5u3_3: ok
xprop_add_5u3_3: ok
xprop_add_5s3_3: ok
xprop_add_5s3_3: ok
xprop_sub_5u3_3: ok
xprop_sub_5u3_3: ok
xprop_sub_5s3_3: ok
xprop_sub_5s3_3: ok
xprop_mul_5u3_3: ok
xprop_mul_5u3_3: ok
xprop_mul_5s3_3: ok
xprop_mul_5s3_3: ok
xprop_div_5u3_3: ok
xprop_div_5u3_3: ok
xprop_div_5s3_3: ok
xprop_div_5s3_3: ok
xprop_mod_5u3_3: ok
xprop_mod_5u3_3: ok
xprop_mod_5s3_3: ok
xprop_mod_5s3_3: ok
xprop_divfloor_5u3_3: ok
xprop_divfloor_5u3_3: ok
xprop_divfloor_5s3_3: ok
xprop_divfloor_5s3_3: ok
xprop_modfloor_5u3_3: ok
xprop_modfloor_5u3_3: ok
xprop_modfloor_5s3_3: ok
xprop_modfloor_5s3_3: ok
xprop_lt_5u3_2: ok
xprop_lt_5u3_2: ok
xprop_lt_5s3_2: ok
xprop_lt_5s3_2: ok
xprop_le_5u3_2: ok
xprop_le_5u3_2: ok
xprop_le_5s3_2: ok
xprop_le_5s3_2: ok
xprop_eq_5u3_2: ok
xprop_eq_5u3_2: ok
xprop_eq_5s3_2: ok
xprop_eq_5s3_2: ok
xprop_ne_5u3_2: ok
xprop_ne_5u3_2: ok
xprop_ne_5s3_2: ok
xprop_ne_5s3_2: ok
xprop_eqx_5u3_2: ok
xprop_eqx_5u3_2: ok
xprop_eqx_5s3_2: ok
xprop_eqx_5s3_2: ok
xprop_nex_5u3_2: ok
xprop_nex_5u3_2: ok
xprop_nex_5s3_2: ok
xprop_nex_5s3_2: ok
xprop_ge_5u3_2: ok
xprop_ge_5u3_2: ok
xprop_ge_5s3_2: ok
xprop_ge_5s3_2: ok
xprop_gt_5u3_2: ok
xprop_gt_5u3_2: ok
xprop_gt_5s3_2: ok
xprop_gt_5s3_2: ok
xprop_reduce_and_3u_3: ok
xprop_reduce_and_3u_3: ok
xprop_reduce_and_3s_3: ok
xprop_reduce_and_3s_3: ok
xprop_reduce_or_3u_3: ok
xprop_reduce_or_3u_3: ok
xprop_reduce_or_3s_3: ok
xprop_reduce_or_3s_3: ok
xprop_reduce_xor_3u_3: ok
xprop_reduce_xor_3u_3: ok
xprop_reduce_xor_3s_3: ok
xprop_reduce_xor_3s_3: ok
xprop_reduce_xnor_3u_3: ok
xprop_reduce_xnor_3u_3: ok
xprop_reduce_xnor_3s_3: ok
xprop_reduce_xnor_3s_3: ok
xprop_reduce_bool_1u_1: ok
xprop_reduce_bool_1u_1: ok
xprop_reduce_bool_3u_3: ok
xprop_reduce_bool_3u_3: ok
xprop_reduce_bool_3s_3: ok
xprop_reduce_bool_3s_3: ok
xprop_reduce_bool_3s_1: ok
xprop_reduce_bool_3s_1: ok
xprop_logic_not_1u_1: ok
xprop_logic_not_1u_1: ok
xprop_logic_not_3u_3: ok
xprop_logic_not_3u_3: ok
xprop_logic_not_3s_3: ok
xprop_logic_not_3s_3: ok
xprop_logic_not_3s_1: ok
xprop_logic_not_3s_1: ok
xprop_logic_and_1u1_1: ok
xprop_logic_and_1u1_1: ok
xprop_logic_and_3u3_3: ok
xprop_logic_and_3u3_3: ok
xprop_logic_and_3s3_3: ok
xprop_logic_and_3s3_3: ok
xprop_logic_and_3s3_1: ok
xprop_logic_and_3s3_1: ok
xprop_logic_or_1u1_1: ok
xprop_logic_or_1u1_1: ok
xprop_logic_or_3u3_3: ok
xprop_logic_or_3u3_3: ok
xprop_logic_or_3s3_3: ok
xprop_logic_or_3s3_3: ok
xprop_logic_or_3s3_1: ok
xprop_logic_or_3s3_1: ok
xprop_shl_4u3u_3: ok
xprop_shl_4u3u_3: ok
xprop_shl_4s3u_3: ok
xprop_shl_4s3u_3: ok
xprop_shr_4u3u_3: ok
xprop_shr_4u3u_3: ok
xprop_shr_4s3u_3: ok
xprop_shr_4s3u_3: ok
xprop_sshl_4u3u_3: ok
xprop_sshl_4u3u_3: ok
xprop_sshl_4s3u_3: ok
xprop_sshl_4s3u_3: ok
xprop_sshr_4u3u_3: ok
xprop_sshr_4u3u_3: ok
xprop_sshr_4s3u_3: ok
xprop_sshr_4s3u_3: ok
xprop_shift_4u3u_3: ok
xprop_shift_4u3u_3: ok
xprop_shift_4s3u_3: ok
xprop_shift_4s3u_3: ok
xprop_shift_4u2s_8: ok
xprop_shift_4u2s_8: ok
xprop_shift_4s2s_8: ok
xprop_shift_4s2s_8: ok
xprop_shift_4u3s_3: ok
xprop_shift_4u3s_3: ok
xprop_shift_4s3s_3: ok
xprop_shift_4s3s_3: ok
xprop_shiftx_4u2s_8: ok
xprop_shiftx_4u2s_8: ok
xprop_shiftx_4u3s_3: ok
xprop_shiftx_4u3s_3: ok
xprop_mux_1: ok
xprop_mux_1: ok
xprop_mux_3: ok
xprop_mux_3: ok
xprop_bmux_1_2: ok
xprop_bmux_1_2: ok
xprop_bmux_2_2: ok
xprop_bmux_2_2: ok
xprop_bmux_3_1: ok
xprop_bmux_3_1: ok
xprop_demux_1_2: ok
xprop_demux_1_2: ok
xprop_demux_2_2: ok
xprop_demux_2_2: ok
xprop_demux_3_1: ok
xprop_demux_3_1: ok
xprop_pmux_1_4: ok
xprop_pmux_1_4: ok
xprop_pmux_2_2: ok
xprop_pmux_2_2: ok
xprop_pmux_3_1: ok
xprop_pmux_3_1: ok
xprop_pmux_4_4: ok
xprop_pmux_4_4: ok
xprop_bwmux_1: ok
xprop_bwmux_1: ok
xprop_bwmux_3: ok
xprop_bwmux_3: ok
xprop_bweqx_1: ok
xprop_bweqx_1: ok
xprop_bweqx_3: ok
xprop_bweqx_3: ok
xprop_ff_1: ok
xprop_ff_1: ok
xprop_ff_3: ok
xprop_ff_3: ok
xprop_dff_1pd: ok
xprop_dff_1pd: ok
xprop_dff_1nd: ok
xprop_dff_1nd: ok
xprop_dff_3pd: ok
xprop_dff_3pd: ok
xprop_dff_3nd: ok
xprop_dff_3nd: ok
xprop_dffe_1pnd: ok
xprop_dffe_1pnd: ok
xprop_dffe_1nnd: ok
xprop_dffe_1nnd: ok
xprop_dffe_3pnd: ok
xprop_dffe_3pnd: ok
xprop_dffe_3nnd: ok
xprop_dffe_3nnd: ok
xprop_dffe_1ppd: ok
xprop_dffe_1ppd: ok
xprop_dffe_1npd: ok
xprop_dffe_1npd: ok
xprop_dffe_3ppd: ok
xprop_dffe_3ppd: ok
xprop_dffe_3npd: ok
xprop_dffe_3npd: ok
done
make[1]: Leaving directory '/builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/tests/xprop'
cd tests/fmt && bash run-test.sh
+ ../../yosys -p 'read_verilog initial_display.v'
+ awk '/<<<BEGIN>>>/,/<<<END>>>/ {print $0}'
+ iverilog -o iverilog-initial_display initial_display.v
+ ./iverilog-initial_display
+ diff yosys-initial_display.log iverilog-initial_display.log
+ test_always_display clk -DEVENT_CLK
+ local subtest=clk
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 0de35d2746, CPU: user 0.01s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 39% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk-1.v
Parsing Verilog input from `yosys-always_display-clk-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: e35e8bb689, CPU: user 0.01s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 35% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ...
+ diff yosys-always_display-clk-1.v yosys-always_display-clk-2.v
+ test_always_display clk_rst -DEVENT_CLK_RST
+ local subtest=clk_rst
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK_RST always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk_rst-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: c95608ddf0, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 38% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_rst-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst-1.v
Parsing Verilog input from `yosys-always_display-clk_rst-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-clk_rst-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-clk_rst-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: faf50513c3, CPU: user 0.01s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 37% 2x opt_expr (0 sec), 21% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_rst-1.v yosys-always_display-clk_rst-2.v
+ test_always_display star -DEVENT_STAR
+ local subtest=star
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_STAR always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-star-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 7b2c5274a5, CPU: user 0.01s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 36% 2x opt_expr (0 sec), 22% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-star-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-star-1.v
Parsing Verilog input from `yosys-always_display-star-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star-1.v:18$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-always_display-star-1.v:18$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-always_display-star-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 8979c5de0b, CPU: user 0.01s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 38% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
+ diff yosys-always_display-star-1.v yosys-always_display-star-2.v
+ test_always_display clk_en -DEVENT_CLK -DCOND_EN
+ local subtest=clk_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:4$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:4$1'.
Removing empty process `m.$proc$always_display.v:4$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 4f8a3b339c, CPU: user 0.01s system 0.00s, MEM: 13.00 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 43% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_en-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_en-1.v
Parsing Verilog input from `yosys-always_display-clk_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_en-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 51e7fa3902, CPU: user 0.01s system 0.00s, MEM: 13.00 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 39% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_en-1.v yosys-always_display-clk_en-2.v
+ test_always_display clk_rst_en -DEVENT_CLK_RST -DCOND_EN
+ local subtest=clk_rst_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_CLK_RST -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:7$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:7$1'.
Removing empty process `m.$proc$always_display.v:7$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_rst_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: f9b4876f33, CPU: user 0.01s system 0.00s, MEM: 13.12 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 42% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-clk_rst_en-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-clk_rst_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-clk_rst_en-1.v
Parsing Verilog input from `yosys-always_display-clk_rst_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
     1/1: $write$yosys-always_display-clk_rst_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-clk_rst_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-clk_rst_en-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 0c4b4eaa9c, CPU: user 0.01s system 0.01s, MEM: 13.00 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 40% 2x opt_expr (0 sec), 18% 1x clean (0 sec), ...
+ diff yosys-always_display-clk_rst_en-1.v yosys-always_display-clk_rst_en-2.v
+ test_always_display star_en -DEVENT_STAR -DCOND_EN
+ local subtest=star_en
+ shift
+ ../../yosys -p 'read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DEVENT_STAR -DCOND_EN always_display.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: always_display.v
Parsing Verilog input from `always_display.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$always_display.v:10$1'.
     1/1: $display$always_display.v:15$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$always_display.v:10$1'.
Removing empty process `m.$proc$always_display.v:10$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-star_en-1.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: d6a7335726, CPU: user 0.01s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 41% 2x opt_expr (0 sec), 20% 1x clean (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' -o yosys-always_display-star_en-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-always_display-star_en-1.v; proc; opt_expr -mux_bool; clean' --

1. Executing Verilog-2005 frontend: yosys-always_display-star_en-1.v
Parsing Verilog input from `yosys-always_display-star_en-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
     1/1: $write$yosys-always_display-star_en-1.v:20$2_EN

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-always_display-star_en-1.v:18$1'.
Removing empty process `m.$proc$yosys-always_display-star_en-1.v:18$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.

3. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
<suppressed ~1 debug messages>
Removed 0 unused cells and 3 unused wires.

-- Writing to `yosys-always_display-star_en-2.v' using backend `verilog' --

4. Executing Verilog backend.

4.1. Executing BMUXMAP pass.

4.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 18895a2046, CPU: user 0.00s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 43% 2x opt_expr (0 sec), 19% 1x clean (0 sec), ...
+ diff yosys-always_display-star_en-1.v yosys-always_display-star_en-2.v
+ test_roundtrip dec_unsigned -DBASE_DEC -DSIGN=
+ local subtest=dec_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-dec_unsigned-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_DEC -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: bfb187b86d, CPU: user 0.00s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' -o yosys-roundtrip-dec_unsigned-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-dec_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-dec_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 4be9539e85, CPU: user 0.00s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-dec_unsigned-1.v yosys-roundtrip-dec_unsigned-2.v
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-1 yosys-roundtrip-dec_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned-1
+ iverilog -DBASE_DEC -DSIGN= -o iverilog-roundtrip-dec_unsigned-2 yosys-roundtrip-dec_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_unsigned-1
+ diff iverilog-roundtrip-dec_unsigned.log iverilog-roundtrip-dec_unsigned-1.log
+ diff iverilog-roundtrip-dec_unsigned-1.log iverilog-roundtrip-dec_unsigned-2.log
+ test_roundtrip dec_signed -DBASE_DEC -DSIGN=signed
+ local subtest=dec_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-dec_signed-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_DEC -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: bbdfa5ca92, CPU: user 0.01s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' -o yosys-roundtrip-dec_signed-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-dec_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-dec_signed-1.v
Parsing Verilog input from `yosys-roundtrip-dec_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-dec_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-dec_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: b233de92a6, CPU: user 0.00s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-dec_signed-1.v yosys-roundtrip-dec_signed-2.v
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-1 yosys-roundtrip-dec_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed-1
+ iverilog -DBASE_DEC -DSIGN=signed -o iverilog-roundtrip-dec_signed-2 yosys-roundtrip-dec_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-dec_signed-1
+ diff iverilog-roundtrip-dec_signed.log iverilog-roundtrip-dec_signed-1.log
+ diff iverilog-roundtrip-dec_signed-1.log iverilog-roundtrip-dec_signed-2.log
+ test_roundtrip hex_unsigned -DBASE_HEX -DSIGN=
+ local subtest=hex_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-hex_unsigned-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 2377f2e106, CPU: user 0.01s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' -o yosys-roundtrip-hex_unsigned-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-hex_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-hex_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 06bfea69c8, CPU: user 0.01s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-hex_unsigned-1.v yosys-roundtrip-hex_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-1 yosys-roundtrip-hex_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-hex_unsigned-2 yosys-roundtrip-hex_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_unsigned-1
+ diff iverilog-roundtrip-hex_unsigned.log iverilog-roundtrip-hex_unsigned-1.log
+ diff iverilog-roundtrip-hex_unsigned-1.log iverilog-roundtrip-hex_unsigned-2.log
+ test_roundtrip hex_signed -DBASE_HEX -DSIGN=signed
+ local subtest=hex_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-hex_signed-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 824c3b1e65, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' -o yosys-roundtrip-hex_signed-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-hex_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-hex_signed-1.v
Parsing Verilog input from `yosys-roundtrip-hex_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-hex_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-hex_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: f18b3fa15b, CPU: user 0.01s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-hex_signed-1.v yosys-roundtrip-hex_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-1 yosys-roundtrip-hex_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-hex_signed-2 yosys-roundtrip-hex_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-hex_signed-1
+ diff iverilog-roundtrip-hex_signed.log iverilog-roundtrip-hex_signed-1.log
+ diff iverilog-roundtrip-hex_signed-1.log iverilog-roundtrip-hex_signed-2.log
+ test_roundtrip oct_unsigned -DBASE_HEX -DSIGN=
+ local subtest=oct_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-oct_unsigned-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: b768358a65, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 24% 1x clean (0 sec), 20% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' -o yosys-roundtrip-oct_unsigned-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-oct_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-oct_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 762621cd95, CPU: user 0.00s system 0.00s, MEM: 12.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-oct_unsigned-1.v yosys-roundtrip-oct_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-1 yosys-roundtrip-oct_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-oct_unsigned-2 yosys-roundtrip-oct_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_unsigned-1
+ diff iverilog-roundtrip-oct_unsigned.log iverilog-roundtrip-oct_unsigned-1.log
+ diff iverilog-roundtrip-oct_unsigned-1.log iverilog-roundtrip-oct_unsigned-2.log
+ test_roundtrip oct_signed -DBASE_HEX -DSIGN=signed
+ local subtest=oct_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-oct_signed-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 7ec82b15e3, CPU: user 0.00s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 26% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' -o yosys-roundtrip-oct_signed-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-oct_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-oct_signed-1.v
Parsing Verilog input from `yosys-roundtrip-oct_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-oct_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-oct_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: a747b9bd4f, CPU: user 0.00s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 22% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-oct_signed-1.v yosys-roundtrip-oct_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-1 yosys-roundtrip-oct_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-oct_signed-2 yosys-roundtrip-oct_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-oct_signed-1
+ diff iverilog-roundtrip-oct_signed.log iverilog-roundtrip-oct_signed-1.log
+ diff iverilog-roundtrip-oct_signed-1.log iverilog-roundtrip-oct_signed-2.log
+ test_roundtrip bin_unsigned -DBASE_HEX -DSIGN=
+ local subtest=bin_unsigned
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' -o yosys-roundtrip-bin_unsigned-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN= roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_unsigned-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 270b564880, CPU: user 0.01s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' -o yosys-roundtrip-bin_unsigned-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-bin_unsigned-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_unsigned-1.v
Parsing Verilog input from `yosys-roundtrip-bin_unsigned-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_unsigned-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_unsigned-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: dc9f56cb10, CPU: user 0.00s system 0.00s, MEM: 12.50 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 26% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_unsigned-1.v yosys-roundtrip-bin_unsigned-2.v
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-1 yosys-roundtrip-bin_unsigned-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned-1
+ iverilog -DBASE_HEX -DSIGN= -o iverilog-roundtrip-bin_unsigned-2 yosys-roundtrip-bin_unsigned-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_unsigned-1
+ diff iverilog-roundtrip-bin_unsigned.log iverilog-roundtrip-bin_unsigned-1.log
+ diff iverilog-roundtrip-bin_unsigned-1.log iverilog-roundtrip-bin_unsigned-2.log
+ test_roundtrip bin_signed -DBASE_HEX -DSIGN=signed
+ local subtest=bin_signed
+ shift
+ ../../yosys -p 'read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' -o yosys-roundtrip-bin_signed-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog -DBASE_HEX -DSIGN=signed roundtrip.v; proc; clean' --

1. Executing Verilog-2005 frontend: roundtrip.v
Parsing Verilog input from `roundtrip.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$roundtrip.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$roundtrip.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_signed-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 7709253822, CPU: user 0.01s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 27% 1x clean (0 sec), 21% 1x opt_expr (0 sec), ...
+ ../../yosys -p 'read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' -o yosys-roundtrip-bin_signed-2.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog yosys-roundtrip-bin_signed-1.v; proc; clean' --

1. Executing Verilog-2005 frontend: yosys-roundtrip-bin_signed-1.v
Parsing Verilog input from `yosys-roundtrip-bin_signed-1.v' to AST representation.
Generating RTLIL representation for module `\m'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 1 empty switch.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 1 redundant assignment.
Promoted 1 assignment to connection.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `m.$proc$yosys-roundtrip-bin_signed-1.v:12$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module m.
Removed 0 unused cells and 1 unused wires.

-- Writing to `yosys-roundtrip-bin_signed-2.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\m'.

End of script. Logfile hash: 7e2d8271c4, CPU: user 0.01s system 0.00s, MEM: 12.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 1x clean (0 sec), 23% 1x opt_expr (0 sec), ...
+ diff yosys-roundtrip-bin_signed-1.v yosys-roundtrip-bin_signed-2.v
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed roundtrip.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-1 yosys-roundtrip-bin_signed-1.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed-1
+ iverilog -DBASE_HEX -DSIGN=signed -o iverilog-roundtrip-bin_signed-2 yosys-roundtrip-bin_signed-2.v roundtrip_tb.v
+ ./iverilog-roundtrip-bin_signed-1
+ diff iverilog-roundtrip-bin_signed.log iverilog-roundtrip-bin_signed-1.log
+ diff iverilog-roundtrip-bin_signed-1.log iverilog-roundtrip-bin_signed-2.log
+ test_cxxrtl always_full
+ local subtest=always_full
+ shift
+ ../../yosys -p 'read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog always_full.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_full.cc' --

1. Executing Verilog-2005 frontend: always_full.v
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.
Removed 0 unused cells and 207 unused wires.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
root of   0 design levels: always_full         
Automatically selected always_full as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \always_full

3.1.3. Analyzing design hierarchy..
Top module:  \always_full
Removed 0 unused modules.
Module always_full directly or indirectly displays text -> setting "keep" attribute.

3.2. Executing FLATTEN pass (flatten design).

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

<suppressed ~12 debug messages>

End of script. Logfile hash: af8795c7c4, CPU: user 0.02s system 0.00s, MEM: 14.62 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 30% 2x read_verilog (0 sec), 27% 2x write_cxxrtl (0 sec), ...
+ gcc -std=c++11 -o yosys-always_full -I../../backends/cxxrtl/runtime always_full_tb.cc -lstdc++
+ ./yosys-always_full
+ iverilog -o iverilog-always_full always_full.v always_full_tb.v
+ ./iverilog-always_full
+ grep -v '\$finish called'
+ diff iverilog-always_full.log yosys-always_full.log
+ test_cxxrtl always_comb
+ local subtest=always_comb
+ shift
+ ../../yosys -p 'read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog always_comb.v; proc; clean; write_cxxrtl -print-output std::cerr yosys-always_comb.cc' --

1. Executing Verilog-2005 frontend: always_comb.v
Parsing Verilog input from `always_comb.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\sub'.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 4 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\top.$proc$always_comb.v:3$13'.
  Set init value: \b = 1'0
Found init rule in `\top.$proc$always_comb.v:2$12'.
  Set init value: \a = 1'0

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.
<suppressed ~1 debug messages>

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\sub.$proc$always_comb.v:23$15'.
     1/1: $display$always_comb.v:23$19_EN
Creating decoders for process `\top.$proc$always_comb.v:3$13'.
Creating decoders for process `\top.$proc$always_comb.v:2$12'.
Creating decoders for process `\top.$proc$always_comb.v:8$1'.

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `\top.\a' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$22' with positive edge clock.
Creating register for signal `\top.\b' using process `\top.$proc$always_comb.v:8$1'.
  created $dff cell `$procdff$23' with positive edge clock.

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `\sub.$proc$always_comb.v:23$15'.
Removing empty process `sub.$proc$always_comb.v:23$15'.
Removing empty process `top.$proc$always_comb.v:3$13'.
Removing empty process `top.$proc$always_comb.v:2$12'.
Removing empty process `top.$proc$always_comb.v:8$1'.
Cleaned up 1 empty switch.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module sub.
Optimizing module top.
Removed 0 unused cells and 7 unused wires.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
root of   0 design levels: sub                 
root of   1 design levels: top                 
Automatically selected top as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub

3.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \sub
Removed 0 unused modules.
Module sub directly or indirectly displays text -> setting "keep" attribute.
Module top directly or indirectly displays text -> setting "keep" attribute.

3.2. Executing FLATTEN pass (flatten design).
Deleting now unused module sub.
<suppressed ~1 debug messages>

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

<suppressed ~12 debug messages>

End of script. Logfile hash: a6b3c2e895, CPU: user 0.01s system 0.01s, MEM: 13.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 30% 2x opt_expr (0 sec), 17% 1x clean (0 sec), ...
+ gcc -std=c++11 -o yosys-always_comb -I../../backends/cxxrtl/runtime always_comb_tb.cc -lstdc++
+ ./yosys-always_comb
+ iverilog -o iverilog-always_comb always_comb.v always_comb_tb.v
+ ./iverilog-always_comb
+ grep -v '\$finish called'
+ diff iverilog-always_comb.log yosys-always_comb.log
+ ../../yosys -p 'read_verilog always_full.v; prep; clean' -o yosys-always_full-1.v

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog always_full.v; prep; clean' --

1. Executing Verilog-2005 frontend: always_full.v
Parsing Verilog input from `always_full.v' to AST representation.
Generating RTLIL representation for module `\always_full'.
Successfully finished Verilog frontend.

2. Executing PREP pass.

2.1. Executing HIERARCHY pass (managing design hierarchy).
Module always_full directly or indirectly displays text -> setting "keep" attribute.

2.2. Executing PROC pass (convert processes to netlists).

2.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 207 redundant assignments.
Promoted 207 assignments to connections.

2.2.4. Executing PROC_INIT pass (extract init attributes).

2.2.5. Executing PROC_ARST pass (detect async resets in processes).

2.2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\always_full.$proc$always_full.v:3$1'.

2.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `always_full.$proc$always_full.v:3$1'.
Cleaned up 0 empty switches.

2.2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.3. Executing FUTURE pass.

2.4. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..
Removed 0 unused cells and 207 unused wires.
<suppressed ~1 debug messages>

2.6. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.

2.7. Executing OPT pass (performing simple optimizations).

2.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \always_full..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

2.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \always_full.
Performed a total of 0 changes.

2.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.7.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..

2.7.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.7.8. Finished OPT passes. (There is nothing left to do.)

2.8. Executing WREDUCE pass (reducing word size of cells).

2.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..

2.10. Executing MEMORY_COLLECT pass (generating $mem cells).

2.11. Executing OPT pass (performing simple optimizations).

2.11.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module always_full.

2.11.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\always_full'.
Removed a total of 0 cells.

2.11.3. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \always_full..

2.11.4. Finished fast OPT passes.

2.12. Printing statistics.

=== always_full ===

   Number of wires:                  1
   Number of wire bits:              1
   Number of public wires:           1
   Number of public wire bits:       1
   Number of ports:                  1
   Number of port bits:              1
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:                207
     $print                        207

2.13. Executing CHECK pass (checking for obvious problems).
Checking module always_full...
Found and reported 0 problems.

-- Writing to `yosys-always_full-1.v' using backend `verilog' --

3. Executing Verilog backend.

3.1. Executing BMUXMAP pass.

3.2. Executing DEMUXMAP pass.
Dumping module `\always_full'.

End of script. Logfile hash: 52e889d7da, CPU: user 0.04s system 0.00s, MEM: 14.38 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 19% 4x opt_clean (0 sec), 17% 1x prep (0 sec), ...
+ iverilog -o iverilog-always_full-1 yosys-always_full-1.v always_full_tb.v
+ ./iverilog-always_full-1
+ grep -v '\$finish called'
+ diff iverilog-always_full.log iverilog-always_full-1.log
+ ../../yosys -p 'read_verilog display_lm.v'
+ ../../yosys -p 'read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog display_lm.v; write_cxxrtl yosys-display_lm.cc' --

1. Executing Verilog-2005 frontend: display_lm.v
Parsing Verilog input from `display_lm.v' to AST representation.
Generating RTLIL representation for module `\top'.
Generating RTLIL representation for module `\mid'.
Generating RTLIL representation for module `\bot'.
%l: \bot
%m: \bot
Successfully finished Verilog frontend.

2. Executing CXXRTL backend.

2.1. Executing HIERARCHY pass (managing design hierarchy).

2.1.1. Finding top of design hierarchy..
root of   0 design levels: bot                 
root of   1 design levels: mid                 
root of   2 design levels: top                 
Automatically selected top as design top module.

2.1.2. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot

2.1.3. Analyzing design hierarchy..
Top module:  \top
Used module:     \mid
Used module:         \bot
Removed 0 unused modules.
Module bot directly or indirectly displays text -> setting "keep" attribute.
Module mid directly or indirectly displays text -> setting "keep" attribute.
Module top directly or indirectly displays text -> setting "keep" attribute.

2.2. Executing FLATTEN pass (flatten design).
Deleting now unused module bot.
Deleting now unused module mid.
<suppressed ~2 debug messages>

2.3. Executing PROC pass (convert processes to netlists).

2.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 2 redundant assignments.
Promoted 2 assignments to connections.

2.3.4. Executing PROC_INIT pass (extract init attributes).

2.3.5. Executing PROC_ARST pass (detect async resets in processes).

2.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
Creating decoders for process `\top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.

2.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:0$3'.
Removing empty process `top.$flatten\mid_uut.\bot_uut.$proc$display_lm.v:11$1'.
Cleaned up 0 empty switches.

2.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

<suppressed ~12 debug messages>

End of script. Logfile hash: 15a147f3a6, CPU: user 0.01s system 0.00s, MEM: 12.75 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 33% 1x opt_expr (0 sec), 16% 2x write_cxxrtl (0 sec), ...
+ gcc -std=c++11 -o yosys-display_lm_cc -I../../backends/cxxrtl/runtime display_lm_tb.cc -lstdc++
+ ./yosys-display_lm_cc
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm.log
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm.log
%m: \bot
+ for log in yosys-display_lm.log yosys-display_lm_cc.log
+ grep '^%l: \\bot$' yosys-display_lm_cc.log
%l: \bot
%l: \bot
+ grep '^%m: \\bot$' yosys-display_lm_cc.log
%m: \bot
%m: \bot
cd tests/cxxrtl && bash run-test.sh
+ run_subtest value
+ local subtest=value
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value -I../../backends/cxxrtl/runtime test_value.cc -lstdc++
+ ./cxxrtl-test-value
+ run_subtest value_fuzz
+ local subtest=value_fuzz
+ shift
+ gcc -std=c++11 -O2 -o cxxrtl-test-value_fuzz -I../../backends/cxxrtl/runtime test_value_fuzz.cc -lstdc++
+ ./cxxrtl-test-value_fuzz
Randomized tests for value::shl:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::shr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sshr:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::add:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sub:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::ctlz:
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::udivmod (div):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::udivmod (mod):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sdivmod (div):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
Randomized tests for value::sdivmod (mod):
Test passed @ Bits = 8.
Test passed @ Bits = 32.
Test passed @ Bits = 42.
Test passed @ Bits = 63.
Test passed @ Bits = 64.
+ ../../yosys -p 'read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc'

 /----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)

-- Running command `read_verilog test_unconnected_output.v; proc; clean; write_cxxrtl cxxrtl-test-unconnected_output.cc' --

1. Executing Verilog-2005 frontend: test_unconnected_output.v
Parsing Verilog input from `test_unconnected_output.v' to AST representation.
Generating RTLIL representation for module `\blackbox'.
Generating RTLIL representation for module `\unconnected_output'.
test_unconnected_output.v:19: Warning: Identifier `\clock' is implicitly declared.
Successfully finished Verilog frontend.

2. Executing PROC pass (convert processes to netlists).

2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

2.4. Executing PROC_INIT pass (extract init attributes).

2.5. Executing PROC_ARST pass (detect async resets in processes).

2.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

2.8. Executing PROC_DLATCH pass (convert process syncs to latches).

2.9. Executing PROC_DFF pass (convert process syncs to FFs).

2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

2.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module unconnected_output.

3. Executing CXXRTL backend.

3.1. Executing HIERARCHY pass (managing design hierarchy).

3.1.1. Finding top of design hierarchy..
root of   1 design levels: unconnected_output  
Automatically selected unconnected_output as design top module.

3.1.2. Analyzing design hierarchy..
Top module:  \unconnected_output

3.1.3. Analyzing design hierarchy..
Top module:  \unconnected_output
Removed 0 unused modules.
Warning: Resizing cell port unconnected_output.bb.out1 from 1 bits to 8 bits.

3.2. Executing FLATTEN pass (flatten design).

3.3. Executing PROC pass (convert processes to netlists).

3.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

3.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

3.3.4. Executing PROC_INIT pass (extract init attributes).

3.3.5. Executing PROC_ARST pass (detect async resets in processes).

3.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

3.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

3.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).

3.3.9. Executing PROC_DFF pass (convert process syncs to FFs).

3.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

3.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

3.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module unconnected_output.

<suppressed ~20 debug messages>

Warnings: 2 unique messages, 2 total
End of script. Logfile hash: 91df85c4b8, CPU: user 0.01s system 0.01s, MEM: 13.00 MB peak
Yosys 0.47+22 (git sha1 f20f913223c42fce6ecc4382b281cf67952e0a72, g++ 14.2.1 -O2 -flto=auto -ffat-lto-objects -fexceptions -fstack-protector-strong -m64 -march=x86-64 -mtune=generic -fasynchronous-unwind-tables -fstack-clash-protection -fcf-protection -mtls-dialect=gnu2 -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -fPIC -O3)
Time spent: 25% 2x opt_expr (0 sec), 19% 2x read_verilog (0 sec), ...
+ gcc -std=c++11 -c -o cxxrtl-test-unconnected_output -I../../backends/cxxrtl/runtime cxxrtl-test-unconnected_output.cc

  Passed "make test".

+ RPM_EC=0
++ jobs -p
+ exit 0
Processing files: yosys-0.47-1.20241110gitf20f913.fc42.x86_64
Executing(%doc): /bin/sh -e /var/tmp/rpm-tmp.InA9SW
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ DOCDIR=/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/doc/yosys
+ export LC_ALL=C.UTF-8
+ LC_ALL=C.UTF-8
+ export DOCDIR
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/doc/yosys
+ cp -pr /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/README.md /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/doc/yosys
+ RPM_EC=0
++ jobs -p
+ exit 0
Executing(%license): /bin/sh -e /var/tmp/rpm-tmp.5Re3xl
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ cd yosys-f20f913223c42fce6ecc4382b281cf67952e0a72
+ LICENSEDIR=/builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/licenses/yosys
+ export LC_ALL=C.UTF-8
+ LC_ALL=C.UTF-8
+ export LICENSEDIR
+ /usr/bin/mkdir -p /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/licenses/yosys
+ cp -pr /builddir/build/BUILD/yosys-0.47-build/yosys-f20f913223c42fce6ecc4382b281cf67952e0a72/COPYING /builddir/build/BUILD/yosys-0.47-build/BUILDROOT/usr/share/licenses/yosys
+ RPM_EC=0
++ jobs -p
+ exit 0
Provides: yosys = 0.47-1.20241110gitf20f913.fc42 yosys(x86-64) = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: /usr/bin/python3 libc.so.6()(64bit) libc.so.6(GLIBC_2.11)(64bit) libc.so.6(GLIBC_2.14)(64bit) libc.so.6(GLIBC_2.15)(64bit) libc.so.6(GLIBC_2.2.5)(64bit) libc.so.6(GLIBC_2.26)(64bit) libc.so.6(GLIBC_2.27)(64bit) libc.so.6(GLIBC_2.3)(64bit) libc.so.6(GLIBC_2.3.4)(64bit) libc.so.6(GLIBC_2.32)(64bit) libc.so.6(GLIBC_2.33)(64bit) libc.so.6(GLIBC_2.34)(64bit) libc.so.6(GLIBC_2.38)(64bit) libc.so.6(GLIBC_2.4)(64bit) libc.so.6(GLIBC_2.8)(64bit) libffi.so.8()(64bit) libffi.so.8(LIBFFI_BASE_8.0)(64bit) libgcc_s.so.1()(64bit) libgcc_s.so.1(GCC_3.0)(64bit) libgcc_s.so.1(GCC_3.3.1)(64bit) libm.so.6()(64bit) libm.so.6(GLIBC_2.2.5)(64bit) libm.so.6(GLIBC_2.29)(64bit) libm.so.6(GLIBC_2.35)(64bit) libm.so.6(GLIBC_2.38)(64bit) libreadline.so.8()(64bit) libstdc++.so.6()(64bit) libstdc++.so.6(CXXABI_1.3)(64bit) libstdc++.so.6(CXXABI_1.3.15)(64bit) libstdc++.so.6(CXXABI_1.3.5)(64bit) libstdc++.so.6(CXXABI_1.3.9)(64bit) libstdc++.so.6(GLIBCXX_3.4)(64bit) libstdc++.so.6(GLIBCXX_3.4.11)(64bit) libstdc++.so.6(GLIBCXX_3.4.14)(64bit) libstdc++.so.6(GLIBCXX_3.4.15)(64bit) libstdc++.so.6(GLIBCXX_3.4.18)(64bit) libstdc++.so.6(GLIBCXX_3.4.20)(64bit) libstdc++.so.6(GLIBCXX_3.4.21)(64bit) libstdc++.so.6(GLIBCXX_3.4.26)(64bit) libstdc++.so.6(GLIBCXX_3.4.29)(64bit) libstdc++.so.6(GLIBCXX_3.4.30)(64bit) libstdc++.so.6(GLIBCXX_3.4.32)(64bit) libstdc++.so.6(GLIBCXX_3.4.5)(64bit) libstdc++.so.6(GLIBCXX_3.4.9)(64bit) libtcl8.6.so()(64bit) libz.so.1()(64bit) libz.so.1(ZLIB_1.2.0)(64bit) rtld(GNU_HASH)
Processing files: yosys-doc-0.47-1.20241110gitf20f913.fc42.x86_64
Provides: yosys-doc = 0.47-1.20241110gitf20f913.fc42 yosys-doc(x86-64) = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-share-0.47-1.20241110gitf20f913.fc42.noarch
Provides: yosys-share = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-devel-0.47-1.20241110gitf20f913.fc42.x86_64
Provides: yosys-devel = 0.47-1.20241110gitf20f913.fc42 yosys-devel(x86-64) = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Requires: /usr/bin/bash
Processing files: yosys-debugsource-0.47-1.20241110gitf20f913.fc42.x86_64
Provides: yosys-debugsource = 0.47-1.20241110gitf20f913.fc42 yosys-debugsource(x86-64) = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Processing files: yosys-debuginfo-0.47-1.20241110gitf20f913.fc42.x86_64
Provides: debuginfo(build-id) = 18956d8ed71767d961a6aa892ec85b5355a7ae69 debuginfo(build-id) = 677f8a99c476560affa831d9eba19b5f6f863283 yosys-debuginfo = 0.47-1.20241110gitf20f913.fc42 yosys-debuginfo(x86-64) = 0.47-1.20241110gitf20f913.fc42
Requires(rpmlib): rpmlib(CompressedFileNames) <= 3.0.4-1 rpmlib(FileDigests) <= 4.6.0-1 rpmlib(PayloadFilesHavePrefix) <= 4.0-1
Recommends: yosys-debugsource(x86-64) = 0.47-1.20241110gitf20f913.fc42
Checking for unpackaged file(s): /usr/lib/rpm/check-files /builddir/build/BUILD/yosys-0.47-build/BUILDROOT
Wrote: /builddir/build/RPMS/yosys-0.47-1.20241110gitf20f913.fc42.x86_64.rpm
Wrote: /builddir/build/RPMS/yosys-share-0.47-1.20241110gitf20f913.fc42.noarch.rpm
Wrote: /builddir/build/RPMS/yosys-debugsource-0.47-1.20241110gitf20f913.fc42.x86_64.rpm
Wrote: /builddir/build/RPMS/yosys-doc-0.47-1.20241110gitf20f913.fc42.x86_64.rpm
Wrote: /builddir/build/RPMS/yosys-devel-0.47-1.20241110gitf20f913.fc42.x86_64.rpm
Wrote: /builddir/build/RPMS/yosys-debuginfo-0.47-1.20241110gitf20f913.fc42.x86_64.rpm
Executing(rmbuild): /bin/sh -e /var/tmp/rpm-tmp.yE6Olt
+ umask 022
+ cd /builddir/build/BUILD/yosys-0.47-build
+ test -d /builddir/build/BUILD/yosys-0.47-build
+ /usr/bin/chmod -Rf a+rX,u+w,g-w,o-w /builddir/build/BUILD/yosys-0.47-build
+ rm -rf /builddir/build/BUILD/yosys-0.47-build
+ RPM_EC=0
++ jobs -p
+ exit 0
Finish: rpmbuild yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
Finish: build phase for yosys-0.47-1.20241110gitf20f913.fc42.src.rpm
INFO: chroot_scan: 1 files copied to /var/lib/copr-rpmbuild/results/chroot_scan
INFO: /var/lib/mock/fedora-rawhide-x86_64-1732107006.500093/root/var/log/dnf5.log
INFO: chroot_scan: creating tarball /var/lib/copr-rpmbuild/results/chroot_scan.tar.gz
/bin/tar: Removing leading `/' from member names
INFO: Done(/var/lib/copr-rpmbuild/results/yosys-0.47-1.20241110gitf20f913.fc42.src.rpm) Config(child) 76 minutes 15 seconds
INFO: Results and/or logs in: /var/lib/copr-rpmbuild/results
INFO: Cleaning up build root ('cleanup_on_success=True')
Start: clean chroot
INFO: unmounting tmpfs.
Finish: clean chroot
Finish: run
Running RPMResults tool
Package info:
{
    "packages": [
        {
            "name": "yosys",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "src"
        },
        {
            "name": "yosys",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "x86_64"
        },
        {
            "name": "yosys-devel",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "x86_64"
        },
        {
            "name": "yosys-share",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "noarch"
        },
        {
            "name": "yosys-debuginfo",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "x86_64"
        },
        {
            "name": "yosys-debugsource",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "x86_64"
        },
        {
            "name": "yosys-doc",
            "epoch": null,
            "version": "0.47",
            "release": "1.20241110gitf20f913.fc42",
            "arch": "x86_64"
        }
    ]
}
RPMResults finished