Available on AArch64 or
target_arch="arm64ec"
only.Expand description
Platform-specific intrinsics for the aarch64
platform.
See the module documentation for more details.
Structs§
- SY
Experimental Full system is the required shareability domain, reads and writes are the required access types
Constants§
- _PREFETC
H_ LOCALIT Y0 Experimental Seeprefetch
. - _PREFETC
H_ LOCALIT Y1 Experimental Seeprefetch
. - _PREFETC
H_ LOCALIT Y2 Experimental Seeprefetch
. - _PREFETC
H_ LOCALIT Y3 Experimental Seeprefetch
. - _PREFETC
H_ READ Experimental Seeprefetch
. - _PREFETC
H_ WRITE Experimental Seeprefetch
. - _TMFAILUR
E_ CNCL Experimental Transaction executed a TCANCEL instruction - _TMFAILUR
E_ DBG Experimental Transaction aborted due to a debug trap. - _TMFAILUR
E_ ERR Experimental Transaction aborted because a non-permissible operation was attempted - _TMFAILUR
E_ IMP Experimental Fallback error type for any other reason - _TMFAILUR
E_ INT Experimental Transaction failed from interrupt - _TMFAILUR
E_ MEM Experimental Transaction aborted because a conflict occurred - _TMFAILUR
E_ NEST Experimental Transaction aborted due to transactional nesting level was exceeded - _TMFAILUR
E_ REASON Experimental Extraction mask for failure reason - _TMFAILUR
E_ RTRY Experimental Transaction retry is possible. - _TMFAILUR
E_ SIZE Experimental Transaction aborted due to read or write set limit was exceeded - _TMFAILUR
E_ TRIVIAL Experimental Indicates a TRIVIAL version of TM is available - _TMSTAR
T_ SUCCESS Experimental Transaction successfully started.
Functions§
- __
crc32b ⚠crc
CRC32 single round checksum for bytes (8 bits). - __
crc32cb ⚠crc
CRC32-C single round checksum for bytes (8 bits). - __
crc32ch ⚠crc
CRC32-C single round checksum for half words (16 bits). - __
crc32cw ⚠crc
CRC32-C single round checksum for words (32 bits). - __
crc32h ⚠crc
CRC32 single round checksum for half words (16 bits). - __
crc32w ⚠crc
CRC32 single round checksum for words (32 bits). - __dmb⚠
Experimental Generates a DMB (data memory barrier) instruction or equivalent CP15 instruction. - __dsb⚠
Experimental Generates a DSB (data synchronization barrier) instruction or equivalent CP15 instruction. - __isb⚠
Experimental Generates an ISB (instruction synchronization barrier) instruction or equivalent CP15 instruction. - __nop⚠
Experimental Generates an unspecified no-op instruction. - __sev⚠
Experimental Generates a SEV (send a global event) hint instruction. - __sevl⚠
Experimental Generates a send a local event hint instruction. - __
tcancel ⚠Experimental tme
Cancels the current transaction and discards all state modifications that were performed transactionally. - __
tcommit ⚠Experimental tme
Commits the current transaction. For a nested transaction, the only effect is that the transactional nesting depth is decreased. For an outer transaction, the state modifications performed transactionally are committed to the architectural state. - __
tstart ⚠Experimental tme
Starts a new transaction. When the transaction starts successfully the return value is 0. If the transaction fails, all state modifications are discarded and a cause of the failure is encoded in the return value. - __ttest⚠
Experimental tme
Tests if executing inside a transaction. If no transaction is currently executing, the return value is 0. Otherwise, this intrinsic returns the depth of the transaction. - __wfe⚠
Experimental Generates a WFE (wait for event) hint instruction, or nothing. - __wfi⚠
Experimental Generates a WFI (wait for interrupt) hint instruction, or nothing. - __yield⚠
Experimental Generates a YIELD hint instruction. - _prefetch⚠
Experimental Fetch the cache line that contains addressp
using the givenRW
andLOCALITY
.