
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 17 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080017   {EOT}  // wr:5h+0, rd:0; simd8_write off=1 (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 07 00 08 12 |         send.urb (8)              null    r13            0x00000000  0x12080007  // wr:9h+0, rd:0; simd8_write (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 27 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080027   {EOT}  // wr:5h+0, rd:0; simd8_write off=2 (8)
skl | 31 00 80 09 0c 02 20 01 40 00 00 06 00 03 28 02 | (W)     send.hdc_ro (16)          r9      r2             0x00000000  0x02280300  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(0)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 17 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080017   {EOT}  // wr:9h+0, rd:0; simd8_write off=1 (8)
skl | 31 00 80 07 04 02 00 00 e0 0f 00 06 10 00 00 82 | (W)     send.ts (16)              null    r127           0x00000000  0x02000010   {EOT}
skl | 31 00 60 02 08 02 80 0f a0 01 00 06 01 a0 43 06 |         send.smpl (8)             r124    r13            0x00000000  0x0643A001  // wr:3+0, rd:4; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f e0 02 00 06 01 a0 85 0c |         send.smpl (16)            r120    r23            0x00000000  0x0C85A001  // wr:6+0, rd:8; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 00 60 06 08 02 40 01 40 00 00 06 28 00 48 02 |         send.urb (8)              r10     r2             0x00000000  0x02480028  // wr:1h+0, rd:4; simd8_read off=2 (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 17 00 0a 14 |         send.urb (8)              null    r8             0x00000000  0x140A0017  // wr:10h+0, rd:0; simd8_write off=1 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 17 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0017   {EOT}  // wr:10h+0, rd:0; simd8_write off=1 per_slot (8)
skl | 31 00 60 02 08 02 40 00 40 01 00 06 01 70 42 08 |         send.smpl (8)             r2      r10            0x00000000  0x08427001  // wr:4+0, rd:4; ld:u,v,lod,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 40 02 00 06 01 70 84 10 |         send.smpl (16)            r2      r18            0x00000000  0x10847001  // wr:8+0, rd:8; ld:u,v,lod,r (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 60 01 00 06 37 00 0a 0c |         send.urb (8)              null    r11            0x00000000  0x0C0A0037  // wr:6h+0, rd:0; simd8_write off=3 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 27 00 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A080027  // wr:5h+0, rd:0; simd8_write off=2 (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 80 08 0c |         send.urb (8)              null    r6             0x00000000  0x0C088017  // wr:6h+0, rd:0; simd8_write off=1 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 80 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A088017  // wr:5h+0, rd:0; simd8_write off=1 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 80 08 08 |         send.urb (8)              null    r6             0x00000000  0x08088017  // wr:4h+0, rd:0; simd8_write off=1 masked (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 17 80 08 06 |         send.urb (8)              null    r2             0x00000000  0x06088017  // wr:3h+0, rd:0; simd8_write off=1 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 07 80 08 0c |         send.urb (8)              null    r6             0x00000000  0x0C088007  // wr:6h+0, rd:0; simd8_write masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 07 80 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A088007  // wr:5h+0, rd:0; simd8_write masked (8)
skl | 31 00 60 06 00 02 00 00 a0 0f 00 06 07 80 08 86 |         send.urb (8)              null    r125           0x00000000  0x06088007   {EOT}  // wr:3h+0, rd:0; simd8_write masked (8)
skl | 31 00 60 02 08 02 e0 00 e0 00 00 06 00 a0 43 04 |         send.smpl (8)             r7      r7             0x00000000  0x0443A000  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 01 c0 00 00 06 01 a0 22 02 |         send.smpl (8)             r10     r6             0x00000000  0x0222A001  // wr:1+0, rd:2; resinfo:lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 60 02 00 06 01 80 4a 08 |         send.smpl (8)             r2      r19            0x00000000  0x084A8001  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 20 03 00 02 00 06 01 a0 44 04 |         send.smpl (16)            r25     r16            0x00000000  0x0444A001  // wr:2+0, rd:4; resinfo:lod (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 01 e0 00 00 06 01 80 8c 0e |         send.smpl (16)            r14     r7             0x00000000  0x0E8C8001  // wr:7h+0, rd:8; gather4:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 60 01 00 06 17 00 08 12 |         send.urb (8)              null    r11            0x00000000  0x12080017  // wr:9h+0, rd:0; simd8_write off=1 (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 37 00 08 12 |         send.urb (8)              null    r20            0x00000000  0x12080037  // wr:9h+0, rd:0; simd8_write off=3 (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 57 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080057   {EOT}  // wr:5h+0, rd:0; simd8_write off=5 (8)
skl | 31 00 60 02 08 02 20 01 c0 00 00 06 01 d0 13 06 |         send.smpl (8)             r9      r6             0x00000000  0x0613D001  // wr:3+0, rd:1; ld_mcs:u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 c0 01 00 06 01 d0 25 0c |         send.smpl (16)            r12     r14            0x00000000  0x0C25D001  // wr:6+0, rd:2; ld_mcs:u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 c0 01 00 06 01 d0 43 06 |         send.smpl (8)             r2      r14            0x00000000  0x0643D001  // wr:3+0, rd:4; ld_mcs:u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 00 01 20 02 00 06 01 e0 43 0a |         send.smpl (8)             r8      r17            0x00000000  0x0A43E001  // wr:5+0, rd:4; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 03 40 01 00 06 01 d0 85 0c |         send.smpl (16)            r26     r10            0x00000000  0x0C85D001  // wr:6+0, rd:8; ld_mcs:u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 04 00 02 00 06 01 e0 85 14 |         send.smpl (16)            r34     r16            0x00000000  0x1485E001  // wr:10+0, rd:8; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 00 40 00 00 06 01 00 32 04 |         send.smpl (8)             r5      r2             0x00000000  0x04320001  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 40 00 00 06 01 00 64 08 |         send.smpl (16)            r7      r2             0x00000000  0x08640001  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 01 40 01 00 06 01 e0 33 0a |         send.smpl (8)             r12     r10            0x00000000  0x0A33E001  // wr:5+0, rd:3; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 40 02 00 06 01 e0 65 14 |         send.smpl (16)            r2      r18            0x00000000  0x1465E001  // wr:10+0, rd:6; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 00 40 00 00 06 01 00 42 04 |         send.smpl (8)             r5      r2             0x00000000  0x04420001  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 40 00 00 06 01 00 84 08 |         send.smpl (16)            r7      r2             0x00000000  0x08840001  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 60 01 20 01 00 06 00 a0 22 02 |         send.smpl (8)             r11     r9             0x00000000  0x0222A000  // wr:1+0, rd:2; resinfo:lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 80 0f a0 01 00 06 00 80 4a 06 |         send.smpl (8)             r124    r13            0x00000000  0x064A8000  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 80 01 a0 00 00 06 00 70 42 02 |         send.smpl (8)             r12     r5             0x00000000  0x02427000  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(0) using sampler index 0
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 37 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080037   {EOT}  // wr:5h+0, rd:0; simd8_write off=3 (8)
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 01 40 4a 14 |         send.smpl (8)             r6      r11            0x00000000  0x144A4001  // wr:10h+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 61 0c 0a 02 a0 0f 60 00 00 06 01 b5 10 02 | (f1.0)  send.hdc1 (8)             r125    r3             0x00000000  0x0210B501  // wr:1+0, rd:1; untyped_atomic_inc simd8 (8) bti(1)
skl | 31 00 81 0c 0a 02 40 0f 80 00 00 06 01 a5 20 04 | (f1.0)  send.hdc1 (16)            r122    r4             0x00000000  0x0420A501  // wr:2+0, rd:2; untyped_atomic_inc simd16 (16) bti(1)
skl | 31 00 60 02 08 02 c0 00 80 01 00 06 01 40 4a 08 |         send.smpl (8)             r6      r12            0x00000000  0x084A4001  // wr:4h+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 0c 20 02 00 06 01 c0 43 0c |         send.smpl (8)             r98     r17            0x00000000  0x0C43C001  // wr:6+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 00 01 00 06 01 80 4a 06 |         send.smpl (8)             r124    r8             0x00000000  0x064A8001  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 80 01 00 06 01 80 8c 0a |         send.smpl (16)            r120    r12            0x00000000  0x0A8C8001  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 60 1a 0a |         send.smpl (8)             r6      r7             0x00000000  0x0A1A6001  // wr:5h+0, rd:1; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 80 01 00 06 02 61 1a 0a |         send.smpl (8)             r7      r12            0x00000000  0x0A1A6102  // wr:5h+0, rd:1; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 01 00 06 01 60 2c 12 |         send.smpl (16)            r10     r12            0x00000000  0x122C6001  // wr:9h+0, rd:2; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 a0 02 00 06 02 61 2c 12 |         send.smpl (16)            r12     r21            0x00000000  0x122C6102  // wr:9h+0, rd:2; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 80 0f 60 00 00 06 00 e0 43 0a |         send.smpl (8)             r124    r3             0x00000000  0x0A43E000  // wr:5+0, rd:4; ld2dms:si,mcs,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 27 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080027   {EOT}  // wr:9h+0, rd:0; simd8_write off=2 (8)
skl | 31 00 60 02 08 02 40 00 60 00 00 06 00 d0 43 06 |         send.smpl (8)             r2      r3             0x00000000  0x0643D000  // wr:3+0, rd:4; ld_mcs:u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 06 00 02 00 00 e0 00 00 06 37 00 08 0a |         send.urb (8)              null    r7             0x00000000  0x0A080037  // wr:5h+0, rd:0; simd8_write off=3 (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 47 00 08 0a |         send.urb (8)              null    r8             0x00000000  0x0A080047  // wr:5h+0, rd:0; simd8_write off=4 (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 17 00 0a 0c |         send.urb (8)              null    r29            0x00000000  0x0C0A0017  // wr:6h+0, rd:0; simd8_write off=1 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 17 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A0017   {EOT}  // wr:6h+0, rd:0; simd8_write off=1 per_slot (8)
skl | 31 00 60 02 08 02 a0 01 40 01 00 06 01 00 32 02 |         send.smpl (8)             r13     r10            0x00000000  0x02320001  // wr:1+0, rd:3; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 02 40 02 00 06 01 00 64 04 |         send.smpl (16)            r22     r18            0x00000000  0x04640001  // wr:2+0, rd:6; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 00 a0 32 02 |         send.smpl (8)             r124    r2             0x00000000  0x0232A000  // wr:1+0, rd:3; resinfo:lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 01 10 4b 0c |         send.smpl (8)             r2      r13            0x00000000  0x0C4B1001  // wr:6h+0, rd:4; gather4_po (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 02 e0 00 00 06 01 10 8d 16 |         send.smpl (16)            r18     r7             0x00000000  0x168D1001  // wr:11h+0, rd:8; gather4_po (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 27 80 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A088027  // wr:5h+0, rd:0; simd8_write off=2 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 00 00 06 37 80 08 0a |         send.urb (8)              null    r7             0x00000000  0x0A088037  // wr:5h+0, rd:0; simd8_write off=3 masked (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 47 80 08 0a |         send.urb (8)              null    r8             0x00000000  0x0A088047  // wr:5h+0, rd:0; simd8_write off=4 masked (8)
skl | 31 00 60 06 00 02 00 00 20 01 00 06 57 80 08 0a |         send.urb (8)              null    r9             0x00000000  0x0A088057  // wr:5h+0, rd:0; simd8_write off=5 masked (8)
skl | 31 00 60 02 08 02 80 0f 60 00 00 06 00 70 42 06 |         send.smpl (8)             r124    r3             0x00000000  0x06427000  // wr:3+0, rd:4; ld:u,v,lod,r (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 40 01 00 06 01 70 42 06 |         send.smpl (8)             r2      r10            0x00000000  0x06427001  // wr:3+0, rd:4; ld:u,v,lod,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 40 02 00 06 01 70 84 0c |         send.smpl (16)            r2      r18            0x00000000  0x0C847001  // wr:6+0, rd:8; ld:u,v,lod,r (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 01 40 42 0c |         send.smpl (8)             r6      r10            0x00000000  0x0C424001  // wr:6+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 e0 00 00 06 00 10 4b 0c |         send.smpl (8)             r2      r7             0x00000000  0x0C4B1000  // wr:6h+0, rd:4; gather4_po (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 80 00 00 06 00 a0 42 02 |         send.smpl (8)             r2      r4             0x00000000  0x0242A000  // wr:1+0, rd:4; resinfo:lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 01 a1 42 02 |         send.smpl (8)             r6      r6             0x00000000  0x0242A101  // wr:1+0, rd:4; resinfo:lod (8) bti(1) using sampler index 1
skl | 31 00 60 02 08 02 40 01 40 01 00 06 02 a2 42 02 |         send.smpl (8)             r10     r10            0x00000000  0x0242A202  // wr:1+0, rd:4; resinfo:lod (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 c0 01 c0 01 00 06 03 a3 42 02 |         send.smpl (8)             r14     r14            0x00000000  0x0242A303  // wr:1+0, rd:4; resinfo:lod (8) bti(3) using sampler index 3
skl | 31 00 60 02 08 02 40 02 40 02 00 06 04 a4 42 02 |         send.smpl (8)             r18     r18            0x00000000  0x0242A404  // wr:1+0, rd:4; resinfo:lod (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 c0 02 c0 02 00 06 05 a5 42 02 |         send.smpl (8)             r22     r22            0x00000000  0x0242A505  // wr:1+0, rd:4; resinfo:lod (8) bti(5) using sampler index 5
skl | 31 00 60 02 08 02 40 03 40 03 00 06 06 a6 42 02 |         send.smpl (8)             r26     r26            0x00000000  0x0242A606  // wr:1+0, rd:4; resinfo:lod (8) bti(6) using sampler index 6
skl | 31 00 60 06 08 02 c0 00 e0 01 00 06 18 03 2a 04 |         send.urb (8)              r6      r15            0x00000000  0x042A0318  // wr:2h+0, rd:2; simd8_read off=49 per_slot (8)
skl | 31 00 60 06 08 02 00 01 e0 01 00 06 18 05 2a 04 |         send.urb (8)              r8      r15            0x00000000  0x042A0518  // wr:2h+0, rd:2; simd8_read off=81 per_slot (8)
skl | 31 00 60 06 08 02 40 01 e0 01 00 06 18 07 2a 04 |         send.urb (8)              r10     r15            0x00000000  0x042A0718  // wr:2h+0, rd:2; simd8_read off=113 per_slot (8)
skl | 31 00 60 06 08 02 80 01 e0 01 00 06 18 09 2a 04 |         send.urb (8)              r12     r15            0x00000000  0x042A0918  // wr:2h+0, rd:2; simd8_read off=145 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 e0 01 00 06 28 01 2a 04 |         send.urb (8)              r14     r15            0x00000000  0x042A0128  // wr:2h+0, rd:2; simd8_read off=18 per_slot (8)
skl | 31 00 60 06 08 02 00 02 c0 01 00 06 18 02 2a 04 |         send.urb (8)              r16     r14            0x00000000  0x042A0218  // wr:2h+0, rd:2; simd8_read off=33 per_slot (8)
skl | 31 00 60 06 08 02 40 02 c0 01 00 06 18 04 2a 04 |         send.urb (8)              r18     r14            0x00000000  0x042A0418  // wr:2h+0, rd:2; simd8_read off=65 per_slot (8)
skl | 31 00 60 06 08 02 80 02 c0 01 00 06 18 06 2a 04 |         send.urb (8)              r20     r14            0x00000000  0x042A0618  // wr:2h+0, rd:2; simd8_read off=97 per_slot (8)
skl | 31 00 60 06 08 02 c0 02 c0 01 00 06 18 08 2a 04 |         send.urb (8)              r22     r14            0x00000000  0x042A0818  // wr:2h+0, rd:2; simd8_read off=129 per_slot (8)
skl | 31 00 60 06 08 02 a0 01 c0 01 00 06 28 00 2a 04 |         send.urb (8)              r13     r14            0x00000000  0x042A0028  // wr:2h+0, rd:2; simd8_read off=2 per_slot (8)
skl | 31 00 60 06 08 02 40 00 c0 03 00 06 08 02 48 02 |         send.urb (8)              r2      r30            0x00000000  0x02480208  // wr:1h+0, rd:4; simd8_read off=32 (8)
skl | 31 00 60 06 08 02 c0 01 c0 03 00 06 08 04 48 02 |         send.urb (8)              r14     r30            0x00000000  0x02480408  // wr:1h+0, rd:4; simd8_read off=64 (8)
skl | 31 00 60 06 08 02 40 02 c0 03 00 06 08 06 48 02 |         send.urb (8)              r18     r30            0x00000000  0x02480608  // wr:1h+0, rd:4; simd8_read off=96 (8)
skl | 31 00 60 06 08 02 c0 02 c0 03 00 06 08 08 48 02 |         send.urb (8)              r22     r30            0x00000000  0x02480808  // wr:1h+0, rd:4; simd8_read off=128 (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 82 0a 0a |         send.urb (8)              null    r6             0x00000000  0x0A0A8217  // wr:5h+0, rd:0; simd8_write off=33 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 27 82 0a 0a |         send.urb (8)              null    r11            0x00000000  0x0A0A8227  // wr:5h+0, rd:0; simd8_write off=34 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 37 82 0a 0a |         send.urb (8)              null    r12            0x00000000  0x0A0A8237  // wr:5h+0, rd:0; simd8_write off=35 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 47 82 0a 0a |         send.urb (8)              null    r13            0x00000000  0x0A0A8247  // wr:5h+0, rd:0; simd8_write off=36 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 57 82 0a 0a |         send.urb (8)              null    r14            0x00000000  0x0A0A8257  // wr:5h+0, rd:0; simd8_write off=37 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 67 82 0a 0a |         send.urb (8)              null    r15            0x00000000  0x0A0A8267  // wr:5h+0, rd:0; simd8_write off=38 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 77 82 0a 0a |         send.urb (8)              null    r16            0x00000000  0x0A0A8277  // wr:5h+0, rd:0; simd8_write off=39 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 87 82 0a 0a |         send.urb (8)              null    r17            0x00000000  0x0A0A8287  // wr:5h+0, rd:0; simd8_write off=40 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 97 82 0a 0a |         send.urb (8)              null    r18            0x00000000  0x0A0A8297  // wr:5h+0, rd:0; simd8_write off=41 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 a7 82 0a 0a |         send.urb (8)              null    r19            0x00000000  0x0A0A82A7  // wr:5h+0, rd:0; simd8_write off=42 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 b7 82 0a 0a |         send.urb (8)              null    r20            0x00000000  0x0A0A82B7  // wr:5h+0, rd:0; simd8_write off=43 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 c7 82 0a 0a |         send.urb (8)              null    r21            0x00000000  0x0A0A82C7  // wr:5h+0, rd:0; simd8_write off=44 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 d7 82 0a 0a |         send.urb (8)              null    r22            0x00000000  0x0A0A82D7  // wr:5h+0, rd:0; simd8_write off=45 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 e7 82 0a 0a |         send.urb (8)              null    r23            0x00000000  0x0A0A82E7  // wr:5h+0, rd:0; simd8_write off=46 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 f7 82 0a 0a |         send.urb (8)              null    r24            0x00000000  0x0A0A82F7  // wr:5h+0, rd:0; simd8_write off=47 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 07 83 0a 0a |         send.urb (8)              null    r25            0x00000000  0x0A0A8307  // wr:5h+0, rd:0; simd8_write off=48 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 17 83 0a 0a |         send.urb (8)              null    r26            0x00000000  0x0A0A8317  // wr:5h+0, rd:0; simd8_write off=49 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 27 83 0a 0a |         send.urb (8)              null    r27            0x00000000  0x0A0A8327  // wr:5h+0, rd:0; simd8_write off=50 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 37 83 0a 0a |         send.urb (8)              null    r28            0x00000000  0x0A0A8337  // wr:5h+0, rd:0; simd8_write off=51 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 47 83 0a 0a |         send.urb (8)              null    r29            0x00000000  0x0A0A8347  // wr:5h+0, rd:0; simd8_write off=52 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 57 83 0a 0a |         send.urb (8)              null    r30            0x00000000  0x0A0A8357  // wr:5h+0, rd:0; simd8_write off=53 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 67 83 0a 0a |         send.urb (8)              null    r31            0x00000000  0x0A0A8367  // wr:5h+0, rd:0; simd8_write off=54 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 77 83 0a 0a |         send.urb (8)              null    r32            0x00000000  0x0A0A8377  // wr:5h+0, rd:0; simd8_write off=55 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 87 83 0a 0a |         send.urb (8)              null    r33            0x00000000  0x0A0A8387  // wr:5h+0, rd:0; simd8_write off=56 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 97 83 0a 0a |         send.urb (8)              null    r34            0x00000000  0x0A0A8397  // wr:5h+0, rd:0; simd8_write off=57 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 a7 83 0a 0a |         send.urb (8)              null    r35            0x00000000  0x0A0A83A7  // wr:5h+0, rd:0; simd8_write off=58 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 b7 83 0a 0a |         send.urb (8)              null    r36            0x00000000  0x0A0A83B7  // wr:5h+0, rd:0; simd8_write off=59 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 c7 83 0a 0a |         send.urb (8)              null    r37            0x00000000  0x0A0A83C7  // wr:5h+0, rd:0; simd8_write off=60 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 d7 83 0a 0a |         send.urb (8)              null    r38            0x00000000  0x0A0A83D7  // wr:5h+0, rd:0; simd8_write off=61 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 e7 83 0a 0a |         send.urb (8)              null    r39            0x00000000  0x0A0A83E7  // wr:5h+0, rd:0; simd8_write off=62 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 f7 83 0a 0a |         send.urb (8)              null    r40            0x00000000  0x0A0A83F7  // wr:5h+0, rd:0; simd8_write off=63 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 27 80 08 08 |         send.urb (8)              null    r11            0x00000000  0x08088027  // wr:4h+0, rd:0; simd8_write off=2 masked (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 37 80 08 08 |         send.urb (8)              null    r12            0x00000000  0x08088037  // wr:4h+0, rd:0; simd8_write off=3 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 47 80 08 08 |         send.urb (8)              null    r13            0x00000000  0x08088047  // wr:4h+0, rd:0; simd8_write off=4 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 57 80 08 08 |         send.urb (8)              null    r14            0x00000000  0x08088057  // wr:4h+0, rd:0; simd8_write off=5 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 67 80 08 08 |         send.urb (8)              null    r15            0x00000000  0x08088067  // wr:4h+0, rd:0; simd8_write off=6 masked (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 77 80 08 08 |         send.urb (8)              null    r16            0x00000000  0x08088077  // wr:4h+0, rd:0; simd8_write off=7 masked (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 87 80 08 08 |         send.urb (8)              null    r17            0x00000000  0x08088087  // wr:4h+0, rd:0; simd8_write off=8 masked (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 97 80 08 08 |         send.urb (8)              null    r18            0x00000000  0x08088097  // wr:4h+0, rd:0; simd8_write off=9 masked (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 a7 80 08 08 |         send.urb (8)              null    r19            0x00000000  0x080880A7  // wr:4h+0, rd:0; simd8_write off=10 masked (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 b7 80 08 08 |         send.urb (8)              null    r20            0x00000000  0x080880B7  // wr:4h+0, rd:0; simd8_write off=11 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 c7 80 08 08 |         send.urb (8)              null    r21            0x00000000  0x080880C7  // wr:4h+0, rd:0; simd8_write off=12 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 d7 80 08 08 |         send.urb (8)              null    r22            0x00000000  0x080880D7  // wr:4h+0, rd:0; simd8_write off=13 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 e7 80 08 08 |         send.urb (8)              null    r23            0x00000000  0x080880E7  // wr:4h+0, rd:0; simd8_write off=14 masked (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 f7 80 08 08 |         send.urb (8)              null    r24            0x00000000  0x080880F7  // wr:4h+0, rd:0; simd8_write off=15 masked (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 07 81 08 08 |         send.urb (8)              null    r25            0x00000000  0x08088107  // wr:4h+0, rd:0; simd8_write off=16 masked (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 17 81 08 08 |         send.urb (8)              null    r26            0x00000000  0x08088117  // wr:4h+0, rd:0; simd8_write off=17 masked (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 27 81 08 08 |         send.urb (8)              null    r27            0x00000000  0x08088127  // wr:4h+0, rd:0; simd8_write off=18 masked (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 37 81 08 08 |         send.urb (8)              null    r28            0x00000000  0x08088137  // wr:4h+0, rd:0; simd8_write off=19 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 47 81 08 08 |         send.urb (8)              null    r29            0x00000000  0x08088147  // wr:4h+0, rd:0; simd8_write off=20 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 57 81 08 08 |         send.urb (8)              null    r30            0x00000000  0x08088157  // wr:4h+0, rd:0; simd8_write off=21 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 67 81 08 08 |         send.urb (8)              null    r31            0x00000000  0x08088167  // wr:4h+0, rd:0; simd8_write off=22 masked (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 77 81 08 08 |         send.urb (8)              null    r32            0x00000000  0x08088177  // wr:4h+0, rd:0; simd8_write off=23 masked (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 87 81 08 08 |         send.urb (8)              null    r33            0x00000000  0x08088187  // wr:4h+0, rd:0; simd8_write off=24 masked (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 97 81 08 08 |         send.urb (8)              null    r34            0x00000000  0x08088197  // wr:4h+0, rd:0; simd8_write off=25 masked (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 a7 81 08 08 |         send.urb (8)              null    r35            0x00000000  0x080881A7  // wr:4h+0, rd:0; simd8_write off=26 masked (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 b7 81 08 08 |         send.urb (8)              null    r36            0x00000000  0x080881B7  // wr:4h+0, rd:0; simd8_write off=27 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 c7 81 08 08 |         send.urb (8)              null    r37            0x00000000  0x080881C7  // wr:4h+0, rd:0; simd8_write off=28 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 d7 81 08 08 |         send.urb (8)              null    r38            0x00000000  0x080881D7  // wr:4h+0, rd:0; simd8_write off=29 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 e7 81 08 08 |         send.urb (8)              null    r39            0x00000000  0x080881E7  // wr:4h+0, rd:0; simd8_write off=30 masked (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 f7 81 08 08 |         send.urb (8)              null    r40            0x00000000  0x080881F7  // wr:4h+0, rd:0; simd8_write off=31 masked (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 18 00 48 02 |         send.urb (8)              r13     r1             0x00000000  0x02480018  // wr:1h+0, rd:4; simd8_read off=1 (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 07 02 0a 0c |         send.urb (8)              null    r11            0x00000000  0x0C0A0207  // wr:6h+0, rd:0; simd8_write off=32 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 57 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080057   {EOT}  // wr:9h+0, rd:0; simd8_write off=5 (8)
skl | 31 00 60 02 08 02 40 01 40 02 00 06 00 80 4a 08 |         send.smpl (8)             r10     r18            0x00000000  0x084A8000  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 90 22 04 |         send.smpl (8)             r124    r2             0x00000000  0x04229001  // wr:2+0, rd:2; lod:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 40 00 00 06 01 90 44 08 |         send.smpl (16)            r120    r2             0x00000000  0x08449001  // wr:4+0, rd:4; lod:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 04 80 05 00 06 01 a0 65 08 |         send.smpl (16)            r32     r44            0x00000000  0x0865A001  // wr:4+0, rd:6; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 00 80 0c 00 02 00 00 a0 00 00 06 02 85 00 04 |         send.hdc1 (16)            null    r5             0x00000000  0x04008502  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(2)
skl | 31 00 60 02 08 02 a0 00 60 00 00 06 01 70 42 02 |         send.smpl (8)             r5      r3             0x00000000  0x02427001  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 01 a0 00 00 06 01 70 84 04 |         send.smpl (16)            r8      r5             0x00000000  0x04847001  // wr:2+0, rd:8; ld:u,v,lod,r (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 07 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080007   {EOT}  // wr:9h+0, rd:0; simd8_write (8)
skl | 31 00 60 06 00 02 00 00 c0 0f 00 06 17 00 08 84 |         send.urb (8)              null    r126           0x00000000  0x04080017   {EOT}  // wr:2h+0, rd:0; simd8_write off=1 (8)
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 01 10 4b 0a |         send.smpl (8)             r2      r13            0x00000000  0x0A4B1001  // wr:5h+0, rd:4; gather4_po (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 02 e0 00 00 06 01 10 8d 12 |         send.smpl (16)            r16     r7             0x00000000  0x128D1001  // wr:9h+0, rd:8; gather4_po (16) bti(1) using sampler index 0
skl | 31 00 60 06 08 02 c0 04 20 00 00 06 28 00 18 02 |         send.urb (8)              r38     r1             0x00000000  0x02180028  // wr:1h+0, rd:1; simd8_read off=2 (8)
skl | 31 00 60 06 08 02 00 05 20 00 00 06 38 00 18 02 |         send.urb (8)              r40     r1             0x00000000  0x02180038  // wr:1h+0, rd:1; simd8_read off=3 (8)
skl | 31 00 60 06 08 02 40 05 20 00 00 06 48 00 18 02 |         send.urb (8)              r42     r1             0x00000000  0x02180048  // wr:1h+0, rd:1; simd8_read off=4 (8)
skl | 31 00 60 06 08 02 80 05 20 00 00 06 58 00 18 02 |         send.urb (8)              r44     r1             0x00000000  0x02180058  // wr:1h+0, rd:1; simd8_read off=5 (8)
skl | 31 00 60 06 08 02 c0 05 20 00 00 06 68 00 18 02 |         send.urb (8)              r46     r1             0x00000000  0x02180068  // wr:1h+0, rd:1; simd8_read off=6 (8)
skl | 31 00 60 06 08 02 00 06 20 00 00 06 78 00 18 02 |         send.urb (8)              r48     r1             0x00000000  0x02180078  // wr:1h+0, rd:1; simd8_read off=7 (8)
skl | 31 00 60 06 08 02 40 06 20 00 00 06 88 00 18 02 |         send.urb (8)              r50     r1             0x00000000  0x02180088  // wr:1h+0, rd:1; simd8_read off=8 (8)
skl | 31 00 60 06 08 02 80 06 20 00 00 06 98 00 18 02 |         send.urb (8)              r52     r1             0x00000000  0x02180098  // wr:1h+0, rd:1; simd8_read off=9 (8)
skl | 31 00 60 06 08 02 c0 06 20 00 00 06 a8 00 18 02 |         send.urb (8)              r54     r1             0x00000000  0x021800A8  // wr:1h+0, rd:1; simd8_read off=10 (8)
skl | 31 00 60 06 08 02 00 07 20 00 00 06 b8 00 18 02 |         send.urb (8)              r56     r1             0x00000000  0x021800B8  // wr:1h+0, rd:1; simd8_read off=11 (8)
skl | 31 00 60 06 08 02 40 07 20 00 00 06 c8 00 18 02 |         send.urb (8)              r58     r1             0x00000000  0x021800C8  // wr:1h+0, rd:1; simd8_read off=12 (8)
skl | 31 00 60 06 08 02 80 07 20 00 00 06 d8 00 18 02 |         send.urb (8)              r60     r1             0x00000000  0x021800D8  // wr:1h+0, rd:1; simd8_read off=13 (8)
skl | 31 00 60 06 08 02 c0 07 20 00 00 06 e8 00 18 02 |         send.urb (8)              r62     r1             0x00000000  0x021800E8  // wr:1h+0, rd:1; simd8_read off=14 (8)
skl | 31 00 60 06 08 02 00 08 20 00 00 06 f8 00 18 02 |         send.urb (8)              r64     r1             0x00000000  0x021800F8  // wr:1h+0, rd:1; simd8_read off=15 (8)
skl | 31 00 60 06 08 02 40 08 20 00 00 06 08 01 18 02 |         send.urb (8)              r66     r1             0x00000000  0x02180108  // wr:1h+0, rd:1; simd8_read off=16 (8)
skl | 31 00 60 06 08 02 80 08 20 00 00 06 18 01 18 02 |         send.urb (8)              r68     r1             0x00000000  0x02180118  // wr:1h+0, rd:1; simd8_read off=17 (8)
skl | 31 00 60 06 08 02 c0 08 20 00 00 06 28 01 18 02 |         send.urb (8)              r70     r1             0x00000000  0x02180128  // wr:1h+0, rd:1; simd8_read off=18 (8)
skl | 31 00 60 06 08 02 00 09 20 00 00 06 38 01 18 02 |         send.urb (8)              r72     r1             0x00000000  0x02180138  // wr:1h+0, rd:1; simd8_read off=19 (8)
skl | 31 00 60 06 08 02 40 09 20 00 00 06 48 01 18 02 |         send.urb (8)              r74     r1             0x00000000  0x02180148  // wr:1h+0, rd:1; simd8_read off=20 (8)
skl | 31 00 60 06 08 02 80 09 20 00 00 06 58 01 18 02 |         send.urb (8)              r76     r1             0x00000000  0x02180158  // wr:1h+0, rd:1; simd8_read off=21 (8)
skl | 31 00 60 06 08 02 c0 09 20 00 00 06 68 01 18 02 |         send.urb (8)              r78     r1             0x00000000  0x02180168  // wr:1h+0, rd:1; simd8_read off=22 (8)
skl | 31 00 60 06 08 02 00 0a 20 00 00 06 78 01 18 02 |         send.urb (8)              r80     r1             0x00000000  0x02180178  // wr:1h+0, rd:1; simd8_read off=23 (8)
skl | 31 00 60 06 08 02 40 0a 20 00 00 06 88 01 18 02 |         send.urb (8)              r82     r1             0x00000000  0x02180188  // wr:1h+0, rd:1; simd8_read off=24 (8)
skl | 31 00 60 06 08 02 80 0a 20 00 00 06 98 01 18 02 |         send.urb (8)              r84     r1             0x00000000  0x02180198  // wr:1h+0, rd:1; simd8_read off=25 (8)
skl | 31 00 60 06 08 02 c0 0a 20 00 00 06 a8 01 18 02 |         send.urb (8)              r86     r1             0x00000000  0x021801A8  // wr:1h+0, rd:1; simd8_read off=26 (8)
skl | 31 00 60 06 08 02 00 0b 20 00 00 06 b8 01 18 02 |         send.urb (8)              r88     r1             0x00000000  0x021801B8  // wr:1h+0, rd:1; simd8_read off=27 (8)
skl | 31 00 60 06 08 02 40 0b 20 00 00 06 c8 01 18 02 |         send.urb (8)              r90     r1             0x00000000  0x021801C8  // wr:1h+0, rd:1; simd8_read off=28 (8)
skl | 31 00 60 06 08 02 80 0b 20 00 00 06 d8 01 18 02 |         send.urb (8)              r92     r1             0x00000000  0x021801D8  // wr:1h+0, rd:1; simd8_read off=29 (8)
skl | 31 00 60 06 08 02 c0 0b 20 00 00 06 e8 01 18 02 |         send.urb (8)              r94     r1             0x00000000  0x021801E8  // wr:1h+0, rd:1; simd8_read off=30 (8)
skl | 31 00 60 06 08 02 00 0c 20 00 00 06 f8 01 18 02 |         send.urb (8)              r96     r1             0x00000000  0x021801F8  // wr:1h+0, rd:1; simd8_read off=31 (8)
skl | 31 00 60 06 08 02 40 0c 20 00 00 06 08 02 18 02 |         send.urb (8)              r98     r1             0x00000000  0x02180208  // wr:1h+0, rd:1; simd8_read off=32 (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 27 00 0a 0c |         send.urb (8)              null    r12            0x00000000  0x0C0A0027  // wr:6h+0, rd:0; simd8_write off=2 per_slot (8)
skl | 31 00 60 0a 00 02 00 00 c0 0f 00 06 fd 02 0a 04 |         send.hdc0 (8)             null    r126           0x00000000  0x040A02FD  // wr:2h+0, rd:0; oword_block_write:owords2 (8) bti(253)
skl | 31 00 60 0a 0c 02 60 0e 60 0e 00 06 fd 02 18 02 | (W)     send.hdc0 (8)             r115    r115           0x00000000  0x021802FD  // wr:1h+0, rd:1; oword_block_read:owords2 (8) bti(253)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 57 00 08 12 |         send.urb (8)              null    r25            0x00000000  0x12080057  // wr:9h+0, rd:0; simd8_write off=5 (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 77 00 08 12 |         send.urb (8)              null    r34            0x00000000  0x12080077  // wr:9h+0, rd:0; simd8_write off=7 (8)
skl | 31 00 60 06 00 02 00 00 60 05 00 06 97 00 08 12 |         send.urb (8)              null    r43            0x00000000  0x12080097  // wr:9h+0, rd:0; simd8_write off=9 (8)
skl | 31 00 60 06 00 02 00 00 80 06 00 06 b7 00 08 12 |         send.urb (8)              null    r52            0x00000000  0x120800B7  // wr:9h+0, rd:0; simd8_write off=11 (8)
skl | 31 00 60 06 00 02 00 00 a0 07 00 06 d7 00 08 12 |         send.urb (8)              null    r61            0x00000000  0x120800D7  // wr:9h+0, rd:0; simd8_write off=13 (8)
skl | 31 00 60 06 00 02 00 00 c0 08 00 06 f7 00 08 12 |         send.urb (8)              null    r70            0x00000000  0x120800F7  // wr:9h+0, rd:0; simd8_write off=15 (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 17 01 08 12 |         send.urb (8)              null    r2             0x00000000  0x12080117  // wr:9h+0, rd:0; simd8_write off=17 (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 37 01 08 12 |         send.urb (8)              null    r2             0x00000000  0x12080137  // wr:9h+0, rd:0; simd8_write off=19 (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 57 01 08 12 |         send.urb (8)              null    r2             0x00000000  0x12080157  // wr:9h+0, rd:0; simd8_write off=21 (8)
skl | 31 00 60 06 00 02 00 00 e0 09 00 06 77 01 08 12 |         send.urb (8)              null    r79            0x00000000  0x12080177  // wr:9h+0, rd:0; simd8_write off=23 (8)
skl | 31 00 60 06 00 02 00 00 00 0b 00 06 97 01 08 12 |         send.urb (8)              null    r88            0x00000000  0x12080197  // wr:9h+0, rd:0; simd8_write off=25 (8)
skl | 31 00 60 06 00 02 00 00 20 0c 00 06 b7 01 08 12 |         send.urb (8)              null    r97            0x00000000  0x120801B7  // wr:9h+0, rd:0; simd8_write off=27 (8)
skl | 31 00 60 06 00 02 00 00 40 0d 00 06 d7 01 08 12 |         send.urb (8)              null    r106           0x00000000  0x120801D7  // wr:9h+0, rd:0; simd8_write off=29 (8)
skl | 31 00 60 06 00 02 00 00 a0 0e 00 06 f7 01 08 92 |         send.urb (8)              null    r117           0x00000000  0x120801F7   {EOT}  // wr:9h+0, rd:0; simd8_write off=31 (8)
skl | 31 00 60 02 08 02 80 0f 60 01 00 06 01 90 22 02 |         send.smpl (8)             r124    r11            0x00000000  0x02229001  // wr:1+0, rd:2; lod:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 60 01 00 06 01 90 44 04 |         send.smpl (16)            r120    r11            0x00000000  0x04449001  // wr:2+0, rd:4; lod:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 60 00 00 06 00 70 42 08 |         send.smpl (8)             r124    r3             0x00000000  0x08427000  // wr:4+0, rd:4; ld:u,v,lod,r (8) bti(0) using sampler index 0
skl | 31 00 80 0c 00 02 00 00 00 05 00 06 01 85 00 04 |         send.hdc1 (16)            null    r40            0x00000000  0x04008501  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(1)
skl | 31 00 60 06 00 02 00 00 e0 0f 00 06 07 00 08 82 |         send.urb (8)              null    r127           0x00000000  0x02080007   {EOT}  // wr:1h+0, rd:0; simd8_write (8)
skl | 31 00 60 02 08 02 80 0f 20 01 00 06 00 80 4a 0a |         send.smpl (8)             r124    r9             0x00000000  0x0A4A8000  // wr:5h+0, rd:4; gather4:u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 e0 02 00 06 01 a0 33 06 |         send.smpl (8)             r2      r23            0x00000000  0x0633A001  // wr:3+0, rd:3; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 00 80 01 00 06 01 a0 65 0c |         send.smpl (16)            r4      r12            0x00000000  0x0C65A001  // wr:6+0, rd:6; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 10 60 02 08 02 40 00 00 02 00 06 01 40 43 0e |         send.smpl (8|M8)          r2      r16            0x00000000  0x0E434001  // wr:7+0, rd:4; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 61 0c 02 02 00 00 80 00 00 06 01 95 00 02 | (f1.0)  send.hdc1 (8)             null    r4             0x00000000  0x02009501  // wr:1+0, rd:0; untyped_atomic_inc simd8 (8) bti(1)
skl | 31 00 60 02 08 02 c0 00 20 01 00 06 01 40 43 08 |         send.smpl (8)             r6      r9             0x00000000  0x08434001  // wr:4+0, rd:4; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 c0 0c 00 06 f7 01 08 12 |         send.urb (8)              null    r102           0x00000000  0x120801F7  // wr:9h+0, rd:0; simd8_write off=31 (8)
skl | 31 00 60 06 00 02 00 00 20 0f 00 06 17 02 08 8a |         send.urb (8)              null    r121           0x00000000  0x0A080217   {EOT}  // wr:5h+0, rd:0; simd8_write off=33 (8)
skl | 31 00 80 03 04 02 00 00 60 00 00 06 04 80 00 02 | (W)     send.gtwy (16)            null    r3             0x00000000  0x02008004  // wr:1+0, rd:0; ?
skl | 31 00 80 0c 08 02 60 00 c0 01 00 06 fe 5e 20 04 |         send.hdc1 (16)            r3      r14            0x00000000  0x04205EFE  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(254)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 27 00 0a 14 |         send.urb (8)              null    r30            0x00000000  0x140A0027  // wr:10h+0, rd:0; simd8_write off=2 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 47 00 0a 0c |         send.urb (8)              null    r40            0x00000000  0x0C0A0047  // wr:6h+0, rd:0; simd8_write off=4 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0f 00 06 07 00 08 84 |         send.urb (8)              null    r126           0x00000000  0x04080007   {EOT}  // wr:2h+0, rd:0; simd8_write (8)
skl | 31 00 60 0c 08 02 a0 00 60 01 00 06 01 50 41 04 |         send.hdc1 (8)             r5      r11            0x00000000  0x04415001  // wr:2+0, rd:4; typed_read:xyzw simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 40 00 60 00 00 06 01 60 41 04 |         send.hdc1 (8|M8)          r2      r3             0x00000000  0x04416001  // wr:2+0, rd:4; typed_read:xyzw simd8 (8) bti(1)
skl | 31 00 60 06 08 02 a0 01 60 00 00 06 38 00 48 02 |         send.urb (8)              r13     r3             0x00000000  0x02480038  // wr:1h+0, rd:4; simd8_read off=3 (8)
skl | 31 00 60 06 00 02 00 00 e0 00 00 06 37 00 0a 14 |         send.urb (8)              null    r7             0x00000000  0x140A0037  // wr:10h+0, rd:0; simd8_write off=3 per_slot (8)
skl | 31 00 60 06 08 02 e0 01 40 00 00 06 38 00 28 02 |         send.urb (8)              r15     r2             0x00000000  0x02280038  // wr:1h+0, rd:2; simd8_read off=3 (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 37 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080037   {EOT}  // wr:9h+0, rd:0; simd8_write off=3 (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 07 00 0a 14 |         send.urb (8)              null    r8             0x00000000  0x140A0007  // wr:10h+0, rd:0; simd8_write per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 07 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0007   {EOT}  // wr:10h+0, rd:0; simd8_write per_slot (8)
skl | 31 00 60 02 08 02 80 0f 80 21 00 00 00 02 00 00 |         send.smpl (8)             r124    r12            0x00000000  a0.0
skl | 31 00 60 06 08 02 40 01 40 00 00 06 48 00 48 02 |         send.urb (8)              r10     r2             0x00000000  0x02480048  // wr:1h+0, rd:4; simd8_read off=4 (8)
skl | 31 00 60 06 08 02 c0 00 40 00 00 06 88 00 48 02 |         send.urb (8)              r6      r2             0x00000000  0x02480088  // wr:1h+0, rd:4; simd8_read off=8 (8)
skl | 31 00 60 06 08 02 c0 01 40 00 00 06 58 00 48 02 |         send.urb (8)              r14     r2             0x00000000  0x02480058  // wr:1h+0, rd:4; simd8_read off=5 (8)
skl | 31 00 60 06 08 02 60 01 40 00 00 06 a8 00 48 02 |         send.urb (8)              r11     r2             0x00000000  0x024800A8  // wr:1h+0, rd:4; simd8_read off=10 (8)
skl | 31 00 60 06 08 02 40 02 40 00 00 06 68 00 48 02 |         send.urb (8)              r18     r2             0x00000000  0x02480068  // wr:1h+0, rd:4; simd8_read off=6 (8)
skl | 31 00 60 06 08 02 00 02 40 00 00 06 c8 00 38 02 |         send.urb (8)              r16     r2             0x00000000  0x023800C8  // wr:1h+0, rd:3; simd8_read off=12 (8)
skl | 31 00 60 06 08 02 c0 02 40 00 00 06 78 00 48 02 |         send.urb (8)              r22     r2             0x00000000  0x02480078  // wr:1h+0, rd:4; simd8_read off=7 (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 b8 00 48 02 |         send.urb (8)              r12     r2             0x00000000  0x024800B8  // wr:1h+0, rd:4; simd8_read off=11 (8)
skl | 31 00 60 06 08 02 e0 00 40 00 00 06 98 00 48 02 |         send.urb (8)              r7      r2             0x00000000  0x02480098  // wr:1h+0, rd:4; simd8_read off=9 (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 b7 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x120800B7   {EOT}  // wr:9h+0, rd:0; simd8_write off=11 (8)
skl | 31 00 60 02 08 02 c0 00 00 01 00 06 00 00 4b 08 |         send.smpl (8)             r6      r8             0x00000000  0x084B0000  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 0b 08 02 e0 00 00 00 00 06 08 00 20 02 |         send.pi (8)               r7      r0             0x00000000  0x02200008  // wr:1+0, rd:2; per_message_offset persp data=0x08 (8)
skl | 31 00 80 0b 08 02 20 01 00 00 00 06 08 00 41 02 |         send.pi (16)              r9      r0             0x00000000  0x02410008  // wr:1+0, rd:4; per_message_offset persp data=0x08 (16)
skl | 31 00 60 02 08 02 40 00 60 01 00 06 01 d0 43 04 |         send.smpl (8)             r2      r11            0x00000000  0x0443D001  // wr:2+0, rd:4; ld_mcs:u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 20 01 00 06 01 e0 43 08 |         send.smpl (8)             r2      r9             0x00000000  0x0843E001  // wr:4+0, rd:4; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 e0 01 00 06 01 d0 85 08 |         send.smpl (16)            r2      r15            0x00000000  0x0885D001  // wr:4+0, rd:8; ld_mcs:u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 05 60 01 00 06 01 e0 85 10 |         send.smpl (16)            r43     r11            0x00000000  0x1085E001  // wr:8+0, rd:8; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 c0 00 00 06 00 10 4b 0a |         send.smpl (8)             r2      r6             0x00000000  0x0A4B1000  // wr:5h+0, rd:4; gather4_po (8) bti(0) using sampler index 0
skl | 31 00 60 06 08 02 40 09 40 00 00 06 28 00 28 02 |         send.urb (8)              r74     r2             0x00000000  0x02280028  // wr:1h+0, rd:2; simd8_read off=2 (8)
skl | 31 00 60 06 08 02 e0 00 40 00 00 06 28 00 38 02 |         send.urb (8)              r7      r2             0x00000000  0x02380028  // wr:1h+0, rd:3; simd8_read off=2 (8)
skl | 31 00 60 06 08 02 e0 01 40 00 00 06 38 00 38 02 |         send.urb (8)              r15     r2             0x00000000  0x02380038  // wr:1h+0, rd:3; simd8_read off=3 (8)
skl | 31 00 60 02 08 02 80 0f 60 00 00 06 00 e0 43 08 |         send.smpl (8)             r124    r3             0x00000000  0x0843E000  // wr:4+0, rd:4; ld2dms:si,mcs,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 60 00 00 06 00 d0 43 04 |         send.smpl (8)             r2      r3             0x00000000  0x0443D000  // wr:2+0, rd:4; ld_mcs:u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 60 02 00 06 01 80 4a 0a |         send.smpl (8)             r2      r19            0x00000000  0x0A4A8001  // wr:5h+0, rd:4; gather4:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 00 02 00 06 01 80 8c 12 |         send.smpl (16)            r7      r16            0x00000000  0x128C8001  // wr:9h+0, rd:8; gather4:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 40 00 00 06 57 00 0a 0c |         send.urb (8)              null    r2             0x00000000  0x0C0A0057  // wr:6h+0, rd:0; simd8_write off=5 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 01 00 06 27 00 08 04 |         send.urb (8)              null    r9             0x00000000  0x04080027  // wr:2h+0, rd:0; simd8_write off=2 (8)
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 40 13 08 |         send.smpl (8)             r6      r7             0x00000000  0x08134001  // wr:4+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 60 01 00 06 02 41 13 08 |         send.smpl (8)             r7      r11            0x00000000  0x08134102  // wr:4+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 a0 01 20 02 00 06 00 b0 1a 02 |         send.smpl (8)             r13     r17            0x00000000  0x021AB000  // wr:1h+0, rd:1; sampleinfo (8) bti(0) using sampler index 0
skl | 31 00 60 06 00 02 00 00 40 06 00 06 57 00 0a 14 |         send.urb (8)              null    r50            0x00000000  0x140A0057  // wr:10h+0, rd:0; simd8_write off=5 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 07 00 06 77 00 0a 14 |         send.urb (8)              null    r60            0x00000000  0x140A0077  // wr:10h+0, rd:0; simd8_write off=7 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 08 00 06 97 00 0a 0c |         send.urb (8)              null    r70            0x00000000  0x0C0A0097  // wr:6h+0, rd:0; simd8_write off=9 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 97 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A0097   {EOT}  // wr:6h+0, rd:0; simd8_write off=9 per_slot (8)
skl | 31 00 60 02 08 02 80 0f c0 00 00 06 00 00 4b 0a |         send.smpl (8)             r124    r6             0x00000000  0x0A4B0000  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 a0 00 c0 00 00 06 01 30 1a 06 |         send.smpl (8)             r5      r6             0x00000000  0x061A3001  // wr:3h+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 20 01 00 06 02 31 1a 06 |         send.smpl (8)             r6      r9             0x00000000  0x061A3102  // wr:3h+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 20 01 60 01 00 06 01 30 2c 0a |         send.smpl (16)            r9      r11            0x00000000  0x0A2C3001  // wr:5h+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 01 40 00 00 06 02 31 2c 0a |         send.smpl (16)            r11     r2             0x00000000  0x0A2C3102  // wr:5h+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 77 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080077   {EOT}  // wr:5h+0, rd:0; simd8_write off=7 (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 67 00 0a 0c |         send.urb (8)              null    r30            0x00000000  0x0C0A0067  // wr:6h+0, rd:0; simd8_write off=6 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 77 00 0a 0c |         send.urb (8)              null    r36            0x00000000  0x0C0A0077  // wr:6h+0, rd:0; simd8_write off=7 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 05 00 06 87 00 0a 0c |         send.urb (8)              null    r42            0x00000000  0x0C0A0087  // wr:6h+0, rd:0; simd8_write off=8 per_slot (8)
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 02 01 42 06 |         send.smpl (8)             r6      r6             0x00000000  0x06420102  // wr:3+0, rd:4; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 40 02 00 06 02 01 84 0c |         send.smpl (16)            r10     r18            0x00000000  0x0C840102  // wr:6+0, rd:8; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 40 00 00 06 02 01 42 04 |         send.smpl (8)             r2      r2             0x00000000  0x04420102  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 04 03 42 06 |         send.smpl (8)             r6      r6             0x00000000  0x06420304  // wr:3+0, rd:4; sample:u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 00 40 01 00 06 02 01 84 08 |         send.smpl (16)            r2      r10            0x00000000  0x08840102  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 40 02 00 06 04 03 84 0c |         send.smpl (16)            r10     r18            0x00000000  0x0C840304  // wr:6+0, rd:8; sample:u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 40 00 40 00 00 06 04 03 42 04 |         send.smpl (8)             r2      r2             0x00000000  0x04420304  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 08 07 42 06 |         send.smpl (8)             r6      r6             0x00000000  0x06420708  // wr:3+0, rd:4; sample:u,v,r,ai (8) bti(8) using sampler index 7
skl | 31 00 80 02 08 02 40 00 40 01 00 06 04 03 84 08 |         send.smpl (16)            r2      r10            0x00000000  0x08840304  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 01 40 02 00 06 08 07 84 0c |         send.smpl (16)            r10     r18            0x00000000  0x0C840708  // wr:6+0, rd:8; sample:u,v,r,ai (16) bti(8) using sampler index 7
skl | 31 00 60 02 08 02 60 00 60 01 00 06 01 c0 43 0a |         send.smpl (8)             r3      r11            0x00000000  0x0A43C001  // wr:5+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 02 a0 00 00 06 01 c0 85 14 |         send.smpl (16)            r16     r5             0x00000000  0x1485C001  // wr:10+0, rd:8; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 80 09 0c 02 80 00 a0 01 00 06 01 03 28 02 | (W)     send.hdc_ro (16)          r4      r13            0x00000000  0x02280301  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(1)
skl | 31 00 60 02 08 02 40 00 40 00 00 06 01 a0 43 04 |         send.smpl (8)             r2      r2             0x00000000  0x0443A001  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 40 01 00 06 01 a0 85 08 |         send.smpl (16)            r2      r10            0x00000000  0x0885A001  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 01 80 01 00 06 01 50 12 06 |         send.smpl (8)             r12     r12            0x00000000  0x06125001  // wr:3+0, rd:1; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 01 e0 01 00 06 02 51 12 06 |         send.smpl (8)             r13     r15            0x00000000  0x06125102  // wr:3+0, rd:1; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 80 02 c0 02 00 06 01 50 24 0c |         send.smpl (16)            r20     r22            0x00000000  0x0C245001  // wr:6+0, rd:2; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 02 80 03 00 06 02 51 24 0c |         send.smpl (16)            r22     r28            0x00000000  0x0C245102  // wr:6+0, rd:2; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 c0 04 40 00 00 06 c8 00 48 02 |         send.urb (8)              r38     r2             0x00000000  0x024800C8  // wr:1h+0, rd:4; simd8_read off=12 (8)
skl | 31 00 60 06 08 02 e0 04 40 00 00 06 d8 00 48 02 |         send.urb (8)              r39     r2             0x00000000  0x024800D8  // wr:1h+0, rd:4; simd8_read off=13 (8)
skl | 31 00 60 06 08 02 00 05 40 00 00 06 e8 00 48 02 |         send.urb (8)              r40     r2             0x00000000  0x024800E8  // wr:1h+0, rd:4; simd8_read off=14 (8)
skl | 31 00 60 06 08 02 20 05 40 00 00 06 f8 00 48 02 |         send.urb (8)              r41     r2             0x00000000  0x024800F8  // wr:1h+0, rd:4; simd8_read off=15 (8)
skl | 31 00 60 06 08 02 40 05 40 00 00 06 08 01 48 02 |         send.urb (8)              r42     r2             0x00000000  0x02480108  // wr:1h+0, rd:4; simd8_read off=16 (8)
skl | 31 00 60 06 08 02 60 05 40 00 00 06 18 01 48 02 |         send.urb (8)              r43     r2             0x00000000  0x02480118  // wr:1h+0, rd:4; simd8_read off=17 (8)
skl | 31 00 60 06 08 02 80 05 40 00 00 06 28 01 48 02 |         send.urb (8)              r44     r2             0x00000000  0x02480128  // wr:1h+0, rd:4; simd8_read off=18 (8)
skl | 31 00 60 06 08 02 a0 05 40 00 00 06 38 01 48 02 |         send.urb (8)              r45     r2             0x00000000  0x02480138  // wr:1h+0, rd:4; simd8_read off=19 (8)
skl | 31 00 60 06 08 02 c0 05 40 00 00 06 48 01 48 02 |         send.urb (8)              r46     r2             0x00000000  0x02480148  // wr:1h+0, rd:4; simd8_read off=20 (8)
skl | 31 00 60 06 08 02 e0 05 40 00 00 06 58 01 48 02 |         send.urb (8)              r47     r2             0x00000000  0x02480158  // wr:1h+0, rd:4; simd8_read off=21 (8)
skl | 31 00 60 06 08 02 00 06 40 00 00 06 68 01 48 02 |         send.urb (8)              r48     r2             0x00000000  0x02480168  // wr:1h+0, rd:4; simd8_read off=22 (8)
skl | 31 00 60 06 08 02 20 06 40 00 00 06 78 01 48 02 |         send.urb (8)              r49     r2             0x00000000  0x02480178  // wr:1h+0, rd:4; simd8_read off=23 (8)
skl | 31 00 60 06 08 02 40 06 40 00 00 06 88 01 48 02 |         send.urb (8)              r50     r2             0x00000000  0x02480188  // wr:1h+0, rd:4; simd8_read off=24 (8)
skl | 31 00 60 06 08 02 60 06 40 00 00 06 98 01 48 02 |         send.urb (8)              r51     r2             0x00000000  0x02480198  // wr:1h+0, rd:4; simd8_read off=25 (8)
skl | 31 00 60 06 08 02 80 06 40 00 00 06 a8 01 48 02 |         send.urb (8)              r52     r2             0x00000000  0x024801A8  // wr:1h+0, rd:4; simd8_read off=26 (8)
skl | 31 00 60 06 08 02 a0 06 40 00 00 06 b8 01 48 02 |         send.urb (8)              r53     r2             0x00000000  0x024801B8  // wr:1h+0, rd:4; simd8_read off=27 (8)
skl | 31 00 60 06 08 02 c0 06 40 00 00 06 c8 01 48 02 |         send.urb (8)              r54     r2             0x00000000  0x024801C8  // wr:1h+0, rd:4; simd8_read off=28 (8)
skl | 31 00 60 06 08 02 e0 06 40 00 00 06 d8 01 48 02 |         send.urb (8)              r55     r2             0x00000000  0x024801D8  // wr:1h+0, rd:4; simd8_read off=29 (8)
skl | 31 00 60 06 08 02 00 07 40 00 00 06 e8 01 48 02 |         send.urb (8)              r56     r2             0x00000000  0x024801E8  // wr:1h+0, rd:4; simd8_read off=30 (8)
skl | 31 00 60 06 08 02 20 07 40 00 00 06 f8 01 48 02 |         send.urb (8)              r57     r2             0x00000000  0x024801F8  // wr:1h+0, rd:4; simd8_read off=31 (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 27 80 0a 08 |         send.urb (8)              null    r19            0x00000000  0x080A8027  // wr:4h+0, rd:0; simd8_write off=2 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 27 80 0a 0a |         send.urb (8)              null    r8             0x00000000  0x0A0A8027  // wr:5h+0, rd:0; simd8_write off=2 masked per_slot (8)
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 01 40 42 0e |         send.smpl (8)             r6      r11            0x00000000  0x0E424001  // wr:7+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f e0 00 00 06 00 a0 12 02 |         send.smpl (8)             r124    r7             0x00000000  0x0212A000  // wr:1+0, rd:1; resinfo:lod (8) bti(0) using sampler index 0
skl | 31 00 60 06 08 02 00 01 c0 01 00 06 28 01 4a 04 |         send.urb (8)              r8      r14            0x00000000  0x044A0128  // wr:2h+0, rd:4; simd8_read off=18 per_slot (8)
skl | 31 00 60 06 08 02 c0 02 00 02 00 06 28 00 4a 04 |         send.urb (8)              r22     r16            0x00000000  0x044A0028  // wr:2h+0, rd:4; simd8_read off=2 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 00 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A080017  // wr:5h+0, rd:0; simd8_write off=1 (8)
skl | 31 00 60 06 00 02 00 00 e0 00 00 06 57 00 08 0a |         send.urb (8)              null    r7             0x00000000  0x0A080057  // wr:5h+0, rd:0; simd8_write off=5 (8)
skl | 31 00 60 0c 08 02 80 00 40 00 00 06 01 60 40 02 |         send.hdc1 (8)             r4      r2             0x00000000  0x02406001  // wr:1+0, rd:4; untyped_read:xyzw simd8 (8) bti(1)
skl | 31 00 80 0c 08 02 a0 00 40 00 00 06 01 50 80 04 |         send.hdc1 (16)            r5      r2             0x00000000  0x04805001  // wr:2+0, rd:8; untyped_read:xyzw simd16 (16) bti(1)
skl | 31 00 60 02 08 02 80 0f a0 01 00 06 01 00 4b 08 |         send.smpl (8)             r124    r13            0x00000000  0x084B0001  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f e0 00 00 06 01 00 8d 0e |         send.smpl (16)            r120    r7             0x00000000  0x0E8D0001  // wr:7h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 01 40 01 00 06 01 40 13 0e |         send.smpl (8)             r10     r10            0x00000000  0x0E134001  // wr:7+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 60 01 20 02 00 06 02 41 13 0e |         send.smpl (8)             r11     r17            0x00000000  0x0E134102  // wr:7+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 01 40 01 00 06 02 82 4a 06 |         send.smpl (8)             r14     r10            0x00000000  0x064A8202  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 01 81 4a 08 |         send.smpl (8)             r6      r6             0x00000000  0x084A8101  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(1) using sampler index 1
skl | 31 00 60 02 08 02 a0 00 c0 00 00 06 01 b0 1a 02 |         send.smpl (8)             r5      r6             0x00000000  0x021AB001  // wr:1h+0, rd:1; sampleinfo (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 00 60 00 00 06 01 b0 2c 02 |         send.smpl (16)            r6      r3             0x00000000  0x022CB001  // wr:1h+0, rd:2; sampleinfo (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 37 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A0037   {EOT}  // wr:6h+0, rd:0; simd8_write off=3 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 01 00 06 27 00 08 12 |         send.urb (8)              null    r10            0x00000000  0x12080027  // wr:9h+0, rd:0; simd8_write off=2 (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 47 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080047   {EOT}  // wr:5h+0, rd:0; simd8_write off=4 (8)
skl | 31 00 60 02 08 02 c0 01 40 00 00 06 00 80 43 04 |         send.smpl (8)             r14     r2             0x00000000  0x04438000  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 06 08 02 a0 07 60 0d 00 06 48 00 38 02 |         send.urb (8)              r61     r107           0x00000000  0x02380048  // wr:1h+0, rd:3; simd8_read off=4 (8)
skl | 31 00 60 06 08 02 00 08 20 0e 00 06 58 00 38 02 |         send.urb (8)              r64     r113           0x00000000  0x02380058  // wr:1h+0, rd:3; simd8_read off=5 (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 47 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080047   {EOT}  // wr:9h+0, rd:0; simd8_write off=4 (8)
skl | 31 00 60 0c 08 02 a0 00 80 00 00 06 01 50 41 06 |         send.hdc1 (8)             r5      r4             0x00000000  0x06415001  // wr:3+0, rd:4; typed_read:xyzw simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 40 00 40 01 00 06 01 60 41 06 |         send.hdc1 (8|M8)          r2      r10            0x00000000  0x06416001  // wr:3+0, rd:4; typed_read:xyzw simd8 (8) bti(1)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 77 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080077   {EOT}  // wr:9h+0, rd:0; simd8_write off=7 (8)
skl | 31 00 60 06 08 02 80 01 00 01 00 06 38 00 4a 04 |         send.urb (8)              r12     r8             0x00000000  0x044A0038  // wr:2h+0, rd:4; simd8_read off=3 per_slot (8)
skl | 31 00 60 06 08 02 a0 02 00 01 00 06 48 00 4a 04 |         send.urb (8)              r21     r8             0x00000000  0x044A0048  // wr:2h+0, rd:4; simd8_read off=4 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 a7 00 0a 0c |         send.urb (8)              null    r22            0x00000000  0x0C0A00A7  // wr:6h+0, rd:0; simd8_write off=10 per_slot (8)
skl | 31 00 80 02 08 02 20 00 20 01 00 06 01 80 85 08 |         send.smpl (16)            r1      r9             0x00000000  0x08858001  // wr:4+0, rd:8; sample_lz:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 00 07 00 06 97 00 0a 14 |         send.urb (8)              null    r56            0x00000000  0x140A0097  // wr:10h+0, rd:0; simd8_write off=9 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 09 00 06 b7 00 0a 0c |         send.urb (8)              null    r76            0x00000000  0x0C0A00B7  // wr:6h+0, rd:0; simd8_write off=11 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 b7 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A00B7   {EOT}  // wr:6h+0, rd:0; simd8_write off=11 per_slot (8)
skl | 31 00 60 02 08 02 80 00 60 00 00 06 01 a0 32 02 |         send.smpl (8)             r4      r3             0x00000000  0x0232A001  // wr:1+0, rd:3; resinfo:lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 01 60 00 00 06 01 a0 64 04 |         send.smpl (16)            r8      r3             0x00000000  0x0464A001  // wr:2+0, rd:6; resinfo:lod (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 07 00 08 0a |         send.urb (8)              null    r6             0x00000000  0x0A080007  // wr:5h+0, rd:0; simd8_write (8)
skl | 31 00 60 02 08 02 c0 0f 40 01 00 06 01 30 12 08 |         send.smpl (8)             r126    r10            0x00000000  0x08123001  // wr:4+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 0f 00 01 00 06 01 30 24 10 |         send.smpl (16)            r124    r8             0x00000000  0x10243001  // wr:8+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 01 80 01 00 06 01 60 12 06 |         send.smpl (8)             r12     r12            0x00000000  0x06126001  // wr:3+0, rd:1; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 01 e0 01 00 06 02 61 12 06 |         send.smpl (8)             r13     r15            0x00000000  0x06126102  // wr:3+0, rd:1; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 80 02 c0 02 00 06 01 60 24 0c |         send.smpl (16)            r20     r22            0x00000000  0x0C246001  // wr:6+0, rd:2; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 02 80 03 00 06 02 61 24 0c |         send.smpl (16)            r22     r28            0x00000000  0x0C246102  // wr:6+0, rd:2; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 0b 08 02 80 00 00 00 00 06 00 10 20 02 |         send.pi (8)               r4      r0             0x00000000  0x02201000  // wr:1+0, rd:2; sample_position persp (8)
skl | 31 00 80 0b 08 02 c0 00 00 00 00 06 00 10 41 02 |         send.pi (16)              r6      r0             0x00000000  0x02411000  // wr:1+0, rd:4; sample_position persp (16)
skl | 31 00 60 02 08 02 80 0f 60 02 00 06 01 00 4b 0a |         send.smpl (8)             r124    r19            0x00000000  0x0A4B0001  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f e0 00 00 06 01 00 8d 12 |         send.smpl (16)            r120    r7             0x00000000  0x128D0001  // wr:9h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 e0 01 00 06 01 20 42 06 |         send.smpl (8)             r2      r15            0x00000000  0x06422001  // wr:3+0, rd:4; sample_l (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 01 00 01 00 06 01 20 84 0c |         send.smpl (16)            r14     r8             0x00000000  0x0C842001  // wr:6+0, rd:8; sample_l (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 37 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0037   {EOT}  // wr:10h+0, rd:0; simd8_write off=3 per_slot (8)
skl | 31 00 60 02 08 02 80 00 a0 00 00 06 01 a0 12 02 |         send.smpl (8)             r4      r5             0x00000000  0x0212A001  // wr:1+0, rd:1; resinfo:lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 00 c0 00 00 06 01 a0 24 04 |         send.smpl (16)            r4      r6             0x00000000  0x0424A001  // wr:2+0, rd:2; resinfo:lod (16) bti(1) using sampler index 0
skl | 31 00 60 06 08 02 00 01 e0 01 00 06 38 01 2a 04 |         send.urb (8)              r8      r15            0x00000000  0x042A0138  // wr:2h+0, rd:2; simd8_read off=19 per_slot (8)
skl | 31 00 60 06 08 02 40 01 e0 01 00 06 38 03 2a 04 |         send.urb (8)              r10     r15            0x00000000  0x042A0338  // wr:2h+0, rd:2; simd8_read off=51 per_slot (8)
skl | 31 00 60 06 08 02 80 01 e0 01 00 06 38 05 2a 04 |         send.urb (8)              r12     r15            0x00000000  0x042A0538  // wr:2h+0, rd:2; simd8_read off=83 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 e0 01 00 06 38 07 2a 04 |         send.urb (8)              r14     r15            0x00000000  0x042A0738  // wr:2h+0, rd:2; simd8_read off=115 per_slot (8)
skl | 31 00 60 06 08 02 00 01 e0 01 00 06 38 00 2a 04 |         send.urb (8)              r8      r15            0x00000000  0x042A0038  // wr:2h+0, rd:2; simd8_read off=3 per_slot (8)
skl | 31 00 60 06 08 02 40 01 e0 01 00 06 38 02 2a 04 |         send.urb (8)              r10     r15            0x00000000  0x042A0238  // wr:2h+0, rd:2; simd8_read off=35 per_slot (8)
skl | 31 00 60 06 08 02 80 01 e0 01 00 06 38 04 2a 04 |         send.urb (8)              r12     r15            0x00000000  0x042A0438  // wr:2h+0, rd:2; simd8_read off=67 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 e0 01 00 06 38 06 2a 04 |         send.urb (8)              r14     r15            0x00000000  0x042A0638  // wr:2h+0, rd:2; simd8_read off=99 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 04 00 06 28 02 48 02 |         send.urb (8)              r2      r35            0x00000000  0x02480228  // wr:1h+0, rd:4; simd8_read off=34 (8)
skl | 31 00 60 06 08 02 00 01 60 04 00 06 28 04 48 02 |         send.urb (8)              r8      r35            0x00000000  0x02480428  // wr:1h+0, rd:4; simd8_read off=66 (8)
skl | 31 00 60 06 08 02 80 01 60 04 00 06 28 06 48 02 |         send.urb (8)              r12     r35            0x00000000  0x02480628  // wr:1h+0, rd:4; simd8_read off=98 (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 37 80 0a 0a |         send.urb (8)              null    r6             0x00000000  0x0A0A8037  // wr:5h+0, rd:0; simd8_write off=3 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 47 80 0a 0a |         send.urb (8)              null    r11            0x00000000  0x0A0A8047  // wr:5h+0, rd:0; simd8_write off=4 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 57 80 0a 0a |         send.urb (8)              null    r12            0x00000000  0x0A0A8057  // wr:5h+0, rd:0; simd8_write off=5 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 67 80 0a 0a |         send.urb (8)              null    r13            0x00000000  0x0A0A8067  // wr:5h+0, rd:0; simd8_write off=6 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 77 80 0a 0a |         send.urb (8)              null    r14            0x00000000  0x0A0A8077  // wr:5h+0, rd:0; simd8_write off=7 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 87 80 0a 0a |         send.urb (8)              null    r15            0x00000000  0x0A0A8087  // wr:5h+0, rd:0; simd8_write off=8 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 97 80 0a 0a |         send.urb (8)              null    r16            0x00000000  0x0A0A8097  // wr:5h+0, rd:0; simd8_write off=9 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 a7 80 0a 0a |         send.urb (8)              null    r17            0x00000000  0x0A0A80A7  // wr:5h+0, rd:0; simd8_write off=10 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 b7 80 0a 0a |         send.urb (8)              null    r18            0x00000000  0x0A0A80B7  // wr:5h+0, rd:0; simd8_write off=11 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 c7 80 0a 0a |         send.urb (8)              null    r19            0x00000000  0x0A0A80C7  // wr:5h+0, rd:0; simd8_write off=12 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 d7 80 0a 0a |         send.urb (8)              null    r20            0x00000000  0x0A0A80D7  // wr:5h+0, rd:0; simd8_write off=13 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 e7 80 0a 0a |         send.urb (8)              null    r21            0x00000000  0x0A0A80E7  // wr:5h+0, rd:0; simd8_write off=14 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 f7 80 0a 0a |         send.urb (8)              null    r22            0x00000000  0x0A0A80F7  // wr:5h+0, rd:0; simd8_write off=15 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 07 81 0a 0a |         send.urb (8)              null    r23            0x00000000  0x0A0A8107  // wr:5h+0, rd:0; simd8_write off=16 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 17 81 0a 0a |         send.urb (8)              null    r24            0x00000000  0x0A0A8117  // wr:5h+0, rd:0; simd8_write off=17 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 27 81 0a 0a |         send.urb (8)              null    r25            0x00000000  0x0A0A8127  // wr:5h+0, rd:0; simd8_write off=18 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 37 81 0a 0a |         send.urb (8)              null    r26            0x00000000  0x0A0A8137  // wr:5h+0, rd:0; simd8_write off=19 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 47 81 0a 0a |         send.urb (8)              null    r27            0x00000000  0x0A0A8147  // wr:5h+0, rd:0; simd8_write off=20 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 57 81 0a 0a |         send.urb (8)              null    r28            0x00000000  0x0A0A8157  // wr:5h+0, rd:0; simd8_write off=21 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 67 81 0a 0a |         send.urb (8)              null    r29            0x00000000  0x0A0A8167  // wr:5h+0, rd:0; simd8_write off=22 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 77 81 0a 0a |         send.urb (8)              null    r30            0x00000000  0x0A0A8177  // wr:5h+0, rd:0; simd8_write off=23 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 87 81 0a 0a |         send.urb (8)              null    r31            0x00000000  0x0A0A8187  // wr:5h+0, rd:0; simd8_write off=24 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 97 81 0a 0a |         send.urb (8)              null    r32            0x00000000  0x0A0A8197  // wr:5h+0, rd:0; simd8_write off=25 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 a7 81 0a 0a |         send.urb (8)              null    r33            0x00000000  0x0A0A81A7  // wr:5h+0, rd:0; simd8_write off=26 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 b7 81 0a 0a |         send.urb (8)              null    r34            0x00000000  0x0A0A81B7  // wr:5h+0, rd:0; simd8_write off=27 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 c7 81 0a 0a |         send.urb (8)              null    r35            0x00000000  0x0A0A81C7  // wr:5h+0, rd:0; simd8_write off=28 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 d7 81 0a 0a |         send.urb (8)              null    r36            0x00000000  0x0A0A81D7  // wr:5h+0, rd:0; simd8_write off=29 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 e7 81 0a 0a |         send.urb (8)              null    r37            0x00000000  0x0A0A81E7  // wr:5h+0, rd:0; simd8_write off=30 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 f7 81 0a 0a |         send.urb (8)              null    r38            0x00000000  0x0A0A81F7  // wr:5h+0, rd:0; simd8_write off=31 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 07 82 0a 0a |         send.urb (8)              null    r39            0x00000000  0x0A0A8207  // wr:5h+0, rd:0; simd8_write off=32 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 27 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A0027   {EOT}  // wr:6h+0, rd:0; simd8_write off=2 per_slot (8)
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 40 42 06 |         send.smpl (8)             r124    r2             0x00000000  0x06424001  // wr:3+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 90 22 06 |         send.smpl (8)             r124    r2             0x00000000  0x06229001  // wr:3+0, rd:2; lod:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 80 01 00 06 01 90 44 0c |         send.smpl (16)            r120    r12            0x00000000  0x0C449001  // wr:6+0, rd:4; lod:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 00 60 02 00 06 02 a1 43 04 |         send.smpl (8)             r5      r19            0x00000000  0x0443A102  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 e0 01 60 01 00 06 02 a1 85 08 |         send.smpl (16)            r15     r11            0x00000000  0x0885A102  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 80 0f 80 01 00 06 00 c0 43 0a |         send.smpl (8)             r124    r12            0x00000000  0x0A43C000  // wr:5+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 80 00 a0 00 00 06 01 00 12 04 |         send.smpl (8)             r4      r5             0x00000000  0x04120001  // wr:2+0, rd:1; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 00 e0 00 00 06 01 00 24 08 |         send.smpl (16)            r4      r7             0x00000000  0x08240001  // wr:4+0, rd:2; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 27 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0027   {EOT}  // wr:10h+0, rd:0; simd8_write off=2 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 67 00 08 12 |         send.urb (8)              null    r2             0x00000000  0x12080067  // wr:9h+0, rd:0; simd8_write off=6 (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 87 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080087   {EOT}  // wr:5h+0, rd:0; simd8_write off=8 (8)
skl | 31 00 60 06 08 02 a0 02 40 00 00 06 68 00 38 02 |         send.urb (8)              r21     r2             0x00000000  0x02380068  // wr:1h+0, rd:3; simd8_read off=6 (8)
skl | 31 00 60 06 08 02 60 04 40 00 00 06 88 00 38 02 |         send.urb (8)              r35     r2             0x00000000  0x02380088  // wr:1h+0, rd:3; simd8_read off=8 (8)
skl | 31 00 60 06 00 02 00 00 a0 00 00 06 67 00 0a 14 |         send.urb (8)              null    r5             0x00000000  0x140A0067  // wr:10h+0, rd:0; simd8_write off=6 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 67 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0067   {EOT}  // wr:10h+0, rd:0; simd8_write off=6 per_slot (8)
skl | 31 00 60 02 08 02 40 00 00 01 00 06 01 00 22 04 |         send.smpl (8)             r2      r8             0x00000000  0x04220001  // wr:2+0, rd:2; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 c0 01 00 06 01 00 44 08 |         send.smpl (16)            r2      r14            0x00000000  0x08440001  // wr:4+0, rd:4; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 d7 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A0800D7   {EOT}  // wr:5h+0, rd:0; simd8_write off=13 (8)
skl | 31 00 60 02 08 02 c0 02 c0 01 00 06 05 84 4a 06 |         send.smpl (8)             r22     r14            0x00000000  0x064A8405  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 02 81 4a 08 |         send.smpl (8)             r6      r6             0x00000000  0x084A8102  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 01 40 01 00 06 03 82 4a 08 |         send.smpl (8)             r14     r10            0x00000000  0x084A8203  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 40 02 40 03 00 06 04 83 4a 0a |         send.smpl (8)             r18     r26            0x00000000  0x0A4A8304  // wr:5h+0, rd:4; gather4:u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 02 60 05 00 06 05 84 8c 0a |         send.smpl (16)            r18     r43            0x00000000  0x0A8C8405  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 60 05 e0 00 00 06 02 81 8c 0e |         send.smpl (16)            r43     r7             0x00000000  0x0E8C8102  // wr:7h+0, rd:8; gather4:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 60 06 00 06 03 82 8c 0e |         send.smpl (16)            r2      r51            0x00000000  0x0E8C8203  // wr:7h+0, rd:8; gather4:u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 01 40 03 00 06 04 83 8c 12 |         send.smpl (16)            r10     r26            0x00000000  0x128C8304  // wr:9h+0, rd:8; gather4:u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 c0 00 e0 01 00 06 01 40 4a 0e |         send.smpl (8)             r6      r15            0x00000000  0x0E4A4001  // wr:7h+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 80 0c 00 02 00 00 40 00 00 06 01 86 00 04 |         send.hdc1 (16)            null    r2             0x00000000  0x04008601  // wr:2+0, rd:0; untyped_atomic_dec simd16 (16) bti(1)
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 20 42 08 |         send.smpl (8)             r124    r2             0x00000000  0x08422001  // wr:4+0, rd:4; sample_l (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 40 00 00 06 01 20 84 10 |         send.smpl (16)            r120    r2             0x00000000  0x10842001  // wr:8+0, rd:8; sample_l (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 60 12 08 |         send.smpl (8)             r6      r7             0x00000000  0x08126001  // wr:4+0, rd:1; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 60 01 00 06 02 61 12 08 |         send.smpl (8)             r7      r11            0x00000000  0x08126102  // wr:4+0, rd:1; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 01 00 06 01 60 24 10 |         send.smpl (16)            r10     r12            0x00000000  0x10246001  // wr:8+0, rd:2; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 80 02 00 06 02 61 24 10 |         send.smpl (16)            r12     r20            0x00000000  0x10246102  // wr:8+0, rd:2; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 06 00 02 00 00 40 02 00 06 47 80 0a 0e |         send.urb (8)              null    r18            0x00000000  0x0E0A8047  // wr:7h+0, rd:0; simd8_write off=4 masked per_slot (8)
skl | 31 00 60 06 08 02 20 01 40 04 00 06 18 02 48 02 |         send.urb (8)              r9      r34            0x00000000  0x02480218  // wr:1h+0, rd:4; simd8_read off=33 (8)
skl | 31 00 60 06 08 02 20 02 40 04 00 06 38 02 48 02 |         send.urb (8)              r17     r34            0x00000000  0x02480238  // wr:1h+0, rd:4; simd8_read off=35 (8)
skl | 31 00 60 06 08 02 40 00 c0 00 00 06 28 01 1a 04 |         send.urb (8)              r2      r6             0x00000000  0x041A0128  // wr:2h+0, rd:1; simd8_read off=18 per_slot (8)
skl | 31 00 60 06 08 02 c0 02 00 01 00 06 28 00 1a 04 |         send.urb (8)              r22     r8             0x00000000  0x041A0028  // wr:2h+0, rd:1; simd8_read off=2 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 00 00 06 27 80 08 06 |         send.urb (8)              null    r2             0x00000000  0x06088027  // wr:3h+0, rd:0; simd8_write off=2 masked (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 37 80 08 06 |         send.urb (8)              null    r12            0x00000000  0x06088037  // wr:3h+0, rd:0; simd8_write off=3 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 47 80 08 06 |         send.urb (8)              null    r13            0x00000000  0x06088047  // wr:3h+0, rd:0; simd8_write off=4 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 57 80 08 06 |         send.urb (8)              null    r14            0x00000000  0x06088057  // wr:3h+0, rd:0; simd8_write off=5 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 67 80 08 06 |         send.urb (8)              null    r15            0x00000000  0x06088067  // wr:3h+0, rd:0; simd8_write off=6 masked (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 77 80 08 06 |         send.urb (8)              null    r16            0x00000000  0x06088077  // wr:3h+0, rd:0; simd8_write off=7 masked (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 87 80 08 06 |         send.urb (8)              null    r17            0x00000000  0x06088087  // wr:3h+0, rd:0; simd8_write off=8 masked (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 97 80 08 06 |         send.urb (8)              null    r18            0x00000000  0x06088097  // wr:3h+0, rd:0; simd8_write off=9 masked (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 a7 80 08 06 |         send.urb (8)              null    r19            0x00000000  0x060880A7  // wr:3h+0, rd:0; simd8_write off=10 masked (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 b7 80 08 06 |         send.urb (8)              null    r20            0x00000000  0x060880B7  // wr:3h+0, rd:0; simd8_write off=11 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 c7 80 08 06 |         send.urb (8)              null    r21            0x00000000  0x060880C7  // wr:3h+0, rd:0; simd8_write off=12 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 d7 80 08 06 |         send.urb (8)              null    r22            0x00000000  0x060880D7  // wr:3h+0, rd:0; simd8_write off=13 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 e7 80 08 06 |         send.urb (8)              null    r23            0x00000000  0x060880E7  // wr:3h+0, rd:0; simd8_write off=14 masked (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 f7 80 08 06 |         send.urb (8)              null    r24            0x00000000  0x060880F7  // wr:3h+0, rd:0; simd8_write off=15 masked (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 07 81 08 06 |         send.urb (8)              null    r25            0x00000000  0x06088107  // wr:3h+0, rd:0; simd8_write off=16 masked (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 17 81 08 06 |         send.urb (8)              null    r26            0x00000000  0x06088117  // wr:3h+0, rd:0; simd8_write off=17 masked (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 27 81 08 06 |         send.urb (8)              null    r27            0x00000000  0x06088127  // wr:3h+0, rd:0; simd8_write off=18 masked (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 37 81 08 06 |         send.urb (8)              null    r28            0x00000000  0x06088137  // wr:3h+0, rd:0; simd8_write off=19 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 47 81 08 06 |         send.urb (8)              null    r29            0x00000000  0x06088147  // wr:3h+0, rd:0; simd8_write off=20 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 57 81 08 06 |         send.urb (8)              null    r30            0x00000000  0x06088157  // wr:3h+0, rd:0; simd8_write off=21 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 67 81 08 06 |         send.urb (8)              null    r31            0x00000000  0x06088167  // wr:3h+0, rd:0; simd8_write off=22 masked (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 77 81 08 06 |         send.urb (8)              null    r32            0x00000000  0x06088177  // wr:3h+0, rd:0; simd8_write off=23 masked (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 87 81 08 06 |         send.urb (8)              null    r33            0x00000000  0x06088187  // wr:3h+0, rd:0; simd8_write off=24 masked (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 97 81 08 06 |         send.urb (8)              null    r34            0x00000000  0x06088197  // wr:3h+0, rd:0; simd8_write off=25 masked (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 a7 81 08 06 |         send.urb (8)              null    r35            0x00000000  0x060881A7  // wr:3h+0, rd:0; simd8_write off=26 masked (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 b7 81 08 06 |         send.urb (8)              null    r36            0x00000000  0x060881B7  // wr:3h+0, rd:0; simd8_write off=27 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 c7 81 08 06 |         send.urb (8)              null    r37            0x00000000  0x060881C7  // wr:3h+0, rd:0; simd8_write off=28 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 d7 81 08 06 |         send.urb (8)              null    r38            0x00000000  0x060881D7  // wr:3h+0, rd:0; simd8_write off=29 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 e7 81 08 06 |         send.urb (8)              null    r39            0x00000000  0x060881E7  // wr:3h+0, rd:0; simd8_write off=30 masked (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 f7 81 08 06 |         send.urb (8)              null    r40            0x00000000  0x060881F7  // wr:3h+0, rd:0; simd8_write off=31 masked (8)
skl | 31 00 60 02 08 02 60 00 40 01 00 06 01 a0 42 02 |         send.smpl (8)             r3      r10            0x00000000  0x0242A001  // wr:1+0, rd:4; resinfo:lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 00 60 01 00 06 01 a0 84 04 |         send.smpl (16)            r3      r11            0x00000000  0x0484A001  // wr:2+0, rd:8; resinfo:lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f c0 00 00 06 01 00 32 06 |         send.smpl (8)             r124    r6             0x00000000  0x06320001  // wr:3+0, rd:3; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 00 01 00 06 01 00 64 0c |         send.smpl (16)            r120    r8             0x00000000  0x0C640001  // wr:6+0, rd:6; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 0c 08 02 80 0f 40 00 00 06 00 60 40 02 |         send.hdc1 (8)             r124    r2             0x00000000  0x02406000  // wr:1+0, rd:4; untyped_read:xyzw simd8 (8) bti(0)
skl | 31 00 60 02 08 02 e0 0f c0 00 00 06 01 00 12 06 |         send.smpl (8)             r127    r6             0x00000000  0x06120001  // wr:3+0, rd:1; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 0f 00 01 00 06 01 00 24 0c |         send.smpl (16)            r126    r8             0x00000000  0x0C240001  // wr:6+0, rd:2; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 0c 08 02 e0 02 40 00 00 06 01 5e 11 04 |         send.hdc1 (8)             r23     r2             0x00000000  0x04115E01  // wr:2+0, rd:1; typed_read:x simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 e0 04 a0 05 00 06 01 6e 11 04 |         send.hdc1 (8|M8)          r39     r45            0x00000000  0x04116E01  // wr:2+0, rd:1; typed_read:x simd8 (8) bti(1)
skl | 31 00 61 0c 02 02 00 00 40 00 00 06 01 85 01 04 | (f1.0)  send.hdc1 (8)             null    r2             0x00000000  0x04018501  // wr:2+0, rd:0; typed_atomic_inc simd16 (8) bti(1)
skl | 31 10 61 0c 02 02 00 00 40 05 00 06 01 95 01 04 | (f1.0)  send.hdc1 (8|M8)          null    r42            0x00000000  0x04019501  // wr:2+0, rd:0; typed_atomic_inc simd8 (8) bti(1)
skl | 31 00 60 02 08 02 40 00 c0 00 00 06 01 30 42 04 |         send.smpl (8)             r2      r6             0x00000000  0x04423001  // wr:2+0, rd:4; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 00 01 00 06 02 31 42 04 |         send.smpl (8)             r6      r8             0x00000000  0x04423102  // wr:2+0, rd:4; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 40 01 00 06 01 30 84 08 |         send.smpl (16)            r2      r10            0x00000000  0x08843001  // wr:4+0, rd:8; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 40 02 00 06 02 31 84 08 |         send.smpl (16)            r10     r18            0x00000000  0x08843102  // wr:4+0, rd:8; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 c0 00 c0 02 00 06 18 03 4a 04 |         send.urb (8)              r6      r22            0x00000000  0x044A0318  // wr:2h+0, rd:4; simd8_read off=49 per_slot (8)
skl | 31 00 60 06 08 02 40 01 c0 02 00 06 18 05 4a 04 |         send.urb (8)              r10     r22            0x00000000  0x044A0518  // wr:2h+0, rd:4; simd8_read off=81 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 c0 02 00 06 18 07 4a 04 |         send.urb (8)              r14     r22            0x00000000  0x044A0718  // wr:2h+0, rd:4; simd8_read off=113 per_slot (8)
skl | 31 00 60 06 08 02 40 02 c0 02 00 06 18 09 4a 04 |         send.urb (8)              r18     r22            0x00000000  0x044A0918  // wr:2h+0, rd:4; simd8_read off=145 per_slot (8)
skl | 31 00 60 06 08 02 a0 01 a0 03 00 06 18 02 4a 04 |         send.urb (8)              r13     r29            0x00000000  0x044A0218  // wr:2h+0, rd:4; simd8_read off=33 per_slot (8)
skl | 31 00 60 06 08 02 20 02 a0 03 00 06 18 04 4a 04 |         send.urb (8)              r17     r29            0x00000000  0x044A0418  // wr:2h+0, rd:4; simd8_read off=65 per_slot (8)
skl | 31 00 60 06 08 02 a0 02 a0 03 00 06 18 06 4a 04 |         send.urb (8)              r21     r29            0x00000000  0x044A0618  // wr:2h+0, rd:4; simd8_read off=97 per_slot (8)
skl | 31 00 60 06 08 02 20 03 a0 03 00 06 18 08 4a 04 |         send.urb (8)              r25     r29            0x00000000  0x044A0818  // wr:2h+0, rd:4; simd8_read off=129 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 02 0a 0c |         send.urb (8)              null    r6             0x00000000  0x0C0A0217  // wr:6h+0, rd:0; simd8_write off=33 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 27 02 0a 0c |         send.urb (8)              null    r12            0x00000000  0x0C0A0227  // wr:6h+0, rd:0; simd8_write off=34 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 37 02 0a 0c |         send.urb (8)              null    r13            0x00000000  0x0C0A0237  // wr:6h+0, rd:0; simd8_write off=35 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 47 02 0a 0c |         send.urb (8)              null    r14            0x00000000  0x0C0A0247  // wr:6h+0, rd:0; simd8_write off=36 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 57 02 0a 0c |         send.urb (8)              null    r15            0x00000000  0x0C0A0257  // wr:6h+0, rd:0; simd8_write off=37 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 67 02 0a 0c |         send.urb (8)              null    r16            0x00000000  0x0C0A0267  // wr:6h+0, rd:0; simd8_write off=38 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 77 02 0a 0c |         send.urb (8)              null    r17            0x00000000  0x0C0A0277  // wr:6h+0, rd:0; simd8_write off=39 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 87 02 0a 0c |         send.urb (8)              null    r18            0x00000000  0x0C0A0287  // wr:6h+0, rd:0; simd8_write off=40 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 97 02 0a 0c |         send.urb (8)              null    r19            0x00000000  0x0C0A0297  // wr:6h+0, rd:0; simd8_write off=41 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 a7 02 0a 0c |         send.urb (8)              null    r20            0x00000000  0x0C0A02A7  // wr:6h+0, rd:0; simd8_write off=42 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 b7 02 0a 0c |         send.urb (8)              null    r21            0x00000000  0x0C0A02B7  // wr:6h+0, rd:0; simd8_write off=43 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 c7 02 0a 0c |         send.urb (8)              null    r22            0x00000000  0x0C0A02C7  // wr:6h+0, rd:0; simd8_write off=44 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 d7 02 0a 0c |         send.urb (8)              null    r23            0x00000000  0x0C0A02D7  // wr:6h+0, rd:0; simd8_write off=45 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 e7 02 0a 0c |         send.urb (8)              null    r24            0x00000000  0x0C0A02E7  // wr:6h+0, rd:0; simd8_write off=46 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 f7 02 0a 0c |         send.urb (8)              null    r25            0x00000000  0x0C0A02F7  // wr:6h+0, rd:0; simd8_write off=47 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 07 03 0a 0c |         send.urb (8)              null    r26            0x00000000  0x0C0A0307  // wr:6h+0, rd:0; simd8_write off=48 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 17 03 0a 0c |         send.urb (8)              null    r27            0x00000000  0x0C0A0317  // wr:6h+0, rd:0; simd8_write off=49 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 27 03 0a 0c |         send.urb (8)              null    r28            0x00000000  0x0C0A0327  // wr:6h+0, rd:0; simd8_write off=50 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 37 03 0a 0c |         send.urb (8)              null    r29            0x00000000  0x0C0A0337  // wr:6h+0, rd:0; simd8_write off=51 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 47 03 0a 0c |         send.urb (8)              null    r30            0x00000000  0x0C0A0347  // wr:6h+0, rd:0; simd8_write off=52 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 57 03 0a 0c |         send.urb (8)              null    r31            0x00000000  0x0C0A0357  // wr:6h+0, rd:0; simd8_write off=53 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 67 03 0a 0c |         send.urb (8)              null    r32            0x00000000  0x0C0A0367  // wr:6h+0, rd:0; simd8_write off=54 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 77 03 0a 0c |         send.urb (8)              null    r33            0x00000000  0x0C0A0377  // wr:6h+0, rd:0; simd8_write off=55 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 87 03 0a 0c |         send.urb (8)              null    r34            0x00000000  0x0C0A0387  // wr:6h+0, rd:0; simd8_write off=56 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 97 03 0a 0c |         send.urb (8)              null    r35            0x00000000  0x0C0A0397  // wr:6h+0, rd:0; simd8_write off=57 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 a7 03 0a 0c |         send.urb (8)              null    r36            0x00000000  0x0C0A03A7  // wr:6h+0, rd:0; simd8_write off=58 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 b7 03 0a 0c |         send.urb (8)              null    r37            0x00000000  0x0C0A03B7  // wr:6h+0, rd:0; simd8_write off=59 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 c7 03 0a 0c |         send.urb (8)              null    r38            0x00000000  0x0C0A03C7  // wr:6h+0, rd:0; simd8_write off=60 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 d7 03 0a 0c |         send.urb (8)              null    r39            0x00000000  0x0C0A03D7  // wr:6h+0, rd:0; simd8_write off=61 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 e7 03 0a 0c |         send.urb (8)              null    r40            0x00000000  0x0C0A03E7  // wr:6h+0, rd:0; simd8_write off=62 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 05 00 06 f7 03 0a 0c |         send.urb (8)              null    r41            0x00000000  0x0C0A03F7  // wr:6h+0, rd:0; simd8_write off=63 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 67 00 08 0a |         send.urb (8)              null    r16            0x00000000  0x0A080067  // wr:5h+0, rd:0; simd8_write off=6 (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 77 00 08 0a |         send.urb (8)              null    r17            0x00000000  0x0A080077  // wr:5h+0, rd:0; simd8_write off=7 (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 87 00 08 0a |         send.urb (8)              null    r18            0x00000000  0x0A080087  // wr:5h+0, rd:0; simd8_write off=8 (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 97 00 08 0a |         send.urb (8)              null    r19            0x00000000  0x0A080097  // wr:5h+0, rd:0; simd8_write off=9 (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 a7 00 08 0a |         send.urb (8)              null    r20            0x00000000  0x0A0800A7  // wr:5h+0, rd:0; simd8_write off=10 (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 b7 00 08 0a |         send.urb (8)              null    r21            0x00000000  0x0A0800B7  // wr:5h+0, rd:0; simd8_write off=11 (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 c7 00 08 0a |         send.urb (8)              null    r22            0x00000000  0x0A0800C7  // wr:5h+0, rd:0; simd8_write off=12 (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 d7 00 08 0a |         send.urb (8)              null    r23            0x00000000  0x0A0800D7  // wr:5h+0, rd:0; simd8_write off=13 (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 e7 00 08 0a |         send.urb (8)              null    r24            0x00000000  0x0A0800E7  // wr:5h+0, rd:0; simd8_write off=14 (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 f7 00 08 0a |         send.urb (8)              null    r25            0x00000000  0x0A0800F7  // wr:5h+0, rd:0; simd8_write off=15 (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 07 01 08 0a |         send.urb (8)              null    r26            0x00000000  0x0A080107  // wr:5h+0, rd:0; simd8_write off=16 (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 17 01 08 0a |         send.urb (8)              null    r27            0x00000000  0x0A080117  // wr:5h+0, rd:0; simd8_write off=17 (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 27 01 08 0a |         send.urb (8)              null    r28            0x00000000  0x0A080127  // wr:5h+0, rd:0; simd8_write off=18 (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 37 01 08 0a |         send.urb (8)              null    r29            0x00000000  0x0A080137  // wr:5h+0, rd:0; simd8_write off=19 (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 47 01 08 0a |         send.urb (8)              null    r30            0x00000000  0x0A080147  // wr:5h+0, rd:0; simd8_write off=20 (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 57 01 08 0a |         send.urb (8)              null    r31            0x00000000  0x0A080157  // wr:5h+0, rd:0; simd8_write off=21 (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 67 01 08 0a |         send.urb (8)              null    r32            0x00000000  0x0A080167  // wr:5h+0, rd:0; simd8_write off=22 (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 77 01 08 0a |         send.urb (8)              null    r33            0x00000000  0x0A080177  // wr:5h+0, rd:0; simd8_write off=23 (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 87 01 08 0a |         send.urb (8)              null    r34            0x00000000  0x0A080187  // wr:5h+0, rd:0; simd8_write off=24 (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 97 01 08 0a |         send.urb (8)              null    r35            0x00000000  0x0A080197  // wr:5h+0, rd:0; simd8_write off=25 (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 a7 01 08 0a |         send.urb (8)              null    r36            0x00000000  0x0A0801A7  // wr:5h+0, rd:0; simd8_write off=26 (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 b7 01 08 0a |         send.urb (8)              null    r37            0x00000000  0x0A0801B7  // wr:5h+0, rd:0; simd8_write off=27 (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 c7 01 08 0a |         send.urb (8)              null    r38            0x00000000  0x0A0801C7  // wr:5h+0, rd:0; simd8_write off=28 (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 d7 01 08 0a |         send.urb (8)              null    r39            0x00000000  0x0A0801D7  // wr:5h+0, rd:0; simd8_write off=29 (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 e7 01 08 0a |         send.urb (8)              null    r40            0x00000000  0x0A0801E7  // wr:5h+0, rd:0; simd8_write off=30 (8)
skl | 31 00 60 06 00 02 00 00 20 05 00 06 f7 01 08 0a |         send.urb (8)              null    r41            0x00000000  0x0A0801F7  // wr:5h+0, rd:0; simd8_write off=31 (8)
skl | 31 00 60 02 08 02 a0 01 40 00 00 06 01 30 12 06 |         send.smpl (8)             r13     r2             0x00000000  0x06123001  // wr:3+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 01 a0 00 00 06 02 31 12 06 |         send.smpl (8)             r14     r5             0x00000000  0x06123102  // wr:3+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 c0 02 40 00 00 06 01 30 24 0c |         send.smpl (16)            r22     r2             0x00000000  0x0C243001  // wr:6+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 03 00 02 00 06 02 31 24 0c |         send.smpl (16)            r24     r16            0x00000000  0x0C243102  // wr:6+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 a0 00 e0 01 00 06 03 02 42 04 |         send.smpl (8)             r5      r15            0x00000000  0x04420203  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 e0 00 60 03 00 06 03 02 84 08 |         send.smpl (16)            r7      r27            0x00000000  0x08840203  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 80 0c 08 02 80 00 20 02 00 06 03 a5 20 04 |         send.hdc1 (16)            r4      r17            0x00000000  0x0420A503  // wr:2+0, rd:2; untyped_atomic_inc simd16 (16) bti(3)
skl | 31 00 80 0c 00 02 00 00 40 02 00 06 04 85 00 04 |         send.hdc1 (16)            null    r18            0x00000000  0x04008504  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(4)
skl | 31 00 80 0c 08 02 60 01 60 02 00 06 02 a6 20 04 |         send.hdc1 (16)            r11     r19            0x00000000  0x0420A602  // wr:2+0, rd:2; untyped_atomic_dec simd16 (16) bti(2)
skl | 31 00 80 0c 00 02 00 00 80 02 00 06 05 85 00 04 |         send.hdc1 (16)            null    r20            0x00000000  0x04008505  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(5)
skl | 31 00 80 0c 08 02 00 02 a0 02 00 06 01 5e 20 04 |         send.hdc1 (16)            r16     r21            0x00000000  0x04205E01  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(1)
skl | 31 00 80 0c 00 02 00 00 c0 02 00 06 06 85 00 04 |         send.hdc1 (16)            null    r22            0x00000000  0x04008506  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(6)
skl | 31 00 60 02 08 02 40 03 40 03 00 06 03 a2 42 02 |         send.smpl (8)             r26     r26            0x00000000  0x0242A203  // wr:1+0, rd:4; resinfo:lod (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 c0 03 c0 03 00 06 04 a3 42 02 |         send.smpl (8)             r30     r30            0x00000000  0x0242A304  // wr:1+0, rd:4; resinfo:lod (8) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 40 04 40 04 00 06 05 a4 42 02 |         send.smpl (8)             r34     r34            0x00000000  0x0242A405  // wr:1+0, rd:4; resinfo:lod (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 c0 04 c0 04 00 06 06 a5 42 02 |         send.smpl (8)             r38     r38            0x00000000  0x0242A506  // wr:1+0, rd:4; resinfo:lod (8) bti(6) using sampler index 5
skl | 31 00 60 02 08 02 c0 02 20 03 00 06 02 a1 42 02 |         send.smpl (8)             r22     r25            0x00000000  0x0242A102  // wr:1+0, rd:4; resinfo:lod (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 05 40 05 00 06 07 a6 42 02 |         send.smpl (8)             r42     r42            0x00000000  0x0242A607  // wr:1+0, rd:4; resinfo:lod (8) bti(7) using sampler index 6
skl | 31 00 60 02 08 02 c0 05 c0 05 00 06 08 a7 42 02 |         send.smpl (8)             r46     r46            0x00000000  0x0242A708  // wr:1+0, rd:4; resinfo:lod (8) bti(8) using sampler index 7
skl | 31 00 60 02 08 02 40 06 40 06 00 06 09 a8 42 02 |         send.smpl (8)             r50     r50            0x00000000  0x0242A809  // wr:1+0, rd:4; resinfo:lod (8) bti(9) using sampler index 8
skl | 31 00 60 02 08 02 40 00 c0 06 00 06 0a a9 42 02 |         send.smpl (8)             r2      r54            0x00000000  0x0242A90A  // wr:1+0, rd:4; resinfo:lod (8) bti(10) using sampler index 9
skl | 31 00 60 02 08 02 c0 00 e0 06 00 06 0b aa 42 02 |         send.smpl (8)             r6      r55            0x00000000  0x0242AA0B  // wr:1+0, rd:4; resinfo:lod (8) bti(11) using sampler index 10
skl | 31 00 60 02 08 02 40 01 00 07 00 06 0c ab 42 02 |         send.smpl (8)             r10     r56            0x00000000  0x0242AB0C  // wr:1+0, rd:4; resinfo:lod (8) bti(12) using sampler index 11
skl | 31 00 60 02 08 02 c0 01 20 07 00 06 0d ac 42 02 |         send.smpl (8)             r14     r57            0x00000000  0x0242AC0D  // wr:1+0, rd:4; resinfo:lod (8) bti(13) using sampler index 12
skl | 31 00 80 02 08 02 40 01 40 02 00 06 02 a1 84 04 |         send.smpl (16)            r10     r18            0x00000000  0x0484A102  // wr:2+0, rd:8; resinfo:lod (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 0a c0 0d 00 06 0b aa 84 04 |         send.smpl (16)            r82     r110           0x00000000  0x0484AA0B  // wr:2+0, rd:8; resinfo:lod (16) bti(11) using sampler index 10
skl | 31 00 80 02 08 02 40 02 40 03 00 06 03 a2 84 04 |         send.smpl (16)            r18     r26            0x00000000  0x0484A203  // wr:2+0, rd:8; resinfo:lod (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 0b 00 0e 00 06 0c ab 84 04 |         send.smpl (16)            r90     r112           0x00000000  0x0484AB0C  // wr:2+0, rd:8; resinfo:lod (16) bti(12) using sampler index 11
skl | 31 00 80 02 08 02 40 0c 40 0d 00 06 0d ac 84 04 |         send.smpl (16)            r98     r106           0x00000000  0x0484AC0D  // wr:2+0, rd:8; resinfo:lod (16) bti(13) using sampler index 12
skl | 31 00 80 02 08 02 40 03 40 04 00 06 04 a3 84 04 |         send.smpl (16)            r26     r34            0x00000000  0x0484A304  // wr:2+0, rd:8; resinfo:lod (16) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 04 40 05 00 06 05 a4 84 04 |         send.smpl (16)            r34     r42            0x00000000  0x0484A405  // wr:2+0, rd:8; resinfo:lod (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 40 05 40 06 00 06 06 a5 84 04 |         send.smpl (16)            r42     r50            0x00000000  0x0484A506  // wr:2+0, rd:8; resinfo:lod (16) bti(6) using sampler index 5
skl | 31 00 80 02 08 02 40 06 40 07 00 06 07 a6 84 04 |         send.smpl (16)            r50     r58            0x00000000  0x0484A607  // wr:2+0, rd:8; resinfo:lod (16) bti(7) using sampler index 6
skl | 31 00 80 02 08 02 40 07 40 08 00 06 08 a7 84 04 |         send.smpl (16)            r58     r66            0x00000000  0x0484A708  // wr:2+0, rd:8; resinfo:lod (16) bti(8) using sampler index 7
skl | 31 00 80 02 08 02 40 08 40 09 00 06 09 a8 84 04 |         send.smpl (16)            r66     r74            0x00000000  0x0484A809  // wr:2+0, rd:8; resinfo:lod (16) bti(9) using sampler index 8
skl | 31 00 80 02 08 02 40 09 80 0d 00 06 0a a9 84 04 |         send.smpl (16)            r74     r108           0x00000000  0x0484A90A  // wr:2+0, rd:8; resinfo:lod (16) bti(10) using sampler index 9
skl | 31 00 80 0c 00 02 00 00 60 00 00 06 fe 85 00 04 |         send.hdc1 (16)            null    r3             0x00000000  0x040085FE  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(254)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 67 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080067   {EOT}  // wr:9h+0, rd:0; simd8_write off=6 (8)
skl | 31 00 60 02 08 02 c0 00 80 02 00 06 01 40 42 12 |         send.smpl (8)             r6      r20            0x00000000  0x12424001  // wr:9+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 20 02 40 00 00 06 01 a0 13 04 |         send.smpl (8)             r17     r2             0x00000000  0x0413A001  // wr:2+0, rd:1; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 e0 00 00 06 01 a0 25 08 |         send.smpl (16)            r2      r7             0x00000000  0x0825A001  // wr:4+0, rd:2; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 20 01 20 02 00 06 00 20 42 06 |         send.smpl (8)             r9      r17            0x00000000  0x06422000  // wr:3+0, rd:4; sample_l (8) bti(0) using sampler index 0
skl | 31 00 80 0a 00 02 00 00 60 0f 00 06 fd 03 0a 06 |         send.hdc0 (16)            null    r123           0x00000000  0x060A03FD  // wr:3h+0, rd:0; oword_block_write:owords4 (16) bti(253)
skl | 31 00 80 0a 0c 02 40 0e 40 0e 00 06 fd 03 28 02 | (W)     send.hdc0 (16)            r114    r114           0x00000000  0x022803FD  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(253)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 27 01 0a 0c |         send.urb (8)              null    r12            0x00000000  0x0C0A0127  // wr:6h+0, rd:0; simd8_write off=18 per_slot (8)
skl | 31 00 60 02 08 02 40 00 60 01 00 06 05 04 42 04 |         send.smpl (8)             r2      r11            0x00000000  0x04420405  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 40 00 80 01 00 06 06 05 42 04 |         send.smpl (8)             r2      r12            0x00000000  0x04420506  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(6) using sampler index 5
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 07 06 42 04 |         send.smpl (8)             r2      r13            0x00000000  0x04420607  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(7) using sampler index 6
skl | 31 00 60 02 08 02 40 00 c0 01 00 06 08 07 42 04 |         send.smpl (8)             r2      r14            0x00000000  0x04420708  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(8) using sampler index 7
skl | 31 00 60 02 08 02 40 00 e0 01 00 06 09 08 42 04 |         send.smpl (8)             r2      r15            0x00000000  0x04420809  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(9) using sampler index 8
skl | 31 00 60 02 08 02 40 00 00 02 00 06 0a 09 42 04 |         send.smpl (8)             r2      r16            0x00000000  0x0442090A  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(10) using sampler index 9
skl | 31 00 60 02 08 02 40 00 20 02 00 06 0b 0a 42 04 |         send.smpl (8)             r2      r17            0x00000000  0x04420A0B  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(11) using sampler index 10
skl | 31 00 60 02 08 02 40 00 40 02 00 06 0c 0b 42 04 |         send.smpl (8)             r2      r18            0x00000000  0x04420B0C  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(12) using sampler index 11
skl | 31 00 60 02 08 02 40 00 60 02 00 06 0d 0c 42 04 |         send.smpl (8)             r2      r19            0x00000000  0x04420C0D  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(13) using sampler index 12
skl | 31 00 60 02 08 02 40 00 80 02 00 06 0e 0d 42 04 |         send.smpl (8)             r2      r20            0x00000000  0x04420D0E  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(14) using sampler index 13
skl | 31 00 60 02 08 02 40 00 a0 02 00 06 0f 0e 42 04 |         send.smpl (8)             r2      r21            0x00000000  0x04420E0F  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(15) using sampler index 14
skl | 31 00 60 02 08 02 40 00 c0 02 00 06 10 0f 42 04 |         send.smpl (8)             r2      r22            0x00000000  0x04420F10  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(16) using sampler index 15
skl | 31 00 60 02 08 02 40 00 40 01 00 06 11 00 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0011  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(17) using sampler index 0
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 12 01 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0112  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(18) using sampler index 1
skl | 31 00 60 02 08 02 40 00 40 01 00 06 13 02 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0213  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(19) using sampler index 2
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 14 03 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0314  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(20) using sampler index 3
skl | 31 00 60 02 08 02 40 00 40 01 00 06 15 04 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0415  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(21) using sampler index 4
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 16 05 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0516  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(22) using sampler index 5
skl | 31 00 60 02 08 02 40 00 40 01 00 06 17 06 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0617  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(23) using sampler index 6
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 18 07 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0718  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(24) using sampler index 7
skl | 31 00 60 02 08 02 40 00 40 01 00 06 19 08 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0819  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(25) using sampler index 8
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 1a 09 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A091A  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(26) using sampler index 9
skl | 31 00 60 02 08 02 40 00 40 01 00 06 1b 0a 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0A1B  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(27) using sampler index 10
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 1c 0b 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0B1C  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(28) using sampler index 11
skl | 31 00 60 02 08 02 40 00 40 01 00 06 1d 0c 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0C1D  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(29) using sampler index 12
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 1e 0d 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0D1E  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(30) using sampler index 13
skl | 31 00 60 02 08 02 40 00 40 01 00 06 1f 0e 4a 06 |         send.smpl (8)             r2      r10            0x00000000  0x064A0E1F  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(31) using sampler index 14
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 20 0f 4a 06 |         send.smpl (8)             r2      r13            0x00000000  0x064A0F20  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(32) using sampler index 15
skl | 31 00 80 02 08 02 40 00 80 03 00 06 05 04 84 08 |         send.smpl (16)            r2      r28            0x00000000  0x08840405  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 40 00 a0 03 00 06 06 05 84 08 |         send.smpl (16)            r2      r29            0x00000000  0x08840506  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(6) using sampler index 5
skl | 31 00 80 02 08 02 40 00 c0 03 00 06 07 06 84 08 |         send.smpl (16)            r2      r30            0x00000000  0x08840607  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(7) using sampler index 6
skl | 31 00 80 02 08 02 40 00 e0 03 00 06 08 07 84 08 |         send.smpl (16)            r2      r31            0x00000000  0x08840708  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(8) using sampler index 7
skl | 31 00 80 02 08 02 40 00 00 04 00 06 09 08 84 08 |         send.smpl (16)            r2      r32            0x00000000  0x08840809  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(9) using sampler index 8
skl | 31 00 80 02 08 02 40 00 20 04 00 06 0a 09 84 08 |         send.smpl (16)            r2      r33            0x00000000  0x0884090A  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(10) using sampler index 9
skl | 31 00 80 02 08 02 40 00 40 04 00 06 0b 0a 84 08 |         send.smpl (16)            r2      r34            0x00000000  0x08840A0B  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(11) using sampler index 10
skl | 31 00 80 02 08 02 40 00 60 04 00 06 0c 0b 84 08 |         send.smpl (16)            r2      r35            0x00000000  0x08840B0C  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(12) using sampler index 11
skl | 31 00 80 02 08 02 40 00 80 04 00 06 0d 0c 84 08 |         send.smpl (16)            r2      r36            0x00000000  0x08840C0D  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(13) using sampler index 12
skl | 31 00 80 02 08 02 40 00 a0 04 00 06 0e 0d 84 08 |         send.smpl (16)            r2      r37            0x00000000  0x08840D0E  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(14) using sampler index 13
skl | 31 00 80 02 08 02 e0 00 c0 04 00 06 0f 0e 84 08 |         send.smpl (16)            r7      r38            0x00000000  0x08840E0F  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(15) using sampler index 14
skl | 31 00 80 02 08 02 e0 02 e0 04 00 06 10 0f 84 08 |         send.smpl (16)            r23     r39            0x00000000  0x08840F10  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(16) using sampler index 15
skl | 31 00 80 02 08 02 20 02 40 00 00 06 11 00 8c 0a |         send.smpl (16)            r17     r2             0x00000000  0x0A8C0011  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(17) using sampler index 0
skl | 31 00 80 02 08 02 a0 03 e0 00 00 06 12 01 8c 0a |         send.smpl (16)            r29     r7             0x00000000  0x0A8C0112  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(18) using sampler index 1
skl | 31 00 80 02 08 02 60 03 80 01 00 06 13 02 8c 0a |         send.smpl (16)            r27     r12            0x00000000  0x0A8C0213  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(19) using sampler index 2
skl | 31 00 80 02 08 02 00 04 20 02 00 06 14 03 8c 0a |         send.smpl (16)            r32     r17            0x00000000  0x0A8C0314  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(20) using sampler index 3
skl | 31 00 80 02 08 02 40 00 c0 02 00 06 15 04 8c 0a |         send.smpl (16)            r2      r22            0x00000000  0x0A8C0415  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(21) using sampler index 4
skl | 31 00 80 02 08 02 40 00 60 03 00 06 16 05 8c 0a |         send.smpl (16)            r2      r27            0x00000000  0x0A8C0516  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(22) using sampler index 5
skl | 31 00 80 02 08 02 40 00 00 04 00 06 17 06 8c 0a |         send.smpl (16)            r2      r32            0x00000000  0x0A8C0617  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(23) using sampler index 6
skl | 31 00 80 02 08 02 40 00 a0 04 00 06 18 07 8c 0a |         send.smpl (16)            r2      r37            0x00000000  0x0A8C0718  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(24) using sampler index 7
skl | 31 00 80 02 08 02 40 00 40 05 00 06 19 08 8c 0a |         send.smpl (16)            r2      r42            0x00000000  0x0A8C0819  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(25) using sampler index 8
skl | 31 00 80 02 08 02 40 00 e0 05 00 06 1a 09 8c 0a |         send.smpl (16)            r2      r47            0x00000000  0x0A8C091A  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(26) using sampler index 9
skl | 31 00 80 02 08 02 40 00 80 06 00 06 1b 0a 8c 0a |         send.smpl (16)            r2      r52            0x00000000  0x0A8C0A1B  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(27) using sampler index 10
skl | 31 00 80 02 08 02 40 00 20 07 00 06 1c 0b 8c 0a |         send.smpl (16)            r2      r57            0x00000000  0x0A8C0B1C  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(28) using sampler index 11
skl | 31 00 80 02 08 02 40 00 c0 07 00 06 1d 0c 8c 0a |         send.smpl (16)            r2      r62            0x00000000  0x0A8C0C1D  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(29) using sampler index 12
skl | 31 00 80 02 08 02 40 00 60 08 00 06 1e 0d 8c 0a |         send.smpl (16)            r2      r67            0x00000000  0x0A8C0D1E  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(30) using sampler index 13
skl | 31 00 80 02 08 02 40 00 00 09 00 06 1f 0e 8c 0a |         send.smpl (16)            r2      r72            0x00000000  0x0A8C0E1F  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(31) using sampler index 14
skl | 31 00 80 02 08 02 40 00 a0 09 00 06 20 0f 8c 0a |         send.smpl (16)            r2      r77            0x00000000  0x0A8C0F20  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(32) using sampler index 15
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 02 01 12 02 |         send.smpl (8)             r124    r2             0x00000000  0x02120102  // wr:1+0, rd:1; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 00 60 00 00 06 02 01 22 02 |         send.smpl (8)             r6      r3             0x00000000  0x02220102  // wr:1+0, rd:2; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 00 01 80 00 00 06 02 01 32 02 |         send.smpl (8)             r8      r4             0x00000000  0x02320102  // wr:1+0, rd:3; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 00 0f 40 00 00 06 02 01 24 04 |         send.smpl (16)            r120    r2             0x00000000  0x04240102  // wr:2+0, rd:2; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 00 00 06 02 01 44 04 |         send.smpl (16)            r10     r4             0x00000000  0x04440102  // wr:2+0, rd:4; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 c0 01 c0 00 00 06 02 01 64 04 |         send.smpl (16)            r14     r6             0x00000000  0x04640102  // wr:2+0, rd:6; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 06 00 02 00 00 00 01 00 06 27 80 0a 0c |         send.urb (8)              null    r8             0x00000000  0x0C0A8027  // wr:6h+0, rd:0; simd8_write off=2 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 47 00 08 12 |         send.urb (8)              null    r13            0x00000000  0x12080047  // wr:9h+0, rd:0; simd8_write off=4 (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 87 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080087   {EOT}  // wr:9h+0, rd:0; simd8_write off=8 (8)
skl | 31 00 60 02 08 02 a0 00 40 01 00 06 01 00 42 06 |         send.smpl (8)             r5      r10            0x00000000  0x06420001  // wr:3+0, rd:4; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 60 02 00 06 01 00 84 0c |         send.smpl (16)            r7      r19            0x00000000  0x0C840001  // wr:6+0, rd:8; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 0c 08 02 20 00 a0 0f 00 06 02 6e 10 02 |         send.hdc1 (8)             r1      r125           0x00000000  0x02106E02  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(2)
skl | 31 00 60 0c 08 02 00 01 c0 02 00 06 fe 6e 10 02 |         send.hdc1 (8)             r8      r22            0x00000000  0x02106EFE  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(254)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 97 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080097   {EOT}  // wr:5h+0, rd:0; simd8_write off=9 (8)
skl | 31 00 60 02 08 02 a0 03 a0 00 00 06 01 20 4b 0e |         send.smpl (8)             r29     r5             0x00000000  0x0E4B2001  // wr:7h+0, rd:4; gather4_po_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 08 00 09 00 06 02 a1 12 02 |         send.smpl (8)             r68     r72            0x00000000  0x0212A102  // wr:1+0, rd:1; resinfo:lod (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 60 08 a0 00 00 06 01 60 12 0a |         send.smpl (8)             r67     r5             0x00000000  0x0A126001  // wr:5+0, rd:1; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 08 40 01 00 06 02 61 12 0a |         send.smpl (8)             r69     r10            0x00000000  0x0A126102  // wr:5+0, rd:1; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 80 04 00 05 00 06 02 a1 24 04 |         send.smpl (16)            r36     r40            0x00000000  0x0424A102  // wr:2+0, rd:2; resinfo:lod (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 e0 00 00 06 01 60 24 14 |         send.smpl (16)            r2      r7             0x00000000  0x14246001  // wr:10+0, rd:2; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 a0 04 20 02 00 06 02 61 24 14 |         send.smpl (16)            r37     r17            0x00000000  0x14246102  // wr:10+0, rd:2; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 a0 0f a0 00 00 06 02 01 22 04 |         send.smpl (8)             r125    r5             0x00000000  0x04220102  // wr:2+0, rd:2; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 0f e0 00 00 06 02 01 44 08 |         send.smpl (16)            r122    r7             0x00000000  0x08440102  // wr:4+0, rd:4; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 37 80 0a 0c |         send.urb (8)              null    r14            0x00000000  0x0C0A8037  // wr:6h+0, rd:0; simd8_write off=3 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 47 80 0a 0c |         send.urb (8)              null    r15            0x00000000  0x0C0A8047  // wr:6h+0, rd:0; simd8_write off=4 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 57 80 0a 0c |         send.urb (8)              null    r16            0x00000000  0x0C0A8057  // wr:6h+0, rd:0; simd8_write off=5 masked per_slot (8)
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 50 1a 08 |         send.smpl (8)             r6      r7             0x00000000  0x081A5001  // wr:4h+0, rd:1; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 60 01 00 06 02 51 1a 08 |         send.smpl (8)             r7      r11            0x00000000  0x081A5102  // wr:4h+0, rd:1; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 01 00 06 01 50 2c 0e |         send.smpl (16)            r10     r12            0x00000000  0x0E2C5001  // wr:7h+0, rd:2; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 60 02 00 06 02 51 2c 0e |         send.smpl (16)            r12     r19            0x00000000  0x0E2C5102  // wr:7h+0, rd:2; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 a0 00 c0 00 00 06 01 30 1a 08 |         send.smpl (8)             r5      r6             0x00000000  0x081A3001  // wr:4h+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 02 31 1a 08 |         send.smpl (8)             r6      r10            0x00000000  0x081A3102  // wr:4h+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 20 01 60 01 00 06 01 30 2c 0e |         send.smpl (16)            r9      r11            0x00000000  0x0E2C3001  // wr:7h+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 01 40 02 00 06 02 31 2c 0e |         send.smpl (16)            r11     r18            0x00000000  0x0E2C3102  // wr:7h+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 a0 00 e0 00 00 06 02 01 32 04 |         send.smpl (8)             r5      r7             0x00000000  0x04320102  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 00 01 c0 01 00 06 02 01 64 08 |         send.smpl (16)            r8      r14            0x00000000  0x08640102  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 60 02 80 01 00 06 03 00 32 04 |         send.smpl (8)             r19     r12            0x00000000  0x04320003  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(3) using sampler index 0
skl | 31 00 80 02 08 02 40 04 20 05 00 06 03 00 64 08 |         send.smpl (16)            r34     r41            0x00000000  0x08640003  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(3) using sampler index 0
skl | 31 00 60 02 08 02 60 01 40 00 00 06 08 a0 43 04 |         send.smpl (8)             r11     r2             0x00000000  0x0443A008  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(8) using sampler index 0
skl | 31 00 60 02 08 02 e0 01 40 00 00 06 09 a1 43 04 |         send.smpl (8)             r15     r2             0x00000000  0x0443A109  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(9) using sampler index 1
skl | 31 00 60 02 08 02 60 02 40 00 00 06 0a a2 43 04 |         send.smpl (8)             r19     r2             0x00000000  0x0443A20A  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(10) using sampler index 2
skl | 31 00 60 02 08 02 e0 02 40 00 00 06 0b a3 43 04 |         send.smpl (8)             r23     r2             0x00000000  0x0443A30B  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(11) using sampler index 3
skl | 31 00 60 02 08 02 60 03 40 00 00 06 0c a4 43 04 |         send.smpl (8)             r27     r2             0x00000000  0x0443A40C  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(12) using sampler index 4
skl | 31 00 60 02 08 02 e0 03 40 00 00 06 0d a5 43 04 |         send.smpl (8)             r31     r2             0x00000000  0x0443A50D  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(13) using sampler index 5
skl | 31 00 60 02 08 02 60 04 40 00 00 06 0e a6 43 04 |         send.smpl (8)             r35     r2             0x00000000  0x0443A60E  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(14) using sampler index 6
skl | 31 00 60 02 08 02 e0 04 40 00 00 06 0f a7 43 04 |         send.smpl (8)             r39     r2             0x00000000  0x0443A70F  // wr:2+0, rd:4; ld_lz:u,v,r (8) bti(15) using sampler index 7
skl | 31 00 80 02 08 02 a0 0b 40 00 00 06 08 a0 85 08 |         send.smpl (16)            r93     r2             0x00000000  0x0885A008  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(8) using sampler index 0
skl | 31 00 80 02 08 02 60 03 40 00 00 06 09 a1 85 08 |         send.smpl (16)            r27     r2             0x00000000  0x0885A109  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(9) using sampler index 1
skl | 31 00 80 02 08 02 a0 04 40 00 00 06 0a a2 85 08 |         send.smpl (16)            r37     r2             0x00000000  0x0885A20A  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(10) using sampler index 2
skl | 31 00 80 02 08 02 e0 05 40 00 00 06 0b a3 85 08 |         send.smpl (16)            r47     r2             0x00000000  0x0885A30B  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(11) using sampler index 3
skl | 31 00 80 02 08 02 20 07 40 00 00 06 0c a4 85 08 |         send.smpl (16)            r57     r2             0x00000000  0x0885A40C  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(12) using sampler index 4
skl | 31 00 80 02 08 02 60 08 40 00 00 06 0d a5 85 08 |         send.smpl (16)            r67     r2             0x00000000  0x0885A50D  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(13) using sampler index 5
skl | 31 00 80 02 08 02 a0 0a 40 00 00 06 0e a6 85 08 |         send.smpl (16)            r85     r2             0x00000000  0x0885A60E  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(14) using sampler index 6
skl | 31 00 80 02 08 02 a0 09 40 00 00 06 0f a7 85 08 |         send.smpl (16)            r77     r2             0x00000000  0x0885A70F  // wr:4+0, rd:8; ld_lz:u,v,r (16) bti(15) using sampler index 7
skl | 31 00 80 0c 08 02 60 0a c0 0a 00 06 00 5e 20 04 |         send.hdc1 (16)            r83     r86            0x00000000  0x04205E00  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(0)
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 47 00 0a 8c |         send.urb (8)              null    r122           0x00000000  0x0C0A0047   {EOT}  // wr:6h+0, rd:0; simd8_write off=4 per_slot (8)
skl | 31 00 60 02 08 02 c0 01 60 01 00 06 02 02 4b 08 |         send.smpl (8)             r14     r11            0x00000000  0x084B0202  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 01 01 4b 0a |         send.smpl (8)             r6      r6             0x00000000  0x0A4B0101  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(1) using sampler index 1
skl | 31 00 60 06 00 02 00 00 60 00 00 06 87 00 08 12 |         send.urb (8)              null    r3             0x00000000  0x12080087  // wr:9h+0, rd:0; simd8_write off=8 (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 a7 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A0800A7   {EOT}  // wr:5h+0, rd:0; simd8_write off=10 (8)
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 60 1a 08 |         send.smpl (8)             r6      r7             0x00000000  0x081A6001  // wr:4h+0, rd:1; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 60 01 00 06 02 61 1a 08 |         send.smpl (8)             r7      r11            0x00000000  0x081A6102  // wr:4h+0, rd:1; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 01 00 06 01 60 2c 0e |         send.smpl (16)            r10     r12            0x00000000  0x0E2C6001  // wr:7h+0, rd:2; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 60 02 00 06 02 61 2c 0e |         send.smpl (16)            r12     r19            0x00000000  0x0E2C6102  // wr:7h+0, rd:2; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 e0 03 80 03 00 06 38 02 38 02 |         send.urb (8)              r31     r28            0x00000000  0x02380238  // wr:1h+0, rd:3; simd8_read off=35 (8)
skl | 31 00 60 06 08 02 40 04 80 03 00 06 38 04 38 02 |         send.urb (8)              r34     r28            0x00000000  0x02380438  // wr:1h+0, rd:3; simd8_read off=67 (8)
skl | 31 00 60 06 08 02 a0 04 80 03 00 06 38 06 38 02 |         send.urb (8)              r37     r28            0x00000000  0x02380638  // wr:1h+0, rd:3; simd8_read off=99 (8)
skl | 31 00 60 06 08 02 c0 02 80 03 00 06 48 02 38 02 |         send.urb (8)              r22     r28            0x00000000  0x02380248  // wr:1h+0, rd:3; simd8_read off=36 (8)
skl | 31 00 60 06 08 02 20 03 80 03 00 06 48 04 38 02 |         send.urb (8)              r25     r28            0x00000000  0x02380448  // wr:1h+0, rd:3; simd8_read off=68 (8)
skl | 31 00 60 06 08 02 80 03 80 03 00 06 48 06 38 02 |         send.urb (8)              r28     r28            0x00000000  0x02380648  // wr:1h+0, rd:3; simd8_read off=100 (8)
skl | 31 00 60 06 08 02 c0 02 a0 03 00 06 58 02 38 02 |         send.urb (8)              r22     r29            0x00000000  0x02380258  // wr:1h+0, rd:3; simd8_read off=37 (8)
skl | 31 00 60 06 08 02 20 03 a0 03 00 06 58 04 38 02 |         send.urb (8)              r25     r29            0x00000000  0x02380458  // wr:1h+0, rd:3; simd8_read off=69 (8)
skl | 31 00 60 06 08 02 80 03 a0 03 00 06 58 06 38 02 |         send.urb (8)              r28     r29            0x00000000  0x02380658  // wr:1h+0, rd:3; simd8_read off=101 (8)
skl | 31 00 60 06 08 02 c0 02 c0 03 00 06 68 02 38 02 |         send.urb (8)              r22     r30            0x00000000  0x02380268  // wr:1h+0, rd:3; simd8_read off=38 (8)
skl | 31 00 60 06 08 02 20 03 c0 03 00 06 68 04 38 02 |         send.urb (8)              r25     r30            0x00000000  0x02380468  // wr:1h+0, rd:3; simd8_read off=70 (8)
skl | 31 00 60 06 08 02 80 03 c0 03 00 06 68 06 38 02 |         send.urb (8)              r28     r30            0x00000000  0x02380668  // wr:1h+0, rd:3; simd8_read off=102 (8)
skl | 31 00 60 06 08 02 c0 02 e0 03 00 06 78 02 38 02 |         send.urb (8)              r22     r31            0x00000000  0x02380278  // wr:1h+0, rd:3; simd8_read off=39 (8)
skl | 31 00 60 06 08 02 20 03 e0 03 00 06 78 04 38 02 |         send.urb (8)              r25     r31            0x00000000  0x02380478  // wr:1h+0, rd:3; simd8_read off=71 (8)
skl | 31 00 60 06 08 02 80 03 e0 03 00 06 78 06 38 02 |         send.urb (8)              r28     r31            0x00000000  0x02380678  // wr:1h+0, rd:3; simd8_read off=103 (8)
skl | 31 00 60 06 08 02 20 03 00 04 00 06 88 04 38 02 |         send.urb (8)              r25     r32            0x00000000  0x02380488  // wr:1h+0, rd:3; simd8_read off=72 (8)
skl | 31 00 60 06 08 02 c0 02 00 04 00 06 88 02 38 02 |         send.urb (8)              r22     r32            0x00000000  0x02380288  // wr:1h+0, rd:3; simd8_read off=40 (8)
skl | 31 00 60 06 08 02 80 03 00 04 00 06 88 06 38 02 |         send.urb (8)              r28     r32            0x00000000  0x02380688  // wr:1h+0, rd:3; simd8_read off=104 (8)
skl | 31 00 60 06 08 02 20 03 20 04 00 06 98 04 38 02 |         send.urb (8)              r25     r33            0x00000000  0x02380498  // wr:1h+0, rd:3; simd8_read off=73 (8)
skl | 31 00 60 06 08 02 c0 02 20 04 00 06 98 02 38 02 |         send.urb (8)              r22     r33            0x00000000  0x02380298  // wr:1h+0, rd:3; simd8_read off=41 (8)
skl | 31 00 60 06 08 02 80 03 20 04 00 06 98 06 38 02 |         send.urb (8)              r28     r33            0x00000000  0x02380698  // wr:1h+0, rd:3; simd8_read off=105 (8)
skl | 31 00 60 06 08 02 20 03 40 04 00 06 a8 06 38 02 |         send.urb (8)              r25     r34            0x00000000  0x023806A8  // wr:1h+0, rd:3; simd8_read off=106 (8)
skl | 31 00 60 06 08 02 00 01 40 04 00 06 a8 02 38 02 |         send.urb (8)              r8      r34            0x00000000  0x023802A8  // wr:1h+0, rd:3; simd8_read off=42 (8)
skl | 31 00 60 06 08 02 c0 02 40 04 00 06 a8 04 38 02 |         send.urb (8)              r22     r34            0x00000000  0x023804A8  // wr:1h+0, rd:3; simd8_read off=74 (8)
skl | 31 00 60 06 08 02 00 01 60 04 00 06 b8 02 38 02 |         send.urb (8)              r8      r35            0x00000000  0x023802B8  // wr:1h+0, rd:3; simd8_read off=43 (8)
skl | 31 00 60 06 08 02 c0 02 60 04 00 06 b8 04 38 02 |         send.urb (8)              r22     r35            0x00000000  0x023804B8  // wr:1h+0, rd:3; simd8_read off=75 (8)
skl | 31 00 60 06 08 02 20 03 60 04 00 06 b8 06 38 02 |         send.urb (8)              r25     r35            0x00000000  0x023806B8  // wr:1h+0, rd:3; simd8_read off=107 (8)
skl | 31 00 60 06 08 02 00 01 80 04 00 06 c8 02 38 02 |         send.urb (8)              r8      r36            0x00000000  0x023802C8  // wr:1h+0, rd:3; simd8_read off=44 (8)
skl | 31 00 60 06 08 02 c0 02 80 04 00 06 c8 04 38 02 |         send.urb (8)              r22     r36            0x00000000  0x023804C8  // wr:1h+0, rd:3; simd8_read off=76 (8)
skl | 31 00 60 06 08 02 20 03 80 04 00 06 c8 06 38 02 |         send.urb (8)              r25     r36            0x00000000  0x023806C8  // wr:1h+0, rd:3; simd8_read off=108 (8)
skl | 31 00 60 06 08 02 00 01 a0 04 00 06 d8 02 38 02 |         send.urb (8)              r8      r37            0x00000000  0x023802D8  // wr:1h+0, rd:3; simd8_read off=45 (8)
skl | 31 00 60 06 08 02 c0 02 a0 04 00 06 d8 04 38 02 |         send.urb (8)              r22     r37            0x00000000  0x023804D8  // wr:1h+0, rd:3; simd8_read off=77 (8)
skl | 31 00 60 06 08 02 20 03 a0 04 00 06 d8 06 38 02 |         send.urb (8)              r25     r37            0x00000000  0x023806D8  // wr:1h+0, rd:3; simd8_read off=109 (8)
skl | 31 00 60 06 08 02 00 01 c0 04 00 06 e8 02 38 02 |         send.urb (8)              r8      r38            0x00000000  0x023802E8  // wr:1h+0, rd:3; simd8_read off=46 (8)
skl | 31 00 60 06 08 02 c0 02 c0 04 00 06 e8 04 38 02 |         send.urb (8)              r22     r38            0x00000000  0x023804E8  // wr:1h+0, rd:3; simd8_read off=78 (8)
skl | 31 00 60 06 08 02 20 03 c0 04 00 06 e8 06 38 02 |         send.urb (8)              r25     r38            0x00000000  0x023806E8  // wr:1h+0, rd:3; simd8_read off=110 (8)
skl | 31 00 60 06 08 02 00 01 e0 04 00 06 f8 02 38 02 |         send.urb (8)              r8      r39            0x00000000  0x023802F8  // wr:1h+0, rd:3; simd8_read off=47 (8)
skl | 31 00 60 06 08 02 c0 02 e0 04 00 06 f8 04 38 02 |         send.urb (8)              r22     r39            0x00000000  0x023804F8  // wr:1h+0, rd:3; simd8_read off=79 (8)
skl | 31 00 60 06 08 02 20 03 e0 04 00 06 f8 06 38 02 |         send.urb (8)              r25     r39            0x00000000  0x023806F8  // wr:1h+0, rd:3; simd8_read off=111 (8)
skl | 31 00 60 06 08 02 00 01 00 05 00 06 08 03 38 02 |         send.urb (8)              r8      r40            0x00000000  0x02380308  // wr:1h+0, rd:3; simd8_read off=48 (8)
skl | 31 00 60 06 08 02 60 01 00 05 00 06 08 05 38 02 |         send.urb (8)              r11     r40            0x00000000  0x02380508  // wr:1h+0, rd:3; simd8_read off=80 (8)
skl | 31 00 60 06 08 02 c0 02 00 05 00 06 08 07 38 02 |         send.urb (8)              r22     r40            0x00000000  0x02380708  // wr:1h+0, rd:3; simd8_read off=112 (8)
skl | 31 00 60 06 08 02 00 01 20 05 00 06 18 03 38 02 |         send.urb (8)              r8      r41            0x00000000  0x02380318  // wr:1h+0, rd:3; simd8_read off=49 (8)
skl | 31 00 60 06 08 02 60 01 20 05 00 06 18 05 38 02 |         send.urb (8)              r11     r41            0x00000000  0x02380518  // wr:1h+0, rd:3; simd8_read off=81 (8)
skl | 31 00 60 06 08 02 c0 02 20 05 00 06 18 07 38 02 |         send.urb (8)              r22     r41            0x00000000  0x02380718  // wr:1h+0, rd:3; simd8_read off=113 (8)
skl | 31 00 60 06 08 02 00 01 60 00 00 06 28 03 38 02 |         send.urb (8)              r8      r3             0x00000000  0x02380328  // wr:1h+0, rd:3; simd8_read off=50 (8)
skl | 31 00 60 06 08 02 60 01 60 00 00 06 28 05 38 02 |         send.urb (8)              r11     r3             0x00000000  0x02380528  // wr:1h+0, rd:3; simd8_read off=82 (8)
skl | 31 00 60 06 08 02 c0 02 60 00 00 06 28 07 38 02 |         send.urb (8)              r22     r3             0x00000000  0x02380728  // wr:1h+0, rd:3; simd8_read off=114 (8)
skl | 31 00 60 06 08 02 00 01 60 05 00 06 38 03 38 02 |         send.urb (8)              r8      r43            0x00000000  0x02380338  // wr:1h+0, rd:3; simd8_read off=51 (8)
skl | 31 00 60 06 08 02 60 01 60 05 00 06 38 05 38 02 |         send.urb (8)              r11     r43            0x00000000  0x02380538  // wr:1h+0, rd:3; simd8_read off=83 (8)
skl | 31 00 60 06 08 02 c0 02 60 05 00 06 38 07 38 02 |         send.urb (8)              r22     r43            0x00000000  0x02380738  // wr:1h+0, rd:3; simd8_read off=115 (8)
skl | 31 00 60 06 08 02 00 01 80 05 00 06 48 03 38 02 |         send.urb (8)              r8      r44            0x00000000  0x02380348  // wr:1h+0, rd:3; simd8_read off=52 (8)
skl | 31 00 60 06 08 02 60 01 80 05 00 06 48 05 38 02 |         send.urb (8)              r11     r44            0x00000000  0x02380548  // wr:1h+0, rd:3; simd8_read off=84 (8)
skl | 31 00 60 06 08 02 c0 02 80 05 00 06 48 07 38 02 |         send.urb (8)              r22     r44            0x00000000  0x02380748  // wr:1h+0, rd:3; simd8_read off=116 (8)
skl | 31 00 60 06 08 02 00 01 a0 05 00 06 58 03 38 02 |         send.urb (8)              r8      r45            0x00000000  0x02380358  // wr:1h+0, rd:3; simd8_read off=53 (8)
skl | 31 00 60 06 08 02 60 01 a0 05 00 06 58 05 38 02 |         send.urb (8)              r11     r45            0x00000000  0x02380558  // wr:1h+0, rd:3; simd8_read off=85 (8)
skl | 31 00 60 06 08 02 c0 02 a0 05 00 06 58 07 38 02 |         send.urb (8)              r22     r45            0x00000000  0x02380758  // wr:1h+0, rd:3; simd8_read off=117 (8)
skl | 31 00 60 06 08 02 00 01 c0 05 00 06 68 03 38 02 |         send.urb (8)              r8      r46            0x00000000  0x02380368  // wr:1h+0, rd:3; simd8_read off=54 (8)
skl | 31 00 60 06 08 02 60 01 c0 05 00 06 68 05 38 02 |         send.urb (8)              r11     r46            0x00000000  0x02380568  // wr:1h+0, rd:3; simd8_read off=86 (8)
skl | 31 00 60 06 08 02 c0 01 c0 05 00 06 68 07 38 02 |         send.urb (8)              r14     r46            0x00000000  0x02380768  // wr:1h+0, rd:3; simd8_read off=118 (8)
skl | 31 00 60 06 08 02 00 01 e0 05 00 06 78 03 38 02 |         send.urb (8)              r8      r47            0x00000000  0x02380378  // wr:1h+0, rd:3; simd8_read off=55 (8)
skl | 31 00 60 06 08 02 60 01 e0 05 00 06 78 05 38 02 |         send.urb (8)              r11     r47            0x00000000  0x02380578  // wr:1h+0, rd:3; simd8_read off=87 (8)
skl | 31 00 60 06 08 02 c0 01 e0 05 00 06 78 07 38 02 |         send.urb (8)              r14     r47            0x00000000  0x02380778  // wr:1h+0, rd:3; simd8_read off=119 (8)
skl | 31 00 60 06 08 02 00 01 00 06 00 06 88 03 38 02 |         send.urb (8)              r8      r48            0x00000000  0x02380388  // wr:1h+0, rd:3; simd8_read off=56 (8)
skl | 31 00 60 06 08 02 60 01 00 06 00 06 88 05 38 02 |         send.urb (8)              r11     r48            0x00000000  0x02380588  // wr:1h+0, rd:3; simd8_read off=88 (8)
skl | 31 00 60 06 08 02 c0 01 00 06 00 06 88 07 38 02 |         send.urb (8)              r14     r48            0x00000000  0x02380788  // wr:1h+0, rd:3; simd8_read off=120 (8)
skl | 31 00 60 06 08 02 00 01 20 06 00 06 98 03 38 02 |         send.urb (8)              r8      r49            0x00000000  0x02380398  // wr:1h+0, rd:3; simd8_read off=57 (8)
skl | 31 00 60 06 08 02 60 01 20 06 00 06 98 05 38 02 |         send.urb (8)              r11     r49            0x00000000  0x02380598  // wr:1h+0, rd:3; simd8_read off=89 (8)
skl | 31 00 60 06 08 02 c0 01 20 06 00 06 98 07 38 02 |         send.urb (8)              r14     r49            0x00000000  0x02380798  // wr:1h+0, rd:3; simd8_read off=121 (8)
skl | 31 00 60 06 08 02 00 01 40 06 00 06 a8 03 38 02 |         send.urb (8)              r8      r50            0x00000000  0x023803A8  // wr:1h+0, rd:3; simd8_read off=58 (8)
skl | 31 00 60 06 08 02 60 01 40 06 00 06 a8 05 38 02 |         send.urb (8)              r11     r50            0x00000000  0x023805A8  // wr:1h+0, rd:3; simd8_read off=90 (8)
skl | 31 00 60 06 08 02 c0 01 40 06 00 06 a8 07 38 02 |         send.urb (8)              r14     r50            0x00000000  0x023807A8  // wr:1h+0, rd:3; simd8_read off=122 (8)
skl | 31 00 60 06 08 02 00 01 c0 06 00 06 b8 03 38 02 |         send.urb (8)              r8      r54            0x00000000  0x023803B8  // wr:1h+0, rd:3; simd8_read off=59 (8)
skl | 31 00 60 06 08 02 60 01 c0 06 00 06 b8 05 38 02 |         send.urb (8)              r11     r54            0x00000000  0x023805B8  // wr:1h+0, rd:3; simd8_read off=91 (8)
skl | 31 00 60 06 08 02 c0 01 c0 06 00 06 b8 07 38 02 |         send.urb (8)              r14     r54            0x00000000  0x023807B8  // wr:1h+0, rd:3; simd8_read off=123 (8)
skl | 31 00 60 06 08 02 00 01 e0 06 00 06 c8 03 38 02 |         send.urb (8)              r8      r55            0x00000000  0x023803C8  // wr:1h+0, rd:3; simd8_read off=60 (8)
skl | 31 00 60 06 08 02 60 01 e0 06 00 06 c8 05 38 02 |         send.urb (8)              r11     r55            0x00000000  0x023805C8  // wr:1h+0, rd:3; simd8_read off=92 (8)
skl | 31 00 60 06 08 02 c0 01 e0 06 00 06 c8 07 38 02 |         send.urb (8)              r14     r55            0x00000000  0x023807C8  // wr:1h+0, rd:3; simd8_read off=124 (8)
skl | 31 00 60 06 08 02 00 01 00 07 00 06 d8 03 38 02 |         send.urb (8)              r8      r56            0x00000000  0x023803D8  // wr:1h+0, rd:3; simd8_read off=61 (8)
skl | 31 00 60 06 08 02 60 01 00 07 00 06 d8 05 38 02 |         send.urb (8)              r11     r56            0x00000000  0x023805D8  // wr:1h+0, rd:3; simd8_read off=93 (8)
skl | 31 00 60 06 08 02 c0 01 00 07 00 06 d8 07 38 02 |         send.urb (8)              r14     r56            0x00000000  0x023807D8  // wr:1h+0, rd:3; simd8_read off=125 (8)
skl | 31 00 60 06 08 02 00 01 20 07 00 06 e8 03 38 02 |         send.urb (8)              r8      r57            0x00000000  0x023803E8  // wr:1h+0, rd:3; simd8_read off=62 (8)
skl | 31 00 60 06 08 02 60 01 20 07 00 06 e8 05 38 02 |         send.urb (8)              r11     r57            0x00000000  0x023805E8  // wr:1h+0, rd:3; simd8_read off=94 (8)
skl | 31 00 60 06 08 02 c0 01 20 07 00 06 e8 07 38 02 |         send.urb (8)              r14     r57            0x00000000  0x023807E8  // wr:1h+0, rd:3; simd8_read off=126 (8)
skl | 31 00 60 06 08 02 00 01 40 07 00 06 f8 03 38 02 |         send.urb (8)              r8      r58            0x00000000  0x023803F8  // wr:1h+0, rd:3; simd8_read off=63 (8)
skl | 31 00 60 06 08 02 60 01 40 07 00 06 f8 05 38 02 |         send.urb (8)              r11     r58            0x00000000  0x023805F8  // wr:1h+0, rd:3; simd8_read off=95 (8)
skl | 31 00 60 06 08 02 c0 01 40 07 00 06 f8 07 38 02 |         send.urb (8)              r14     r58            0x00000000  0x023807F8  // wr:1h+0, rd:3; simd8_read off=127 (8)
skl | 31 00 60 06 08 02 00 01 60 07 00 06 08 02 38 02 |         send.urb (8)              r8      r59            0x00000000  0x02380208  // wr:1h+0, rd:3; simd8_read off=32 (8)
skl | 31 00 60 06 08 02 60 01 60 07 00 06 08 04 38 02 |         send.urb (8)              r11     r59            0x00000000  0x02380408  // wr:1h+0, rd:3; simd8_read off=64 (8)
skl | 31 00 60 06 08 02 c0 01 60 07 00 06 08 06 38 02 |         send.urb (8)              r14     r59            0x00000000  0x02380608  // wr:1h+0, rd:3; simd8_read off=96 (8)
skl | 31 00 60 06 08 02 20 02 60 07 00 06 08 08 38 02 |         send.urb (8)              r17     r59            0x00000000  0x02380808  // wr:1h+0, rd:3; simd8_read off=128 (8)
skl | 31 00 60 06 08 02 00 01 80 07 00 06 18 02 38 02 |         send.urb (8)              r8      r60            0x00000000  0x02380218  // wr:1h+0, rd:3; simd8_read off=33 (8)
skl | 31 00 60 06 08 02 60 01 80 07 00 06 18 04 38 02 |         send.urb (8)              r11     r60            0x00000000  0x02380418  // wr:1h+0, rd:3; simd8_read off=65 (8)
skl | 31 00 60 06 08 02 c0 01 80 07 00 06 18 06 38 02 |         send.urb (8)              r14     r60            0x00000000  0x02380618  // wr:1h+0, rd:3; simd8_read off=97 (8)
skl | 31 00 60 06 08 02 20 02 80 07 00 06 18 08 38 02 |         send.urb (8)              r17     r60            0x00000000  0x02380818  // wr:1h+0, rd:3; simd8_read off=129 (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 67 80 0a 0c |         send.urb (8)              null    r14            0x00000000  0x0C0A8067  // wr:6h+0, rd:0; simd8_write off=6 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 77 80 0a 0c |         send.urb (8)              null    r15            0x00000000  0x0C0A8077  // wr:6h+0, rd:0; simd8_write off=7 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 87 80 0a 0c |         send.urb (8)              null    r16            0x00000000  0x0C0A8087  // wr:6h+0, rd:0; simd8_write off=8 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 97 80 0a 0c |         send.urb (8)              null    r17            0x00000000  0x0C0A8097  // wr:6h+0, rd:0; simd8_write off=9 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 a7 80 0a 0c |         send.urb (8)              null    r18            0x00000000  0x0C0A80A7  // wr:6h+0, rd:0; simd8_write off=10 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 b7 80 0a 0c |         send.urb (8)              null    r19            0x00000000  0x0C0A80B7  // wr:6h+0, rd:0; simd8_write off=11 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 c7 80 0a 0c |         send.urb (8)              null    r20            0x00000000  0x0C0A80C7  // wr:6h+0, rd:0; simd8_write off=12 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 d7 80 0a 0c |         send.urb (8)              null    r21            0x00000000  0x0C0A80D7  // wr:6h+0, rd:0; simd8_write off=13 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 e7 80 0a 0c |         send.urb (8)              null    r22            0x00000000  0x0C0A80E7  // wr:6h+0, rd:0; simd8_write off=14 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 f7 80 0a 0c |         send.urb (8)              null    r23            0x00000000  0x0C0A80F7  // wr:6h+0, rd:0; simd8_write off=15 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 07 81 0a 0c |         send.urb (8)              null    r24            0x00000000  0x0C0A8107  // wr:6h+0, rd:0; simd8_write off=16 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 17 81 0a 0c |         send.urb (8)              null    r25            0x00000000  0x0C0A8117  // wr:6h+0, rd:0; simd8_write off=17 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 27 81 0a 0c |         send.urb (8)              null    r26            0x00000000  0x0C0A8127  // wr:6h+0, rd:0; simd8_write off=18 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 37 81 0a 0c |         send.urb (8)              null    r27            0x00000000  0x0C0A8137  // wr:6h+0, rd:0; simd8_write off=19 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 47 81 0a 0c |         send.urb (8)              null    r28            0x00000000  0x0C0A8147  // wr:6h+0, rd:0; simd8_write off=20 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 57 81 0a 0c |         send.urb (8)              null    r29            0x00000000  0x0C0A8157  // wr:6h+0, rd:0; simd8_write off=21 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 67 81 0a 0c |         send.urb (8)              null    r30            0x00000000  0x0C0A8167  // wr:6h+0, rd:0; simd8_write off=22 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 77 81 0a 0c |         send.urb (8)              null    r31            0x00000000  0x0C0A8177  // wr:6h+0, rd:0; simd8_write off=23 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 87 81 0a 0c |         send.urb (8)              null    r32            0x00000000  0x0C0A8187  // wr:6h+0, rd:0; simd8_write off=24 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 97 81 0a 0c |         send.urb (8)              null    r33            0x00000000  0x0C0A8197  // wr:6h+0, rd:0; simd8_write off=25 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 a7 81 0a 0c |         send.urb (8)              null    r34            0x00000000  0x0C0A81A7  // wr:6h+0, rd:0; simd8_write off=26 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 b7 81 0a 0c |         send.urb (8)              null    r35            0x00000000  0x0C0A81B7  // wr:6h+0, rd:0; simd8_write off=27 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 c7 81 0a 0c |         send.urb (8)              null    r36            0x00000000  0x0C0A81C7  // wr:6h+0, rd:0; simd8_write off=28 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 d7 81 0a 0c |         send.urb (8)              null    r37            0x00000000  0x0C0A81D7  // wr:6h+0, rd:0; simd8_write off=29 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 e7 81 0a 0c |         send.urb (8)              null    r38            0x00000000  0x0C0A81E7  // wr:6h+0, rd:0; simd8_write off=30 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 f7 81 0a 0c |         send.urb (8)              null    r39            0x00000000  0x0C0A81F7  // wr:6h+0, rd:0; simd8_write off=31 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 07 82 0a 0c |         send.urb (8)              null    r40            0x00000000  0x0C0A8207  // wr:6h+0, rd:0; simd8_write off=32 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 05 00 06 17 82 0a 0c |         send.urb (8)              null    r41            0x00000000  0x0C0A8217  // wr:6h+0, rd:0; simd8_write off=33 masked per_slot (8)
skl | 31 00 60 0c 08 02 80 0f 40 00 00 06 01 6e 10 02 |         send.hdc1 (8)             r124    r2             0x00000000  0x02106E01  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(1)
skl | 31 00 80 0c 08 02 60 01 60 02 00 06 01 a6 20 04 |         send.hdc1 (16)            r11     r19            0x00000000  0x0420A601  // wr:2+0, rd:2; untyped_atomic_dec simd16 (16) bti(1)
skl | 31 00 80 0c 00 02 00 00 80 02 00 06 03 85 00 04 |         send.hdc1 (16)            null    r20            0x00000000  0x04008503  // wr:2+0, rd:0; untyped_atomic_inc simd16 (16) bti(3)
skl | 31 00 60 02 08 02 20 02 60 01 00 06 01 e0 13 08 |         send.smpl (8)             r17     r11            0x00000000  0x0813E001  // wr:4+0, rd:1; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 02 40 00 00 06 01 e0 25 10 |         send.smpl (16)            r22     r2             0x00000000  0x1025E001  // wr:8+0, rd:2; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 40 0f 00 06 07 80 08 8c |         send.urb (8)              null    r122           0x00000000  0x0C088007   {EOT}  // wr:6h+0, rd:0; simd8_write masked (8)
skl | 31 00 60 02 08 02 40 00 40 00 00 06 01 30 42 06 |         send.smpl (8)             r2      r2             0x00000000  0x06423001  // wr:3+0, rd:4; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 02 31 42 06 |         send.smpl (8)             r6      r6             0x00000000  0x06423102  // wr:3+0, rd:4; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 80 02 00 06 01 30 84 0c |         send.smpl (16)            r2      r20            0x00000000  0x0C843001  // wr:6+0, rd:8; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 40 03 00 06 02 31 84 0c |         send.smpl (16)            r10     r26            0x00000000  0x0C843102  // wr:6+0, rd:8; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 01 c0 01 00 06 01 50 1a 0a |         send.smpl (8)             r14     r14            0x00000000  0x0A1A5001  // wr:5h+0, rd:1; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 01 60 02 00 06 02 51 1a 0a |         send.smpl (8)             r15     r19            0x00000000  0x0A1A5102  // wr:5h+0, rd:1; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 e0 04 e0 00 00 06 01 50 2c 12 |         send.smpl (16)            r39     r7             0x00000000  0x122C5001  // wr:9h+0, rd:2; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 20 05 00 02 00 06 02 51 2c 12 |         send.smpl (16)            r41     r16            0x00000000  0x122C5102  // wr:9h+0, rd:2; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 01 20 4b 0c |         send.smpl (8)             r2      r13            0x00000000  0x0C4B2001  // wr:6h+0, rd:4; gather4_po_c (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 05 e0 00 00 06 01 20 8d 16 |         send.smpl (16)            r43     r7             0x00000000  0x168D2001  // wr:11h+0, rd:8; gather4_po_c (16) bti(1) using sampler index 0
skl | 31 00 60 06 08 02 c0 06 e0 00 00 06 48 00 28 02 |         send.urb (8)              r54     r7             0x00000000  0x02280048  // wr:1h+0, rd:2; simd8_read off=4 (8)
skl | 31 00 60 02 08 02 40 00 00 01 00 06 01 00 42 02 |         send.smpl (8)             r2      r8             0x00000000  0x02420001  // wr:1+0, rd:4; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 e0 01 00 06 01 00 84 04 |         send.smpl (16)            r2      r15            0x00000000  0x04840001  // wr:2+0, rd:8; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 0c 08 02 e0 00 80 05 00 06 00 6e 10 02 |         send.hdc1 (8)             r7      r44            0x00000000  0x02106E00  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(0)
skl | 31 00 60 0c 00 02 00 00 80 05 00 06 00 95 00 02 |         send.hdc1 (8)             null    r44            0x00000000  0x02009500  // wr:1+0, rd:0; untyped_atomic_inc simd8 (8) bti(0)
skl | 31 00 60 06 08 02 e0 00 a0 04 00 06 38 04 48 02 |         send.urb (8)              r7      r37            0x00000000  0x02480438  // wr:1h+0, rd:4; simd8_read off=67 (8)
skl | 31 00 60 06 08 02 60 01 a0 04 00 06 38 06 48 02 |         send.urb (8)              r11     r37            0x00000000  0x02480638  // wr:1h+0, rd:4; simd8_read off=99 (8)
skl | 31 00 60 06 08 02 a0 01 c0 01 00 06 48 01 2a 04 |         send.urb (8)              r13     r14            0x00000000  0x042A0148  // wr:2h+0, rd:2; simd8_read off=20 per_slot (8)
skl | 31 00 60 06 08 02 40 00 c0 01 00 06 48 00 2a 04 |         send.urb (8)              r2      r14            0x00000000  0x042A0048  // wr:2h+0, rd:2; simd8_read off=4 per_slot (8)
skl | 31 00 60 02 08 02 80 0f a0 01 00 06 00 c0 43 0c |         send.smpl (8)             r124    r13            0x00000000  0x0C43C000  // wr:6+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 c0 02 c0 01 00 06 04 84 4a 06 |         send.smpl (8)             r22     r14            0x00000000  0x064A8404  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 c0 01 40 01 00 06 02 82 4a 08 |         send.smpl (8)             r14     r10            0x00000000  0x084A8202  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 40 02 40 03 00 06 03 83 4a 0a |         send.smpl (8)             r18     r26            0x00000000  0x0A4A8303  // wr:5h+0, rd:4; gather4:u,v,r,ai (8) bti(3) using sampler index 3
skl | 31 00 60 02 08 02 c0 00 c0 01 00 06 02 41 43 0e |         send.smpl (8)             r6      r14            0x00000000  0x0E434102  // wr:7+0, rd:4; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 00 01 e0 00 00 06 01 40 1b 12 |         send.smpl (8)             r8      r7             0x00000000  0x121B4001  // wr:9h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 20 01 00 02 00 06 02 41 1b 12 |         send.smpl (8)             r9      r16            0x00000000  0x121B4102  // wr:9h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 40 00 40 00 00 06 78 00 38 02 |         send.urb (8)              r2      r2             0x00000000  0x02380078  // wr:1h+0, rd:3; simd8_read off=7 (8)
skl | 31 00 60 02 08 02 c0 01 40 01 00 06 03 82 4a 06 |         send.smpl (8)             r14     r10            0x00000000  0x064A8203  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 03 40 04 00 06 03 82 8c 0a |         send.smpl (16)            r26     r34            0x00000000  0x0A8C8203  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 60 06 08 02 40 06 60 06 00 06 18 00 18 02 |         send.urb (8)              r50     r51            0x00000000  0x02180018  // wr:1h+0, rd:1; simd8_read off=1 (8)
skl | 31 00 60 02 08 02 60 07 00 08 00 06 02 70 42 02 |         send.smpl (8)             r59     r64            0x00000000  0x02427002  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(2) using sampler index 0
skl | 31 00 60 02 08 02 40 00 00 08 00 06 03 70 42 02 |         send.smpl (8)             r2      r64            0x00000000  0x02427003  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(3) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 00 08 00 06 04 70 42 02 |         send.smpl (8)             r6      r64            0x00000000  0x02427004  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(4) using sampler index 0
skl | 31 00 60 02 08 02 40 01 00 08 00 06 05 70 42 02 |         send.smpl (8)             r10     r64            0x00000000  0x02427005  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(5) using sampler index 0
skl | 31 00 60 02 08 02 c0 01 00 08 00 06 06 70 42 02 |         send.smpl (8)             r14     r64            0x00000000  0x02427006  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(6) using sampler index 0
skl | 31 00 60 02 08 02 40 02 00 08 00 06 07 70 42 02 |         send.smpl (8)             r18     r64            0x00000000  0x02427007  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(7) using sampler index 0
skl | 31 00 60 02 08 02 c0 02 00 08 00 06 08 70 42 02 |         send.smpl (8)             r22     r64            0x00000000  0x02427008  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(8) using sampler index 0
skl | 31 00 60 02 08 02 40 03 00 08 00 06 09 70 42 02 |         send.smpl (8)             r26     r64            0x00000000  0x02427009  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(9) using sampler index 0
skl | 31 00 60 02 08 02 c0 03 00 08 00 06 0a 70 42 02 |         send.smpl (8)             r30     r64            0x00000000  0x0242700A  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(10) using sampler index 0
skl | 31 00 60 02 08 02 40 04 00 08 00 06 0b 70 42 02 |         send.smpl (8)             r34     r64            0x00000000  0x0242700B  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(11) using sampler index 0
skl | 31 00 60 02 08 02 c0 04 00 08 00 06 0c 70 42 02 |         send.smpl (8)             r38     r64            0x00000000  0x0242700C  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(12) using sampler index 0
skl | 31 00 60 02 08 02 40 05 00 08 00 06 0d 70 42 02 |         send.smpl (8)             r42     r64            0x00000000  0x0242700D  // wr:1+0, rd:4; ld:u,v,lod,r (8) bti(13) using sampler index 0
skl | 31 00 60 02 08 02 80 0f c0 00 00 06 05 85 43 04 |         send.smpl (8)             r124    r6             0x00000000  0x04438505  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(5) using sampler index 5
skl | 31 00 60 06 00 02 00 00 00 02 00 06 67 80 08 0a |         send.urb (8)              null    r16            0x00000000  0x0A088067  // wr:5h+0, rd:0; simd8_write off=6 masked (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 77 80 08 0a |         send.urb (8)              null    r17            0x00000000  0x0A088077  // wr:5h+0, rd:0; simd8_write off=7 masked (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 87 80 08 0a |         send.urb (8)              null    r18            0x00000000  0x0A088087  // wr:5h+0, rd:0; simd8_write off=8 masked (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 97 80 08 0a |         send.urb (8)              null    r19            0x00000000  0x0A088097  // wr:5h+0, rd:0; simd8_write off=9 masked (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 a7 80 08 0a |         send.urb (8)              null    r20            0x00000000  0x0A0880A7  // wr:5h+0, rd:0; simd8_write off=10 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 b7 80 08 0a |         send.urb (8)              null    r21            0x00000000  0x0A0880B7  // wr:5h+0, rd:0; simd8_write off=11 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 c7 80 08 0a |         send.urb (8)              null    r22            0x00000000  0x0A0880C7  // wr:5h+0, rd:0; simd8_write off=12 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 d7 80 08 0a |         send.urb (8)              null    r23            0x00000000  0x0A0880D7  // wr:5h+0, rd:0; simd8_write off=13 masked (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 e7 80 08 0a |         send.urb (8)              null    r24            0x00000000  0x0A0880E7  // wr:5h+0, rd:0; simd8_write off=14 masked (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 f7 80 08 0a |         send.urb (8)              null    r25            0x00000000  0x0A0880F7  // wr:5h+0, rd:0; simd8_write off=15 masked (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 07 81 08 0a |         send.urb (8)              null    r26            0x00000000  0x0A088107  // wr:5h+0, rd:0; simd8_write off=16 masked (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 17 81 08 0a |         send.urb (8)              null    r27            0x00000000  0x0A088117  // wr:5h+0, rd:0; simd8_write off=17 masked (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 27 81 08 0a |         send.urb (8)              null    r28            0x00000000  0x0A088127  // wr:5h+0, rd:0; simd8_write off=18 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 37 81 08 0a |         send.urb (8)              null    r29            0x00000000  0x0A088137  // wr:5h+0, rd:0; simd8_write off=19 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 47 81 08 0a |         send.urb (8)              null    r30            0x00000000  0x0A088147  // wr:5h+0, rd:0; simd8_write off=20 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 57 81 08 0a |         send.urb (8)              null    r31            0x00000000  0x0A088157  // wr:5h+0, rd:0; simd8_write off=21 masked (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 67 81 08 0a |         send.urb (8)              null    r32            0x00000000  0x0A088167  // wr:5h+0, rd:0; simd8_write off=22 masked (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 77 81 08 0a |         send.urb (8)              null    r33            0x00000000  0x0A088177  // wr:5h+0, rd:0; simd8_write off=23 masked (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 87 81 08 0a |         send.urb (8)              null    r34            0x00000000  0x0A088187  // wr:5h+0, rd:0; simd8_write off=24 masked (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 97 81 08 0a |         send.urb (8)              null    r35            0x00000000  0x0A088197  // wr:5h+0, rd:0; simd8_write off=25 masked (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 a7 81 08 0a |         send.urb (8)              null    r36            0x00000000  0x0A0881A7  // wr:5h+0, rd:0; simd8_write off=26 masked (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 b7 81 08 0a |         send.urb (8)              null    r37            0x00000000  0x0A0881B7  // wr:5h+0, rd:0; simd8_write off=27 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 c7 81 08 0a |         send.urb (8)              null    r38            0x00000000  0x0A0881C7  // wr:5h+0, rd:0; simd8_write off=28 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 d7 81 08 0a |         send.urb (8)              null    r39            0x00000000  0x0A0881D7  // wr:5h+0, rd:0; simd8_write off=29 masked (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 e7 81 08 0a |         send.urb (8)              null    r40            0x00000000  0x0A0881E7  // wr:5h+0, rd:0; simd8_write off=30 masked (8)
skl | 31 00 60 06 00 02 00 00 20 05 00 06 f7 81 08 0a |         send.urb (8)              null    r41            0x00000000  0x0A0881F7  // wr:5h+0, rd:0; simd8_write off=31 masked (8)
skl | 31 00 60 06 00 02 00 00 80 00 00 06 27 80 0a 0e |         send.urb (8)              null    r4             0x00000000  0x0E0A8027  // wr:7h+0, rd:0; simd8_write off=2 masked per_slot (8)
skl | 31 00 60 02 08 02 a0 00 c0 00 00 06 01 30 12 04 |         send.smpl (8)             r5      r6             0x00000000  0x04123001  // wr:2+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 40 00 00 06 02 31 12 04 |         send.smpl (8)             r6      r2             0x00000000  0x04123102  // wr:2+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 20 01 60 01 00 06 01 30 24 08 |         send.smpl (16)            r9      r11            0x00000000  0x08243001  // wr:4+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 01 40 00 00 06 02 31 24 08 |         send.smpl (16)            r11     r2             0x00000000  0x08243102  // wr:4+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 40 00 00 06 02 d0 43 04 |         send.smpl (8)             r2      r2             0x00000000  0x0443D002  // wr:2+0, rd:4; ld_mcs:u,v,r,lod (8) bti(2) using sampler index 0
skl | 31 00 60 02 08 02 60 00 c0 01 00 06 02 c1 43 0a |         send.smpl (8)             r3      r14            0x00000000  0x0A43C102  // wr:5+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 40 01 00 06 02 d0 85 08 |         send.smpl (16)            r2      r10            0x00000000  0x0885D002  // wr:4+0, rd:8; ld_mcs:u,v,r,lod (16) bti(2) using sampler index 0
skl | 31 00 80 02 08 02 60 00 20 03 00 06 02 c1 85 14 |         send.smpl (16)            r3      r25            0x00000000  0x1485C102  // wr:10+0, rd:8; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 01 60 01 00 06 01 30 12 0a |         send.smpl (8)             r10     r11            0x00000000  0x0A123001  // wr:5+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 60 01 00 02 00 06 02 31 12 0a |         send.smpl (8)             r11     r16            0x00000000  0x0A123102  // wr:5+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 04 20 01 00 06 01 30 24 14 |         send.smpl (16)            r34     r9             0x00000000  0x14243001  // wr:10+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 04 60 02 00 06 02 31 24 14 |         send.smpl (16)            r36     r19            0x00000000  0x14243102  // wr:10+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 e0 00 00 06 01 60 42 08 |         send.smpl (8)             r2      r7             0x00000000  0x08426001  // wr:4+0, rd:4; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 02 61 42 08 |         send.smpl (8)             r6      r11            0x00000000  0x08426102  // wr:4+0, rd:4; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 60 01 00 06 01 60 84 10 |         send.smpl (16)            r2      r11            0x00000000  0x10846001  // wr:8+0, rd:8; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 60 02 00 06 02 61 84 10 |         send.smpl (16)            r10     r19            0x00000000  0x10846102  // wr:8+0, rd:8; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 61 0c 0a 02 80 00 40 01 00 06 02 b5 10 02 | (f1.0)  send.hdc1 (8)             r4      r10            0x00000000  0x0210B502  // wr:1+0, rd:1; untyped_atomic_inc simd8 (8) bti(2)
skl | 31 00 81 0c 0a 02 a0 00 a0 01 00 06 02 a5 20 04 | (f1.0)  send.hdc1 (16)            r5      r13            0x00000000  0x0420A502  // wr:2+0, rd:2; untyped_atomic_inc simd16 (16) bti(2)
skl | 31 00 60 02 08 02 00 01 20 01 00 06 01 10 32 06 |         send.smpl (8)             r8      r9             0x00000000  0x06321001  // wr:3+0, rd:3; sample_b (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 c0 01 00 06 01 10 64 0c |         send.smpl (16)            r2      r14            0x00000000  0x0C641001  // wr:6+0, rd:6; sample_b (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f c0 00 00 06 00 80 33 04 |         send.smpl (8)             r124    r6             0x00000000  0x04338000  // wr:2+0, rd:3; sample_lz:u,v,r,ai (8) bti(0) using sampler index 0
skl | 31 00 60 06 08 02 80 01 20 00 00 06 58 00 28 02 |         send.urb (8)              r12     r1             0x00000000  0x02280058  // wr:1h+0, rd:2; simd8_read off=5 (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 67 80 0a 0e |         send.urb (8)              null    r12            0x00000000  0x0E0A8067  // wr:7h+0, rd:0; simd8_write off=6 masked per_slot (8)
skl | 31 00 60 06 08 02 80 01 20 00 00 06 78 00 28 02 |         send.urb (8)              r12     r1             0x00000000  0x02280078  // wr:1h+0, rd:2; simd8_read off=7 (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 87 80 0a 0e |         send.urb (8)              null    r12            0x00000000  0x0E0A8087  // wr:7h+0, rd:0; simd8_write off=8 masked per_slot (8)
skl | 31 00 60 06 08 02 80 01 20 00 00 06 98 00 28 02 |         send.urb (8)              r12     r1             0x00000000  0x02280098  // wr:1h+0, rd:2; simd8_read off=9 (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 a7 80 0a 0e |         send.urb (8)              null    r12            0x00000000  0x0E0A80A7  // wr:7h+0, rd:0; simd8_write off=10 masked per_slot (8)
skl | 31 00 80 02 08 02 20 01 20 02 00 06 02 70 84 04 |         send.smpl (16)            r9      r17            0x00000000  0x04847002  // wr:2+0, rd:8; ld:u,v,lod,r (16) bti(2) using sampler index 0
skl | 31 00 80 0c 08 02 e0 02 00 04 00 06 02 5e 20 04 |         send.hdc1 (16)            r23     r32            0x00000000  0x04205E02  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(2)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 68 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280068  // wr:1h+0, rd:2; simd8_read off=6 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 88 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280088  // wr:1h+0, rd:2; simd8_read off=8 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 a8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800A8  // wr:1h+0, rd:2; simd8_read off=10 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 b8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800B8  // wr:1h+0, rd:2; simd8_read off=11 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 c8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800C8  // wr:1h+0, rd:2; simd8_read off=12 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 d8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800D8  // wr:1h+0, rd:2; simd8_read off=13 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 e8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800E8  // wr:1h+0, rd:2; simd8_read off=14 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 f8 00 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022800F8  // wr:1h+0, rd:2; simd8_read off=15 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 08 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280108  // wr:1h+0, rd:2; simd8_read off=16 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 18 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280118  // wr:1h+0, rd:2; simd8_read off=17 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 28 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280128  // wr:1h+0, rd:2; simd8_read off=18 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 38 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280138  // wr:1h+0, rd:2; simd8_read off=19 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 48 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280148  // wr:1h+0, rd:2; simd8_read off=20 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 58 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280158  // wr:1h+0, rd:2; simd8_read off=21 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 68 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280168  // wr:1h+0, rd:2; simd8_read off=22 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 78 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280178  // wr:1h+0, rd:2; simd8_read off=23 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 88 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280188  // wr:1h+0, rd:2; simd8_read off=24 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 98 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280198  // wr:1h+0, rd:2; simd8_read off=25 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 a8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801A8  // wr:1h+0, rd:2; simd8_read off=26 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 b8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801B8  // wr:1h+0, rd:2; simd8_read off=27 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 c8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801C8  // wr:1h+0, rd:2; simd8_read off=28 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 d8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801D8  // wr:1h+0, rd:2; simd8_read off=29 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 e8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801E8  // wr:1h+0, rd:2; simd8_read off=30 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 f8 01 28 02 |         send.urb (8)              r8      r1             0x00000000  0x022801F8  // wr:1h+0, rd:2; simd8_read off=31 (8)
skl | 31 00 60 06 08 02 00 01 20 00 00 06 08 02 28 02 |         send.urb (8)              r8      r1             0x00000000  0x02280208  // wr:1h+0, rd:2; simd8_read off=32 (8)
skl | 31 00 60 0b 08 02 40 00 60 00 00 06 00 30 20 04 |         send.pi (8)               r2      r3             0x00000000  0x04203000  // wr:2+0, rd:2; per_slot_offset persp (8)
skl | 31 00 80 0b 08 02 40 00 60 01 00 06 00 30 41 08 |         send.pi (16)              r2      r11            0x00000000  0x08413000  // wr:4+0, rd:4; per_slot_offset persp (16)
skl | 31 00 60 0b 08 02 40 00 00 00 00 06 10 10 20 02 |         send.pi (8)               r2      r0             0x00000000  0x02201010  // wr:1+0, rd:2; sample_position persp data=0x10 (8)
skl | 31 00 80 0b 08 02 40 00 00 00 00 06 10 10 41 02 |         send.pi (16)              r2      r0             0x00000000  0x02411010  // wr:1+0, rd:4; sample_position persp data=0x10 (16)
skl | 31 00 60 0b 08 02 40 00 00 00 00 06 20 10 20 02 |         send.pi (8)               r2      r0             0x00000000  0x02201020  // wr:1+0, rd:2; sample_position persp data=0x20 (8)
skl | 31 00 80 0b 08 02 40 00 00 00 00 06 20 10 41 02 |         send.pi (16)              r2      r0             0x00000000  0x02411020  // wr:1+0, rd:4; sample_position persp data=0x20 (16)
skl | 31 00 60 0b 08 02 40 00 00 00 00 06 30 10 20 02 |         send.pi (8)               r2      r0             0x00000000  0x02201030  // wr:1+0, rd:2; sample_position persp data=0x30 (8)
skl | 31 00 80 0b 08 02 40 00 00 00 00 06 30 10 41 02 |         send.pi (16)              r2      r0             0x00000000  0x02411030  // wr:1+0, rd:4; sample_position persp data=0x30 (16)
skl | 31 00 60 02 08 02 80 02 e0 01 00 06 03 02 32 04 |         send.smpl (8)             r20     r15            0x00000000  0x04320203  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 60 01 40 03 00 06 05 04 32 04 |         send.smpl (8)             r11     r26            0x00000000  0x04320405  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 00 01 00 03 00 06 04 03 32 04 |         send.smpl (8)             r8      r24            0x00000000  0x04320304  // wr:2+0, rd:3; sample:u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 03 a0 02 00 06 03 02 64 08 |         send.smpl (16)            r26     r21            0x00000000  0x08640203  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 80 01 00 06 00 06 05 04 64 08 |         send.smpl (16)            r12     r48            0x00000000  0x08640405  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 c0 04 80 05 00 06 04 03 64 08 |         send.smpl (16)            r38     r44            0x00000000  0x08640304  // wr:4+0, rd:6; sample:u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 61 0c 02 02 00 00 c0 0b 00 06 01 96 00 02 | (f1.0)  send.hdc1 (8)             null    r94            0x00000000  0x02009601  // wr:1+0, rd:0; untyped_atomic_dec simd8 (8) bti(1)
skl | 31 00 61 0c 0a 02 e0 05 c0 0b 00 06 01 b6 10 02 | (f1.0)  send.hdc1 (8)             r47     r94            0x00000000  0x0210B601  // wr:1+0, rd:1; untyped_atomic_dec simd8 (8) bti(1)
skl | 31 00 80 0c 08 02 80 00 20 00 00 06 02 5c 40 04 |         send.hdc1 (16)            r4      r1             0x00000000  0x04405C02  // wr:2+0, rd:4; untyped_read:xy simd16 (16) bti(2)
skl | 31 00 60 0c 00 02 00 00 80 0c 00 06 00 96 00 02 |         send.hdc1 (8)             null    r100           0x00000000  0x02009600  // wr:1+0, rd:0; untyped_atomic_dec simd8 (8) bti(0)
skl | 31 00 60 0c 08 02 60 06 80 0c 00 06 00 b6 10 02 |         send.hdc1 (8)             r51     r100           0x00000000  0x0210B600  // wr:1+0, rd:1; untyped_atomic_dec simd8 (8) bti(0)
skl | 31 00 60 02 08 02 a0 00 60 01 00 06 01 00 4a 06 |         send.smpl (8)             r5      r11            0x00000000  0x064A0001  // wr:3h+0, rd:4; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 60 02 00 06 01 00 8c 0a |         send.smpl (16)            r7      r19            0x00000000  0x0A8C0001  // wr:5h+0, rd:8; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 17 01 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080117   {EOT}  // wr:5h+0, rd:0; simd8_write off=17 (8)
skl | 31 00 60 0c 08 02 60 00 60 00 00 06 02 50 41 02 |         send.hdc1 (8)             r3      r3             0x00000000  0x02415002  // wr:1+0, rd:4; typed_read:xyzw simd16 (8) bti(2)
skl | 31 10 60 0c 08 02 a0 00 80 00 00 06 02 60 41 02 |         send.hdc1 (8|M8)          r5      r4             0x00000000  0x02416002  // wr:1+0, rd:4; typed_read:xyzw simd8 (8) bti(2)
skl | 31 00 60 0c 08 02 c0 00 00 02 00 06 00 b5 10 02 |         send.hdc1 (8)             r6      r16            0x00000000  0x0210B500  // wr:1+0, rd:1; untyped_atomic_inc simd8 (8) bti(0)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 97 00 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080097   {EOT}  // wr:9h+0, rd:0; simd8_write off=9 (8)
skl | 31 00 60 06 00 02 00 00 80 00 00 06 c7 00 08 12 |         send.urb (8)              null    r4             0x00000000  0x120800C7  // wr:9h+0, rd:0; simd8_write off=12 (8)
skl | 31 00 60 06 00 02 00 00 a0 00 00 06 e7 00 08 12 |         send.urb (8)              null    r5             0x00000000  0x120800E7  // wr:9h+0, rd:0; simd8_write off=14 (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 07 01 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080107   {EOT}  // wr:5h+0, rd:0; simd8_write off=16 (8)
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 02 41 43 08 |         send.smpl (8)             r6      r11            0x00000000  0x08434102  // wr:4+0, rd:4; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 60 08 80 04 00 06 00 e0 23 08 |         send.smpl (8)             r67     r36            0x00000000  0x0823E000  // wr:4+0, rd:2; ld2dms:si,mcs,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 40 00 40 00 00 06 00 c0 23 0a |         send.smpl (8)             r2      r2             0x00000000  0x0A23C000  // wr:5+0, rd:2; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 20 01 e0 01 00 06 01 b1 1a 02 |         send.smpl (8)             r9      r15            0x00000000  0x021AB101  // wr:1h+0, rd:1; sampleinfo (8) bti(1) using sampler index 1
skl | 31 00 60 02 08 02 40 01 00 02 00 06 02 b2 1a 02 |         send.smpl (8)             r10     r16            0x00000000  0x021AB202  // wr:1h+0, rd:1; sampleinfo (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 60 01 20 02 00 06 03 b3 1a 02 |         send.smpl (8)             r11     r17            0x00000000  0x021AB303  // wr:1h+0, rd:1; sampleinfo (8) bti(3) using sampler index 3
skl | 31 00 60 02 08 02 80 01 40 02 00 06 04 b4 1a 02 |         send.smpl (8)             r12     r18            0x00000000  0x021AB404  // wr:1h+0, rd:1; sampleinfo (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 a0 01 60 02 00 06 05 b5 1a 02 |         send.smpl (8)             r13     r19            0x00000000  0x021AB505  // wr:1h+0, rd:1; sampleinfo (8) bti(5) using sampler index 5
skl | 31 00 60 02 08 02 c0 01 40 02 00 06 02 31 12 08 |         send.smpl (8)             r14     r18            0x00000000  0x08123102  // wr:4+0, rd:1; sample_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 00 03 00 04 00 06 02 31 24 10 |         send.smpl (16)            r24     r32            0x00000000  0x10243102  // wr:8+0, rd:2; sample_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 0c 08 02 a0 00 a0 00 00 06 00 50 41 04 |         send.hdc1 (8)             r5      r5             0x00000000  0x04415000  // wr:2+0, rd:4; typed_read:xyzw simd16 (8) bti(0)
skl | 31 00 60 06 08 02 40 00 20 01 00 06 28 00 3a 04 |         send.urb (8)              r2      r9             0x00000000  0x043A0028  // wr:2h+0, rd:3; simd8_read off=2 per_slot (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 98 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x02380098  // wr:1h+0, rd:3; simd8_read off=9 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 a8 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x023800A8  // wr:1h+0, rd:3; simd8_read off=10 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 b8 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x023800B8  // wr:1h+0, rd:3; simd8_read off=11 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 d8 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x023800D8  // wr:1h+0, rd:3; simd8_read off=13 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 e8 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x023800E8  // wr:1h+0, rd:3; simd8_read off=14 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 f8 00 38 02 |         send.urb (8)              r13     r1             0x00000000  0x023800F8  // wr:1h+0, rd:3; simd8_read off=15 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 08 01 38 02 |         send.urb (8)              r13     r1             0x00000000  0x02380108  // wr:1h+0, rd:3; simd8_read off=16 (8)
skl | 31 00 60 06 08 02 a0 01 20 00 00 06 18 01 38 02 |         send.urb (8)              r13     r1             0x00000000  0x02380118  // wr:1h+0, rd:3; simd8_read off=17 (8)
skl | 31 00 60 06 00 02 00 00 80 07 00 06 a7 00 08 12 |         send.urb (8)              null    r60            0x00000000  0x120800A7  // wr:9h+0, rd:0; simd8_write off=10 (8)
skl | 31 00 60 06 00 02 00 00 e0 0e 00 06 07 01 08 92 |         send.urb (8)              null    r119           0x00000000  0x12080107   {EOT}  // wr:9h+0, rd:0; simd8_write off=16 (8)
skl | 31 00 60 0c 08 02 60 00 e0 00 00 06 01 5e 11 02 |         send.hdc1 (8)             r3      r7             0x00000000  0x02115E01  // wr:1+0, rd:1; typed_read:x simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 a0 00 60 01 00 06 01 6e 11 02 |         send.hdc1 (8|M8)          r5      r11            0x00000000  0x02116E01  // wr:1+0, rd:1; typed_read:x simd8 (8) bti(1)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 67 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080067   {EOT}  // wr:5h+0, rd:0; simd8_write off=6 (8)
skl | 31 00 60 06 00 02 00 00 00 0a 00 06 b7 00 0a 14 |         send.urb (8)              null    r80            0x00000000  0x140A00B7  // wr:10h+0, rd:0; simd8_write off=11 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 d7 00 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A00D7  // wr:10h+0, rd:0; simd8_write off=13 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 f7 00 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A00F7  // wr:10h+0, rd:0; simd8_write off=15 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 17 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A0117  // wr:10h+0, rd:0; simd8_write off=17 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 37 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A0137  // wr:10h+0, rd:0; simd8_write off=19 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 0b 00 06 57 01 0a 14 |         send.urb (8)              null    r90            0x00000000  0x140A0157  // wr:10h+0, rd:0; simd8_write off=21 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 0c 00 06 77 01 0a 14 |         send.urb (8)              null    r100           0x00000000  0x140A0177  // wr:10h+0, rd:0; simd8_write off=23 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0d 00 06 97 01 0a 0c |         send.urb (8)              null    r110           0x00000000  0x0C0A0197  // wr:6h+0, rd:0; simd8_write off=25 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 0f 00 06 97 01 0a 8c |         send.urb (8)              null    r120           0x00000000  0x0C0A0197   {EOT}  // wr:6h+0, rd:0; simd8_write off=25 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 b7 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A0800B7   {EOT}  // wr:5h+0, rd:0; simd8_write off=11 (8)
skl | 31 00 60 06 08 02 c0 02 a0 06 00 06 38 02 18 02 |         send.urb (8)              r22     r53            0x00000000  0x02180238  // wr:1h+0, rd:1; simd8_read off=35 (8)
skl | 31 00 60 06 08 02 c0 06 a0 06 00 06 38 04 18 02 |         send.urb (8)              r54     r53            0x00000000  0x02180438  // wr:1h+0, rd:1; simd8_read off=67 (8)
skl | 31 00 60 06 08 02 60 08 a0 06 00 06 38 06 18 02 |         send.urb (8)              r67     r53            0x00000000  0x02180638  // wr:1h+0, rd:1; simd8_read off=99 (8)
skl | 31 00 60 06 08 02 a0 07 a0 06 00 06 48 02 18 02 |         send.urb (8)              r61     r53            0x00000000  0x02180248  // wr:1h+0, rd:1; simd8_read off=36 (8)
skl | 31 00 60 06 08 02 40 08 a0 06 00 06 48 04 18 02 |         send.urb (8)              r66     r53            0x00000000  0x02180448  // wr:1h+0, rd:1; simd8_read off=68 (8)
skl | 31 00 60 06 08 02 e0 07 a0 06 00 06 48 06 18 02 |         send.urb (8)              r63     r53            0x00000000  0x02180648  // wr:1h+0, rd:1; simd8_read off=100 (8)
skl | 31 00 60 06 08 02 80 08 20 08 00 06 58 02 18 02 |         send.urb (8)              r68     r65            0x00000000  0x02180258  // wr:1h+0, rd:1; simd8_read off=37 (8)
skl | 31 00 60 06 08 02 a0 08 20 08 00 06 58 04 18 02 |         send.urb (8)              r69     r65            0x00000000  0x02180458  // wr:1h+0, rd:1; simd8_read off=69 (8)
skl | 31 00 60 06 08 02 c0 08 20 08 00 06 58 06 18 02 |         send.urb (8)              r70     r65            0x00000000  0x02180658  // wr:1h+0, rd:1; simd8_read off=101 (8)
skl | 31 00 60 06 08 02 60 09 00 03 00 06 68 02 18 02 |         send.urb (8)              r75     r24            0x00000000  0x02180268  // wr:1h+0, rd:1; simd8_read off=38 (8)
skl | 31 00 60 06 08 02 80 09 00 03 00 06 68 04 18 02 |         send.urb (8)              r76     r24            0x00000000  0x02180468  // wr:1h+0, rd:1; simd8_read off=70 (8)
skl | 31 00 60 06 08 02 a0 09 00 03 00 06 68 06 18 02 |         send.urb (8)              r77     r24            0x00000000  0x02180668  // wr:1h+0, rd:1; simd8_read off=102 (8)
skl | 31 00 60 06 08 02 40 0a 20 03 00 06 78 02 18 02 |         send.urb (8)              r82     r25            0x00000000  0x02180278  // wr:1h+0, rd:1; simd8_read off=39 (8)
skl | 31 00 60 06 08 02 60 0a 20 03 00 06 78 04 18 02 |         send.urb (8)              r83     r25            0x00000000  0x02180478  // wr:1h+0, rd:1; simd8_read off=71 (8)
skl | 31 00 60 06 08 02 80 0a 20 03 00 06 78 06 18 02 |         send.urb (8)              r84     r25            0x00000000  0x02180678  // wr:1h+0, rd:1; simd8_read off=103 (8)
skl | 31 00 60 06 08 02 20 0b 40 03 00 06 88 02 18 02 |         send.urb (8)              r89     r26            0x00000000  0x02180288  // wr:1h+0, rd:1; simd8_read off=40 (8)
skl | 31 00 60 06 08 02 40 0b 40 03 00 06 88 04 18 02 |         send.urb (8)              r90     r26            0x00000000  0x02180488  // wr:1h+0, rd:1; simd8_read off=72 (8)
skl | 31 00 60 06 08 02 60 0b 40 03 00 06 88 06 18 02 |         send.urb (8)              r91     r26            0x00000000  0x02180688  // wr:1h+0, rd:1; simd8_read off=104 (8)
skl | 31 00 60 06 08 02 00 0c 60 03 00 06 98 02 18 02 |         send.urb (8)              r96     r27            0x00000000  0x02180298  // wr:1h+0, rd:1; simd8_read off=41 (8)
skl | 31 00 60 06 08 02 20 0c 60 03 00 06 98 04 18 02 |         send.urb (8)              r97     r27            0x00000000  0x02180498  // wr:1h+0, rd:1; simd8_read off=73 (8)
skl | 31 00 60 06 08 02 40 0c 60 03 00 06 98 06 18 02 |         send.urb (8)              r98     r27            0x00000000  0x02180698  // wr:1h+0, rd:1; simd8_read off=105 (8)
skl | 31 00 60 06 08 02 e0 0c 80 03 00 06 a8 02 18 02 |         send.urb (8)              r103    r28            0x00000000  0x021802A8  // wr:1h+0, rd:1; simd8_read off=42 (8)
skl | 31 00 60 06 08 02 00 0d 80 03 00 06 a8 04 18 02 |         send.urb (8)              r104    r28            0x00000000  0x021804A8  // wr:1h+0, rd:1; simd8_read off=74 (8)
skl | 31 00 60 06 08 02 20 0d 80 03 00 06 a8 06 18 02 |         send.urb (8)              r105    r28            0x00000000  0x021806A8  // wr:1h+0, rd:1; simd8_read off=106 (8)
skl | 31 00 60 06 08 02 c0 0d a0 03 00 06 b8 02 18 02 |         send.urb (8)              r110    r29            0x00000000  0x021802B8  // wr:1h+0, rd:1; simd8_read off=43 (8)
skl | 31 00 60 06 08 02 e0 0d a0 03 00 06 b8 04 18 02 |         send.urb (8)              r111    r29            0x00000000  0x021804B8  // wr:1h+0, rd:1; simd8_read off=75 (8)
skl | 31 00 60 06 08 02 00 0e a0 03 00 06 b8 06 18 02 |         send.urb (8)              r112    r29            0x00000000  0x021806B8  // wr:1h+0, rd:1; simd8_read off=107 (8)
skl | 31 00 60 06 08 02 a0 0e c0 03 00 06 c8 02 18 02 |         send.urb (8)              r117    r30            0x00000000  0x021802C8  // wr:1h+0, rd:1; simd8_read off=44 (8)
skl | 31 00 60 06 08 02 c0 0e c0 03 00 06 c8 04 18 02 |         send.urb (8)              r118    r30            0x00000000  0x021804C8  // wr:1h+0, rd:1; simd8_read off=76 (8)
skl | 31 00 60 06 08 02 e0 0e c0 03 00 06 c8 06 18 02 |         send.urb (8)              r119    r30            0x00000000  0x021806C8  // wr:1h+0, rd:1; simd8_read off=108 (8)
skl | 31 00 60 06 08 02 80 0f e0 03 00 06 d8 02 18 02 |         send.urb (8)              r124    r31            0x00000000  0x021802D8  // wr:1h+0, rd:1; simd8_read off=45 (8)
skl | 31 00 60 06 08 02 a0 0f e0 03 00 06 d8 04 18 02 |         send.urb (8)              r125    r31            0x00000000  0x021804D8  // wr:1h+0, rd:1; simd8_read off=77 (8)
skl | 31 00 60 06 08 02 c0 0f e0 03 00 06 d8 06 18 02 |         send.urb (8)              r126    r31            0x00000000  0x021806D8  // wr:1h+0, rd:1; simd8_read off=109 (8)
skl | 31 00 60 06 08 02 40 01 00 04 00 06 e8 02 18 02 |         send.urb (8)              r10     r32            0x00000000  0x021802E8  // wr:1h+0, rd:1; simd8_read off=46 (8)
skl | 31 00 60 06 08 02 60 01 00 04 00 06 e8 04 18 02 |         send.urb (8)              r11     r32            0x00000000  0x021804E8  // wr:1h+0, rd:1; simd8_read off=78 (8)
skl | 31 00 60 06 08 02 80 01 00 04 00 06 e8 06 18 02 |         send.urb (8)              r12     r32            0x00000000  0x021806E8  // wr:1h+0, rd:1; simd8_read off=110 (8)
skl | 31 00 60 06 08 02 40 03 20 04 00 06 f8 02 18 02 |         send.urb (8)              r26     r33            0x00000000  0x021802F8  // wr:1h+0, rd:1; simd8_read off=47 (8)
skl | 31 00 60 06 08 02 60 03 20 04 00 06 f8 04 18 02 |         send.urb (8)              r27     r33            0x00000000  0x021804F8  // wr:1h+0, rd:1; simd8_read off=79 (8)
skl | 31 00 60 06 08 02 80 03 20 04 00 06 f8 06 18 02 |         send.urb (8)              r28     r33            0x00000000  0x021806F8  // wr:1h+0, rd:1; simd8_read off=111 (8)
skl | 31 00 60 06 08 02 20 04 60 04 00 06 08 03 18 02 |         send.urb (8)              r33     r35            0x00000000  0x02180308  // wr:1h+0, rd:1; simd8_read off=48 (8)
skl | 31 00 60 06 08 02 40 04 60 04 00 06 08 05 18 02 |         send.urb (8)              r34     r35            0x00000000  0x02180508  // wr:1h+0, rd:1; simd8_read off=80 (8)
skl | 31 00 60 06 08 02 60 04 60 04 00 06 08 07 18 02 |         send.urb (8)              r35     r35            0x00000000  0x02180708  // wr:1h+0, rd:1; simd8_read off=112 (8)
skl | 31 00 60 06 08 02 00 08 80 04 00 06 18 03 18 02 |         send.urb (8)              r64     r36            0x00000000  0x02180318  // wr:1h+0, rd:1; simd8_read off=49 (8)
skl | 31 00 60 06 08 02 20 05 80 04 00 06 18 05 18 02 |         send.urb (8)              r41     r36            0x00000000  0x02180518  // wr:1h+0, rd:1; simd8_read off=81 (8)
skl | 31 00 60 06 08 02 40 05 80 04 00 06 18 07 18 02 |         send.urb (8)              r42     r36            0x00000000  0x02180718  // wr:1h+0, rd:1; simd8_read off=113 (8)
skl | 31 00 60 06 08 02 c0 00 a0 04 00 06 28 03 18 02 |         send.urb (8)              r6      r37            0x00000000  0x02180328  // wr:1h+0, rd:1; simd8_read off=50 (8)
skl | 31 00 60 06 08 02 00 06 a0 04 00 06 28 05 18 02 |         send.urb (8)              r48     r37            0x00000000  0x02180528  // wr:1h+0, rd:1; simd8_read off=82 (8)
skl | 31 00 60 06 08 02 20 06 a0 04 00 06 28 07 18 02 |         send.urb (8)              r49     r37            0x00000000  0x02180728  // wr:1h+0, rd:1; simd8_read off=114 (8)
skl | 31 00 60 06 08 02 60 08 c0 04 00 06 38 03 18 02 |         send.urb (8)              r67     r38            0x00000000  0x02180338  // wr:1h+0, rd:1; simd8_read off=51 (8)
skl | 31 00 60 06 08 02 00 07 c0 04 00 06 38 05 18 02 |         send.urb (8)              r56     r38            0x00000000  0x02180538  // wr:1h+0, rd:1; simd8_read off=83 (8)
skl | 31 00 60 06 08 02 20 07 c0 04 00 06 38 07 18 02 |         send.urb (8)              r57     r38            0x00000000  0x02180738  // wr:1h+0, rd:1; simd8_read off=115 (8)
skl | 31 00 60 06 08 02 40 08 e0 04 00 06 48 03 18 02 |         send.urb (8)              r66     r39            0x00000000  0x02180348  // wr:1h+0, rd:1; simd8_read off=52 (8)
skl | 31 00 60 06 08 02 e0 07 e0 04 00 06 48 05 18 02 |         send.urb (8)              r63     r39            0x00000000  0x02180548  // wr:1h+0, rd:1; simd8_read off=84 (8)
skl | 31 00 60 06 08 02 00 05 e0 04 00 06 48 07 18 02 |         send.urb (8)              r40     r39            0x00000000  0x02180748  // wr:1h+0, rd:1; simd8_read off=116 (8)
skl | 31 00 60 06 08 02 a0 08 00 08 00 06 58 03 18 02 |         send.urb (8)              r69     r64            0x00000000  0x02180358  // wr:1h+0, rd:1; simd8_read off=53 (8)
skl | 31 00 60 06 08 02 c0 08 00 08 00 06 58 05 18 02 |         send.urb (8)              r70     r64            0x00000000  0x02180558  // wr:1h+0, rd:1; simd8_read off=85 (8)
skl | 31 00 60 06 08 02 e0 08 00 08 00 06 58 07 18 02 |         send.urb (8)              r71     r64            0x00000000  0x02180758  // wr:1h+0, rd:1; simd8_read off=117 (8)
skl | 31 00 60 06 08 02 80 09 20 05 00 06 68 03 18 02 |         send.urb (8)              r76     r41            0x00000000  0x02180368  // wr:1h+0, rd:1; simd8_read off=54 (8)
skl | 31 00 60 06 08 02 a0 09 20 05 00 06 68 05 18 02 |         send.urb (8)              r77     r41            0x00000000  0x02180568  // wr:1h+0, rd:1; simd8_read off=86 (8)
skl | 31 00 60 06 08 02 c0 09 20 05 00 06 68 07 18 02 |         send.urb (8)              r78     r41            0x00000000  0x02180768  // wr:1h+0, rd:1; simd8_read off=118 (8)
skl | 31 00 60 06 08 02 60 0a 40 05 00 06 78 03 18 02 |         send.urb (8)              r83     r42            0x00000000  0x02180378  // wr:1h+0, rd:1; simd8_read off=55 (8)
skl | 31 00 60 06 08 02 80 0a 40 05 00 06 78 05 18 02 |         send.urb (8)              r84     r42            0x00000000  0x02180578  // wr:1h+0, rd:1; simd8_read off=87 (8)
skl | 31 00 60 06 08 02 a0 0a 40 05 00 06 78 07 18 02 |         send.urb (8)              r85     r42            0x00000000  0x02180778  // wr:1h+0, rd:1; simd8_read off=119 (8)
skl | 31 00 60 06 08 02 40 0b 60 05 00 06 88 03 18 02 |         send.urb (8)              r90     r43            0x00000000  0x02180388  // wr:1h+0, rd:1; simd8_read off=56 (8)
skl | 31 00 60 06 08 02 60 0b 60 05 00 06 88 05 18 02 |         send.urb (8)              r91     r43            0x00000000  0x02180588  // wr:1h+0, rd:1; simd8_read off=88 (8)
skl | 31 00 60 06 08 02 80 0b 60 05 00 06 88 07 18 02 |         send.urb (8)              r92     r43            0x00000000  0x02180788  // wr:1h+0, rd:1; simd8_read off=120 (8)
skl | 31 00 60 06 08 02 20 0c 80 05 00 06 98 03 18 02 |         send.urb (8)              r97     r44            0x00000000  0x02180398  // wr:1h+0, rd:1; simd8_read off=57 (8)
skl | 31 00 60 06 08 02 40 0c 80 05 00 06 98 05 18 02 |         send.urb (8)              r98     r44            0x00000000  0x02180598  // wr:1h+0, rd:1; simd8_read off=89 (8)
skl | 31 00 60 06 08 02 60 0c 80 05 00 06 98 07 18 02 |         send.urb (8)              r99     r44            0x00000000  0x02180798  // wr:1h+0, rd:1; simd8_read off=121 (8)
skl | 31 00 60 06 08 02 00 0d a0 05 00 06 a8 03 18 02 |         send.urb (8)              r104    r45            0x00000000  0x021803A8  // wr:1h+0, rd:1; simd8_read off=58 (8)
skl | 31 00 60 06 08 02 20 0d a0 05 00 06 a8 05 18 02 |         send.urb (8)              r105    r45            0x00000000  0x021805A8  // wr:1h+0, rd:1; simd8_read off=90 (8)
skl | 31 00 60 06 08 02 40 0d a0 05 00 06 a8 07 18 02 |         send.urb (8)              r106    r45            0x00000000  0x021807A8  // wr:1h+0, rd:1; simd8_read off=122 (8)
skl | 31 00 60 06 08 02 e0 0d c0 05 00 06 b8 03 18 02 |         send.urb (8)              r111    r46            0x00000000  0x021803B8  // wr:1h+0, rd:1; simd8_read off=59 (8)
skl | 31 00 60 06 08 02 00 0e c0 05 00 06 b8 05 18 02 |         send.urb (8)              r112    r46            0x00000000  0x021805B8  // wr:1h+0, rd:1; simd8_read off=91 (8)
skl | 31 00 60 06 08 02 20 0e c0 05 00 06 b8 07 18 02 |         send.urb (8)              r113    r46            0x00000000  0x021807B8  // wr:1h+0, rd:1; simd8_read off=123 (8)
skl | 31 00 60 06 08 02 c0 0e c0 00 00 06 c8 03 18 02 |         send.urb (8)              r118    r6             0x00000000  0x021803C8  // wr:1h+0, rd:1; simd8_read off=60 (8)
skl | 31 00 60 06 08 02 e0 0e c0 00 00 06 c8 05 18 02 |         send.urb (8)              r119    r6             0x00000000  0x021805C8  // wr:1h+0, rd:1; simd8_read off=92 (8)
skl | 31 00 60 06 08 02 00 0f c0 00 00 06 c8 07 18 02 |         send.urb (8)              r120    r6             0x00000000  0x021807C8  // wr:1h+0, rd:1; simd8_read off=124 (8)
skl | 31 00 60 06 08 02 a0 0f 00 06 00 06 d8 03 18 02 |         send.urb (8)              r125    r48            0x00000000  0x021803D8  // wr:1h+0, rd:1; simd8_read off=61 (8)
skl | 31 00 60 06 08 02 c0 0f 00 06 00 06 d8 05 18 02 |         send.urb (8)              r126    r48            0x00000000  0x021805D8  // wr:1h+0, rd:1; simd8_read off=93 (8)
skl | 31 00 60 06 08 02 40 00 00 06 00 06 d8 07 18 02 |         send.urb (8)              r2      r48            0x00000000  0x021807D8  // wr:1h+0, rd:1; simd8_read off=125 (8)
skl | 31 00 60 06 08 02 80 01 20 06 00 06 e8 03 18 02 |         send.urb (8)              r12     r49            0x00000000  0x021803E8  // wr:1h+0, rd:1; simd8_read off=62 (8)
skl | 31 00 60 06 08 02 a0 01 20 06 00 06 e8 05 18 02 |         send.urb (8)              r13     r49            0x00000000  0x021805E8  // wr:1h+0, rd:1; simd8_read off=94 (8)
skl | 31 00 60 06 08 02 c0 01 20 06 00 06 e8 07 18 02 |         send.urb (8)              r14     r49            0x00000000  0x021807E8  // wr:1h+0, rd:1; simd8_read off=126 (8)
skl | 31 00 60 06 08 02 60 02 40 06 00 06 f8 03 18 02 |         send.urb (8)              r19     r50            0x00000000  0x021803F8  // wr:1h+0, rd:1; simd8_read off=63 (8)
skl | 31 00 60 06 08 02 80 02 40 06 00 06 f8 05 18 02 |         send.urb (8)              r20     r50            0x00000000  0x021805F8  // wr:1h+0, rd:1; simd8_read off=95 (8)
skl | 31 00 60 06 08 02 a0 06 40 06 00 06 f8 07 18 02 |         send.urb (8)              r53     r50            0x00000000  0x021807F8  // wr:1h+0, rd:1; simd8_read off=127 (8)
skl | 31 00 60 06 08 02 80 03 60 06 00 06 08 04 18 02 |         send.urb (8)              r28     r51            0x00000000  0x02180408  // wr:1h+0, rd:1; simd8_read off=64 (8)
skl | 31 00 60 06 08 02 a0 03 60 06 00 06 08 06 18 02 |         send.urb (8)              r29     r51            0x00000000  0x02180608  // wr:1h+0, rd:1; simd8_read off=96 (8)
skl | 31 00 60 06 08 02 c0 03 60 06 00 06 08 08 18 02 |         send.urb (8)              r30     r51            0x00000000  0x02180808  // wr:1h+0, rd:1; simd8_read off=128 (8)
skl | 31 00 60 06 08 02 60 04 c0 02 00 06 18 02 18 02 |         send.urb (8)              r35     r22            0x00000000  0x02180218  // wr:1h+0, rd:1; simd8_read off=33 (8)
skl | 31 00 60 06 08 02 80 04 c0 02 00 06 18 04 18 02 |         send.urb (8)              r36     r22            0x00000000  0x02180418  // wr:1h+0, rd:1; simd8_read off=65 (8)
skl | 31 00 60 06 08 02 a0 04 c0 02 00 06 18 06 18 02 |         send.urb (8)              r37     r22            0x00000000  0x02180618  // wr:1h+0, rd:1; simd8_read off=97 (8)
skl | 31 00 60 06 08 02 c0 04 c0 02 00 06 18 08 18 02 |         send.urb (8)              r38     r22            0x00000000  0x02180818  // wr:1h+0, rd:1; simd8_read off=129 (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 37 80 0a 08 |         send.urb (8)              null    r6             0x00000000  0x080A8037  // wr:4h+0, rd:0; simd8_write off=3 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 01 00 06 47 80 0a 08 |         send.urb (8)              null    r10            0x00000000  0x080A8047  // wr:4h+0, rd:0; simd8_write off=4 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 57 80 0a 08 |         send.urb (8)              null    r11            0x00000000  0x080A8057  // wr:4h+0, rd:0; simd8_write off=5 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 67 80 0a 08 |         send.urb (8)              null    r12            0x00000000  0x080A8067  // wr:4h+0, rd:0; simd8_write off=6 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 77 80 0a 08 |         send.urb (8)              null    r13            0x00000000  0x080A8077  // wr:4h+0, rd:0; simd8_write off=7 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 87 80 0a 08 |         send.urb (8)              null    r14            0x00000000  0x080A8087  // wr:4h+0, rd:0; simd8_write off=8 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 97 80 0a 08 |         send.urb (8)              null    r15            0x00000000  0x080A8097  // wr:4h+0, rd:0; simd8_write off=9 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 a7 80 0a 08 |         send.urb (8)              null    r16            0x00000000  0x080A80A7  // wr:4h+0, rd:0; simd8_write off=10 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 b7 80 0a 08 |         send.urb (8)              null    r17            0x00000000  0x080A80B7  // wr:4h+0, rd:0; simd8_write off=11 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 c7 80 0a 08 |         send.urb (8)              null    r18            0x00000000  0x080A80C7  // wr:4h+0, rd:0; simd8_write off=12 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 d7 80 0a 08 |         send.urb (8)              null    r19            0x00000000  0x080A80D7  // wr:4h+0, rd:0; simd8_write off=13 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 e7 80 0a 08 |         send.urb (8)              null    r20            0x00000000  0x080A80E7  // wr:4h+0, rd:0; simd8_write off=14 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 f7 80 0a 08 |         send.urb (8)              null    r21            0x00000000  0x080A80F7  // wr:4h+0, rd:0; simd8_write off=15 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 07 81 0a 08 |         send.urb (8)              null    r22            0x00000000  0x080A8107  // wr:4h+0, rd:0; simd8_write off=16 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 17 81 0a 08 |         send.urb (8)              null    r23            0x00000000  0x080A8117  // wr:4h+0, rd:0; simd8_write off=17 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 27 81 0a 08 |         send.urb (8)              null    r24            0x00000000  0x080A8127  // wr:4h+0, rd:0; simd8_write off=18 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 37 81 0a 08 |         send.urb (8)              null    r25            0x00000000  0x080A8137  // wr:4h+0, rd:0; simd8_write off=19 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 47 81 0a 08 |         send.urb (8)              null    r26            0x00000000  0x080A8147  // wr:4h+0, rd:0; simd8_write off=20 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 57 81 0a 08 |         send.urb (8)              null    r27            0x00000000  0x080A8157  // wr:4h+0, rd:0; simd8_write off=21 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 67 81 0a 08 |         send.urb (8)              null    r28            0x00000000  0x080A8167  // wr:4h+0, rd:0; simd8_write off=22 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 77 81 0a 08 |         send.urb (8)              null    r29            0x00000000  0x080A8177  // wr:4h+0, rd:0; simd8_write off=23 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 87 81 0a 08 |         send.urb (8)              null    r30            0x00000000  0x080A8187  // wr:4h+0, rd:0; simd8_write off=24 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 97 81 0a 08 |         send.urb (8)              null    r31            0x00000000  0x080A8197  // wr:4h+0, rd:0; simd8_write off=25 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 a7 81 0a 08 |         send.urb (8)              null    r32            0x00000000  0x080A81A7  // wr:4h+0, rd:0; simd8_write off=26 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 b7 81 0a 08 |         send.urb (8)              null    r33            0x00000000  0x080A81B7  // wr:4h+0, rd:0; simd8_write off=27 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 c7 81 0a 08 |         send.urb (8)              null    r34            0x00000000  0x080A81C7  // wr:4h+0, rd:0; simd8_write off=28 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 d7 81 0a 08 |         send.urb (8)              null    r35            0x00000000  0x080A81D7  // wr:4h+0, rd:0; simd8_write off=29 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 e7 81 0a 08 |         send.urb (8)              null    r36            0x00000000  0x080A81E7  // wr:4h+0, rd:0; simd8_write off=30 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 f7 81 0a 08 |         send.urb (8)              null    r37            0x00000000  0x080A81F7  // wr:4h+0, rd:0; simd8_write off=31 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 07 82 0a 08 |         send.urb (8)              null    r38            0x00000000  0x080A8207  // wr:4h+0, rd:0; simd8_write off=32 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 17 82 0a 08 |         send.urb (8)              null    r39            0x00000000  0x080A8217  // wr:4h+0, rd:0; simd8_write off=33 masked per_slot (8)
skl | 31 00 60 0c 08 02 40 02 60 02 00 06 00 5e 11 04 |         send.hdc1 (8)             r18     r19            0x00000000  0x04115E00  // wr:2+0, rd:1; typed_read:x simd16 (8) bti(0)
skl | 31 00 60 02 08 02 40 00 c0 00 00 06 01 d0 23 06 |         send.smpl (8)             r2      r6             0x00000000  0x0623D001  // wr:3+0, rd:2; ld_mcs:u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 00 01 00 06 01 d0 45 0c |         send.smpl (16)            r2      r8             0x00000000  0x0C45D001  // wr:6+0, rd:4; ld_mcs:u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 0c 40 01 00 06 01 c0 33 0c |         send.smpl (8)             r101    r10            0x00000000  0x0C33C001  // wr:6+0, rd:3; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 01 60 01 00 06 03 02 4b 08 |         send.smpl (8)             r14     r11            0x00000000  0x084B0203  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 02 01 4b 0a |         send.smpl (8)             r6      r6             0x00000000  0x0A4B0102  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 03 40 00 00 06 03 02 8d 0e |         send.smpl (16)            r26     r2             0x00000000  0x0E8D0203  // wr:7h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 01 40 04 00 06 02 01 8d 12 |         send.smpl (16)            r10     r34            0x00000000  0x128D0102  // wr:9h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 40 1b 0a |         send.smpl (8)             r6      r7             0x00000000  0x0A1B4001  // wr:5h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 80 01 00 06 02 41 1b 0a |         send.smpl (8)             r7      r12            0x00000000  0x0A1B4102  // wr:5h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 40 04 40 05 00 06 48 02 48 02 |         send.urb (8)              r34     r42            0x00000000  0x02480248  // wr:1h+0, rd:4; simd8_read off=36 (8)
skl | 31 00 60 06 08 02 c0 04 40 05 00 06 48 04 48 02 |         send.urb (8)              r38     r42            0x00000000  0x02480448  // wr:1h+0, rd:4; simd8_read off=68 (8)
skl | 31 00 60 06 08 02 40 05 40 05 00 06 48 06 48 02 |         send.urb (8)              r42     r42            0x00000000  0x02480648  // wr:1h+0, rd:4; simd8_read off=100 (8)
skl | 31 00 60 06 08 02 c0 02 60 05 00 06 58 02 48 02 |         send.urb (8)              r22     r43            0x00000000  0x02480258  // wr:1h+0, rd:4; simd8_read off=37 (8)
skl | 31 00 60 06 08 02 40 03 60 05 00 06 58 04 48 02 |         send.urb (8)              r26     r43            0x00000000  0x02480458  // wr:1h+0, rd:4; simd8_read off=69 (8)
skl | 31 00 60 06 08 02 c0 03 60 05 00 06 58 06 48 02 |         send.urb (8)              r30     r43            0x00000000  0x02480658  // wr:1h+0, rd:4; simd8_read off=101 (8)
skl | 31 00 60 06 08 02 c0 02 80 05 00 06 68 02 48 02 |         send.urb (8)              r22     r44            0x00000000  0x02480268  // wr:1h+0, rd:4; simd8_read off=38 (8)
skl | 31 00 60 06 08 02 40 03 80 05 00 06 68 04 48 02 |         send.urb (8)              r26     r44            0x00000000  0x02480468  // wr:1h+0, rd:4; simd8_read off=70 (8)
skl | 31 00 60 06 08 02 c0 03 80 05 00 06 68 06 48 02 |         send.urb (8)              r30     r44            0x00000000  0x02480668  // wr:1h+0, rd:4; simd8_read off=102 (8)
skl | 31 00 60 06 08 02 c0 02 a0 05 00 06 78 02 48 02 |         send.urb (8)              r22     r45            0x00000000  0x02480278  // wr:1h+0, rd:4; simd8_read off=39 (8)
skl | 31 00 60 06 08 02 40 03 a0 05 00 06 78 04 48 02 |         send.urb (8)              r26     r45            0x00000000  0x02480478  // wr:1h+0, rd:4; simd8_read off=71 (8)
skl | 31 00 60 06 08 02 c0 03 a0 05 00 06 78 06 48 02 |         send.urb (8)              r30     r45            0x00000000  0x02480678  // wr:1h+0, rd:4; simd8_read off=103 (8)
skl | 31 00 60 06 08 02 c0 02 e0 06 00 06 88 02 48 02 |         send.urb (8)              r22     r55            0x00000000  0x02480288  // wr:1h+0, rd:4; simd8_read off=40 (8)
skl | 31 00 60 06 08 02 40 03 e0 06 00 06 88 04 48 02 |         send.urb (8)              r26     r55            0x00000000  0x02480488  // wr:1h+0, rd:4; simd8_read off=72 (8)
skl | 31 00 60 06 08 02 c0 03 e0 06 00 06 88 06 48 02 |         send.urb (8)              r30     r55            0x00000000  0x02480688  // wr:1h+0, rd:4; simd8_read off=104 (8)
skl | 31 00 60 06 08 02 40 03 00 07 00 06 98 04 48 02 |         send.urb (8)              r26     r56            0x00000000  0x02480498  // wr:1h+0, rd:4; simd8_read off=73 (8)
skl | 31 00 60 06 08 02 c0 02 00 07 00 06 98 02 48 02 |         send.urb (8)              r22     r56            0x00000000  0x02480298  // wr:1h+0, rd:4; simd8_read off=41 (8)
skl | 31 00 60 06 08 02 c0 03 00 07 00 06 98 06 48 02 |         send.urb (8)              r30     r56            0x00000000  0x02480698  // wr:1h+0, rd:4; simd8_read off=105 (8)
skl | 31 00 60 06 08 02 40 03 40 0a 00 06 a8 04 48 02 |         send.urb (8)              r26     r82            0x00000000  0x024804A8  // wr:1h+0, rd:4; simd8_read off=74 (8)
skl | 31 00 60 06 08 02 c0 02 40 0a 00 06 a8 02 48 02 |         send.urb (8)              r22     r82            0x00000000  0x024802A8  // wr:1h+0, rd:4; simd8_read off=42 (8)
skl | 31 00 60 06 08 02 c0 03 40 0a 00 06 a8 06 48 02 |         send.urb (8)              r30     r82            0x00000000  0x024806A8  // wr:1h+0, rd:4; simd8_read off=106 (8)
skl | 31 00 60 06 08 02 40 03 60 0a 00 06 b8 04 48 02 |         send.urb (8)              r26     r83            0x00000000  0x024804B8  // wr:1h+0, rd:4; simd8_read off=75 (8)
skl | 31 00 60 06 08 02 c0 02 60 0a 00 06 b8 02 48 02 |         send.urb (8)              r22     r83            0x00000000  0x024802B8  // wr:1h+0, rd:4; simd8_read off=43 (8)
skl | 31 00 60 06 08 02 c0 03 60 0a 00 06 b8 06 48 02 |         send.urb (8)              r30     r83            0x00000000  0x024806B8  // wr:1h+0, rd:4; simd8_read off=107 (8)
skl | 31 00 60 06 08 02 40 03 80 0a 00 06 c8 06 48 02 |         send.urb (8)              r26     r84            0x00000000  0x024806C8  // wr:1h+0, rd:4; simd8_read off=108 (8)
skl | 31 00 60 06 08 02 00 01 80 0a 00 06 c8 02 48 02 |         send.urb (8)              r8      r84            0x00000000  0x024802C8  // wr:1h+0, rd:4; simd8_read off=44 (8)
skl | 31 00 60 06 08 02 c0 02 80 0a 00 06 c8 04 48 02 |         send.urb (8)              r22     r84            0x00000000  0x024804C8  // wr:1h+0, rd:4; simd8_read off=76 (8)
skl | 31 00 60 06 08 02 00 01 a0 0a 00 06 d8 02 48 02 |         send.urb (8)              r8      r85            0x00000000  0x024802D8  // wr:1h+0, rd:4; simd8_read off=45 (8)
skl | 31 00 60 06 08 02 c0 02 a0 0a 00 06 d8 04 48 02 |         send.urb (8)              r22     r85            0x00000000  0x024804D8  // wr:1h+0, rd:4; simd8_read off=77 (8)
skl | 31 00 60 06 08 02 40 03 a0 0a 00 06 d8 06 48 02 |         send.urb (8)              r26     r85            0x00000000  0x024806D8  // wr:1h+0, rd:4; simd8_read off=109 (8)
skl | 31 00 60 06 08 02 00 01 c0 00 00 06 e8 02 48 02 |         send.urb (8)              r8      r6             0x00000000  0x024802E8  // wr:1h+0, rd:4; simd8_read off=46 (8)
skl | 31 00 60 06 08 02 c0 02 c0 00 00 06 e8 04 48 02 |         send.urb (8)              r22     r6             0x00000000  0x024804E8  // wr:1h+0, rd:4; simd8_read off=78 (8)
skl | 31 00 60 06 08 02 40 03 c0 00 00 06 e8 06 48 02 |         send.urb (8)              r26     r6             0x00000000  0x024806E8  // wr:1h+0, rd:4; simd8_read off=110 (8)
skl | 31 00 60 06 08 02 00 01 60 00 00 06 f8 02 48 02 |         send.urb (8)              r8      r3             0x00000000  0x024802F8  // wr:1h+0, rd:4; simd8_read off=47 (8)
skl | 31 00 60 06 08 02 c0 02 60 00 00 06 f8 04 48 02 |         send.urb (8)              r22     r3             0x00000000  0x024804F8  // wr:1h+0, rd:4; simd8_read off=79 (8)
skl | 31 00 60 06 08 02 40 03 60 00 00 06 f8 06 48 02 |         send.urb (8)              r26     r3             0x00000000  0x024806F8  // wr:1h+0, rd:4; simd8_read off=111 (8)
skl | 31 00 60 06 08 02 00 01 c0 05 00 06 08 03 48 02 |         send.urb (8)              r8      r46            0x00000000  0x02480308  // wr:1h+0, rd:4; simd8_read off=48 (8)
skl | 31 00 60 06 08 02 c0 02 c0 05 00 06 08 05 48 02 |         send.urb (8)              r22     r46            0x00000000  0x02480508  // wr:1h+0, rd:4; simd8_read off=80 (8)
skl | 31 00 60 06 08 02 40 03 c0 05 00 06 08 07 48 02 |         send.urb (8)              r26     r46            0x00000000  0x02480708  // wr:1h+0, rd:4; simd8_read off=112 (8)
skl | 31 00 60 06 08 02 00 01 e0 05 00 06 18 03 48 02 |         send.urb (8)              r8      r47            0x00000000  0x02480318  // wr:1h+0, rd:4; simd8_read off=49 (8)
skl | 31 00 60 06 08 02 c0 02 e0 05 00 06 18 05 48 02 |         send.urb (8)              r22     r47            0x00000000  0x02480518  // wr:1h+0, rd:4; simd8_read off=81 (8)
skl | 31 00 60 06 08 02 40 03 e0 05 00 06 18 07 48 02 |         send.urb (8)              r26     r47            0x00000000  0x02480718  // wr:1h+0, rd:4; simd8_read off=113 (8)
skl | 31 00 60 06 08 02 00 01 20 07 00 06 28 03 48 02 |         send.urb (8)              r8      r57            0x00000000  0x02480328  // wr:1h+0, rd:4; simd8_read off=50 (8)
skl | 31 00 60 06 08 02 c0 02 20 07 00 06 28 05 48 02 |         send.urb (8)              r22     r57            0x00000000  0x02480528  // wr:1h+0, rd:4; simd8_read off=82 (8)
skl | 31 00 60 06 08 02 40 03 20 07 00 06 28 07 48 02 |         send.urb (8)              r26     r57            0x00000000  0x02480728  // wr:1h+0, rd:4; simd8_read off=114 (8)
skl | 31 00 60 06 08 02 00 01 40 07 00 06 38 03 48 02 |         send.urb (8)              r8      r58            0x00000000  0x02480338  // wr:1h+0, rd:4; simd8_read off=51 (8)
skl | 31 00 60 06 08 02 c0 02 40 07 00 06 38 05 48 02 |         send.urb (8)              r22     r58            0x00000000  0x02480538  // wr:1h+0, rd:4; simd8_read off=83 (8)
skl | 31 00 60 06 08 02 40 03 40 07 00 06 38 07 48 02 |         send.urb (8)              r26     r58            0x00000000  0x02480738  // wr:1h+0, rd:4; simd8_read off=115 (8)
skl | 31 00 60 06 08 02 00 01 60 07 00 06 48 03 48 02 |         send.urb (8)              r8      r59            0x00000000  0x02480348  // wr:1h+0, rd:4; simd8_read off=52 (8)
skl | 31 00 60 06 08 02 80 01 60 07 00 06 48 05 48 02 |         send.urb (8)              r12     r59            0x00000000  0x02480548  // wr:1h+0, rd:4; simd8_read off=84 (8)
skl | 31 00 60 06 08 02 c0 02 60 07 00 06 48 07 48 02 |         send.urb (8)              r22     r59            0x00000000  0x02480748  // wr:1h+0, rd:4; simd8_read off=116 (8)
skl | 31 00 60 06 08 02 00 01 80 07 00 06 58 03 48 02 |         send.urb (8)              r8      r60            0x00000000  0x02480358  // wr:1h+0, rd:4; simd8_read off=53 (8)
skl | 31 00 60 06 08 02 80 01 80 07 00 06 58 05 48 02 |         send.urb (8)              r12     r60            0x00000000  0x02480558  // wr:1h+0, rd:4; simd8_read off=85 (8)
skl | 31 00 60 06 08 02 c0 02 80 07 00 06 58 07 48 02 |         send.urb (8)              r22     r60            0x00000000  0x02480758  // wr:1h+0, rd:4; simd8_read off=117 (8)
skl | 31 00 60 06 08 02 00 01 a0 07 00 06 68 03 48 02 |         send.urb (8)              r8      r61            0x00000000  0x02480368  // wr:1h+0, rd:4; simd8_read off=54 (8)
skl | 31 00 60 06 08 02 80 01 a0 07 00 06 68 05 48 02 |         send.urb (8)              r12     r61            0x00000000  0x02480568  // wr:1h+0, rd:4; simd8_read off=86 (8)
skl | 31 00 60 06 08 02 c0 02 a0 07 00 06 68 07 48 02 |         send.urb (8)              r22     r61            0x00000000  0x02480768  // wr:1h+0, rd:4; simd8_read off=118 (8)
skl | 31 00 60 06 08 02 00 01 c0 07 00 06 78 03 48 02 |         send.urb (8)              r8      r62            0x00000000  0x02480378  // wr:1h+0, rd:4; simd8_read off=55 (8)
skl | 31 00 60 06 08 02 80 01 c0 07 00 06 78 05 48 02 |         send.urb (8)              r12     r62            0x00000000  0x02480578  // wr:1h+0, rd:4; simd8_read off=87 (8)
skl | 31 00 60 06 08 02 c0 02 c0 07 00 06 78 07 48 02 |         send.urb (8)              r22     r62            0x00000000  0x02480778  // wr:1h+0, rd:4; simd8_read off=119 (8)
skl | 31 00 60 06 08 02 00 01 e0 07 00 06 88 03 48 02 |         send.urb (8)              r8      r63            0x00000000  0x02480388  // wr:1h+0, rd:4; simd8_read off=56 (8)
skl | 31 00 60 06 08 02 80 01 e0 07 00 06 88 05 48 02 |         send.urb (8)              r12     r63            0x00000000  0x02480588  // wr:1h+0, rd:4; simd8_read off=88 (8)
skl | 31 00 60 06 08 02 c0 02 e0 07 00 06 88 07 48 02 |         send.urb (8)              r22     r63            0x00000000  0x02480788  // wr:1h+0, rd:4; simd8_read off=120 (8)
skl | 31 00 60 06 08 02 00 01 00 08 00 06 98 03 48 02 |         send.urb (8)              r8      r64            0x00000000  0x02480398  // wr:1h+0, rd:4; simd8_read off=57 (8)
skl | 31 00 60 06 08 02 80 01 00 08 00 06 98 05 48 02 |         send.urb (8)              r12     r64            0x00000000  0x02480598  // wr:1h+0, rd:4; simd8_read off=89 (8)
skl | 31 00 60 06 08 02 c0 02 00 08 00 06 98 07 48 02 |         send.urb (8)              r22     r64            0x00000000  0x02480798  // wr:1h+0, rd:4; simd8_read off=121 (8)
skl | 31 00 60 06 08 02 00 01 80 08 00 06 a8 03 48 02 |         send.urb (8)              r8      r68            0x00000000  0x024803A8  // wr:1h+0, rd:4; simd8_read off=58 (8)
skl | 31 00 60 06 08 02 80 01 80 08 00 06 a8 05 48 02 |         send.urb (8)              r12     r68            0x00000000  0x024805A8  // wr:1h+0, rd:4; simd8_read off=90 (8)
skl | 31 00 60 06 08 02 c0 02 80 08 00 06 a8 07 48 02 |         send.urb (8)              r22     r68            0x00000000  0x024807A8  // wr:1h+0, rd:4; simd8_read off=122 (8)
skl | 31 00 60 06 08 02 00 01 a0 08 00 06 b8 03 48 02 |         send.urb (8)              r8      r69            0x00000000  0x024803B8  // wr:1h+0, rd:4; simd8_read off=59 (8)
skl | 31 00 60 06 08 02 80 01 a0 08 00 06 b8 05 48 02 |         send.urb (8)              r12     r69            0x00000000  0x024805B8  // wr:1h+0, rd:4; simd8_read off=91 (8)
skl | 31 00 60 06 08 02 c0 02 a0 08 00 06 b8 07 48 02 |         send.urb (8)              r22     r69            0x00000000  0x024807B8  // wr:1h+0, rd:4; simd8_read off=123 (8)
skl | 31 00 60 06 08 02 00 01 c0 08 00 06 c8 03 48 02 |         send.urb (8)              r8      r70            0x00000000  0x024803C8  // wr:1h+0, rd:4; simd8_read off=60 (8)
skl | 31 00 60 06 08 02 80 01 c0 08 00 06 c8 05 48 02 |         send.urb (8)              r12     r70            0x00000000  0x024805C8  // wr:1h+0, rd:4; simd8_read off=92 (8)
skl | 31 00 60 06 08 02 00 02 c0 08 00 06 c8 07 48 02 |         send.urb (8)              r16     r70            0x00000000  0x024807C8  // wr:1h+0, rd:4; simd8_read off=124 (8)
skl | 31 00 60 06 08 02 00 01 e0 08 00 06 d8 03 48 02 |         send.urb (8)              r8      r71            0x00000000  0x024803D8  // wr:1h+0, rd:4; simd8_read off=61 (8)
skl | 31 00 60 06 08 02 80 01 e0 08 00 06 d8 05 48 02 |         send.urb (8)              r12     r71            0x00000000  0x024805D8  // wr:1h+0, rd:4; simd8_read off=93 (8)
skl | 31 00 60 06 08 02 00 02 e0 08 00 06 d8 07 48 02 |         send.urb (8)              r16     r71            0x00000000  0x024807D8  // wr:1h+0, rd:4; simd8_read off=125 (8)
skl | 31 00 60 06 08 02 00 01 00 09 00 06 e8 03 48 02 |         send.urb (8)              r8      r72            0x00000000  0x024803E8  // wr:1h+0, rd:4; simd8_read off=62 (8)
skl | 31 00 60 06 08 02 80 01 00 09 00 06 e8 05 48 02 |         send.urb (8)              r12     r72            0x00000000  0x024805E8  // wr:1h+0, rd:4; simd8_read off=94 (8)
skl | 31 00 60 06 08 02 00 02 00 09 00 06 e8 07 48 02 |         send.urb (8)              r16     r72            0x00000000  0x024807E8  // wr:1h+0, rd:4; simd8_read off=126 (8)
skl | 31 00 60 06 08 02 00 01 20 09 00 06 f8 03 48 02 |         send.urb (8)              r8      r73            0x00000000  0x024803F8  // wr:1h+0, rd:4; simd8_read off=63 (8)
skl | 31 00 60 06 08 02 80 01 20 09 00 06 f8 05 48 02 |         send.urb (8)              r12     r73            0x00000000  0x024805F8  // wr:1h+0, rd:4; simd8_read off=95 (8)
skl | 31 00 60 06 08 02 00 02 20 09 00 06 f8 07 48 02 |         send.urb (8)              r16     r73            0x00000000  0x024807F8  // wr:1h+0, rd:4; simd8_read off=127 (8)
skl | 31 00 60 06 08 02 80 01 60 09 00 06 18 04 48 02 |         send.urb (8)              r12     r75            0x00000000  0x02480418  // wr:1h+0, rd:4; simd8_read off=65 (8)
skl | 31 00 60 06 08 02 00 02 60 09 00 06 18 06 48 02 |         send.urb (8)              r16     r75            0x00000000  0x02480618  // wr:1h+0, rd:4; simd8_read off=97 (8)
skl | 31 00 60 06 08 02 80 02 60 09 00 06 18 08 48 02 |         send.urb (8)              r20     r75            0x00000000  0x02480818  // wr:1h+0, rd:4; simd8_read off=129 (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 c7 00 0a 0c |         send.urb (8)              null    r20            0x00000000  0x0C0A00C7  // wr:6h+0, rd:0; simd8_write off=12 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 d7 00 0a 0c |         send.urb (8)              null    r21            0x00000000  0x0C0A00D7  // wr:6h+0, rd:0; simd8_write off=13 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 e7 00 0a 0c |         send.urb (8)              null    r22            0x00000000  0x0C0A00E7  // wr:6h+0, rd:0; simd8_write off=14 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 f7 00 0a 0c |         send.urb (8)              null    r23            0x00000000  0x0C0A00F7  // wr:6h+0, rd:0; simd8_write off=15 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 07 01 0a 0c |         send.urb (8)              null    r24            0x00000000  0x0C0A0107  // wr:6h+0, rd:0; simd8_write off=16 per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 17 01 0a 0c |         send.urb (8)              null    r25            0x00000000  0x0C0A0117  // wr:6h+0, rd:0; simd8_write off=17 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 37 01 0a 0c |         send.urb (8)              null    r27            0x00000000  0x0C0A0137  // wr:6h+0, rd:0; simd8_write off=19 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 47 01 0a 0c |         send.urb (8)              null    r28            0x00000000  0x0C0A0147  // wr:6h+0, rd:0; simd8_write off=20 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 57 01 0a 0c |         send.urb (8)              null    r29            0x00000000  0x0C0A0157  // wr:6h+0, rd:0; simd8_write off=21 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 67 01 0a 0c |         send.urb (8)              null    r30            0x00000000  0x0C0A0167  // wr:6h+0, rd:0; simd8_write off=22 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 77 01 0a 0c |         send.urb (8)              null    r31            0x00000000  0x0C0A0177  // wr:6h+0, rd:0; simd8_write off=23 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 87 01 0a 0c |         send.urb (8)              null    r32            0x00000000  0x0C0A0187  // wr:6h+0, rd:0; simd8_write off=24 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 a7 01 0a 0c |         send.urb (8)              null    r34            0x00000000  0x0C0A01A7  // wr:6h+0, rd:0; simd8_write off=26 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 b7 01 0a 0c |         send.urb (8)              null    r35            0x00000000  0x0C0A01B7  // wr:6h+0, rd:0; simd8_write off=27 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 c7 01 0a 0c |         send.urb (8)              null    r36            0x00000000  0x0C0A01C7  // wr:6h+0, rd:0; simd8_write off=28 per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 d7 01 0a 0c |         send.urb (8)              null    r37            0x00000000  0x0C0A01D7  // wr:6h+0, rd:0; simd8_write off=29 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 e7 01 0a 0c |         send.urb (8)              null    r38            0x00000000  0x0C0A01E7  // wr:6h+0, rd:0; simd8_write off=30 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 f7 01 0a 0c |         send.urb (8)              null    r39            0x00000000  0x0C0A01F7  // wr:6h+0, rd:0; simd8_write off=31 per_slot (8)
skl | 31 00 80 09 0c 02 c0 05 80 01 00 06 02 03 28 02 | (W)     send.hdc_ro (16)          r46     r12            0x00000000  0x02280302  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(2)
skl | 31 00 80 09 0c 02 40 06 e0 01 00 06 04 03 28 02 | (W)     send.hdc_ro (16)          r50     r15            0x00000000  0x02280304  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(4)
skl | 31 00 80 09 0c 02 40 04 80 02 00 06 03 03 28 02 | (W)     send.hdc_ro (16)          r34     r20            0x00000000  0x02280303  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(3)
skl | 31 00 80 09 0c 02 00 02 a0 02 00 06 06 03 28 02 | (W)     send.hdc_ro (16)          r16     r21            0x00000000  0x02280306  // wr:1h+0, rd:2; oword_block_read:owords4 (16) bti(6)
skl | 31 00 60 0c 08 02 a0 00 60 02 00 06 03 6e 10 02 |         send.hdc1 (8)             r5      r19            0x00000000  0x02106E03  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(3)
skl | 31 00 60 0c 08 02 00 01 a0 02 00 06 04 6e 10 02 |         send.hdc1 (8)             r8      r21            0x00000000  0x02106E04  // wr:1+0, rd:1; untyped_read:x simd8 (8) bti(4)
skl | 31 00 80 0c 08 02 00 01 40 04 00 06 03 5e 20 04 |         send.hdc1 (16)            r8      r34            0x00000000  0x04205E03  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(3)
skl | 31 00 80 0c 08 02 c0 01 a0 04 00 06 04 5e 20 04 |         send.hdc1 (16)            r14     r37            0x00000000  0x04205E04  // wr:2+0, rd:2; untyped_read:x simd16 (16) bti(4)
skl | 31 00 60 06 08 02 e0 01 80 01 00 06 38 00 1a 04 |         send.urb (8)              r15     r12            0x00000000  0x041A0038  // wr:2h+0, rd:1; simd8_read off=3 per_slot (8)
skl | 31 00 60 02 08 02 40 00 c0 06 00 06 07 a7 42 02 |         send.smpl (8)             r2      r54            0x00000000  0x0242A707  // wr:1+0, rd:4; resinfo:lod (8) bti(7) using sampler index 7
skl | 31 00 60 02 08 02 c0 00 e0 06 00 06 08 a8 42 02 |         send.smpl (8)             r6      r55            0x00000000  0x0242A808  // wr:1+0, rd:4; resinfo:lod (8) bti(8) using sampler index 8
skl | 31 00 60 02 08 02 40 01 00 07 00 06 09 a9 42 02 |         send.smpl (8)             r10     r56            0x00000000  0x0242A909  // wr:1+0, rd:4; resinfo:lod (8) bti(9) using sampler index 9
skl | 31 00 60 02 08 02 c0 01 20 07 00 06 0a aa 42 02 |         send.smpl (8)             r14     r57            0x00000000  0x0242AA0A  // wr:1+0, rd:4; resinfo:lod (8) bti(10) using sampler index 10
skl | 31 00 60 02 08 02 40 02 40 07 00 06 0b ab 42 02 |         send.smpl (8)             r18     r58            0x00000000  0x0242AB0B  // wr:1+0, rd:4; resinfo:lod (8) bti(11) using sampler index 11
skl | 31 00 60 02 08 02 c0 02 60 07 00 06 0c ac 42 02 |         send.smpl (8)             r22     r59            0x00000000  0x0242AC0C  // wr:1+0, rd:4; resinfo:lod (8) bti(12) using sampler index 12
skl | 31 00 60 06 00 02 00 00 20 01 00 06 27 80 08 0c |         send.urb (8)              null    r9             0x00000000  0x0C088027  // wr:6h+0, rd:0; simd8_write off=2 masked (8)
skl | 31 00 60 06 00 02 00 00 40 01 00 06 47 80 08 0c |         send.urb (8)              null    r10            0x00000000  0x0C088047  // wr:6h+0, rd:0; simd8_write off=4 masked (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 67 80 08 0c |         send.urb (8)              null    r11            0x00000000  0x0C088067  // wr:6h+0, rd:0; simd8_write off=6 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 37 80 08 0c |         send.urb (8)              null    r6             0x00000000  0x0C088037  // wr:6h+0, rd:0; simd8_write off=3 masked (8)
skl | 31 00 60 06 00 02 00 00 e0 00 00 06 57 80 08 0c |         send.urb (8)              null    r7             0x00000000  0x0C088057  // wr:6h+0, rd:0; simd8_write off=5 masked (8)
skl | 31 00 60 06 00 02 00 00 00 01 00 06 77 80 08 0c |         send.urb (8)              null    r8             0x00000000  0x0C088077  // wr:6h+0, rd:0; simd8_write off=7 masked (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 97 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A0197  // wr:10h+0, rd:0; simd8_write off=25 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 b7 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A01B7  // wr:10h+0, rd:0; simd8_write off=27 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 d7 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A01D7  // wr:10h+0, rd:0; simd8_write off=29 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 00 00 06 f7 01 0a 14 |         send.urb (8)              null    r6             0x00000000  0x140A01F7  // wr:10h+0, rd:0; simd8_write off=31 per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 0f 00 06 17 02 0a 8c |         send.urb (8)              null    r120           0x00000000  0x0C0A0217   {EOT}  // wr:6h+0, rd:0; simd8_write off=33 per_slot (8)
skl | 31 00 60 06 08 02 00 01 c0 00 00 06 18 03 1a 04 |         send.urb (8)              r8      r6             0x00000000  0x041A0318  // wr:2h+0, rd:1; simd8_read off=49 per_slot (8)
skl | 31 00 60 06 08 02 20 01 c0 00 00 06 18 05 1a 04 |         send.urb (8)              r9      r6             0x00000000  0x041A0518  // wr:2h+0, rd:1; simd8_read off=81 per_slot (8)
skl | 31 00 60 06 08 02 40 01 c0 00 00 06 18 07 1a 04 |         send.urb (8)              r10     r6             0x00000000  0x041A0718  // wr:2h+0, rd:1; simd8_read off=113 per_slot (8)
skl | 31 00 60 06 08 02 60 01 c0 00 00 06 18 09 1a 04 |         send.urb (8)              r11     r6             0x00000000  0x041A0918  // wr:2h+0, rd:1; simd8_read off=145 per_slot (8)
skl | 31 00 60 06 08 02 e0 00 60 01 00 06 18 02 1a 04 |         send.urb (8)              r7      r11            0x00000000  0x041A0218  // wr:2h+0, rd:1; simd8_read off=33 per_slot (8)
skl | 31 00 60 06 08 02 00 01 60 01 00 06 18 04 1a 04 |         send.urb (8)              r8      r11            0x00000000  0x041A0418  // wr:2h+0, rd:1; simd8_read off=65 per_slot (8)
skl | 31 00 60 06 08 02 20 01 60 01 00 06 18 06 1a 04 |         send.urb (8)              r9      r11            0x00000000  0x041A0618  // wr:2h+0, rd:1; simd8_read off=97 per_slot (8)
skl | 31 00 60 06 08 02 40 01 60 01 00 06 18 08 1a 04 |         send.urb (8)              r10     r11            0x00000000  0x041A0818  // wr:2h+0, rd:1; simd8_read off=129 per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 01 00 06 27 82 0a 08 |         send.urb (8)              null    r10            0x00000000  0x080A8227  // wr:4h+0, rd:0; simd8_write off=34 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 37 82 0a 08 |         send.urb (8)              null    r11            0x00000000  0x080A8237  // wr:4h+0, rd:0; simd8_write off=35 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 47 82 0a 08 |         send.urb (8)              null    r12            0x00000000  0x080A8247  // wr:4h+0, rd:0; simd8_write off=36 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 57 82 0a 08 |         send.urb (8)              null    r13            0x00000000  0x080A8257  // wr:4h+0, rd:0; simd8_write off=37 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 67 82 0a 08 |         send.urb (8)              null    r14            0x00000000  0x080A8267  // wr:4h+0, rd:0; simd8_write off=38 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 77 82 0a 08 |         send.urb (8)              null    r15            0x00000000  0x080A8277  // wr:4h+0, rd:0; simd8_write off=39 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 87 82 0a 08 |         send.urb (8)              null    r16            0x00000000  0x080A8287  // wr:4h+0, rd:0; simd8_write off=40 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 97 82 0a 08 |         send.urb (8)              null    r17            0x00000000  0x080A8297  // wr:4h+0, rd:0; simd8_write off=41 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 a7 82 0a 08 |         send.urb (8)              null    r18            0x00000000  0x080A82A7  // wr:4h+0, rd:0; simd8_write off=42 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 b7 82 0a 08 |         send.urb (8)              null    r19            0x00000000  0x080A82B7  // wr:4h+0, rd:0; simd8_write off=43 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 c7 82 0a 08 |         send.urb (8)              null    r20            0x00000000  0x080A82C7  // wr:4h+0, rd:0; simd8_write off=44 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 d7 82 0a 08 |         send.urb (8)              null    r21            0x00000000  0x080A82D7  // wr:4h+0, rd:0; simd8_write off=45 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 e7 82 0a 08 |         send.urb (8)              null    r22            0x00000000  0x080A82E7  // wr:4h+0, rd:0; simd8_write off=46 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 f7 82 0a 08 |         send.urb (8)              null    r23            0x00000000  0x080A82F7  // wr:4h+0, rd:0; simd8_write off=47 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 07 83 0a 08 |         send.urb (8)              null    r24            0x00000000  0x080A8307  // wr:4h+0, rd:0; simd8_write off=48 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 17 83 0a 08 |         send.urb (8)              null    r25            0x00000000  0x080A8317  // wr:4h+0, rd:0; simd8_write off=49 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 27 83 0a 08 |         send.urb (8)              null    r26            0x00000000  0x080A8327  // wr:4h+0, rd:0; simd8_write off=50 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 37 83 0a 08 |         send.urb (8)              null    r27            0x00000000  0x080A8337  // wr:4h+0, rd:0; simd8_write off=51 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 47 83 0a 08 |         send.urb (8)              null    r28            0x00000000  0x080A8347  // wr:4h+0, rd:0; simd8_write off=52 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 57 83 0a 08 |         send.urb (8)              null    r29            0x00000000  0x080A8357  // wr:4h+0, rd:0; simd8_write off=53 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 67 83 0a 08 |         send.urb (8)              null    r30            0x00000000  0x080A8367  // wr:4h+0, rd:0; simd8_write off=54 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 77 83 0a 08 |         send.urb (8)              null    r31            0x00000000  0x080A8377  // wr:4h+0, rd:0; simd8_write off=55 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 87 83 0a 08 |         send.urb (8)              null    r32            0x00000000  0x080A8387  // wr:4h+0, rd:0; simd8_write off=56 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 97 83 0a 08 |         send.urb (8)              null    r33            0x00000000  0x080A8397  // wr:4h+0, rd:0; simd8_write off=57 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 a7 83 0a 08 |         send.urb (8)              null    r34            0x00000000  0x080A83A7  // wr:4h+0, rd:0; simd8_write off=58 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 b7 83 0a 08 |         send.urb (8)              null    r35            0x00000000  0x080A83B7  // wr:4h+0, rd:0; simd8_write off=59 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 c7 83 0a 08 |         send.urb (8)              null    r36            0x00000000  0x080A83C7  // wr:4h+0, rd:0; simd8_write off=60 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 d7 83 0a 08 |         send.urb (8)              null    r37            0x00000000  0x080A83D7  // wr:4h+0, rd:0; simd8_write off=61 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 e7 83 0a 08 |         send.urb (8)              null    r38            0x00000000  0x080A83E7  // wr:4h+0, rd:0; simd8_write off=62 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 f7 83 0a 08 |         send.urb (8)              null    r39            0x00000000  0x080A83F7  // wr:4h+0, rd:0; simd8_write off=63 masked per_slot (8)
skl | 31 00 60 06 08 02 00 01 20 01 00 06 08 00 48 02 |         send.urb (8)              r8      r9             0x00000000  0x02480008  // wr:1h+0, rd:4; simd8_read (8)
skl | 31 00 60 06 00 02 00 00 60 0f 00 06 07 00 08 8a |         send.urb (8)              null    r123           0x00000000  0x0A080007   {EOT}  // wr:5h+0, rd:0; simd8_write (8)
skl | 31 00 60 0c 08 02 80 00 40 00 00 06 01 5c 21 04 |         send.hdc1 (8)             r4      r2             0x00000000  0x04215C01  // wr:2+0, rd:2; typed_read:xy simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 00 05 c0 04 00 06 01 6c 21 04 |         send.hdc1 (8|M8)          r40     r38            0x00000000  0x04216C01  // wr:2+0, rd:2; typed_read:xy simd8 (8) bti(1)
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 01 40 4a 10 |         send.smpl (8)             r6      r11            0x00000000  0x104A4001  // wr:8h+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 20 42 04 |         send.smpl (8)             r124    r2             0x00000000  0x04422001  // wr:2+0, rd:4; sample_l (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 40 00 00 06 01 20 84 08 |         send.smpl (16)            r120    r2             0x00000000  0x08842001  // wr:4+0, rd:8; sample_l (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 e0 00 00 06 01 50 42 06 |         send.smpl (8)             r2      r7             0x00000000  0x06425001  // wr:3+0, rd:4; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 02 51 42 06 |         send.smpl (8)             r6      r10            0x00000000  0x06425102  // wr:3+0, rd:4; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 60 01 00 06 01 50 84 0c |         send.smpl (16)            r2      r11            0x00000000  0x0C845001  // wr:6+0, rd:8; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 40 02 00 06 02 51 84 0c |         send.smpl (16)            r10     r18            0x00000000  0x0C845102  // wr:6+0, rd:8; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 06 00 02 00 00 20 0f 00 06 97 01 08 8a |         send.urb (8)              null    r121           0x00000000  0x0A080197   {EOT}  // wr:5h+0, rd:0; simd8_write off=25 (8)
skl | 31 00 60 0c 08 02 80 0f c0 00 00 06 00 50 41 02 |         send.hdc1 (8)             r124    r6             0x00000000  0x02415000  // wr:1+0, rd:4; typed_read:xyzw simd16 (8) bti(0)
skl | 31 00 60 0c 08 02 80 0f c0 00 00 06 00 50 41 06 |         send.hdc1 (8)             r124    r6             0x00000000  0x06415000  // wr:3+0, rd:4; typed_read:xyzw simd16 (8) bti(0)
skl | 31 00 60 0c 08 02 80 0f c0 00 00 06 00 5c 21 02 |         send.hdc1 (8)             r124    r6             0x00000000  0x02215C00  // wr:1+0, rd:2; typed_read:xy simd16 (8) bti(0)
skl | 31 00 60 0c 08 02 20 02 60 03 00 06 00 5e 11 02 |         send.hdc1 (8)             r17     r27            0x00000000  0x02115E00  // wr:1+0, rd:1; typed_read:x simd16 (8) bti(0)
skl | 31 00 60 0c 08 02 80 0f 40 00 00 06 01 50 41 02 |         send.hdc1 (8)             r124    r2             0x00000000  0x02415001  // wr:1+0, rd:4; typed_read:xyzw simd16 (8) bti(1)
skl | 31 10 60 0c 08 02 40 00 a0 03 00 06 01 60 41 02 |         send.hdc1 (8|M8)          r2      r29            0x00000000  0x02416001  // wr:1+0, rd:4; typed_read:xyzw simd8 (8) bti(1)
skl | 31 00 60 02 08 02 20 01 60 02 00 06 02 e1 43 08 |         send.smpl (8)             r9      r19            0x00000000  0x0843E102  // wr:4+0, rd:4; ld2dms:si,mcs,u,v,r,lod (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 e0 02 e0 00 00 06 02 e1 85 10 |         send.smpl (16)            r23     r7             0x00000000  0x1085E102  // wr:8+0, rd:8; ld2dms:si,mcs,u,v,r,lod (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 80 0f a0 00 00 06 01 00 4b 0c |         send.smpl (8)             r124    r5             0x00000000  0x0C4B0001  // wr:6h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f e0 00 00 06 01 00 8d 16 |         send.smpl (16)            r120    r7             0x00000000  0x168D0001  // wr:11h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 40 13 0a |         send.smpl (8)             r6      r7             0x00000000  0x0A134001  // wr:5+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 80 01 00 06 02 41 13 0a |         send.smpl (8)             r7      r12            0x00000000  0x0A134102  // wr:5+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 c0 02 40 01 00 06 38 01 1a 04 |         send.urb (8)              r22     r10            0x00000000  0x041A0138  // wr:2h+0, rd:1; simd8_read off=19 per_slot (8)
skl | 31 00 60 06 08 02 a0 02 40 01 00 06 38 03 1a 04 |         send.urb (8)              r21     r10            0x00000000  0x041A0338  // wr:2h+0, rd:1; simd8_read off=51 per_slot (8)
skl | 31 00 60 06 08 02 20 08 40 01 00 06 38 05 1a 04 |         send.urb (8)              r65     r10            0x00000000  0x041A0538  // wr:2h+0, rd:1; simd8_read off=83 per_slot (8)
skl | 31 00 60 06 08 02 40 01 40 01 00 06 38 07 1a 04 |         send.urb (8)              r10     r10            0x00000000  0x041A0738  // wr:2h+0, rd:1; simd8_read off=115 per_slot (8)
skl | 31 00 60 06 08 02 20 08 60 01 00 06 38 02 1a 04 |         send.urb (8)              r65     r11            0x00000000  0x041A0238  // wr:2h+0, rd:1; simd8_read off=35 per_slot (8)
skl | 31 00 60 06 08 02 40 01 60 01 00 06 38 04 1a 04 |         send.urb (8)              r10     r11            0x00000000  0x041A0438  // wr:2h+0, rd:1; simd8_read off=67 per_slot (8)
skl | 31 00 60 06 08 02 60 01 60 01 00 06 38 06 1a 04 |         send.urb (8)              r11     r11            0x00000000  0x041A0638  // wr:2h+0, rd:1; simd8_read off=99 per_slot (8)
skl | 31 00 60 06 08 02 00 01 e0 00 00 06 48 00 1a 04 |         send.urb (8)              r8      r7             0x00000000  0x041A0048  // wr:2h+0, rd:1; simd8_read off=4 per_slot (8)
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 01 40 4a 0a |         send.smpl (8)             r6      r10            0x00000000  0x0A4A4001  // wr:5h+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 e0 00 00 06 01 60 42 06 |         send.smpl (8)             r2      r7             0x00000000  0x06426001  // wr:3+0, rd:4; sample_l_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 02 61 42 06 |         send.smpl (8)             r6      r10            0x00000000  0x06426102  // wr:3+0, rd:4; sample_l_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 60 01 00 06 01 60 84 0c |         send.smpl (16)            r2      r11            0x00000000  0x0C846001  // wr:6+0, rd:8; sample_l_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 40 02 00 06 02 61 84 0c |         send.smpl (16)            r10     r18            0x00000000  0x0C846102  // wr:6+0, rd:8; sample_l_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 80 0f 40 00 00 06 01 00 32 08 |         send.smpl (8)             r124    r2             0x00000000  0x08320001  // wr:4+0, rd:3; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 00 0f 40 00 00 06 01 00 64 10 |         send.smpl (16)            r120    r2             0x00000000  0x10640001  // wr:8+0, rd:6; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 40 1b 0c |         send.smpl (8)             r6      r7             0x00000000  0x0C1B4001  // wr:6h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 a0 01 00 06 02 41 1b 0c |         send.smpl (8)             r7      r13            0x00000000  0x0C1B4102  // wr:6h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 e0 00 00 06 01 50 42 08 |         send.smpl (8)             r2      r7             0x00000000  0x08425001  // wr:4+0, rd:4; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 60 01 00 06 02 51 42 08 |         send.smpl (8)             r6      r11            0x00000000  0x08425102  // wr:4+0, rd:4; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 00 60 01 00 06 01 50 84 10 |         send.smpl (16)            r2      r11            0x00000000  0x10845001  // wr:8+0, rd:8; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 01 60 02 00 06 02 51 84 10 |         send.smpl (16)            r10     r19            0x00000000  0x10845102  // wr:8+0, rd:8; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 0c 08 02 80 0f 40 00 00 06 01 68 30 02 |         send.hdc1 (8)             r124    r2             0x00000000  0x02306801  // wr:1+0, rd:3; untyped_read:xyz simd8 (8) bti(1)
skl | 31 00 80 0c 08 02 00 0f 40 00 00 06 01 58 60 04 |         send.hdc1 (16)            r120    r2             0x00000000  0x04605801  // wr:2+0, rd:6; untyped_read:xyz simd16 (16) bti(1)
skl | 31 00 60 06 08 02 00 01 e0 00 00 06 28 01 3a 04 |         send.urb (8)              r8      r7             0x00000000  0x043A0128  // wr:2h+0, rd:3; simd8_read off=18 per_slot (8)
skl | 31 00 60 02 08 02 80 01 a0 00 00 06 01 e0 33 08 |         send.smpl (8)             r12     r5             0x00000000  0x0833E001  // wr:4+0, rd:3; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 01 20 02 00 06 01 e0 23 08 |         send.smpl (8)             r15     r17            0x00000000  0x0823E001  // wr:4+0, rd:2; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 a0 01 00 06 01 e0 65 10 |         send.smpl (16)            r7      r13            0x00000000  0x1065E001  // wr:8+0, rd:6; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 20 04 a0 02 00 06 01 e0 45 10 |         send.smpl (16)            r33     r21            0x00000000  0x1045E001  // wr:8+0, rd:4; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 c0 01 c0 01 00 06 01 40 1b 10 |         send.smpl (8)             r14     r14            0x00000000  0x101B4001  // wr:8h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 01 c0 02 00 06 02 41 1b 10 |         send.smpl (8)             r15     r22            0x00000000  0x101B4102  // wr:8h+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 00 01 80 02 00 06 38 01 4a 04 |         send.urb (8)              r8      r20            0x00000000  0x044A0138  // wr:2h+0, rd:4; simd8_read off=19 per_slot (8)
skl | 31 00 60 06 08 02 80 01 80 02 00 06 38 03 4a 04 |         send.urb (8)              r12     r20            0x00000000  0x044A0338  // wr:2h+0, rd:4; simd8_read off=51 per_slot (8)
skl | 31 00 60 06 08 02 00 02 80 02 00 06 38 05 4a 04 |         send.urb (8)              r16     r20            0x00000000  0x044A0538  // wr:2h+0, rd:4; simd8_read off=83 per_slot (8)
skl | 31 00 60 06 08 02 80 02 80 02 00 06 38 07 4a 04 |         send.urb (8)              r20     r20            0x00000000  0x044A0738  // wr:2h+0, rd:4; simd8_read off=115 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 c0 02 00 06 38 02 4a 04 |         send.urb (8)              r14     r22            0x00000000  0x044A0238  // wr:2h+0, rd:4; simd8_read off=35 per_slot (8)
skl | 31 00 60 06 08 02 40 02 c0 02 00 06 38 04 4a 04 |         send.urb (8)              r18     r22            0x00000000  0x044A0438  // wr:2h+0, rd:4; simd8_read off=67 per_slot (8)
skl | 31 00 60 06 08 02 c0 02 c0 02 00 06 38 06 4a 04 |         send.urb (8)              r22     r22            0x00000000  0x044A0638  // wr:2h+0, rd:4; simd8_read off=99 per_slot (8)
skl | 31 00 60 02 08 02 60 01 a0 00 00 06 03 00 12 04 |         send.smpl (8)             r11     r5             0x00000000  0x04120003  // wr:2+0, rd:1; sample:u,v,r,ai (8) bti(3) using sampler index 0
skl | 31 00 60 02 08 02 80 01 a0 00 00 06 04 00 12 04 |         send.smpl (8)             r12     r5             0x00000000  0x04120004  // wr:2+0, rd:1; sample:u,v,r,ai (8) bti(4) using sampler index 0
skl | 31 00 80 02 08 02 00 01 80 01 00 06 03 00 24 08 |         send.smpl (16)            r8      r12            0x00000000  0x08240003  // wr:4+0, rd:2; sample:u,v,r,ai (16) bti(3) using sampler index 0
skl | 31 00 80 02 08 02 40 01 80 01 00 06 04 00 24 08 |         send.smpl (16)            r10     r12            0x00000000  0x08240004  // wr:4+0, rd:2; sample:u,v,r,ai (16) bti(4) using sampler index 0
skl | 31 00 60 02 08 02 c0 00 e0 00 00 06 01 50 12 08 |         send.smpl (8)             r6      r7             0x00000000  0x08125001  // wr:4+0, rd:1; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 00 60 01 00 06 02 51 12 08 |         send.smpl (8)             r7      r11            0x00000000  0x08125102  // wr:4+0, rd:1; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 40 01 80 01 00 06 01 50 24 10 |         send.smpl (16)            r10     r12            0x00000000  0x10245001  // wr:8+0, rd:2; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 01 80 02 00 06 02 51 24 10 |         send.smpl (16)            r12     r20            0x00000000  0x10245102  // wr:8+0, rd:2; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 a0 01 00 06 01 a0 23 06 |         send.smpl (8)             r2      r13            0x00000000  0x0623A001  // wr:3+0, rd:2; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 00 e0 02 00 06 01 a0 45 0c |         send.smpl (16)            r6      r23            0x00000000  0x0C45A001  // wr:6+0, rd:4; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f e0 00 00 06 00 20 4b 0c |         send.smpl (8)             r124    r7             0x00000000  0x0C4B2000  // wr:6h+0, rd:4; gather4_po_c (8) bti(0) using sampler index 0
skl | 31 00 60 06 08 02 a0 01 e0 04 00 06 58 00 1a 04 |         send.urb (8)              r13     r39            0x00000000  0x041A0058  // wr:2h+0, rd:1; simd8_read off=5 per_slot (8)
skl | 31 00 60 06 08 02 80 00 40 01 00 06 68 00 1a 04 |         send.urb (8)              r4      r10            0x00000000  0x041A0068  // wr:2h+0, rd:1; simd8_read off=6 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 78 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A0078  // wr:2h+0, rd:1; simd8_read off=7 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 88 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A0088  // wr:2h+0, rd:1; simd8_read off=8 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 98 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A0098  // wr:2h+0, rd:1; simd8_read off=9 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 a8 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A00A8  // wr:2h+0, rd:1; simd8_read off=10 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 b8 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A00B8  // wr:2h+0, rd:1; simd8_read off=11 per_slot (8)
skl | 31 00 60 06 08 02 80 00 60 00 00 06 c8 00 1a 04 |         send.urb (8)              r4      r3             0x00000000  0x041A00C8  // wr:2h+0, rd:1; simd8_read off=12 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 d8 00 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A00D8  // wr:2h+0, rd:1; simd8_read off=13 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 e8 00 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A00E8  // wr:2h+0, rd:1; simd8_read off=14 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 f8 00 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A00F8  // wr:2h+0, rd:1; simd8_read off=15 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 08 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0108  // wr:2h+0, rd:1; simd8_read off=16 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 18 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0118  // wr:2h+0, rd:1; simd8_read off=17 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 48 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0148  // wr:2h+0, rd:1; simd8_read off=20 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 58 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0158  // wr:2h+0, rd:1; simd8_read off=21 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 68 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0168  // wr:2h+0, rd:1; simd8_read off=22 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 78 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0178  // wr:2h+0, rd:1; simd8_read off=23 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 88 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0188  // wr:2h+0, rd:1; simd8_read off=24 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 98 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0198  // wr:2h+0, rd:1; simd8_read off=25 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 a8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01A8  // wr:2h+0, rd:1; simd8_read off=26 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 b8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01B8  // wr:2h+0, rd:1; simd8_read off=27 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 c8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01C8  // wr:2h+0, rd:1; simd8_read off=28 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 d8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01D8  // wr:2h+0, rd:1; simd8_read off=29 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 e8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01E8  // wr:2h+0, rd:1; simd8_read off=30 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 f8 01 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A01F8  // wr:2h+0, rd:1; simd8_read off=31 per_slot (8)
skl | 31 00 60 06 08 02 60 00 40 00 00 06 08 02 1a 04 |         send.urb (8)              r3      r2             0x00000000  0x041A0208  // wr:2h+0, rd:1; simd8_read off=32 per_slot (8)
skl | 31 00 60 02 08 02 c0 04 c0 04 00 06 05 84 4a 08 |         send.smpl (8)             r38     r38            0x00000000  0x084A8405  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 c0 05 e0 02 00 06 04 83 4a 06 |         send.smpl (8)             r46     r23            0x00000000  0x064A8304  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 80 03 80 03 00 06 06 85 4a 06 |         send.smpl (8)             r28     r28            0x00000000  0x064A8506  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(6) using sampler index 5
skl | 31 00 60 02 08 02 80 01 e0 02 00 06 07 86 4a 06 |         send.smpl (8)             r12     r23            0x00000000  0x064A8607  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(7) using sampler index 6
skl | 31 00 60 02 08 02 80 01 00 04 00 06 08 87 4a 08 |         send.smpl (8)             r12     r32            0x00000000  0x084A8708  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(8) using sampler index 7
skl | 31 00 60 02 08 02 40 03 a0 01 00 06 09 88 4a 06 |         send.smpl (8)             r26     r13            0x00000000  0x064A8809  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(9) using sampler index 8
skl | 31 00 60 02 08 02 40 03 40 03 00 06 0a 09 4b 08 |         send.smpl (8)             r26     r26            0x00000000  0x084B090A  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(10) using sampler index 9
skl | 31 00 60 02 08 02 40 00 40 00 00 06 0b 0a 4b 0a |         send.smpl (8)             r2      r2             0x00000000  0x0A4B0A0B  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(11) using sampler index 10
skl | 31 00 60 02 08 02 c0 00 c0 00 00 06 0c 0b 4b 08 |         send.smpl (8)             r6      r6             0x00000000  0x084B0B0C  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(12) using sampler index 11
skl | 31 00 80 02 08 02 c0 03 20 09 00 06 04 83 8c 0a |         send.smpl (16)            r30     r73            0x00000000  0x0A8C8304  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 00 05 40 00 00 06 05 84 8c 0e |         send.smpl (16)            r40     r2             0x00000000  0x0E8C8405  // wr:7h+0, rd:8; gather4:u,v,r,ai (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 a0 00 20 04 00 06 06 85 8c 0a |         send.smpl (16)            r5      r33            0x00000000  0x0A8C8506  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(6) using sampler index 5
skl | 31 00 80 02 08 02 00 04 e0 06 00 06 07 86 8c 0a |         send.smpl (16)            r32     r55            0x00000000  0x0A8C8607  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(7) using sampler index 6
skl | 31 00 80 02 08 02 c0 03 e0 02 00 06 08 87 8c 0e |         send.smpl (16)            r30     r23            0x00000000  0x0E8C8708  // wr:7h+0, rd:8; gather4:u,v,r,ai (16) bti(8) using sampler index 7
skl | 31 00 80 02 08 02 a0 00 00 05 00 06 09 88 8c 0a |         send.smpl (16)            r5      r40            0x00000000  0x0A8C8809  // wr:5h+0, rd:8; gather4:u,v,r,ai (16) bti(9) using sampler index 8
skl | 31 00 80 02 08 02 c0 04 60 08 00 06 0a 09 8d 0e |         send.smpl (16)            r38     r67            0x00000000  0x0E8D090A  // wr:7h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(10) using sampler index 9
skl | 31 00 80 02 08 02 c0 04 40 00 00 06 0b 0a 8d 12 |         send.smpl (16)            r38     r2             0x00000000  0x128D0A0B  // wr:9h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(11) using sampler index 10
skl | 31 00 80 02 08 02 40 01 e0 04 00 06 0c 0b 8d 0e |         send.smpl (16)            r10     r39            0x00000000  0x0E8D0B0C  // wr:7h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(12) using sampler index 11
skl | 31 00 60 02 08 02 40 00 c0 00 00 06 00 20 4b 0e |         send.smpl (8)             r2      r6             0x00000000  0x0E4B2000  // wr:7h+0, rd:4; gather4_po_c (8) bti(0) using sampler index 0
skl | 31 00 60 02 08 02 60 01 e0 00 00 06 02 01 12 04 |         send.smpl (8)             r11     r7             0x00000000  0x04120102  // wr:2+0, rd:1; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 80 01 e0 00 00 06 03 02 12 04 |         send.smpl (8)             r12     r7             0x00000000  0x04120203  // wr:2+0, rd:1; sample:u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 c0 00 60 01 00 06 02 01 24 08 |         send.smpl (16)            r6      r11            0x00000000  0x08240102  // wr:4+0, rd:2; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 00 01 60 01 00 06 03 02 24 08 |         send.smpl (16)            r8      r11            0x00000000  0x08240203  // wr:4+0, rd:2; sample:u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 a0 00 c0 00 00 06 03 00 22 04 |         send.smpl (8)             r5      r6             0x00000000  0x04220003  // wr:2+0, rd:2; sample:u,v,r,ai (8) bti(3) using sampler index 0
skl | 31 00 80 02 08 02 00 01 80 01 00 06 03 00 44 08 |         send.smpl (16)            r8      r12            0x00000000  0x08440003  // wr:4+0, rd:4; sample:u,v,r,ai (16) bti(3) using sampler index 0
skl | 31 00 60 02 08 02 a0 00 40 00 00 06 01 90 12 04 |         send.smpl (8)             r5      r2             0x00000000  0x04129001  // wr:2+0, rd:1; lod:u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 c0 00 40 00 00 06 01 90 24 08 |         send.smpl (16)            r6      r2             0x00000000  0x08249001  // wr:4+0, rd:2; lod:u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 0c 08 02 60 01 80 00 00 06 02 50 41 04 |         send.hdc1 (8)             r11     r4             0x00000000  0x04415002  // wr:2+0, rd:4; typed_read:xyzw simd16 (8) bti(2)
skl | 31 10 60 0c 08 02 e0 00 a0 00 00 06 02 60 41 04 |         send.hdc1 (8|M8)          r7      r5             0x00000000  0x04416002  // wr:2+0, rd:4; typed_read:xyzw simd8 (8) bti(2)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 57 80 0a 0e |         send.urb (8)              null    r16            0x00000000  0x0E0A8057  // wr:7h+0, rd:0; simd8_write off=5 masked per_slot (8)
skl | 31 00 60 06 08 02 c0 00 40 02 00 06 18 03 3a 04 |         send.urb (8)              r6      r18            0x00000000  0x043A0318  // wr:2h+0, rd:3; simd8_read off=49 per_slot (8)
skl | 31 00 60 06 08 02 20 01 40 02 00 06 18 05 3a 04 |         send.urb (8)              r9      r18            0x00000000  0x043A0518  // wr:2h+0, rd:3; simd8_read off=81 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 02 00 06 18 07 3a 04 |         send.urb (8)              r12     r18            0x00000000  0x043A0718  // wr:2h+0, rd:3; simd8_read off=113 per_slot (8)
skl | 31 00 60 06 08 02 e0 01 40 02 00 06 18 09 3a 04 |         send.urb (8)              r15     r18            0x00000000  0x043A0918  // wr:2h+0, rd:3; simd8_read off=145 per_slot (8)
skl | 31 00 60 06 08 02 60 01 e0 02 00 06 18 02 3a 04 |         send.urb (8)              r11     r23            0x00000000  0x043A0218  // wr:2h+0, rd:3; simd8_read off=33 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 e0 02 00 06 18 04 3a 04 |         send.urb (8)              r14     r23            0x00000000  0x043A0418  // wr:2h+0, rd:3; simd8_read off=65 per_slot (8)
skl | 31 00 60 06 08 02 20 02 e0 02 00 06 18 06 3a 04 |         send.urb (8)              r17     r23            0x00000000  0x043A0618  // wr:2h+0, rd:3; simd8_read off=97 per_slot (8)
skl | 31 00 60 06 08 02 80 02 e0 02 00 06 18 08 3a 04 |         send.urb (8)              r20     r23            0x00000000  0x043A0818  // wr:2h+0, rd:3; simd8_read off=129 per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 01 00 06 27 82 0a 0c |         send.urb (8)              null    r12            0x00000000  0x0C0A8227  // wr:6h+0, rd:0; simd8_write off=34 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 01 00 06 37 82 0a 0c |         send.urb (8)              null    r13            0x00000000  0x0C0A8237  // wr:6h+0, rd:0; simd8_write off=35 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 01 00 06 47 82 0a 0c |         send.urb (8)              null    r14            0x00000000  0x0C0A8247  // wr:6h+0, rd:0; simd8_write off=36 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 01 00 06 57 82 0a 0c |         send.urb (8)              null    r15            0x00000000  0x0C0A8257  // wr:6h+0, rd:0; simd8_write off=37 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 02 00 06 67 82 0a 0c |         send.urb (8)              null    r16            0x00000000  0x0C0A8267  // wr:6h+0, rd:0; simd8_write off=38 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 02 00 06 77 82 0a 0c |         send.urb (8)              null    r17            0x00000000  0x0C0A8277  // wr:6h+0, rd:0; simd8_write off=39 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 02 00 06 87 82 0a 0c |         send.urb (8)              null    r18            0x00000000  0x0C0A8287  // wr:6h+0, rd:0; simd8_write off=40 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 02 00 06 97 82 0a 0c |         send.urb (8)              null    r19            0x00000000  0x0C0A8297  // wr:6h+0, rd:0; simd8_write off=41 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 02 00 06 a7 82 0a 0c |         send.urb (8)              null    r20            0x00000000  0x0C0A82A7  // wr:6h+0, rd:0; simd8_write off=42 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 02 00 06 b7 82 0a 0c |         send.urb (8)              null    r21            0x00000000  0x0C0A82B7  // wr:6h+0, rd:0; simd8_write off=43 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 02 00 06 c7 82 0a 0c |         send.urb (8)              null    r22            0x00000000  0x0C0A82C7  // wr:6h+0, rd:0; simd8_write off=44 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 02 00 06 d7 82 0a 0c |         send.urb (8)              null    r23            0x00000000  0x0C0A82D7  // wr:6h+0, rd:0; simd8_write off=45 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 03 00 06 e7 82 0a 0c |         send.urb (8)              null    r24            0x00000000  0x0C0A82E7  // wr:6h+0, rd:0; simd8_write off=46 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 03 00 06 f7 82 0a 0c |         send.urb (8)              null    r25            0x00000000  0x0C0A82F7  // wr:6h+0, rd:0; simd8_write off=47 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 03 00 06 07 83 0a 0c |         send.urb (8)              null    r26            0x00000000  0x0C0A8307  // wr:6h+0, rd:0; simd8_write off=48 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 03 00 06 17 83 0a 0c |         send.urb (8)              null    r27            0x00000000  0x0C0A8317  // wr:6h+0, rd:0; simd8_write off=49 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 03 00 06 27 83 0a 0c |         send.urb (8)              null    r28            0x00000000  0x0C0A8327  // wr:6h+0, rd:0; simd8_write off=50 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 03 00 06 37 83 0a 0c |         send.urb (8)              null    r29            0x00000000  0x0C0A8337  // wr:6h+0, rd:0; simd8_write off=51 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 03 00 06 47 83 0a 0c |         send.urb (8)              null    r30            0x00000000  0x0C0A8347  // wr:6h+0, rd:0; simd8_write off=52 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 57 83 0a 0c |         send.urb (8)              null    r31            0x00000000  0x0C0A8357  // wr:6h+0, rd:0; simd8_write off=53 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 04 00 06 67 83 0a 0c |         send.urb (8)              null    r32            0x00000000  0x0C0A8367  // wr:6h+0, rd:0; simd8_write off=54 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 04 00 06 77 83 0a 0c |         send.urb (8)              null    r33            0x00000000  0x0C0A8377  // wr:6h+0, rd:0; simd8_write off=55 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 40 04 00 06 87 83 0a 0c |         send.urb (8)              null    r34            0x00000000  0x0C0A8387  // wr:6h+0, rd:0; simd8_write off=56 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 04 00 06 97 83 0a 0c |         send.urb (8)              null    r35            0x00000000  0x0C0A8397  // wr:6h+0, rd:0; simd8_write off=57 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 80 04 00 06 a7 83 0a 0c |         send.urb (8)              null    r36            0x00000000  0x0C0A83A7  // wr:6h+0, rd:0; simd8_write off=58 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 a0 04 00 06 b7 83 0a 0c |         send.urb (8)              null    r37            0x00000000  0x0C0A83B7  // wr:6h+0, rd:0; simd8_write off=59 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 04 00 06 c7 83 0a 0c |         send.urb (8)              null    r38            0x00000000  0x0C0A83C7  // wr:6h+0, rd:0; simd8_write off=60 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 04 00 06 d7 83 0a 0c |         send.urb (8)              null    r39            0x00000000  0x0C0A83D7  // wr:6h+0, rd:0; simd8_write off=61 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 00 05 00 06 e7 83 0a 0c |         send.urb (8)              null    r40            0x00000000  0x0C0A83E7  // wr:6h+0, rd:0; simd8_write off=62 masked per_slot (8)
skl | 31 00 60 06 00 02 00 00 20 05 00 06 f7 83 0a 0c |         send.urb (8)              null    r41            0x00000000  0x0C0A83F7  // wr:6h+0, rd:0; simd8_write off=63 masked per_slot (8)
skl | 31 00 60 02 08 02 00 01 e0 00 00 06 01 40 13 10 |         send.smpl (8)             r8      r7             0x00000000  0x10134001  // wr:8+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 20 01 e0 01 00 06 02 41 13 10 |         send.smpl (8)             r9      r15            0x00000000  0x10134102  // wr:8+0, rd:1; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(2) using sampler index 1
skl | 31 00 60 06 08 02 00 02 00 02 00 06 48 01 4a 04 |         send.urb (8)              r16     r16            0x00000000  0x044A0148  // wr:2h+0, rd:4; simd8_read off=20 per_slot (8)
skl | 31 00 60 02 08 02 c0 04 c0 04 00 06 04 84 4a 08 |         send.smpl (8)             r38     r38            0x00000000  0x084A8404  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 c0 05 e0 02 00 06 03 83 4a 06 |         send.smpl (8)             r46     r23            0x00000000  0x064A8303  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(3) using sampler index 3
skl | 31 00 60 02 08 02 80 03 80 03 00 06 05 85 4a 06 |         send.smpl (8)             r28     r28            0x00000000  0x064A8505  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(5) using sampler index 5
skl | 31 00 60 02 08 02 80 01 e0 02 00 06 06 86 4a 06 |         send.smpl (8)             r12     r23            0x00000000  0x064A8606  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(6) using sampler index 6
skl | 31 00 60 02 08 02 80 01 00 04 00 06 07 87 4a 08 |         send.smpl (8)             r12     r32            0x00000000  0x084A8707  // wr:4h+0, rd:4; gather4:u,v,r,ai (8) bti(7) using sampler index 7
skl | 31 00 60 02 08 02 40 03 a0 01 00 06 08 88 4a 06 |         send.smpl (8)             r26     r13            0x00000000  0x064A8808  // wr:3h+0, rd:4; gather4:u,v,r,ai (8) bti(8) using sampler index 8
skl | 31 00 60 02 08 02 40 03 40 03 00 06 09 09 4b 08 |         send.smpl (8)             r26     r26            0x00000000  0x084B0909  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(9) using sampler index 9
skl | 31 00 60 02 08 02 40 00 40 00 00 06 0a 0a 4b 0a |         send.smpl (8)             r2      r2             0x00000000  0x0A4B0A0A  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(10) using sampler index 10
skl | 31 00 60 02 08 02 40 01 40 01 00 06 0b 0b 4b 08 |         send.smpl (8)             r10     r10            0x00000000  0x084B0B0B  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(11) using sampler index 11
skl | 31 00 60 06 08 02 40 00 e0 01 00 06 48 00 3a 04 |         send.urb (8)              r2      r15            0x00000000  0x043A0048  // wr:2h+0, rd:3; simd8_read off=4 per_slot (8)
skl | 31 00 60 06 08 02 80 01 e0 01 00 06 58 00 3a 04 |         send.urb (8)              r12     r15            0x00000000  0x043A0058  // wr:2h+0, rd:3; simd8_read off=5 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 68 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0068  // wr:2h+0, rd:3; simd8_read off=6 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 78 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0078  // wr:2h+0, rd:3; simd8_read off=7 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 88 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0088  // wr:2h+0, rd:3; simd8_read off=8 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 98 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0098  // wr:2h+0, rd:3; simd8_read off=9 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 a8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00A8  // wr:2h+0, rd:3; simd8_read off=10 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 b8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00B8  // wr:2h+0, rd:3; simd8_read off=11 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 c8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00C8  // wr:2h+0, rd:3; simd8_read off=12 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 d8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00D8  // wr:2h+0, rd:3; simd8_read off=13 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 e8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00E8  // wr:2h+0, rd:3; simd8_read off=14 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 f8 00 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A00F8  // wr:2h+0, rd:3; simd8_read off=15 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 08 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0108  // wr:2h+0, rd:3; simd8_read off=16 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 18 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0118  // wr:2h+0, rd:3; simd8_read off=17 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 38 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0138  // wr:2h+0, rd:3; simd8_read off=19 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 48 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0148  // wr:2h+0, rd:3; simd8_read off=20 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 58 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0158  // wr:2h+0, rd:3; simd8_read off=21 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 68 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0168  // wr:2h+0, rd:3; simd8_read off=22 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 78 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0178  // wr:2h+0, rd:3; simd8_read off=23 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 88 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0188  // wr:2h+0, rd:3; simd8_read off=24 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 98 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0198  // wr:2h+0, rd:3; simd8_read off=25 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 a8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01A8  // wr:2h+0, rd:3; simd8_read off=26 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 b8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01B8  // wr:2h+0, rd:3; simd8_read off=27 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 c8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01C8  // wr:2h+0, rd:3; simd8_read off=28 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 d8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01D8  // wr:2h+0, rd:3; simd8_read off=29 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 e8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01E8  // wr:2h+0, rd:3; simd8_read off=30 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 f8 01 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A01F8  // wr:2h+0, rd:3; simd8_read off=31 per_slot (8)
skl | 31 00 60 06 08 02 40 00 40 00 00 06 08 02 3a 04 |         send.urb (8)              r2      r2             0x00000000  0x043A0208  // wr:2h+0, rd:3; simd8_read off=32 per_slot (8)
skl | 31 00 60 06 00 02 00 00 60 01 00 06 47 00 0a 14 |         send.urb (8)              null    r11            0x00000000  0x140A0047  // wr:10h+0, rd:0; simd8_write off=4 per_slot (8)
skl | 31 00 60 06 00 02 00 00 e0 03 00 06 87 00 0a 14 |         send.urb (8)              null    r31            0x00000000  0x140A0087  // wr:10h+0, rd:0; simd8_write off=8 per_slot (8)
skl | 31 00 60 06 00 02 00 00 c0 0e 00 06 87 00 0a 94 |         send.urb (8)              null    r118           0x00000000  0x140A0087   {EOT}  // wr:10h+0, rd:0; simd8_write off=8 per_slot (8)
skl | 31 00 60 02 08 02 c0 01 60 01 00 06 02 02 4b 0a |         send.smpl (8)             r14     r11            0x00000000  0x0A4B0202  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 40 02 40 02 00 06 03 03 4b 0c |         send.smpl (8)             r18     r18            0x00000000  0x0C4B0303  // wr:6h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(3) using sampler index 3
skl | 31 00 60 02 08 02 c0 02 00 03 00 06 04 04 4b 08 |         send.smpl (8)             r22     r24            0x00000000  0x084B0404  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 e0 01 40 00 00 06 03 32 42 06 |         send.smpl (8)             r15     r2             0x00000000  0x06423203  // wr:3+0, rd:4; sample_c:ref,u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 60 02 60 03 00 06 03 32 84 0c |         send.smpl (16)            r19     r27            0x00000000  0x0C843203  // wr:6+0, rd:8; sample_c:ref,u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 e0 00 20 01 00 06 01 c0 13 0a |         send.smpl (8)             r7      r9             0x00000000  0x0A13C001  // wr:5+0, rd:1; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 80 02 e0 00 00 06 01 c0 25 14 |         send.smpl (16)            r20     r7             0x00000000  0x1425C001  // wr:10+0, rd:2; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 a0 02 a0 00 00 06 01 c0 33 0a |         send.smpl (8)             r21     r5             0x00000000  0x0A33C001  // wr:5+0, rd:3; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 02 00 03 00 06 01 c0 23 0a |         send.smpl (8)             r18     r24            0x00000000  0x0A23C001  // wr:5+0, rd:2; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 01 a0 02 00 06 01 c0 65 14 |         send.smpl (16)            r15     r21            0x00000000  0x1465C001  // wr:10+0, rd:6; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 e0 00 e0 03 00 06 01 c0 45 14 |         send.smpl (16)            r7      r31            0x00000000  0x1445C001  // wr:10+0, rd:4; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 80 0f c0 00 00 06 03 83 43 04 |         send.smpl (8)             r124    r6             0x00000000  0x04438303  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(3) using sampler index 3
skl | 31 00 60 06 08 02 60 01 20 02 00 06 38 03 3a 04 |         send.urb (8)              r11     r17            0x00000000  0x043A0338  // wr:2h+0, rd:3; simd8_read off=51 per_slot (8)
skl | 31 00 60 06 08 02 c0 01 20 02 00 06 38 05 3a 04 |         send.urb (8)              r14     r17            0x00000000  0x043A0538  // wr:2h+0, rd:3; simd8_read off=83 per_slot (8)
skl | 31 00 60 06 08 02 20 02 20 02 00 06 38 07 3a 04 |         send.urb (8)              r17     r17            0x00000000  0x043A0738  // wr:2h+0, rd:3; simd8_read off=115 per_slot (8)
skl | 31 00 60 06 08 02 20 01 40 02 00 06 38 00 3a 04 |         send.urb (8)              r9      r18            0x00000000  0x043A0038  // wr:2h+0, rd:3; simd8_read off=3 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 02 00 06 38 02 3a 04 |         send.urb (8)              r12     r18            0x00000000  0x043A0238  // wr:2h+0, rd:3; simd8_read off=35 per_slot (8)
skl | 31 00 60 06 08 02 e0 01 40 02 00 06 38 04 3a 04 |         send.urb (8)              r15     r18            0x00000000  0x043A0438  // wr:2h+0, rd:3; simd8_read off=67 per_slot (8)
skl | 31 00 60 06 08 02 40 02 40 02 00 06 38 06 3a 04 |         send.urb (8)              r18     r18            0x00000000  0x043A0638  // wr:2h+0, rd:3; simd8_read off=99 per_slot (8)
skl | 31 00 60 02 08 02 c0 00 40 01 00 06 01 40 42 08 |         send.smpl (8)             r6      r10            0x00000000  0x08424001  // wr:4+0, rd:4; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 20 01 a0 00 00 06 02 00 42 04 |         send.smpl (8)             r9      r5             0x00000000  0x04420002  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(2) using sampler index 0
skl | 31 00 80 02 08 02 a0 01 e0 00 00 06 02 00 84 08 |         send.smpl (16)            r13     r7             0x00000000  0x08840002  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(2) using sampler index 0
skl | 31 00 61 0c 0a 02 80 0f 40 00 00 06 01 a5 11 02 | (f1.0)  send.hdc1 (8)             r124    r2             0x00000000  0x0211A501  // wr:1+0, rd:1; typed_atomic_inc simd16 (8) bti(1)
skl | 31 10 61 0c 0a 02 20 0f 60 00 00 06 01 b5 11 02 | (f1.0)  send.hdc1 (8|M8)          r121    r3             0x00000000  0x0211B501  // wr:1+0, rd:1; typed_atomic_inc simd8 (8) bti(1)
skl | 31 00 60 06 08 02 c0 02 00 04 00 06 38 02 28 02 |         send.urb (8)              r22     r32            0x00000000  0x02280238  // wr:1h+0, rd:2; simd8_read off=35 (8)
skl | 31 00 60 06 08 02 00 03 00 04 00 06 38 04 28 02 |         send.urb (8)              r24     r32            0x00000000  0x02280438  // wr:1h+0, rd:2; simd8_read off=67 (8)
skl | 31 00 60 06 08 02 40 03 00 04 00 06 38 06 28 02 |         send.urb (8)              r26     r32            0x00000000  0x02280638  // wr:1h+0, rd:2; simd8_read off=99 (8)
skl | 31 00 60 06 08 02 80 03 00 04 00 06 48 02 28 02 |         send.urb (8)              r28     r32            0x00000000  0x02280248  // wr:1h+0, rd:2; simd8_read off=36 (8)
skl | 31 00 60 06 08 02 c0 03 00 04 00 06 48 04 28 02 |         send.urb (8)              r30     r32            0x00000000  0x02280448  // wr:1h+0, rd:2; simd8_read off=68 (8)
skl | 31 00 60 06 08 02 00 04 00 04 00 06 48 06 28 02 |         send.urb (8)              r32     r32            0x00000000  0x02280648  // wr:1h+0, rd:2; simd8_read off=100 (8)
skl | 31 00 60 06 08 02 c0 02 20 04 00 06 58 02 28 02 |         send.urb (8)              r22     r33            0x00000000  0x02280258  // wr:1h+0, rd:2; simd8_read off=37 (8)
skl | 31 00 60 06 08 02 00 03 20 04 00 06 58 04 28 02 |         send.urb (8)              r24     r33            0x00000000  0x02280458  // wr:1h+0, rd:2; simd8_read off=69 (8)
skl | 31 00 60 06 08 02 40 03 20 04 00 06 58 06 28 02 |         send.urb (8)              r26     r33            0x00000000  0x02280658  // wr:1h+0, rd:2; simd8_read off=101 (8)
skl | 31 00 60 06 08 02 c0 02 40 04 00 06 68 02 28 02 |         send.urb (8)              r22     r34            0x00000000  0x02280268  // wr:1h+0, rd:2; simd8_read off=38 (8)
skl | 31 00 60 06 08 02 00 03 40 04 00 06 68 04 28 02 |         send.urb (8)              r24     r34            0x00000000  0x02280468  // wr:1h+0, rd:2; simd8_read off=70 (8)
skl | 31 00 60 06 08 02 40 03 40 04 00 06 68 06 28 02 |         send.urb (8)              r26     r34            0x00000000  0x02280668  // wr:1h+0, rd:2; simd8_read off=102 (8)
skl | 31 00 60 06 08 02 00 03 60 04 00 06 78 04 28 02 |         send.urb (8)              r24     r35            0x00000000  0x02280478  // wr:1h+0, rd:2; simd8_read off=71 (8)
skl | 31 00 60 06 08 02 c0 02 60 04 00 06 78 02 28 02 |         send.urb (8)              r22     r35            0x00000000  0x02280278  // wr:1h+0, rd:2; simd8_read off=39 (8)
skl | 31 00 60 06 08 02 40 03 60 04 00 06 78 06 28 02 |         send.urb (8)              r26     r35            0x00000000  0x02280678  // wr:1h+0, rd:2; simd8_read off=103 (8)
skl | 31 00 60 06 08 02 00 03 80 04 00 06 88 06 28 02 |         send.urb (8)              r24     r36            0x00000000  0x02280688  // wr:1h+0, rd:2; simd8_read off=104 (8)
skl | 31 00 60 06 08 02 00 01 80 04 00 06 88 02 28 02 |         send.urb (8)              r8      r36            0x00000000  0x02280288  // wr:1h+0, rd:2; simd8_read off=40 (8)
skl | 31 00 60 06 08 02 c0 02 80 04 00 06 88 04 28 02 |         send.urb (8)              r22     r36            0x00000000  0x02280488  // wr:1h+0, rd:2; simd8_read off=72 (8)
skl | 31 00 60 06 08 02 00 01 a0 04 00 06 98 02 28 02 |         send.urb (8)              r8      r37            0x00000000  0x02280298  // wr:1h+0, rd:2; simd8_read off=41 (8)
skl | 31 00 60 06 08 02 c0 02 a0 04 00 06 98 04 28 02 |         send.urb (8)              r22     r37            0x00000000  0x02280498  // wr:1h+0, rd:2; simd8_read off=73 (8)
skl | 31 00 60 06 08 02 00 03 a0 04 00 06 98 06 28 02 |         send.urb (8)              r24     r37            0x00000000  0x02280698  // wr:1h+0, rd:2; simd8_read off=105 (8)
skl | 31 00 60 06 08 02 00 01 c0 04 00 06 a8 02 28 02 |         send.urb (8)              r8      r38            0x00000000  0x022802A8  // wr:1h+0, rd:2; simd8_read off=42 (8)
skl | 31 00 60 06 08 02 c0 02 c0 04 00 06 a8 04 28 02 |         send.urb (8)              r22     r38            0x00000000  0x022804A8  // wr:1h+0, rd:2; simd8_read off=74 (8)
skl | 31 00 60 06 08 02 00 03 c0 04 00 06 a8 06 28 02 |         send.urb (8)              r24     r38            0x00000000  0x022806A8  // wr:1h+0, rd:2; simd8_read off=106 (8)
skl | 31 00 60 06 08 02 00 01 e0 04 00 06 b8 02 28 02 |         send.urb (8)              r8      r39            0x00000000  0x022802B8  // wr:1h+0, rd:2; simd8_read off=43 (8)
skl | 31 00 60 06 08 02 c0 02 e0 04 00 06 b8 04 28 02 |         send.urb (8)              r22     r39            0x00000000  0x022804B8  // wr:1h+0, rd:2; simd8_read off=75 (8)
skl | 31 00 60 06 08 02 00 03 e0 04 00 06 b8 06 28 02 |         send.urb (8)              r24     r39            0x00000000  0x022806B8  // wr:1h+0, rd:2; simd8_read off=107 (8)
skl | 31 00 60 06 08 02 00 01 00 05 00 06 c8 02 28 02 |         send.urb (8)              r8      r40            0x00000000  0x022802C8  // wr:1h+0, rd:2; simd8_read off=44 (8)
skl | 31 00 60 06 08 02 40 01 00 05 00 06 c8 04 28 02 |         send.urb (8)              r10     r40            0x00000000  0x022804C8  // wr:1h+0, rd:2; simd8_read off=76 (8)
skl | 31 00 60 06 08 02 c0 02 00 05 00 06 c8 06 28 02 |         send.urb (8)              r22     r40            0x00000000  0x022806C8  // wr:1h+0, rd:2; simd8_read off=108 (8)
skl | 31 00 60 06 08 02 00 01 20 05 00 06 d8 02 28 02 |         send.urb (8)              r8      r41            0x00000000  0x022802D8  // wr:1h+0, rd:2; simd8_read off=45 (8)
skl | 31 00 60 06 08 02 40 01 20 05 00 06 d8 04 28 02 |         send.urb (8)              r10     r41            0x00000000  0x022804D8  // wr:1h+0, rd:2; simd8_read off=77 (8)
skl | 31 00 60 06 08 02 c0 02 20 05 00 06 d8 06 28 02 |         send.urb (8)              r22     r41            0x00000000  0x022806D8  // wr:1h+0, rd:2; simd8_read off=109 (8)
skl | 31 00 60 06 08 02 00 01 40 05 00 06 e8 02 28 02 |         send.urb (8)              r8      r42            0x00000000  0x022802E8  // wr:1h+0, rd:2; simd8_read off=46 (8)
skl | 31 00 60 06 08 02 40 01 40 05 00 06 e8 04 28 02 |         send.urb (8)              r10     r42            0x00000000  0x022804E8  // wr:1h+0, rd:2; simd8_read off=78 (8)
skl | 31 00 60 06 08 02 c0 02 40 05 00 06 e8 06 28 02 |         send.urb (8)              r22     r42            0x00000000  0x022806E8  // wr:1h+0, rd:2; simd8_read off=110 (8)
skl | 31 00 60 06 08 02 00 01 60 05 00 06 f8 02 28 02 |         send.urb (8)              r8      r43            0x00000000  0x022802F8  // wr:1h+0, rd:2; simd8_read off=47 (8)
skl | 31 00 60 06 08 02 40 01 60 05 00 06 f8 04 28 02 |         send.urb (8)              r10     r43            0x00000000  0x022804F8  // wr:1h+0, rd:2; simd8_read off=79 (8)
skl | 31 00 60 06 08 02 c0 02 60 05 00 06 f8 06 28 02 |         send.urb (8)              r22     r43            0x00000000  0x022806F8  // wr:1h+0, rd:2; simd8_read off=111 (8)
skl | 31 00 60 06 08 02 00 01 80 05 00 06 08 03 28 02 |         send.urb (8)              r8      r44            0x00000000  0x02280308  // wr:1h+0, rd:2; simd8_read off=48 (8)
skl | 31 00 60 06 08 02 40 01 80 05 00 06 08 05 28 02 |         send.urb (8)              r10     r44            0x00000000  0x02280508  // wr:1h+0, rd:2; simd8_read off=80 (8)
skl | 31 00 60 06 08 02 80 01 80 05 00 06 08 07 28 02 |         send.urb (8)              r12     r44            0x00000000  0x02280708  // wr:1h+0, rd:2; simd8_read off=112 (8)
skl | 31 00 60 06 08 02 00 01 a0 05 00 06 18 03 28 02 |         send.urb (8)              r8      r45            0x00000000  0x02280318  // wr:1h+0, rd:2; simd8_read off=49 (8)
skl | 31 00 60 06 08 02 40 01 a0 05 00 06 18 05 28 02 |         send.urb (8)              r10     r45            0x00000000  0x02280518  // wr:1h+0, rd:2; simd8_read off=81 (8)
skl | 31 00 60 06 08 02 80 01 a0 05 00 06 18 07 28 02 |         send.urb (8)              r12     r45            0x00000000  0x02280718  // wr:1h+0, rd:2; simd8_read off=113 (8)
skl | 31 00 60 06 08 02 00 01 c0 05 00 06 28 03 28 02 |         send.urb (8)              r8      r46            0x00000000  0x02280328  // wr:1h+0, rd:2; simd8_read off=50 (8)
skl | 31 00 60 06 08 02 40 01 c0 05 00 06 28 05 28 02 |         send.urb (8)              r10     r46            0x00000000  0x02280528  // wr:1h+0, rd:2; simd8_read off=82 (8)
skl | 31 00 60 06 08 02 80 01 c0 05 00 06 28 07 28 02 |         send.urb (8)              r12     r46            0x00000000  0x02280728  // wr:1h+0, rd:2; simd8_read off=114 (8)
skl | 31 00 60 06 08 02 00 01 e0 05 00 06 38 03 28 02 |         send.urb (8)              r8      r47            0x00000000  0x02280338  // wr:1h+0, rd:2; simd8_read off=51 (8)
skl | 31 00 60 06 08 02 40 01 e0 05 00 06 38 05 28 02 |         send.urb (8)              r10     r47            0x00000000  0x02280538  // wr:1h+0, rd:2; simd8_read off=83 (8)
skl | 31 00 60 06 08 02 80 01 e0 05 00 06 38 07 28 02 |         send.urb (8)              r12     r47            0x00000000  0x02280738  // wr:1h+0, rd:2; simd8_read off=115 (8)
skl | 31 00 60 06 08 02 00 01 00 06 00 06 48 03 28 02 |         send.urb (8)              r8      r48            0x00000000  0x02280348  // wr:1h+0, rd:2; simd8_read off=52 (8)
skl | 31 00 60 06 08 02 40 01 00 06 00 06 48 05 28 02 |         send.urb (8)              r10     r48            0x00000000  0x02280548  // wr:1h+0, rd:2; simd8_read off=84 (8)
skl | 31 00 60 06 08 02 80 01 00 06 00 06 48 07 28 02 |         send.urb (8)              r12     r48            0x00000000  0x02280748  // wr:1h+0, rd:2; simd8_read off=116 (8)
skl | 31 00 60 06 08 02 00 01 20 06 00 06 58 03 28 02 |         send.urb (8)              r8      r49            0x00000000  0x02280358  // wr:1h+0, rd:2; simd8_read off=53 (8)
skl | 31 00 60 06 08 02 40 01 20 06 00 06 58 05 28 02 |         send.urb (8)              r10     r49            0x00000000  0x02280558  // wr:1h+0, rd:2; simd8_read off=85 (8)
skl | 31 00 60 06 08 02 80 01 20 06 00 06 58 07 28 02 |         send.urb (8)              r12     r49            0x00000000  0x02280758  // wr:1h+0, rd:2; simd8_read off=117 (8)
skl | 31 00 60 06 08 02 00 01 40 06 00 06 68 03 28 02 |         send.urb (8)              r8      r50            0x00000000  0x02280368  // wr:1h+0, rd:2; simd8_read off=54 (8)
skl | 31 00 60 06 08 02 40 01 40 06 00 06 68 05 28 02 |         send.urb (8)              r10     r50            0x00000000  0x02280568  // wr:1h+0, rd:2; simd8_read off=86 (8)
skl | 31 00 60 06 08 02 80 01 40 06 00 06 68 07 28 02 |         send.urb (8)              r12     r50            0x00000000  0x02280768  // wr:1h+0, rd:2; simd8_read off=118 (8)
skl | 31 00 60 06 08 02 00 01 a0 06 00 06 78 03 28 02 |         send.urb (8)              r8      r53            0x00000000  0x02280378  // wr:1h+0, rd:2; simd8_read off=55 (8)
skl | 31 00 60 06 08 02 40 01 a0 06 00 06 78 05 28 02 |         send.urb (8)              r10     r53            0x00000000  0x02280578  // wr:1h+0, rd:2; simd8_read off=87 (8)
skl | 31 00 60 06 08 02 80 01 a0 06 00 06 78 07 28 02 |         send.urb (8)              r12     r53            0x00000000  0x02280778  // wr:1h+0, rd:2; simd8_read off=119 (8)
skl | 31 00 60 06 08 02 00 01 c0 06 00 06 88 03 28 02 |         send.urb (8)              r8      r54            0x00000000  0x02280388  // wr:1h+0, rd:2; simd8_read off=56 (8)
skl | 31 00 60 06 08 02 40 01 c0 06 00 06 88 05 28 02 |         send.urb (8)              r10     r54            0x00000000  0x02280588  // wr:1h+0, rd:2; simd8_read off=88 (8)
skl | 31 00 60 06 08 02 80 01 c0 06 00 06 88 07 28 02 |         send.urb (8)              r12     r54            0x00000000  0x02280788  // wr:1h+0, rd:2; simd8_read off=120 (8)
skl | 31 00 60 06 08 02 00 01 e0 06 00 06 98 03 28 02 |         send.urb (8)              r8      r55            0x00000000  0x02280398  // wr:1h+0, rd:2; simd8_read off=57 (8)
skl | 31 00 60 06 08 02 40 01 e0 06 00 06 98 05 28 02 |         send.urb (8)              r10     r55            0x00000000  0x02280598  // wr:1h+0, rd:2; simd8_read off=89 (8)
skl | 31 00 60 06 08 02 80 01 e0 06 00 06 98 07 28 02 |         send.urb (8)              r12     r55            0x00000000  0x02280798  // wr:1h+0, rd:2; simd8_read off=121 (8)
skl | 31 00 60 06 08 02 00 01 00 07 00 06 a8 03 28 02 |         send.urb (8)              r8      r56            0x00000000  0x022803A8  // wr:1h+0, rd:2; simd8_read off=58 (8)
skl | 31 00 60 06 08 02 40 01 00 07 00 06 a8 05 28 02 |         send.urb (8)              r10     r56            0x00000000  0x022805A8  // wr:1h+0, rd:2; simd8_read off=90 (8)
skl | 31 00 60 06 08 02 80 01 00 07 00 06 a8 07 28 02 |         send.urb (8)              r12     r56            0x00000000  0x022807A8  // wr:1h+0, rd:2; simd8_read off=122 (8)
skl | 31 00 60 06 08 02 00 01 20 07 00 06 b8 03 28 02 |         send.urb (8)              r8      r57            0x00000000  0x022803B8  // wr:1h+0, rd:2; simd8_read off=59 (8)
skl | 31 00 60 06 08 02 40 01 20 07 00 06 b8 05 28 02 |         send.urb (8)              r10     r57            0x00000000  0x022805B8  // wr:1h+0, rd:2; simd8_read off=91 (8)
skl | 31 00 60 06 08 02 80 01 20 07 00 06 b8 07 28 02 |         send.urb (8)              r12     r57            0x00000000  0x022807B8  // wr:1h+0, rd:2; simd8_read off=123 (8)
skl | 31 00 60 06 08 02 00 01 40 07 00 06 c8 03 28 02 |         send.urb (8)              r8      r58            0x00000000  0x022803C8  // wr:1h+0, rd:2; simd8_read off=60 (8)
skl | 31 00 60 06 08 02 40 01 40 07 00 06 c8 05 28 02 |         send.urb (8)              r10     r58            0x00000000  0x022805C8  // wr:1h+0, rd:2; simd8_read off=92 (8)
skl | 31 00 60 06 08 02 80 01 40 07 00 06 c8 07 28 02 |         send.urb (8)              r12     r58            0x00000000  0x022807C8  // wr:1h+0, rd:2; simd8_read off=124 (8)
skl | 31 00 60 06 08 02 00 01 60 07 00 06 d8 03 28 02 |         send.urb (8)              r8      r59            0x00000000  0x022803D8  // wr:1h+0, rd:2; simd8_read off=61 (8)
skl | 31 00 60 06 08 02 40 01 60 07 00 06 d8 05 28 02 |         send.urb (8)              r10     r59            0x00000000  0x022805D8  // wr:1h+0, rd:2; simd8_read off=93 (8)
skl | 31 00 60 06 08 02 80 01 60 07 00 06 d8 07 28 02 |         send.urb (8)              r12     r59            0x00000000  0x022807D8  // wr:1h+0, rd:2; simd8_read off=125 (8)
skl | 31 00 60 06 08 02 00 01 80 07 00 06 e8 03 28 02 |         send.urb (8)              r8      r60            0x00000000  0x022803E8  // wr:1h+0, rd:2; simd8_read off=62 (8)
skl | 31 00 60 06 08 02 40 01 80 07 00 06 e8 05 28 02 |         send.urb (8)              r10     r60            0x00000000  0x022805E8  // wr:1h+0, rd:2; simd8_read off=94 (8)
skl | 31 00 60 06 08 02 80 01 80 07 00 06 e8 07 28 02 |         send.urb (8)              r12     r60            0x00000000  0x022807E8  // wr:1h+0, rd:2; simd8_read off=126 (8)
skl | 31 00 60 06 08 02 00 01 a0 07 00 06 f8 03 28 02 |         send.urb (8)              r8      r61            0x00000000  0x022803F8  // wr:1h+0, rd:2; simd8_read off=63 (8)
skl | 31 00 60 06 08 02 40 01 a0 07 00 06 f8 05 28 02 |         send.urb (8)              r10     r61            0x00000000  0x022805F8  // wr:1h+0, rd:2; simd8_read off=95 (8)
skl | 31 00 60 06 08 02 80 01 a0 07 00 06 f8 07 28 02 |         send.urb (8)              r12     r61            0x00000000  0x022807F8  // wr:1h+0, rd:2; simd8_read off=127 (8)
skl | 31 00 60 06 08 02 40 01 c0 07 00 06 08 04 28 02 |         send.urb (8)              r10     r62            0x00000000  0x02280408  // wr:1h+0, rd:2; simd8_read off=64 (8)
skl | 31 00 60 06 08 02 80 01 c0 07 00 06 08 06 28 02 |         send.urb (8)              r12     r62            0x00000000  0x02280608  // wr:1h+0, rd:2; simd8_read off=96 (8)
skl | 31 00 60 06 08 02 c0 01 c0 07 00 06 08 08 28 02 |         send.urb (8)              r14     r62            0x00000000  0x02280808  // wr:1h+0, rd:2; simd8_read off=128 (8)
skl | 31 00 60 06 08 02 00 01 e0 07 00 06 18 02 28 02 |         send.urb (8)              r8      r63            0x00000000  0x02280218  // wr:1h+0, rd:2; simd8_read off=33 (8)
skl | 31 00 60 06 08 02 40 01 e0 07 00 06 18 04 28 02 |         send.urb (8)              r10     r63            0x00000000  0x02280418  // wr:1h+0, rd:2; simd8_read off=65 (8)
skl | 31 00 60 06 08 02 80 01 e0 07 00 06 18 06 28 02 |         send.urb (8)              r12     r63            0x00000000  0x02280618  // wr:1h+0, rd:2; simd8_read off=97 (8)
skl | 31 00 60 06 08 02 c0 01 e0 07 00 06 18 08 28 02 |         send.urb (8)              r14     r63            0x00000000  0x02280818  // wr:1h+0, rd:2; simd8_read off=129 (8)
skl | 31 00 60 02 08 02 a0 03 40 02 00 06 08 00 42 04 |         send.smpl (8)             r29     r18            0x00000000  0x04420008  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(8) using sampler index 0
skl | 31 00 60 02 08 02 60 04 40 02 00 06 09 01 42 04 |         send.smpl (8)             r35     r18            0x00000000  0x04420109  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(9) using sampler index 1
skl | 31 00 60 02 08 02 20 05 40 02 00 06 0a 02 42 04 |         send.smpl (8)             r41     r18            0x00000000  0x0442020A  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(10) using sampler index 2
skl | 31 00 60 02 08 02 40 00 40 02 00 06 0b 03 42 04 |         send.smpl (8)             r2      r18            0x00000000  0x0442030B  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(11) using sampler index 3
skl | 31 00 60 02 08 02 c0 00 40 02 00 06 0c 04 42 04 |         send.smpl (8)             r6      r18            0x00000000  0x0442040C  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(12) using sampler index 4
skl | 31 00 60 02 08 02 40 01 40 02 00 06 0d 05 42 04 |         send.smpl (8)             r10     r18            0x00000000  0x0442050D  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(13) using sampler index 5
skl | 31 00 60 02 08 02 c0 01 40 02 00 06 0e 06 42 04 |         send.smpl (8)             r14     r18            0x00000000  0x0442060E  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(14) using sampler index 6
skl | 31 00 60 02 08 02 40 02 40 02 00 06 0f 07 42 04 |         send.smpl (8)             r18     r18            0x00000000  0x0442070F  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(15) using sampler index 7
skl | 31 00 80 02 08 02 00 04 c0 02 00 06 08 00 84 08 |         send.smpl (16)            r32     r22            0x00000000  0x08840008  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(8) using sampler index 0
skl | 31 00 80 02 08 02 40 05 c0 02 00 06 09 01 84 08 |         send.smpl (16)            r42     r22            0x00000000  0x08840109  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(9) using sampler index 1
skl | 31 00 80 02 08 02 80 07 c0 02 00 06 0a 02 84 08 |         send.smpl (16)            r60     r22            0x00000000  0x0884020A  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(10) using sampler index 2
skl | 31 00 80 02 08 02 c0 08 c0 02 00 06 0b 03 84 08 |         send.smpl (16)            r70     r22            0x00000000  0x0884030B  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(11) using sampler index 3
skl | 31 00 80 02 08 02 c0 09 c0 02 00 06 0c 04 84 08 |         send.smpl (16)            r78     r22            0x00000000  0x0884040C  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(12) using sampler index 4
skl | 31 00 80 02 08 02 c0 0a c0 02 00 06 0d 05 84 08 |         send.smpl (16)            r86     r22            0x00000000  0x0884050D  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(13) using sampler index 5
skl | 31 00 80 02 08 02 c0 0b c0 02 00 06 0e 06 84 08 |         send.smpl (16)            r94     r22            0x00000000  0x0884060E  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(14) using sampler index 6
skl | 31 00 80 02 08 02 80 06 c0 02 00 06 0f 07 84 08 |         send.smpl (16)            r52     r22            0x00000000  0x0884070F  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(15) using sampler index 7
skl | 31 00 60 02 08 02 00 02 40 05 00 06 01 81 43 04 |         send.smpl (8)             r16     r42            0x00000000  0x04438101  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(1) using sampler index 1
skl | 31 00 60 02 08 02 80 02 40 05 00 06 02 82 43 04 |         send.smpl (8)             r20     r42            0x00000000  0x04438202  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(2) using sampler index 2
skl | 31 00 60 02 08 02 a0 03 40 05 00 06 04 84 43 04 |         send.smpl (8)             r29     r42            0x00000000  0x04438404  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(4) using sampler index 4
skl | 31 00 60 02 08 02 c0 04 40 05 00 06 06 86 43 04 |         send.smpl (8)             r38     r42            0x00000000  0x04438606  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(6) using sampler index 6
skl | 31 00 60 02 08 02 80 0f 40 05 00 06 07 87 43 04 |         send.smpl (8)             r124    r42            0x00000000  0x04438707  // wr:2+0, rd:4; sample_lz:u,v,r,ai (8) bti(7) using sampler index 7
skl | 31 00 60 06 08 02 80 01 00 02 00 06 58 00 4a 04 |         send.urb (8)              r12     r16            0x00000000  0x044A0058  // wr:2h+0, rd:4; simd8_read off=5 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 68 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0068  // wr:2h+0, rd:4; simd8_read off=6 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 78 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0078  // wr:2h+0, rd:4; simd8_read off=7 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 88 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0088  // wr:2h+0, rd:4; simd8_read off=8 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 98 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0098  // wr:2h+0, rd:4; simd8_read off=9 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 a8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00A8  // wr:2h+0, rd:4; simd8_read off=10 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 b8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00B8  // wr:2h+0, rd:4; simd8_read off=11 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 c8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00C8  // wr:2h+0, rd:4; simd8_read off=12 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 d8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00D8  // wr:2h+0, rd:4; simd8_read off=13 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 e8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00E8  // wr:2h+0, rd:4; simd8_read off=14 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 f8 00 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A00F8  // wr:2h+0, rd:4; simd8_read off=15 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 08 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0108  // wr:2h+0, rd:4; simd8_read off=16 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 18 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0118  // wr:2h+0, rd:4; simd8_read off=17 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 58 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0158  // wr:2h+0, rd:4; simd8_read off=21 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 68 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0168  // wr:2h+0, rd:4; simd8_read off=22 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 78 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0178  // wr:2h+0, rd:4; simd8_read off=23 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 88 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0188  // wr:2h+0, rd:4; simd8_read off=24 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 98 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0198  // wr:2h+0, rd:4; simd8_read off=25 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 a8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01A8  // wr:2h+0, rd:4; simd8_read off=26 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 b8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01B8  // wr:2h+0, rd:4; simd8_read off=27 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 c8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01C8  // wr:2h+0, rd:4; simd8_read off=28 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 d8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01D8  // wr:2h+0, rd:4; simd8_read off=29 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 e8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01E8  // wr:2h+0, rd:4; simd8_read off=30 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 f8 01 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A01F8  // wr:2h+0, rd:4; simd8_read off=31 per_slot (8)
skl | 31 00 60 06 08 02 80 01 40 00 00 06 08 02 4a 04 |         send.urb (8)              r12     r2             0x00000000  0x044A0208  // wr:2h+0, rd:4; simd8_read off=32 per_slot (8)
skl | 31 00 60 02 08 02 c0 01 e0 01 00 06 01 50 12 0a |         send.smpl (8)             r14     r15            0x00000000  0x0A125001  // wr:5+0, rd:1; sample_b_c (8) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 e0 01 80 02 00 06 02 51 12 0a |         send.smpl (8)             r15     r20            0x00000000  0x0A125102  // wr:5+0, rd:1; sample_b_c (8) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 20 05 e0 00 00 06 01 50 24 14 |         send.smpl (16)            r41     r7             0x00000000  0x14245001  // wr:10+0, rd:2; sample_b_c (16) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 60 05 20 02 00 06 02 51 24 14 |         send.smpl (16)            r43     r17            0x00000000  0x14245102  // wr:10+0, rd:2; sample_b_c (16) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 00 a0 00 00 06 01 30 22 06 |         send.smpl (8)             r2      r5             0x00000000  0x06223001  // wr:3+0, rd:2; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 e0 00 00 06 01 30 44 0c |         send.smpl (16)            r2      r7             0x00000000  0x0C443001  // wr:6+0, rd:4; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 02 08 02 40 00 40 00 00 06 01 30 32 06 |         send.smpl (8)             r2      r2             0x00000000  0x06323001  // wr:3+0, rd:3; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 31 00 80 02 08 02 40 00 00 03 00 06 01 30 64 0c |         send.smpl (16)            r2      r24            0x00000000  0x0C643001  // wr:6+0, rd:6; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 31 00 60 06 00 02 00 00 00 0f 00 06 17 01 0a 8c |         send.urb (8)              null    r120           0x00000000  0x0C0A0117   {EOT}  // wr:6h+0, rd:0; simd8_write off=17 per_slot (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 28 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380128  // wr:1h+0, rd:3; simd8_read off=18 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 38 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380138  // wr:1h+0, rd:3; simd8_read off=19 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 48 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380148  // wr:1h+0, rd:3; simd8_read off=20 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 58 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380158  // wr:1h+0, rd:3; simd8_read off=21 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 68 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380168  // wr:1h+0, rd:3; simd8_read off=22 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 78 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380178  // wr:1h+0, rd:3; simd8_read off=23 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 88 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380188  // wr:1h+0, rd:3; simd8_read off=24 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 98 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x02380198  // wr:1h+0, rd:3; simd8_read off=25 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 a8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801A8  // wr:1h+0, rd:3; simd8_read off=26 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 b8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801B8  // wr:1h+0, rd:3; simd8_read off=27 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 c8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801C8  // wr:1h+0, rd:3; simd8_read off=28 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 d8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801D8  // wr:1h+0, rd:3; simd8_read off=29 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 e8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801E8  // wr:1h+0, rd:3; simd8_read off=30 (8)
skl | 31 00 60 06 08 02 60 01 20 00 00 06 f8 01 38 02 |         send.urb (8)              r11     r1             0x00000000  0x023801F8  // wr:1h+0, rd:3; simd8_read off=31 (8)
skl | 31 00 60 02 08 02 40 01 40 00 00 06 04 00 42 04 |         send.smpl (8)             r10     r2             0x00000000  0x04420004  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(4) using sampler index 0
skl | 31 00 80 02 08 02 40 02 40 00 00 06 04 00 84 08 |         send.smpl (16)            r18     r2             0x00000000  0x08840004  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(4) using sampler index 0
skl | 31 00 60 02 08 02 40 01 40 00 00 06 03 00 42 04 |         send.smpl (8)             r10     r2             0x00000000  0x04420003  // wr:2+0, rd:4; sample:u,v,r,ai (8) bti(3) using sampler index 0
skl | 31 00 80 02 08 02 40 02 40 00 00 06 03 00 84 08 |         send.smpl (16)            r18     r2             0x00000000  0x08840003  // wr:4+0, rd:8; sample:u,v,r,ai (16) bti(3) using sampler index 0
skl | 31 00 60 06 08 02 60 01 a0 01 00 06 58 00 2a 04 |         send.urb (8)              r11     r13            0x00000000  0x042A0058  // wr:2h+0, rd:2; simd8_read off=5 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 68 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0068  // wr:2h+0, rd:2; simd8_read off=6 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 78 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0078  // wr:2h+0, rd:2; simd8_read off=7 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 88 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0088  // wr:2h+0, rd:2; simd8_read off=8 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 98 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0098  // wr:2h+0, rd:2; simd8_read off=9 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 a8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00A8  // wr:2h+0, rd:2; simd8_read off=10 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 b8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00B8  // wr:2h+0, rd:2; simd8_read off=11 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 c8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00C8  // wr:2h+0, rd:2; simd8_read off=12 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 d8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00D8  // wr:2h+0, rd:2; simd8_read off=13 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 e8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00E8  // wr:2h+0, rd:2; simd8_read off=14 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 f8 00 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A00F8  // wr:2h+0, rd:2; simd8_read off=15 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 08 01 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0108  // wr:2h+0, rd:2; simd8_read off=16 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 01 00 06 18 01 2a 04 |         send.urb (8)              r2      r11            0x00000000  0x042A0118  // wr:2h+0, rd:2; simd8_read off=17 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 58 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0158  // wr:2h+0, rd:2; simd8_read off=21 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 68 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0168  // wr:2h+0, rd:2; simd8_read off=22 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 78 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0178  // wr:2h+0, rd:2; simd8_read off=23 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 88 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0188  // wr:2h+0, rd:2; simd8_read off=24 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 98 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0198  // wr:2h+0, rd:2; simd8_read off=25 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 a8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01A8  // wr:2h+0, rd:2; simd8_read off=26 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 b8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01B8  // wr:2h+0, rd:2; simd8_read off=27 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 c8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01C8  // wr:2h+0, rd:2; simd8_read off=28 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 d8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01D8  // wr:2h+0, rd:2; simd8_read off=29 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 e8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01E8  // wr:2h+0, rd:2; simd8_read off=30 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 f8 01 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A01F8  // wr:2h+0, rd:2; simd8_read off=31 per_slot (8)
skl | 31 00 60 06 08 02 40 00 60 00 00 06 08 02 2a 04 |         send.urb (8)              r2      r3             0x00000000  0x042A0208  // wr:2h+0, rd:2; simd8_read off=32 per_slot (8)
skl | 31 00 60 02 08 02 20 01 e0 01 00 06 02 b1 1a 02 |         send.smpl (8)             r9      r15            0x00000000  0x021AB102  // wr:1h+0, rd:1; sampleinfo (8) bti(2) using sampler index 1
skl | 31 00 60 02 08 02 40 01 00 02 00 06 03 b2 1a 02 |         send.smpl (8)             r10     r16            0x00000000  0x021AB203  // wr:1h+0, rd:1; sampleinfo (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 60 01 20 02 00 06 04 b3 1a 02 |         send.smpl (8)             r11     r17            0x00000000  0x021AB304  // wr:1h+0, rd:1; sampleinfo (8) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 80 01 40 02 00 06 05 b4 1a 02 |         send.smpl (8)             r12     r18            0x00000000  0x021AB405  // wr:1h+0, rd:1; sampleinfo (8) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 a0 01 60 02 00 06 06 b5 1a 02 |         send.smpl (8)             r13     r19            0x00000000  0x021AB506  // wr:1h+0, rd:1; sampleinfo (8) bti(6) using sampler index 5
skl | 31 00 80 02 08 02 c0 01 00 02 00 06 02 b1 2c 02 |         send.smpl (16)            r14     r16            0x00000000  0x022CB102  // wr:1h+0, rd:2; sampleinfo (16) bti(2) using sampler index 1
skl | 31 00 80 02 08 02 00 02 40 02 00 06 03 b2 2c 02 |         send.smpl (16)            r16     r18            0x00000000  0x022CB203  // wr:1h+0, rd:2; sampleinfo (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 02 80 02 00 06 04 b3 2c 02 |         send.smpl (16)            r18     r20            0x00000000  0x022CB304  // wr:1h+0, rd:2; sampleinfo (16) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 80 02 c0 02 00 06 05 b4 2c 02 |         send.smpl (16)            r20     r22            0x00000000  0x022CB405  // wr:1h+0, rd:2; sampleinfo (16) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 c0 02 00 03 00 06 06 b5 2c 02 |         send.smpl (16)            r22     r24            0x00000000  0x022CB506  // wr:1h+0, rd:2; sampleinfo (16) bti(6) using sampler index 5
skl | 31 00 60 02 08 02 c0 01 60 01 00 06 03 02 4b 0a |         send.smpl (8)             r14     r11            0x00000000  0x0A4B0203  // wr:5h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(3) using sampler index 2
skl | 31 00 60 02 08 02 40 02 40 02 00 06 04 03 4b 0c |         send.smpl (8)             r18     r18            0x00000000  0x0C4B0304  // wr:6h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(4) using sampler index 3
skl | 31 00 60 02 08 02 c0 02 00 03 00 06 05 04 4b 08 |         send.smpl (8)             r22     r24            0x00000000  0x084B0405  // wr:4h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(5) using sampler index 4
skl | 31 00 80 02 08 02 40 02 40 03 00 06 03 02 8d 12 |         send.smpl (16)            r18     r26            0x00000000  0x128D0203  // wr:9h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(3) using sampler index 2
skl | 31 00 80 02 08 02 40 03 60 04 00 06 04 03 8d 16 |         send.smpl (16)            r26     r35            0x00000000  0x168D0304  // wr:11h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(4) using sampler index 3
skl | 31 00 80 02 08 02 40 04 c0 05 00 06 05 04 8d 0e |         send.smpl (16)            r34     r46            0x00000000  0x0E8D0405  // wr:7h+0, rd:8; gather4_c:ref,u,v,r,ai (16) bti(5) using sampler index 4
skl | 31 00 60 02 08 02 80 0f 20 01 00 06 00 00 4b 0c |         send.smpl (8)             r124    r9             0x00000000  0x0C4B0000  // wr:6h+0, rd:4; gather4_c:ref,u,v,r,ai (8) bti(0) using sampler index 0

skl | 32 00 60 05 00 02 00 00 80 0f 00 06 00 14 03 88 |         sendc.render (8)          null    r124           0x00000000  0x08031400   {EOT}  // wr:4+0, rd:0; simd8 rt_write last_rt (8) bti(0)
skl | 32 00 80 05 00 02 00 00 00 0f 00 06 00 10 03 90 |         sendc.render (16)         null    r120           0x00000000  0x10031000   {EOT}  // wr:8+0, rd:0; simd16 rt_write last_rt (16) bti(0)
skl | 32 00 80 05 00 02 00 00 40 0e 00 06 00 11 03 82 |         sendc.render (16)         null    r114           0x00000000  0x02031100   {EOT}  // wr:1+0, rd:0; simd16_repdata rt_write last_rt (16) bti(0)
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 a0 0b 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080BA001   {EOT}  // wr:4h+0, rd:0; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 a0 0d 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0DA001   {EOT}  // wr:7h+0, rd:0; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 00 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A0001   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 00 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C0001   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 61 05 01 02 00 00 80 0f 00 06 00 14 03 88 | (f0.1)  sendc.render (8)          null    r124           0x00000000  0x08031400   {EOT}  // wr:4+0, rd:0; simd8 rt_write last_rt (8) bti(0)
skl | 32 00 60 02 00 02 00 00 40 0f 00 06 01 e0 0b 8c |         sendc.smpl (8)            null    r122           0x00000000  0x0C0BE001   {EOT}  // wr:6h+0, rd:0; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 a0 0e 00 06 01 e0 0d 96 |         sendc.smpl (16)           null    r117           0x00000000  0x160DE001   {EOT}  // wr:11h+0, rd:0; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 00 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A0001   {EOT}  // wr:4h+0, rd:0; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 00 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C0001   {EOT}  // wr:7h+0, rd:0; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 c0 0e 00 06 01 40 0a 94 |         sendc.smpl (8)            null    r118           0x00000000  0x140A4001   {EOT}  // wr:10h+0, rd:0; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 2f 00 00 00 02 00 80 |         sendc.smpl (8)            null    r125           0x00000000  a0.0         {EOT}
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 40 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A4001   {EOT}  // wr:4h+0, rd:0; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 20 0f 00 06 01 c0 0b 8e |         sendc.smpl (8)            null    r121           0x00000000  0x0E0BC001   {EOT}  // wr:7h+0, rd:0; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 20 0f 00 06 01 40 0a 8e |         sendc.smpl (8)            null    r121           0x00000000  0x0E0A4001   {EOT}  // wr:7h+0, rd:0; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 20 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A2001   {EOT}  // wr:3h+0, rd:0; sample_l (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 20 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C2001   {EOT}  // wr:5h+0, rd:0; sample_l (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 01 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1401   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(1)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 01 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1001   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(1)
skl | 32 00 60 05 00 02 00 00 a0 01 00 06 01 04 0b 0e |         sendc.render (8)          null    r13            0x00000000  0x0E0B0401  // wr:7h+0, rd:0; simd8 rt_write (8) bti(1)
skl | 32 00 60 05 00 02 00 00 20 0f 00 06 02 14 0b 8e |         sendc.render (8)          null    r121           0x00000000  0x0E0B1402   {EOT}  // wr:7h+0, rd:0; simd8 rt_write last_rt (8) bti(2)
skl | 32 00 80 05 00 02 00 00 e0 00 00 06 01 00 0b 18 |         sendc.render (16)         null    r7             0x00000000  0x180B0001  // wr:12h+0, rd:0; simd16 rt_write (16) bti(1)
skl | 32 00 80 05 00 02 00 00 80 0e 00 06 02 10 0b 98 |         sendc.render (16)         null    r116           0x00000000  0x180B1002   {EOT}  // wr:12h+0, rd:0; simd16 rt_write last_rt (16) bti(2)
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 10 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A1001   {EOT}  // wr:5h+0, rd:0; sample_b (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 10 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C1001   {EOT}  // wr:9h+0, rd:0; sample_b (16) bti(1) using sampler index 0
skl | 32 00 00 0a 0c 02 40 00 40 00 00 06 00 c0 09 02 | (W)     sendc.hdc0 (1)            r2      r2             0x00000000  0x0209C000  // wr:1h+0, rd:0; memory_fence (1)
skl | 32 00 60 02 00 02 00 00 00 0f 00 06 01 40 0b 90 |         sendc.smpl (8)            null    r120           0x00000000  0x100B4001   {EOT}  // wr:8h+0, rd:0; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 40 0b 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0B4001   {EOT}  // wr:5h+0, rd:0; sample_d_c:ref,u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai (8) bti(1) using sampler index 0
skl | 32 00 60 05 08 02 c0 00 40 00 00 06 00 41 4b 04 |         sendc.render (8)          r6      r2             0x00000000  0x044B4100  // wr:2h+0, rd:4; simd8 rt_read (8) bti(0)
skl | 32 00 80 05 08 02 20 01 60 03 00 06 00 40 8b 04 |         sendc.render (16)         r9      r27            0x00000000  0x048B4000  // wr:2h+0, rd:8; simd16 rt_read (16) bti(0)
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 30 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A3001   {EOT}  // wr:4h+0, rd:0; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 30 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C3001   {EOT}  // wr:7h+0, rd:0; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 60 0f 00 06 00 14 03 8a |         sendc.render (8)          null    r123           0x00000000  0x0A031400   {EOT}  // wr:5+0, rd:0; simd8 rt_write last_rt (8) bti(0)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 00 10 03 94 |         sendc.render (16)         null    r118           0x00000000  0x14031000   {EOT}  // wr:10+0, rd:0; simd16 rt_write last_rt (16) bti(0)
skl | 32 00 60 05 00 02 00 00 a0 00 00 06 00 04 0b 0c |         sendc.render (8)          null    r5             0x00000000  0x0C0B0400  // wr:6h+0, rd:0; simd8 rt_write (8) bti(0)
skl | 32 00 60 05 00 02 00 00 a0 00 00 06 01 04 0b 0c |         sendc.render (8)          null    r5             0x00000000  0x0C0B0401  // wr:6h+0, rd:0; simd8 rt_write (8) bti(1)
skl | 32 00 60 05 00 02 00 00 a0 00 00 06 02 04 0b 0c |         sendc.render (8)          null    r5             0x00000000  0x0C0B0402  // wr:6h+0, rd:0; simd8 rt_write (8) bti(2)
skl | 32 00 60 05 00 02 00 00 a0 00 00 06 03 04 0b 0c |         sendc.render (8)          null    r5             0x00000000  0x0C0B0403  // wr:6h+0, rd:0; simd8 rt_write (8) bti(3)
skl | 32 00 60 05 00 02 00 00 a0 00 00 06 04 04 0b 0c |         sendc.render (8)          null    r5             0x00000000  0x0C0B0404  // wr:6h+0, rd:0; simd8 rt_write (8) bti(4)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 05 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1405   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(5)
skl | 32 00 80 05 00 02 00 00 a0 00 00 06 00 00 0b 14 |         sendc.render (16)         null    r5             0x00000000  0x140B0000  // wr:10h+0, rd:0; simd16 rt_write (16) bti(0)
skl | 32 00 80 05 00 02 00 00 a0 00 00 06 01 00 0b 14 |         sendc.render (16)         null    r5             0x00000000  0x140B0001  // wr:10h+0, rd:0; simd16 rt_write (16) bti(1)
skl | 32 00 80 05 00 02 00 00 a0 00 00 06 02 00 0b 14 |         sendc.render (16)         null    r5             0x00000000  0x140B0002  // wr:10h+0, rd:0; simd16 rt_write (16) bti(2)
skl | 32 00 80 05 00 02 00 00 a0 00 00 06 03 00 0b 14 |         sendc.render (16)         null    r5             0x00000000  0x140B0003  // wr:10h+0, rd:0; simd16 rt_write (16) bti(3)
skl | 32 00 80 05 00 02 00 00 a0 00 00 06 04 00 0b 14 |         sendc.render (16)         null    r5             0x00000000  0x140B0004  // wr:10h+0, rd:0; simd16 rt_write (16) bti(4)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 05 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1005   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(5)
skl | 32 00 60 05 08 02 c0 00 c0 00 00 06 01 41 4b 04 |         sendc.render (8)          r6      r6             0x00000000  0x044B4101  // wr:2h+0, rd:4; simd8 rt_read (8) bti(1)
skl | 32 00 60 05 08 02 40 01 40 01 00 06 02 41 4b 04 |         sendc.render (8)          r10     r10            0x00000000  0x044B4102  // wr:2h+0, rd:4; simd8 rt_read (8) bti(2)
skl | 32 00 60 05 08 02 c0 01 c0 01 00 06 03 41 4b 04 |         sendc.render (8)          r14     r14            0x00000000  0x044B4103  // wr:2h+0, rd:4; simd8 rt_read (8) bti(3)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 03 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1403   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(3)
skl | 32 00 80 05 08 02 00 04 c0 01 00 06 01 40 8b 04 |         sendc.render (16)         r32     r14            0x00000000  0x048B4001  // wr:2h+0, rd:8; simd16 rt_read (16) bti(1)
skl | 32 00 80 05 08 02 00 05 00 02 00 06 02 40 8b 04 |         sendc.render (16)         r40     r16            0x00000000  0x048B4002  // wr:2h+0, rd:8; simd16 rt_read (16) bti(2)
skl | 32 00 80 05 08 02 00 06 40 02 00 06 03 40 8b 04 |         sendc.render (16)         r48     r18            0x00000000  0x048B4003  // wr:2h+0, rd:8; simd16 rt_read (16) bti(3)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 03 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1003   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(3)
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 10 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A1001   {EOT}  // wr:4h+0, rd:0; sample_b (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 10 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C1001   {EOT}  // wr:7h+0, rd:0; sample_b (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 a0 0b 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060BA001   {EOT}  // wr:3h+0, rd:0; ld_lz:u,v,r (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 a0 0d 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0DA001   {EOT}  // wr:5h+0, rd:0; ld_lz:u,v,r (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 c0 0f 00 06 01 00 0a 84 |         sendc.smpl (8)            null    r126           0x00000000  0x040A0001   {EOT}  // wr:2h+0, rd:0; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 a0 0f 00 06 01 00 0c 86 |         sendc.smpl (16)           null    r125           0x00000000  0x060C0001   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 20 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A2001   {EOT}  // wr:4h+0, rd:0; sample_l (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 20 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C2001   {EOT}  // wr:7h+0, rd:0; sample_l (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 e0 0b 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0BE001   {EOT}  // wr:5h+0, rd:0; ld2dms:si,mcs,u,v,r,lod (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 e0 0d 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120DE001   {EOT}  // wr:9h+0, rd:0; ld2dms:si,mcs,u,v,r,lod (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 00 0f 00 06 01 40 0a 90 |         sendc.smpl (8)            null    r120           0x00000000  0x100A4001   {EOT}  // wr:8h+0, rd:0; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 20 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A2001   {EOT}  // wr:5h+0, rd:0; sample_l (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 20 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C2001   {EOT}  // wr:9h+0, rd:0; sample_l (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 04 03 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A0304   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (8) bti(4) using sampler index 3
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 04 03 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C0304   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (16) bti(4) using sampler index 3
skl | 32 00 60 02 00 02 00 00 40 0f 00 06 01 10 0a 8c |         sendc.smpl (8)            null    r122           0x00000000  0x0C0A1001   {EOT}  // wr:6h+0, rd:0; sample_b (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 a0 0e 00 06 01 10 0c 96 |         sendc.smpl (16)           null    r117           0x00000000  0x160C1001   {EOT}  // wr:11h+0, rd:0; sample_b (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 30 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A3001   {EOT}  // wr:3h+0, rd:0; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 30 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C3001   {EOT}  // wr:5h+0, rd:0; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 02 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1402   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(2)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 02 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1002   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(2)
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 60 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A6001   {EOT}  // wr:4h+0, rd:0; sample_l_c (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 60 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C6001   {EOT}  // wr:7h+0, rd:0; sample_l_c (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 50 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A5001   {EOT}  // wr:5h+0, rd:0; sample_b_c (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 50 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C5001   {EOT}  // wr:9h+0, rd:0; sample_b_c (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 40 0f 00 06 01 20 0a 8c |         sendc.smpl (8)            null    r122           0x00000000  0x0C0A2001   {EOT}  // wr:6h+0, rd:0; sample_l (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 a0 0e 00 06 01 20 0c 96 |         sendc.smpl (16)           null    r117           0x00000000  0x160C2001   {EOT}  // wr:11h+0, rd:0; sample_l (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 40 0f 00 06 01 c0 0b 8c |         sendc.smpl (8)            null    r122           0x00000000  0x0C0BC001   {EOT}  // wr:6h+0, rd:0; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 a0 0e 00 06 01 c0 0d 96 |         sendc.smpl (16)           null    r117           0x00000000  0x160DC001   {EOT}  // wr:11h+0, rd:0; ld2dms_w:si,mcsl,mcsh,u,v,r,lod (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 00 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1400   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(0)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 00 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1000   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(0)
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 70 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A7001   {EOT}  // wr:4h+0, rd:0; ld:u,v,lod,r (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 70 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C7001   {EOT}  // wr:7h+0, rd:0; ld:u,v,lod,r (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 c0 0e 00 06 00 12 0b 94 |         sendc.render (8)          null    r118           0x00000000  0x140B1200   {EOT}  // wr:10h+0, rd:0; simd8_dualsrc_low rt_write last_rt (8) bti(0)
skl | 32 00 60 05 00 02 00 00 60 00 00 06 00 12 0b 14 |         sendc.render (8)          null    r3             0x00000000  0x140B1200  // wr:10h+0, rd:0; simd8_dualsrc_low rt_write last_rt (8) bti(0)
skl | 32 10 60 05 00 02 00 00 c0 0e 00 06 00 13 0b 94 |         sendc.render (8|M8)       null    r118           0x00000000  0x140B1300   {EOT}  // wr:10h+0, rd:0; simd8_dualsrc_high rt_write last_rt (8) bti(0)
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 00 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A0001   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 00 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C0001   {EOT}  // wr:9h+0, rd:0; sample:u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 80 05 08 02 60 01 a0 04 00 06 00 60 8b 04 |         sendc.render (16)         r11     r37            0x00000000  0x048B6000  // wr:2h+0, rd:8; simd16 rt_read per_sample (16) bti(0)
skl | 32 00 60 05 00 02 00 00 e0 02 00 06 05 04 0b 0c |         sendc.render (8)          null    r23            0x00000000  0x0C0B0405  // wr:6h+0, rd:0; simd8 rt_write (8) bti(5)
skl | 32 00 60 05 00 02 00 00 a0 03 00 06 06 04 0b 0c |         sendc.render (8)          null    r29            0x00000000  0x0C0B0406  // wr:6h+0, rd:0; simd8 rt_write (8) bti(6)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 07 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1407   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(7)
skl | 32 00 80 05 00 02 00 00 20 07 00 06 05 00 0b 14 |         sendc.render (16)         null    r57            0x00000000  0x140B0005  // wr:10h+0, rd:0; simd16 rt_write (16) bti(5)
skl | 32 00 80 05 00 02 00 00 60 08 00 06 06 00 0b 14 |         sendc.render (16)         null    r67            0x00000000  0x140B0006  // wr:10h+0, rd:0; simd16 rt_write (16) bti(6)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 07 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1007   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(7)
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 10 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A1001   {EOT}  // wr:3h+0, rd:0; sample_b (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 10 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C1001   {EOT}  // wr:5h+0, rd:0; sample_b (16) bti(1) using sampler index 0
skl | 32 00 60 05 00 02 00 00 40 01 00 06 00 04 0b 0e |         sendc.render (8)          null    r10            0x00000000  0x0E0B0400  // wr:7h+0, rd:0; simd8 rt_write (8) bti(0)
skl | 32 00 60 05 00 02 00 00 20 0f 00 06 01 14 0b 8e |         sendc.render (8)          null    r121           0x00000000  0x0E0B1401   {EOT}  // wr:7h+0, rd:0; simd8 rt_write last_rt (8) bti(1)
skl | 32 00 80 05 00 02 00 00 40 00 00 06 00 00 0b 16 |         sendc.render (16)         null    r2             0x00000000  0x160B0000  // wr:11h+0, rd:0; simd16 rt_write (16) bti(0)
skl | 32 00 80 05 00 02 00 00 a0 0e 00 06 01 10 0b 96 |         sendc.render (16)         null    r117           0x00000000  0x160B1001   {EOT}  // wr:11h+0, rd:0; simd16 rt_write last_rt (16) bti(1)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 04 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1404   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(4)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 04 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1004   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(4)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 06 14 0b 8c |         sendc.render (8)          null    r122           0x00000000  0x0C0B1406   {EOT}  // wr:6h+0, rd:0; simd8 rt_write last_rt (8) bti(6)
skl | 32 00 80 05 00 02 00 00 c0 0e 00 06 06 10 0b 94 |         sendc.render (16)         null    r118           0x00000000  0x140B1006   {EOT}  // wr:10h+0, rd:0; simd16 rt_write last_rt (16) bti(6)
skl | 32 00 80 05 00 02 00 00 e0 0e 00 06 00 10 03 92 |         sendc.render (16)         null    r119           0x00000000  0x12031000   {EOT}  // wr:9+0, rd:0; simd16 rt_write last_rt (16) bti(0)
skl | 32 00 80 05 00 02 00 00 80 0e 00 06 01 10 0b 98 |         sendc.render (16)         null    r116           0x00000000  0x180B1001   {EOT}  // wr:12h+0, rd:0; simd16 rt_write last_rt (16) bti(1)
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 60 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A6001   {EOT}  // wr:5h+0, rd:0; sample_l_c (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 60 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C6001   {EOT}  // wr:9h+0, rd:0; sample_l_c (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 02 01 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A0102   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 02 01 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C0102   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 32 00 60 02 00 02 00 00 80 0f 00 06 01 50 0a 88 |         sendc.smpl (8)            null    r124           0x00000000  0x080A5001   {EOT}  // wr:4h+0, rd:0; sample_b_c (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 20 0f 00 06 01 50 0c 8e |         sendc.smpl (16)           null    r121           0x00000000  0x0E0C5001   {EOT}  // wr:7h+0, rd:0; sample_b_c (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 40 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A4001   {EOT}  // wr:5h+0, rd:0; sample_d:u,dudx,dudy,v,dvdx,dvdy,r,drdx,drdy,ai,mlod (8) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 60 0f 00 06 01 30 0a 8a |         sendc.smpl (8)            null    r123           0x00000000  0x0A0A3001   {EOT}  // wr:5h+0, rd:0; sample_c:ref,u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 e0 0e 00 06 01 30 0c 92 |         sendc.smpl (16)           null    r119           0x00000000  0x120C3001   {EOT}  // wr:9h+0, rd:0; sample_c:ref,u,v,r,ai (16) bti(1) using sampler index 0
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 10 0f 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A0F10   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (8) bti(16) using sampler index 15
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 10 0f 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C0F10   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (16) bti(16) using sampler index 15
skl | 32 00 60 02 00 02 00 00 c0 0f 00 06 02 01 0a 84 |         sendc.smpl (8)            null    r126           0x00000000  0x040A0102   {EOT}  // wr:2h+0, rd:0; sample:u,v,r,ai (8) bti(2) using sampler index 1
skl | 32 00 80 02 00 02 00 00 a0 0f 00 06 02 01 0c 86 |         sendc.smpl (16)           null    r125           0x00000000  0x060C0102   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (16) bti(2) using sampler index 1
skl | 32 00 80 05 00 02 00 00 60 01 00 06 00 00 0b 18 |         sendc.render (16)         null    r11            0x00000000  0x180B0000  // wr:12h+0, rd:0; simd16 rt_write (16) bti(0)
skl | 32 00 60 05 00 02 00 00 40 0f 00 06 00 14 03 8c |         sendc.render (8)          null    r122           0x00000000  0x0C031400   {EOT}  // wr:6+0, rd:0; simd8 rt_write last_rt (8) bti(0)
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 06 05 0a 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060A0506   {EOT}  // wr:3h+0, rd:0; sample:u,v,r,ai (8) bti(6) using sampler index 5
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 06 05 0c 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0C0506   {EOT}  // wr:5h+0, rd:0; sample:u,v,r,ai (16) bti(6) using sampler index 5
skl | 32 00 60 02 00 02 00 00 a0 0f 00 06 01 80 0b 86 |         sendc.smpl (8)            null    r125           0x00000000  0x060B8001   {EOT}  // wr:3h+0, rd:0; sample_lz:u,v,r,ai (8) bti(1) using sampler index 0
skl | 32 00 80 02 00 02 00 00 60 0f 00 06 01 80 0d 8a |         sendc.smpl (16)           null    r123           0x00000000  0x0A0D8001   {EOT}  // wr:5h+0, rd:0; sample_lz:u,v,r,ai (16) bti(1) using sampler index 0

skl | 33 00 60 0c 10 40 02 00 44 04 00 00 01 50 03 04 |         sends.hdc1 (8)            null    r34    r36     0x00000100  0x04035001  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
skl | 33 10 60 0c 10 30 00 00 24 00 00 00 01 60 03 04 |         sends.hdc1 (8|M8)         null    r1     r3      0x00000100  0x04036001  // wr:2+4, rd:0; typed_write:xyzw simd8 (8) bti(1)
skl | 33 00 60 0c 10 70 01 00 a4 02 00 00 01 50 03 04 |         sends.hdc1 (8)            null    r21    r23     0x00000100  0x04035001  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
skl | 33 00 61 0c 1a 30 20 01 41 00 00 00 01 b2 10 02 | (f1.0)  sends.hdc1 (8)            r9      r2     r3      0x00000040  0x0210B201  // wr:1+1, rd:1; untyped_atomic_or simd8 (8) bti(1)
skl | 33 00 81 0c 1a 60 60 01 42 00 00 00 01 a2 20 04 | (f1.0)  sends.hdc1 (16)           r11     r2     r6      0x00000080  0x0420A201  // wr:2+2, rd:2; untyped_atomic_or simd16 (16) bti(1)
skl | 33 00 80 0c 10 80 00 00 c2 00 00 00 fe 5e 02 04 |         sends.hdc1 (16)           null    r6     r8      0x00000080  0x04025EFE  // wr:2+2, rd:0; untyped_write:x simd16 (16) bti(254)
skl | 33 00 80 0c 10 c0 00 00 42 01 00 00 fe 87 00 04 |         sends.hdc1 (16)           null    r10    r12     0x00000080  0x040087FE  // wr:2+2, rd:0; untyped_atomic_add simd16 (16) bti(254)
skl | 33 00 61 0c 12 50 00 00 64 01 00 00 02 50 03 04 | (f1.0)  sends.hdc1 (8)            null    r11    r5      0x00000100  0x04035002  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(2)
skl | 33 10 61 0c 12 b0 00 00 44 00 00 00 02 60 03 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r11     0x00000100  0x04036002  // wr:2+4, rd:0; typed_write:xyzw simd8 (8) bti(2)
skl | 33 00 61 0c 12 40 00 00 64 00 00 00 01 60 02 02 | (f1.0)  sends.hdc1 (8)            null    r3     r4      0x00000100  0x02026001  // wr:1+4, rd:0; untyped_write:xyzw simd8 (8) bti(1)
skl | 33 00 81 0c 12 50 00 00 68 00 00 00 01 50 02 04 | (f1.0)  sends.hdc1 (16)           null    r3     r5      0x00000200  0x04025001  // wr:2+8, rd:0; untyped_write:xyzw simd16 (16) bti(1)
skl | 33 00 60 0c 10 30 00 00 41 00 00 00 00 9b 00 02 |         sends.hdc1 (8)            null    r2     r3      0x00000040  0x02009B00  // wr:1+1, rd:0; untyped_atomic_imin simd8 (8) bti(0)
skl | 33 00 61 0c 12 40 00 00 41 00 00 00 01 5e 03 04 | (f1.0)  sends.hdc1 (8)            null    r2     r4      0x00000040  0x04035E01  // wr:2+1, rd:0; typed_write:x simd16 (8) bti(1)
skl | 33 10 61 0c 12 90 02 00 a1 05 00 00 01 6e 03 04 | (f1.0)  sends.hdc1 (8|M8)         null    r45    r41     0x00000040  0x04036E01  // wr:2+1, rd:0; typed_write:x simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 00 00 41 00 00 00 01 8c 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r4      0x00000040  0x04018C01  // wr:2+1, rd:0; typed_atomic_umax simd16 (8) bti(1)
skl | 33 10 61 0c 12 90 02 00 a1 05 00 00 01 9c 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r45    r41     0x00000040  0x04019C01  // wr:2+1, rd:0; typed_atomic_umax simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 00 00 41 00 00 00 01 84 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r4      0x00000040  0x04018401  // wr:2+1, rd:0; typed_atomic_mov simd16 (8) bti(1)
skl | 33 10 61 0c 12 90 02 00 a1 05 00 00 01 94 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r45    r41     0x00000040  0x04019401  // wr:2+1, rd:0; typed_atomic_mov simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 00 00 42 00 00 00 01 8e 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r4      0x00000080  0x04018E01  // wr:2+2, rd:0; typed_atomic_cmpwr simd16 (8) bti(1)
skl | 33 10 61 0c 12 d0 00 00 62 01 00 00 01 9e 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r11    r13     0x00000080  0x04019E01  // wr:2+2, rd:0; typed_atomic_cmpwr simd8 (8) bti(1)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 8d 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x04008DFE  // wr:2+2, rd:0; untyped_atomic_umin simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8b 00 04 |         sends.hdc1 (16)           null    r5     r1      0x00000080  0x04008BFE  // wr:2+2, rd:0; untyped_atomic_imin simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 8c 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x04008CFE  // wr:2+2, rd:0; untyped_atomic_umax simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 a2 00 00 00 fe 8a 00 04 |         sends.hdc1 (16)           null    r5     r1      0x00000080  0x04008AFE  // wr:2+2, rd:0; untyped_atomic_imax simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 81 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x040081FE  // wr:2+2, rd:0; untyped_atomic_and simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 82 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x040082FE  // wr:2+2, rd:0; untyped_atomic_or simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 83 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x040083FE  // wr:2+2, rd:0; untyped_atomic_xor simd16 (16) bti(254)
skl | 33 00 80 0c 10 10 00 00 62 00 00 00 fe 84 00 04 |         sends.hdc1 (16)           null    r3     r1      0x00000080  0x040084FE  // wr:2+2, rd:0; untyped_atomic_mov simd16 (16) bti(254)
skl | 33 00 80 0c 10 70 00 00 64 00 00 00 fe 8e 00 04 |         sends.hdc1 (16)           null    r3     r7      0x00000100  0x04008EFE  // wr:2+4, rd:0; untyped_atomic_cmpwr simd16 (16) bti(254)
skl | 33 00 80 0c 18 50 21 00 62 02 00 00 fe a4 20 04 |         sends.hdc1 (16)           r1      r19    r21     0x00000080  0x0420A4FE  // wr:2+2, rd:2; untyped_atomic_mov simd16 (16) bti(254)
skl | 33 00 80 0c 18 90 a1 01 e2 02 00 00 fe a2 20 04 |         sends.hdc1 (16)           r13     r23    r25     0x00000080  0x0420A2FE  // wr:2+2, rd:2; untyped_atomic_or simd16 (16) bti(254)
skl | 33 00 60 0c 10 a0 00 00 c4 01 00 00 00 60 02 02 |         sends.hdc1 (8)            null    r14    r10     0x00000100  0x02026000  // wr:1+4, rd:0; untyped_write:xyzw simd8 (8) bti(0)
skl | 33 00 60 0c 10 20 00 00 81 00 00 00 fe 6e 02 02 |         sends.hdc1 (8)            null    r4     r2      0x00000040  0x02026EFE  // wr:1+1, rd:0; untyped_write:x simd8 (8) bti(254)
skl | 33 00 60 0c 18 40 e1 00 61 02 00 00 fe bd 10 02 |         sends.hdc1 (8)            r7      r19    r20     0x00000040  0x0210BDFE  // wr:1+1, rd:1; untyped_atomic_umin simd8 (8) bti(254)
skl | 33 00 60 0c 18 a0 61 01 21 03 00 00 fe b4 10 02 |         sends.hdc1 (8)            r11     r25    r26     0x00000040  0x0210B4FE  // wr:1+1, rd:1; untyped_atomic_mov simd8 (8) bti(254)
skl | 33 00 80 0c 18 00 21 00 c2 01 00 00 fe a7 20 04 |         sends.hdc1 (16)           r1      r14    r16     0x00000080  0x0420A7FE  // wr:2+2, rd:2; untyped_atomic_add simd16 (16) bti(254)
skl | 33 00 61 0c 12 d0 00 00 44 20 00 00 00 00 00 00 | (f1.0)  sends.hdc1 (8)            null    r2     r13     0x00000100  a0.0
skl | 33 00 61 0c 12 60 00 00 a1 00 00 00 01 6e 02 02 | (f1.0)  sends.hdc1 (8)            null    r5     r6      0x00000040  0x02026E01  // wr:1+1, rd:0; untyped_write:x simd8 (8) bti(1)
skl | 33 00 61 0c 12 60 00 00 a1 00 00 00 02 6e 02 02 | (f1.0)  sends.hdc1 (8)            null    r5     r6      0x00000040  0x02026E02  // wr:1+1, rd:0; untyped_write:x simd8 (8) bti(2)
skl | 33 00 81 0c 12 80 00 00 c2 00 00 00 01 5e 02 04 | (f1.0)  sends.hdc1 (16)           null    r6     r8      0x00000080  0x04025E01  // wr:2+2, rd:0; untyped_write:x simd16 (16) bti(1)
skl | 33 00 81 0c 12 80 00 00 c2 00 00 00 02 5e 02 04 | (f1.0)  sends.hdc1 (16)           null    r6     r8      0x00000080  0x04025E02  // wr:2+2, rd:0; untyped_write:x simd16 (16) bti(2)
skl | 33 00 61 0c 1a 90 60 00 01 01 00 00 02 b7 10 02 | (f1.0)  sends.hdc1 (8)            r3      r8     r9      0x00000040  0x0210B702  // wr:1+1, rd:1; untyped_atomic_add simd8 (8) bti(2)
skl | 33 00 81 0c 1a d0 80 00 62 01 00 00 02 a7 20 04 | (f1.0)  sends.hdc1 (16)           r4      r11    r13     0x00000080  0x0420A702  // wr:2+2, rd:2; untyped_atomic_add simd16 (16) bti(2)
skl | 33 00 61 0c 12 30 00 00 a2 00 00 00 01 6c 02 02 | (f1.0)  sends.hdc1 (8)            null    r5     r3      0x00000080  0x02026C01  // wr:1+2, rd:0; untyped_write:xy simd8 (8) bti(1)
skl | 33 00 81 0c 12 50 01 00 64 02 00 00 01 5c 02 04 | (f1.0)  sends.hdc1 (16)           null    r19    r21     0x00000100  0x04025C01  // wr:2+4, rd:0; untyped_write:xy simd16 (16) bti(1)
skl | 33 00 60 0c 10 f0 00 00 c1 01 00 00 00 6e 02 02 |         sends.hdc1 (8)            null    r14    r15     0x00000040  0x02026E00  // wr:1+1, rd:0; untyped_write:x simd8 (8) bti(0)
skl | 33 00 60 0c 10 90 00 00 02 02 00 00 00 6c 02 02 |         sends.hdc1 (8)            null    r16    r9      0x00000080  0x02026C00  // wr:1+2, rd:0; untyped_write:xy simd8 (8) bti(0)
skl | 33 00 61 0c 12 20 01 00 e4 01 00 00 01 50 03 06 | (f1.0)  sends.hdc1 (8)            null    r15    r18     0x00000100  0x06035001  // wr:3+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
skl | 33 10 61 0c 12 b0 00 00 44 04 00 00 01 60 03 06 | (f1.0)  sends.hdc1 (8|M8)         null    r34    r11     0x00000100  0x06036001  // wr:3+4, rd:0; typed_write:xyzw simd8 (8) bti(1)
skl | 33 00 61 0c 1a 30 a1 01 41 02 00 00 02 bb 10 02 | (f1.0)  sends.hdc1 (8)            r13     r18    r19     0x00000040  0x0210BB02  // wr:1+1, rd:1; untyped_atomic_imin simd8 (8) bti(2)
skl | 33 00 61 0c 1a e0 01 02 21 03 00 00 02 b4 10 02 | (f1.0)  sends.hdc1 (8)            r16     r25    r30     0x00000040  0x0210B402  // wr:1+1, rd:1; untyped_atomic_mov simd8 (8) bti(2)
skl | 33 00 81 0c 1a d0 c1 02 62 03 00 00 02 ab 20 04 | (f1.0)  sends.hdc1 (16)           r22     r27    r29     0x00000080  0x0420AB02  // wr:2+2, rd:2; untyped_atomic_imin simd16 (16) bti(2)
skl | 33 00 81 0c 1a 20 20 03 a2 04 00 00 02 a4 20 04 | (f1.0)  sends.hdc1 (16)           r25     r37    r2      0x00000080  0x0420A402  // wr:2+2, rd:2; untyped_atomic_mov simd16 (16) bti(2)
skl | 33 00 80 0c 10 a0 00 00 04 01 00 00 02 5c 02 04 |         sends.hdc1 (16)           null    r8     r10     0x00000100  0x04025C02  // wr:2+4, rd:0; untyped_write:xy simd16 (16) bti(2)
skl | 33 00 61 0c 1a 90 e0 0f 41 00 00 00 01 a4 11 04 | (f1.0)  sends.hdc1 (8)            r127    r2     r9      0x00000040  0x0411A401  // wr:2+1, rd:1; typed_atomic_mov simd16 (8) bti(1)
skl | 33 10 61 0c 1a 40 e0 0f 41 00 00 00 01 b4 11 04 | (f1.0)  sends.hdc1 (8|M8)         r127    r2     r4      0x00000040  0x0411B401  // wr:2+1, rd:1; typed_atomic_mov simd8 (8) bti(1)
skl | 33 00 61 0c 12 f0 00 00 c1 01 00 00 01 92 00 02 | (f1.0)  sends.hdc1 (8)            null    r14    r15     0x00000040  0x02009201  // wr:1+1, rd:0; untyped_atomic_or simd8 (8) bti(1)
skl | 33 00 81 0c 12 a0 01 00 02 03 00 00 01 82 00 04 | (f1.0)  sends.hdc1 (16)           null    r24    r26     0x00000080  0x04008201  // wr:2+2, rd:0; untyped_atomic_or simd16 (16) bti(1)
skl | 33 00 60 0c 10 b0 00 00 84 0f 00 00 00 50 03 04 |         sends.hdc1 (8)            null    r124   r11     0x00000100  0x04035000  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(0)
skl | 33 00 61 0c 12 60 00 00 a1 00 00 00 02 5e 03 02 | (f1.0)  sends.hdc1 (8)            null    r5     r6      0x00000040  0x02035E02  // wr:1+1, rd:0; typed_write:x simd16 (8) bti(2)
skl | 33 10 61 0c 12 90 00 00 e1 00 00 00 02 6e 03 02 | (f1.0)  sends.hdc1 (8|M8)         null    r7     r9      0x00000040  0x02036E02  // wr:1+1, rd:0; typed_write:x simd8 (8) bti(2)
skl | 33 00 60 0c 10 50 01 00 61 01 00 00 00 5e 03 04 |         sends.hdc1 (8)            null    r11    r21     0x00000040  0x04035E00  // wr:2+1, rd:0; typed_write:x simd16 (8) bti(0)
skl | 33 00 60 0c 10 b0 01 00 e1 01 00 00 02 5e 03 04 |         sends.hdc1 (8)            null    r15    r27     0x00000040  0x04035E02  // wr:2+1, rd:0; typed_write:x simd16 (8) bti(2)
skl | 33 10 60 0c 10 c0 01 00 01 02 00 00 02 6e 03 04 |         sends.hdc1 (8|M8)         null    r16    r28     0x00000040  0x04036E02  // wr:2+1, rd:0; typed_write:x simd8 (8) bti(2)
skl | 33 00 61 0c 1a 40 a1 01 61 02 00 00 02 bd 10 02 | (f1.0)  sends.hdc1 (8)            r13     r19    r20     0x00000040  0x0210BD02  // wr:1+1, rd:1; untyped_atomic_umin simd8 (8) bti(2)
skl | 33 00 81 0c 1a e0 c1 02 82 03 00 00 02 ad 20 04 | (f1.0)  sends.hdc1 (16)           r22     r28    r30     0x00000080  0x0420AD02  // wr:2+2, rd:2; untyped_atomic_umin simd16 (16) bti(2)
skl | 33 00 61 0c 12 40 00 00 42 00 00 00 02 5c 03 04 | (f1.0)  sends.hdc1 (8)            null    r2     r4      0x00000080  0x04035C02  // wr:2+2, rd:0; typed_write:xy simd16 (8) bti(2)
skl | 33 10 61 0c 12 80 02 00 c2 04 00 00 02 6c 03 04 | (f1.0)  sends.hdc1 (8|M8)         null    r38    r40     0x00000080  0x04036C02  // wr:2+2, rd:0; typed_write:xy simd8 (8) bti(2)
skl | 33 00 60 0c 10 60 00 00 24 02 00 00 00 50 03 02 |         sends.hdc1 (8)            null    r17    r6      0x00000100  0x02035000  // wr:1+4, rd:0; typed_write:xyzw simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 a7 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211A700  // wr:1+1, rd:1; typed_atomic_add simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 ad 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211AD00  // wr:1+1, rd:1; typed_atomic_umin simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 ac 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211AC00  // wr:1+1, rd:1; typed_atomic_umax simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 a1 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211A100  // wr:1+1, rd:1; typed_atomic_and simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 a2 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211A200  // wr:1+1, rd:1; typed_atomic_or simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 a3 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211A300  // wr:1+1, rd:1; typed_atomic_xor simd16 (8) bti(0)
skl | 33 00 60 0c 18 50 81 0f 81 02 00 00 00 a4 11 02 |         sends.hdc1 (8)            r124    r20    r21     0x00000040  0x0211A400  // wr:1+1, rd:1; typed_atomic_mov simd16 (8) bti(0)
skl | 33 00 60 0c 18 60 80 0f a2 02 00 00 00 ae 11 02 |         sends.hdc1 (8)            r124    r21    r6      0x00000080  0x0211AE00  // wr:1+2, rd:1; typed_atomic_cmpwr simd16 (8) bti(0)
skl | 33 00 61 0c 12 20 00 00 04 02 00 00 01 50 03 02 | (f1.0)  sends.hdc1 (8)            null    r16    r2      0x00000100  0x02035001  // wr:1+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
skl | 33 10 61 0c 12 80 00 00 a4 03 00 00 01 60 03 02 | (f1.0)  sends.hdc1 (8|M8)         null    r29    r8      0x00000100  0x02036001  // wr:1+4, rd:0; typed_write:xyzw simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 c1 01 00 00 01 5e 03 02 | (f1.0)  sends.hdc1 (8)            null    r14    r18     0x00000040  0x02035E01  // wr:1+1, rd:0; typed_write:x simd16 (8) bti(1)
skl | 33 10 61 0c 12 70 00 00 e1 02 00 00 01 6e 03 02 | (f1.0)  sends.hdc1 (8|M8)         null    r23    r7      0x00000040  0x02036E01  // wr:1+1, rd:0; typed_write:x simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 00 00 24 02 00 00 02 50 03 02 | (f1.0)  sends.hdc1 (8)            null    r17    r2      0x00000100  0x02035002  // wr:1+4, rd:0; typed_write:xyzw simd16 (8) bti(2)
skl | 33 10 61 0c 12 30 00 00 84 03 00 00 02 60 03 02 | (f1.0)  sends.hdc1 (8|M8)         null    r28    r3      0x00000100  0x02036002  // wr:1+4, rd:0; typed_write:xyzw simd8 (8) bti(2)
skl | 33 00 61 0c 12 20 00 00 24 02 00 00 03 50 03 02 | (f1.0)  sends.hdc1 (8)            null    r17    r2      0x00000100  0x02035003  // wr:1+4, rd:0; typed_write:xyzw simd16 (8) bti(3)
skl | 33 10 61 0c 12 60 00 00 e4 02 00 00 03 60 03 02 | (f1.0)  sends.hdc1 (8|M8)         null    r23    r6      0x00000100  0x02036003  // wr:1+4, rd:0; typed_write:xyzw simd8 (8) bti(3)
skl | 33 00 61 0c 12 d0 00 00 81 01 00 00 01 97 00 02 | (f1.0)  sends.hdc1 (8)            null    r12    r13     0x00000040  0x02009701  // wr:1+1, rd:0; untyped_atomic_add simd8 (8) bti(1)
skl | 33 00 81 0c 12 60 01 00 82 02 00 00 01 87 00 04 | (f1.0)  sends.hdc1 (16)           null    r20    r22     0x00000080  0x04008701  // wr:2+2, rd:0; untyped_atomic_add simd16 (16) bti(1)
skl | 33 00 60 0c 18 30 e1 00 41 02 00 00 fe bb 10 02 |         sends.hdc1 (8)            r7      r18    r19     0x00000040  0x0210BBFE  // wr:1+1, rd:1; untyped_atomic_imin simd8 (8) bti(254)
skl | 33 00 60 0c 10 10 00 00 c4 00 00 00 03 50 03 04 |         sends.hdc1 (8)            null    r6     r1      0x00000100  0x04035003  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(3)
skl | 33 10 60 0c 10 a0 00 00 04 01 00 00 03 60 03 04 |         sends.hdc1 (8|M8)         null    r8     r10     0x00000100  0x04036003  // wr:2+4, rd:0; typed_write:xyzw simd8 (8) bti(3)
skl | 33 00 61 0c 1a 40 61 00 a1 02 00 00 01 b7 10 02 | (f1.0)  sends.hdc1 (8)            r3      r21    r20     0x00000040  0x0210B701  // wr:1+1, rd:1; untyped_atomic_add simd8 (8) bti(1)
skl | 33 00 61 0c 1a 40 a1 00 a1 02 00 00 01 bd 10 02 | (f1.0)  sends.hdc1 (8)            r5      r21    r20     0x00000040  0x0210BD01  // wr:1+1, rd:1; untyped_atomic_umin simd8 (8) bti(1)
skl | 33 00 61 0c 1a 40 c1 00 a1 02 00 00 01 bc 10 02 | (f1.0)  sends.hdc1 (8)            r6      r21    r20     0x00000040  0x0210BC01  // wr:1+1, rd:1; untyped_atomic_umax simd8 (8) bti(1)
skl | 33 00 61 0c 1a 40 e1 00 a1 02 00 00 01 b1 10 02 | (f1.0)  sends.hdc1 (8)            r7      r21    r20     0x00000040  0x0210B101  // wr:1+1, rd:1; untyped_atomic_and simd8 (8) bti(1)
skl | 33 00 61 0c 1a 40 21 01 a1 02 00 00 01 b3 10 02 | (f1.0)  sends.hdc1 (8)            r9      r21    r20     0x00000040  0x0210B301  // wr:1+1, rd:1; untyped_atomic_xor simd8 (8) bti(1)
skl | 33 00 61 0c 1a 40 41 01 a1 02 00 00 01 b4 10 02 | (f1.0)  sends.hdc1 (8)            r10     r21    r20     0x00000040  0x0210B401  // wr:1+1, rd:1; untyped_atomic_mov simd8 (8) bti(1)
skl | 33 00 61 0c 1a b0 60 01 a2 02 00 00 01 be 10 02 | (f1.0)  sends.hdc1 (8)            r11     r21    r11     0x00000080  0x0210BE01  // wr:1+2, rd:1; untyped_atomic_cmpwr simd8 (8) bti(1)
skl | 33 00 81 0c 1a 40 62 00 c2 04 00 00 01 a7 20 04 | (f1.0)  sends.hdc1 (16)           r3      r38    r36     0x00000080  0x0420A701  // wr:2+2, rd:2; untyped_atomic_add simd16 (16) bti(1)
skl | 33 00 81 0c 1a 40 e2 00 c2 04 00 00 01 ad 20 04 | (f1.0)  sends.hdc1 (16)           r7      r38    r36     0x00000080  0x0420AD01  // wr:2+2, rd:2; untyped_atomic_umin simd16 (16) bti(1)
skl | 33 00 81 0c 1a 40 22 01 c2 04 00 00 01 ac 20 04 | (f1.0)  sends.hdc1 (16)           r9      r38    r36     0x00000080  0x0420AC01  // wr:2+2, rd:2; untyped_atomic_umax simd16 (16) bti(1)
skl | 33 00 81 0c 1a 40 62 01 c2 04 00 00 01 a1 20 04 | (f1.0)  sends.hdc1 (16)           r11     r38    r36     0x00000080  0x0420A101  // wr:2+2, rd:2; untyped_atomic_and simd16 (16) bti(1)
skl | 33 00 81 0c 1a 40 e2 01 c2 04 00 00 01 a3 20 04 | (f1.0)  sends.hdc1 (16)           r15     r38    r36     0x00000080  0x0420A301  // wr:2+2, rd:2; untyped_atomic_xor simd16 (16) bti(1)
skl | 33 00 81 0c 1a 40 22 02 c2 04 00 00 01 a4 20 04 | (f1.0)  sends.hdc1 (16)           r17     r38    r36     0x00000080  0x0420A401  // wr:2+2, rd:2; untyped_atomic_mov simd16 (16) bti(1)
skl | 33 00 81 0c 1a 50 61 02 c4 04 00 00 01 ae 20 04 | (f1.0)  sends.hdc1 (16)           r19     r38    r21     0x00000100  0x0420AE01  // wr:2+4, rd:2; untyped_atomic_cmpwr simd16 (16) bti(1)
skl | 33 00 60 0c 10 c0 00 00 81 00 00 00 09 5e 03 04 |         sends.hdc1 (8)            null    r4     r12     0x00000040  0x04035E09  // wr:2+1, rd:0; typed_write:x simd16 (8) bti(9)
skl | 33 10 60 0c 10 d0 00 00 a1 00 00 00 09 6e 03 04 |         sends.hdc1 (8|M8)         null    r5     r13     0x00000040  0x04036E09  // wr:2+1, rd:0; typed_write:x simd8 (8) bti(9)
skl | 33 00 61 0c 12 20 01 00 c1 01 00 00 01 9d 00 02 | (f1.0)  sends.hdc1 (8)            null    r14    r18     0x00000040  0x02009D01  // wr:1+1, rd:0; untyped_atomic_umin simd8 (8) bti(1)
skl | 33 00 61 0c 12 30 01 00 21 02 00 00 01 9c 00 02 | (f1.0)  sends.hdc1 (8)            null    r17    r19     0x00000040  0x02009C01  // wr:1+1, rd:0; untyped_atomic_umax simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 01 00 61 02 00 00 01 91 00 02 | (f1.0)  sends.hdc1 (8)            null    r19    r20     0x00000040  0x02009101  // wr:1+1, rd:0; untyped_atomic_and simd8 (8) bti(1)
skl | 33 00 61 0c 12 60 01 00 61 03 00 00 01 93 00 02 | (f1.0)  sends.hdc1 (8)            null    r27    r22     0x00000040  0x02009301  // wr:1+1, rd:0; untyped_atomic_xor simd8 (8) bti(1)
skl | 33 00 61 0c 12 70 01 00 a1 03 00 00 01 94 00 02 | (f1.0)  sends.hdc1 (8)            null    r29    r23     0x00000040  0x02009401  // wr:1+1, rd:0; untyped_atomic_mov simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 00 00 02 04 00 00 01 9e 00 02 | (f1.0)  sends.hdc1 (8)            null    r32    r2      0x00000080  0x02009E01  // wr:1+2, rd:0; untyped_atomic_cmpwr simd8 (8) bti(1)
skl | 33 00 81 0c 12 00 02 00 42 02 00 00 01 8d 00 04 | (f1.0)  sends.hdc1 (16)           null    r18    r32     0x00000080  0x04008D01  // wr:2+2, rd:0; untyped_atomic_umin simd16 (16) bti(1)
skl | 33 00 81 0c 12 10 02 00 02 03 00 00 01 8c 00 04 | (f1.0)  sends.hdc1 (16)           null    r24    r33     0x00000080  0x04008C01  // wr:2+2, rd:0; untyped_atomic_umax simd16 (16) bti(1)
skl | 33 00 81 0c 12 20 02 00 c2 03 00 00 01 81 00 04 | (f1.0)  sends.hdc1 (16)           null    r30    r34     0x00000080  0x04008101  // wr:2+2, rd:0; untyped_atomic_and simd16 (16) bti(1)
skl | 33 00 81 0c 12 40 02 00 c2 05 00 00 01 83 00 04 | (f1.0)  sends.hdc1 (16)           null    r46    r36     0x00000080  0x04008301  // wr:2+2, rd:0; untyped_atomic_xor simd16 (16) bti(1)
skl | 33 00 81 0c 12 50 02 00 22 06 00 00 01 84 00 04 | (f1.0)  sends.hdc1 (16)           null    r49    r37     0x00000080  0x04008401  // wr:2+2, rd:0; untyped_atomic_mov simd16 (16) bti(1)
skl | 33 00 81 0c 12 20 00 00 04 07 00 00 01 8e 00 04 | (f1.0)  sends.hdc1 (16)           null    r56    r2      0x00000100  0x04008E01  // wr:2+4, rd:0; untyped_atomic_cmpwr simd16 (16) bti(1)
skl | 33 00 61 0c 12 50 01 00 81 02 00 00 01 81 01 02 | (f1.0)  sends.hdc1 (8)            null    r20    r21     0x00000040  0x02018101  // wr:1+1, rd:0; typed_atomic_and simd16 (8) bti(1)
skl | 33 10 61 0c 12 60 02 00 61 00 00 00 01 91 01 02 | (f1.0)  sends.hdc1 (8|M8)         null    r3     r38     0x00000040  0x02019101  // wr:1+1, rd:0; typed_atomic_and simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 01 00 61 02 00 00 01 82 01 02 | (f1.0)  sends.hdc1 (8)            null    r19    r20     0x00000040  0x02018201  // wr:1+1, rd:0; typed_atomic_or simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 02 00 61 00 00 00 01 92 01 02 | (f1.0)  sends.hdc1 (8|M8)         null    r3     r36     0x00000040  0x02019201  // wr:1+1, rd:0; typed_atomic_or simd8 (8) bti(1)
skl | 33 00 61 0c 12 40 01 00 61 02 00 00 01 83 01 02 | (f1.0)  sends.hdc1 (8)            null    r19    r20     0x00000040  0x02018301  // wr:1+1, rd:0; typed_atomic_xor simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 02 00 61 00 00 00 01 93 01 02 | (f1.0)  sends.hdc1 (8|M8)         null    r3     r36     0x00000040  0x02019301  // wr:1+1, rd:0; typed_atomic_xor simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 41 00 00 00 01 87 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r18     0x00000040  0x04018701  // wr:2+1, rd:0; typed_atomic_add simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 00 00 41 00 00 00 01 97 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r4      0x00000040  0x04019701  // wr:2+1, rd:0; typed_atomic_add simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 41 00 00 00 01 8d 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r18     0x00000040  0x04018D01  // wr:2+1, rd:0; typed_atomic_umin simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 00 00 41 00 00 00 01 9d 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r4      0x00000040  0x04019D01  // wr:2+1, rd:0; typed_atomic_umin simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 41 00 00 00 01 81 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r18     0x00000040  0x04018101  // wr:2+1, rd:0; typed_atomic_and simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 00 00 41 00 00 00 01 91 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r4      0x00000040  0x04019101  // wr:2+1, rd:0; typed_atomic_and simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 41 00 00 00 01 82 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r18     0x00000040  0x04018201  // wr:2+1, rd:0; typed_atomic_or simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 00 00 41 00 00 00 01 92 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r4      0x00000040  0x04019201  // wr:2+1, rd:0; typed_atomic_or simd8 (8) bti(1)
skl | 33 00 61 0c 12 20 01 00 41 00 00 00 01 83 01 04 | (f1.0)  sends.hdc1 (8)            null    r2     r18     0x00000040  0x04018301  // wr:2+1, rd:0; typed_atomic_xor simd16 (8) bti(1)
skl | 33 10 61 0c 12 40 00 00 41 00 00 00 01 93 01 04 | (f1.0)  sends.hdc1 (8|M8)         null    r2     r4      0x00000040  0x04019301  // wr:2+1, rd:0; typed_atomic_xor simd8 (8) bti(1)

tgl | 31 96 04 00 00 00 05 71 04 0c 00 c0 00 00 00 00 |         send.hdc1 (16)            r113    r12    null    0x00000000  a0.0         {@1,$6}
tgl | 31 94 84 01 00 00 01 00 04 0f 00 c0 14 11 00 00 | (f1.0)  send.hdc1 (16)            null    r15    r17     0x00000080  a0.0         {@1,$4}
tgl | 31 48 13 00 00 00 0c 68 14 77 26 cc 00 00 5a 00 |         send.hdc1 (8|M8)          r104    r119   null    0x00000000  0x04116E13   {$8}  // wr:2+0, rd:1; typed_read:x simd8 (8) bti(19)
tgl | 31 98 03 00 00 01 02 00 0c 5c f8 c1 04 75 d4 00 |         send.hdc1 (8)             null    r92    r117    a0.2        0x020350FC   {@1,$8}  // wr:1+a0.2, rd:0; ?
tgl | 31 b9 03 88 00 00 0c 37 0c 76 02 a4 00 00 10 02 | (W&f0.0.any8h) send.hdc0 (8)      r55     r118   null    0x00000000  0x02184201   {@3,$9}  // wr:1h+0, rd:1; oword_unaligned_block_read:owords2 (8) bti(1)
tgl | 31 01 03 80 04 00 00 00 0c 7e 00 70 00 00 00 00 | (W)     send.ts (8)               null    r126   null    0x00000000  0x02000000   {EOT,@1}
tgl | 31 41 03 00 00 00 0c 12 14 18 20 cc 00 00 56 00 |         send.hdc1 (8)             r18     r24    null    0x00000000  0x04115E10   {$1}  // wr:2+0, rd:1; typed_read:x simd16 (8) bti(16)
tgl | 31 f2 13 00 00 00 0c 13 14 1c 20 cc 00 00 5a 00 |         send.hdc1 (8|M8)          r19     r28    null    0x00000000  0x04116E10   {@7,$2}  // wr:2+0, rd:1; typed_read:x simd8 (8) bti(16)
tgl | 31 93 04 00 00 00 05 32 04 24 00 20 00 00 00 00 |         send.smpl (16)            r50     r36    null    0x00000000  a0.0         {@1,$3}
tgl | 31 49 03 00 00 00 00 00 0c 19 02 c0 24 15 d4 00 |         send.hdc1 (8)             null    r25    r21     0x00000100  0x02035001   {$9}  // wr:1+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
tgl | 31 4a 03 00 00 00 24 05 0c 19 02 c0 00 00 54 00 |         send.hdc1 (8)             r5      r25    null    0x00000000  0x02415001   {$10}  // wr:1+0, rd:4; typed_read:xyzw simd16 (8) bti(1)
tgl | 31 90 03 00 00 00 0c 1b 14 23 fa cd 00 00 1a 01 |         send.hdc1 (8)             r27     r35    null    0x00000000  0x04146EFD   {@1,$0}  // wr:2+0, rd:1; a64_untyped_read:x simd8 (8) flat+0x0
tgl | 31 91 03 00 00 00 00 00 14 24 02 c0 24 26 d4 00 |         send.hdc1 (8)             null    r36    r38     0x00000100  0x04035001   {@1,$1}  // wr:2+4, rd:0; typed_write:xyzw simd16 (8) bti(1)
tgl | 31 01 03 00 04 00 00 00 0c 7e 0e 60 44 76 00 02 |         send.urb (8)              null    r126   r118    0x00000200  0x02080007   {EOT,@1}  // wr:1h+8, rd:0; simd8_write (8)
tgl | 31 90 03 00 00 00 0c 0e 0c 25 02 a8 00 00 40 00 |         send.hdc0 (8)             r14     r37    null    0x00000000  0x02110401   {@1,$0}  // wr:1+0, rd:1; byte_scattered_read:d16 simd8 (8) bti(1)
tgl | 31 41 00 80 00 00 0c 64 0c 00 00 a0 00 00 78 02 | (W)     send.hdc0 (1)             r100    r0     null    0x00000000  0x0219E000   {$1}  // wr:1h+0, rd:1; memory_fence (1)
tgl | 31 45 00 80 00 00 0c 0f 0c 00 00 a0 00 00 78 02 | (W)     send.hdc0 (1)             r15     r0     null    0x00000000  0x0219E000   {$5}  // wr:1h+0, rd:1; memory_fence (1)
tgl | 32 01 04 00 04 00 00 00 44 77 00 50 00 00 c4 00 |         sendc.render (16)         null    r119   null    0x00000000  0x10031000   {EOT,@1}  // wr:8+0, rd:0; simd16 rt_write last_rt (16) bti(0)
tgl | 32 01 03 00 04 00 00 00 14 7d 00 58 14 7b c4 00 |         sendc.render (8)          null    r125   r123    0x00000080  0x04031400   {EOT,@1}  // wr:2+2, rd:0; simd8 rt_write last_rt (8) bti(0)
tgl | 32 01 04 00 04 00 00 00 24 7b 00 50 24 77 c4 00 |         sendc.render (16)         null    r123   r119    0x00000100  0x08031000   {EOT,@1}  // wr:4+4, rd:0; simd16 rt_write last_rt (16) bti(0)

dg2 | 31 45 00 88 00 00 0c 39 8e 3a 00 fa 00 00 30 04 | (W&f0.0.any8h) send.ugm (1)       r57     r58    null:0  0x02000000  0x6210C500   {$5}  // wr:1+0, rd:1; load.ugm.d32x8t.a32.bti[2]
dg2 | 31 42 00 88 00 00 0c 1c 8e 1d 00 fa 00 00 30 04 | (W&f0.0.any8h) send.ugm (1)       r28     r29    null:0  0x02000000  0x6210C500   {$2}  // wr:1+0, rd:1; load.ugm.d32x8t.a32.bti[2]
dg2 | 31 40 00 8c 00 00 0c 39 8e 3a 00 fa 00 00 30 04 | (W&f0.0.any32h) send.ugm (1)      r57     r58    null:0  0x02000000  0x6210C500   {$0}  // wr:1+0, rd:1; load.ugm.d32x8t.a32.bti[2]
dg2 | 31 40 03 00 00 00 00 00 8c 4f 0c fa 25 0a 3c 04 |         send.ugm (8)              null    r79    r10:4   0x04000100  0x6200F506   {$0}  // wr:1+4, rd:0; store_cmask.ugm.d32.xyzw.a32.bti[4]
dg2 | 31 90 04 00 00 01 02 00 14 09 08 fa 04 07 00 04 |         send.ugm (16)             null    r9     r7      a0.2        0x44000504   {@1,$0}  // wr:2+a0.2, rd:0; store.ugm.d32.a32.ss[a0.2]
dg2 | 31 43 00 80 00 00 0c 04 0c 00 3e da 00 00 04 00 | (W)     send.tgm (1)              r4      r0     null:0  0x00000000  0x0210151F   {$3}  // wr:1+0, rd:1; fence.tgm.tile.evict
dg2 | 31 41 03 00 00 00 00 00 0c 24 08 e6 0c 25 02 00 |         send.slm (8)              null    r36    r37:1   0x00000040  0x02000B04   {$1}  // wr:1+1, rd:0; store.slm.d16u32.a32
dg2 | 31 40 03 00 00 00 00 00 0c 22 08 e6 0c 23 02 00 |         send.slm (8)              null    r34    r35:1   0x00000040  0x02000B04   {$0}  // wr:1+1, rd:0; store.slm.d16u32.a32
dg2 | 31 46 03 00 00 00 00 00 0c 06 0c ea 24 07 3c 00 |         send.slm (8)              null    r6     r7:4    0x00000100  0x0200F506   {$6}  // wr:1+4, rd:0; store_cmask.slm.d32.xyzw.a32
dg2 | 31 40 24 00 00 00 00 00 14 52 32 ea 14 5b 00 01 |         send.slm (16|M16)         null    r82    r91:2   0x00000080  0x04040519   {$0}  // wr:2+2, rd:0; atomic_or.slm.d32.a32.uc.wb
dg2 | 31 41 00 80 00 00 0c 0a 0c 00 3e e2 00 00 00 00 | (W)     send.slm (1)              r10     r0     null:0  0x00000000  0x0210011F   {$1}  // wr:1+0, rd:1; fence.slm.threadgroup.none
dg2 | 31 9a 00 80 80 01 0e 17 8c 75 00 fa 00 00 30 00 | (W)     send.ugm (1)              r23     r117   null:0  a0.2        0x2210C500   {ExBSO,@1,$10}  // wr:1+a0.2, rd:1; load.ugm.d32x8t.a32.bss[a0.2]
dg2 | 31 95 03 00 80 01 02 00 14 0e f8 c1 24 18 d4 00 |         send.hdc1 (8)             null    r14    r24:4   a0.2        0x040350FC   {ExBSO,@1,$5}  // wr:2+4, rd:0; ?
dg2 | 31 42 03 00 00 00 00 00 0c 33 00 80 0c 34 00 00 |         send.rtaccel (8)          null    r51    r52:1   0x00000040  0x02000000   {$2}  // wr:1+1, rd:0; trace_ray simd8 (8)
dg2 | 31 46 04 00 00 00 00 00 0c 58 00 82 14 62 00 00 |         send.rtaccel (16)         null    r88    r98:2   0x00000080  0x02000100   {$6}  // wr:1+2, rd:0; trace_ray simd16 (16)
